1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) !! 1 /*
2 // Copyright (C) 2016 ARM Ltd. !! 2 * Copyright (C) 2016 ARM Ltd.
>> 3 *
>> 4 * This file is dual-licensed: you can use it either under the terms
>> 5 * of the GPL or the X11 license, at your option. Note that this dual
>> 6 * licensing only applies to this file, and not this project as a
>> 7 * whole.
>> 8 *
>> 9 * a) This file is free software; you can redistribute it and/or
>> 10 * modify it under the terms of the GNU General Public License as
>> 11 * published by the Free Software Foundation; either version 2 of the
>> 12 * License, or (at your option) any later version.
>> 13 *
>> 14 * This file is distributed in the hope that it will be useful,
>> 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 17 * GNU General Public License for more details.
>> 18 *
>> 19 * Or, alternatively,
>> 20 *
>> 21 * b) Permission is hereby granted, free of charge, to any person
>> 22 * obtaining a copy of this software and associated documentation
>> 23 * files (the "Software"), to deal in the Software without
>> 24 * restriction, including without limitation the rights to use,
>> 25 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 26 * sell copies of the Software, and to permit persons to whom the
>> 27 * Software is furnished to do so, subject to the following
>> 28 * conditions:
>> 29 *
>> 30 * The above copyright notice and this permission notice shall be
>> 31 * included in all copies or substantial portions of the Software.
>> 32 *
>> 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 40 * OTHER DEALINGS IN THE SOFTWARE.
>> 41 */
3 42
4 #include <arm/allwinner/sunxi-h3-h5.dtsi> !! 43 #include <arm/sunxi-h3-h5.dtsi>
5 <<
6 #include <dt-bindings/thermal/thermal.h> <<
7 44
8 / { 45 / {
9 cpus { 46 cpus {
10 #address-cells = <1>; 47 #address-cells = <1>;
11 #size-cells = <0>; 48 #size-cells = <0>;
12 49
13 cpu0: cpu@0 { 50 cpu0: cpu@0 {
14 compatible = "arm,cort !! 51 compatible = "arm,cortex-a53", "arm,armv8";
15 device_type = "cpu"; 52 device_type = "cpu";
16 reg = <0>; 53 reg = <0>;
17 enable-method = "psci" 54 enable-method = "psci";
18 clocks = <&ccu CLK_CPU <<
19 clock-latency-ns = <24 <<
20 #cooling-cells = <2>; <<
21 }; 55 };
22 56
23 cpu1: cpu@1 { !! 57 cpu@1 {
24 compatible = "arm,cort !! 58 compatible = "arm,cortex-a53", "arm,armv8";
25 device_type = "cpu"; 59 device_type = "cpu";
26 reg = <1>; 60 reg = <1>;
27 enable-method = "psci" 61 enable-method = "psci";
28 clocks = <&ccu CLK_CPU <<
29 clock-latency-ns = <24 <<
30 #cooling-cells = <2>; <<
31 }; 62 };
32 63
33 cpu2: cpu@2 { !! 64 cpu@2 {
34 compatible = "arm,cort !! 65 compatible = "arm,cortex-a53", "arm,armv8";
35 device_type = "cpu"; 66 device_type = "cpu";
36 reg = <2>; 67 reg = <2>;
37 enable-method = "psci" 68 enable-method = "psci";
38 clocks = <&ccu CLK_CPU <<
39 clock-latency-ns = <24 <<
40 #cooling-cells = <2>; <<
41 }; 69 };
42 70
43 cpu3: cpu@3 { !! 71 cpu@3 {
44 compatible = "arm,cort !! 72 compatible = "arm,cortex-a53", "arm,armv8";
45 device_type = "cpu"; 73 device_type = "cpu";
46 reg = <3>; 74 reg = <3>;
47 enable-method = "psci" 75 enable-method = "psci";
48 clocks = <&ccu CLK_CPU <<
49 clock-latency-ns = <24 <<
50 #cooling-cells = <2>; <<
51 }; 76 };
52 }; 77 };
53 78
54 pmu { <<
55 compatible = "arm,cortex-a53-p <<
56 interrupts = <GIC_SPI 116 IRQ_ <<
57 <GIC_SPI 117 IRQ_ <<
58 <GIC_SPI 118 IRQ_ <<
59 <GIC_SPI 119 IRQ_ <<
60 interrupt-affinity = <&cpu0>, <<
61 }; <<
62 <<
63 psci { 79 psci {
64 compatible = "arm,psci-0.2"; 80 compatible = "arm,psci-0.2";
65 method = "smc"; 81 method = "smc";
66 }; 82 };
67 83
68 timer { 84 timer {
69 compatible = "arm,armv8-timer" 85 compatible = "arm,armv8-timer";
70 arm,no-tick-in-suspend; <<
71 interrupts = <GIC_PPI 13 86 interrupts = <GIC_PPI 13
72 (GIC_CPU_MASK_ 87 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 88 <GIC_PPI 14
74 (GIC_CPU_MASK_ 89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 11 90 <GIC_PPI 11
76 (GIC_CPU_MASK_ 91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 92 <GIC_PPI 10
78 (GIC_CPU_MASK_ 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
79 }; 94 };
80 95
81 soc { 96 soc {
82 syscon: system-control@1c00000 <<
83 compatible = "allwinne <<
84 reg = <0x01c00000 0x10 <<
85 #address-cells = <1>; <<
86 #size-cells = <1>; <<
87 ranges; <<
88 <<
89 sram_c1: sram@18000 { <<
90 compatible = " <<
91 reg = <0x00018 <<
92 #address-cells <<
93 #size-cells = <<
94 ranges = <0 0x <<
95 <<
96 ve_sram: sram- <<
97 compat <<
98 <<
99 reg = <<
100 }; <<
101 }; <<
102 }; <<
103 <<
104 video-codec@1c0e000 { <<
105 compatible = "allwinne <<
106 reg = <0x01c0e000 0x10 <<
107 clocks = <&ccu CLK_BUS <<
108 <&ccu CLK_DRA <<
109 clock-names = "ahb", " <<
110 resets = <&ccu RST_BUS <<
111 interrupts = <GIC_SPI <<
112 allwinner,sram = <&ve_ <<
113 }; <<
114 <<
115 crypto: crypto@1c15000 { <<
116 compatible = "allwinne <<
117 reg = <0x01c15000 0x10 <<
118 interrupts = <GIC_SPI <<
119 clocks = <&ccu CLK_BUS <<
120 clock-names = "bus", " <<
121 resets = <&ccu RST_BUS <<
122 }; <<
123 <<
124 deinterlace: deinterlace@1e000 <<
125 compatible = "allwinne <<
126 reg = <0x01e00000 0x20 <<
127 clocks = <&ccu CLK_BUS <<
128 <&ccu CLK_DEI <<
129 <&ccu CLK_DRA <<
130 clock-names = "bus", " <<
131 resets = <&ccu RST_BUS <<
132 interrupts = <GIC_SPI <<
133 interconnects = <&mbus <<
134 interconnect-names = " <<
135 }; <<
136 <<
137 mali: gpu@1e80000 { 97 mali: gpu@1e80000 {
138 compatible = "allwinne 98 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
139 reg = <0x01e80000 0x30 99 reg = <0x01e80000 0x30000>;
140 /* 100 /*
141 * While the datasheet 101 * While the datasheet lists an interrupt for the
142 * PMU, the actual sil 102 * PMU, the actual silicon does not have the PMU
143 * block. Reads all re 103 * block. Reads all return zero, and writes are
144 * ignored. 104 * ignored.
145 */ 105 */
146 interrupts = <GIC_SPI 106 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 107 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 108 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 109 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 110 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 113 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 114 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI !! 116 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> 117 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-names = "gp" 118 interrupt-names = "gp",
158 "gpm 119 "gpmmu",
159 "pp" 120 "pp",
160 "pp0 121 "pp0",
161 "ppm 122 "ppmmu0",
162 "pp1 123 "pp1",
163 "ppm 124 "ppmmu1",
164 "pp2 125 "pp2",
165 "ppm 126 "ppmmu2",
166 "pp3 127 "pp3",
167 "ppm !! 128 "ppmmu3",
>> 129 "pmu";
168 clocks = <&ccu CLK_BUS 130 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
169 clock-names = "bus", " 131 clock-names = "bus", "core";
170 resets = <&ccu RST_BUS 132 resets = <&ccu RST_BUS_GPU>;
171 133
172 assigned-clocks = <&cc 134 assigned-clocks = <&ccu CLK_GPU>;
173 assigned-clock-rates = 135 assigned-clock-rates = <384000000>;
174 }; 136 };
175 <<
176 ths: thermal-sensor@1c25000 { <<
177 compatible = "allwinne <<
178 reg = <0x01c25000 0x40 <<
179 interrupts = <GIC_SPI <<
180 resets = <&ccu RST_BUS <<
181 clocks = <&ccu CLK_BUS <<
182 clock-names = "bus", " <<
183 nvmem-cells = <&ths_ca <<
184 nvmem-cell-names = "ca <<
185 #thermal-sensor-cells <<
186 }; <<
187 }; <<
188 <<
189 thermal-zones { <<
190 cpu_thermal: cpu-thermal { <<
191 polling-delay-passive <<
192 polling-delay = <0>; <<
193 thermal-sensors = <&th <<
194 <<
195 trips { <<
196 cpu_hot_trip: <<
197 temper <<
198 hyster <<
199 type = <<
200 }; <<
201 <<
202 cpu_very_hot_t <<
203 temper <<
204 hyster <<
205 type = <<
206 }; <<
207 }; <<
208 <<
209 cooling-maps { <<
210 cpu-hot-limit <<
211 trip = <<
212 coolin <<
213 <<
214 <<
215 <<
216 }; <<
217 }; <<
218 }; <<
219 <<
220 gpu-thermal { <<
221 polling-delay-passive <<
222 polling-delay = <0>; <<
223 thermal-sensors = <&th <<
224 }; <<
225 }; 137 };
226 }; 138 };
227 139
228 &ccu { 140 &ccu {
229 compatible = "allwinner,sun50i-h5-ccu" 141 compatible = "allwinner,sun50i-h5-ccu";
230 }; 142 };
231 143
232 &display_clocks { 144 &display_clocks {
233 compatible = "allwinner,sun50i-h5-de2- 145 compatible = "allwinner,sun50i-h5-de2-clk";
234 }; 146 };
235 147
236 &mbus { <<
237 compatible = "allwinner,sun50i-h5-mbus <<
238 }; <<
239 <<
240 &mmc0 { 148 &mmc0 {
241 compatible = "allwinner,sun50i-h5-mmc" 149 compatible = "allwinner,sun50i-h5-mmc",
242 "allwinner,sun50i-a64-mmc 150 "allwinner,sun50i-a64-mmc";
243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CL 151 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
244 clock-names = "ahb", "mmc"; 152 clock-names = "ahb", "mmc";
245 }; 153 };
246 154
247 &mmc1 { 155 &mmc1 {
248 compatible = "allwinner,sun50i-h5-mmc" 156 compatible = "allwinner,sun50i-h5-mmc",
249 "allwinner,sun50i-a64-mmc 157 "allwinner,sun50i-a64-mmc";
250 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CL 158 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
251 clock-names = "ahb", "mmc"; 159 clock-names = "ahb", "mmc";
252 }; 160 };
253 161
254 &mmc2 { 162 &mmc2 {
255 compatible = "allwinner,sun50i-h5-emmc 163 compatible = "allwinner,sun50i-h5-emmc",
256 "allwinner,sun50i-a64-emm 164 "allwinner,sun50i-a64-emmc";
257 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CL 165 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
258 clock-names = "ahb", "mmc"; 166 clock-names = "ahb", "mmc";
259 }; 167 };
260 168
261 &pio { 169 &pio {
262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVE 170 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 17 IRQ_TYPE_LEVE 171 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 23 IRQ_TYPE_LEVE 172 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
265 compatible = "allwinner,sun50i-h5-pinc 173 compatible = "allwinner,sun50i-h5-pinctrl";
266 }; <<
267 <<
268 &rtc { <<
269 compatible = "allwinner,sun50i-h5-rtc" <<
270 }; <<
271 <<
272 &sid { <<
273 compatible = "allwinner,sun50i-h5-sid" <<
274 }; 174 };
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