1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 3
4 #include <arm/allwinner/sunxi-h3-h5.dtsi> !! 4 #include <arm/sunxi-h3-h5.dtsi>
5 <<
6 #include <dt-bindings/thermal/thermal.h> <<
7 5
8 / { 6 / {
9 cpus { 7 cpus {
10 #address-cells = <1>; 8 #address-cells = <1>;
11 #size-cells = <0>; 9 #size-cells = <0>;
12 10
13 cpu0: cpu@0 { 11 cpu0: cpu@0 {
14 compatible = "arm,cort 12 compatible = "arm,cortex-a53";
15 device_type = "cpu"; 13 device_type = "cpu";
16 reg = <0>; 14 reg = <0>;
17 enable-method = "psci" 15 enable-method = "psci";
18 clocks = <&ccu CLK_CPU <<
19 clock-latency-ns = <24 <<
20 #cooling-cells = <2>; <<
21 }; 16 };
22 17
23 cpu1: cpu@1 { 18 cpu1: cpu@1 {
24 compatible = "arm,cort 19 compatible = "arm,cortex-a53";
25 device_type = "cpu"; 20 device_type = "cpu";
26 reg = <1>; 21 reg = <1>;
27 enable-method = "psci" 22 enable-method = "psci";
28 clocks = <&ccu CLK_CPU <<
29 clock-latency-ns = <24 <<
30 #cooling-cells = <2>; <<
31 }; 23 };
32 24
33 cpu2: cpu@2 { 25 cpu2: cpu@2 {
34 compatible = "arm,cort 26 compatible = "arm,cortex-a53";
35 device_type = "cpu"; 27 device_type = "cpu";
36 reg = <2>; 28 reg = <2>;
37 enable-method = "psci" 29 enable-method = "psci";
38 clocks = <&ccu CLK_CPU <<
39 clock-latency-ns = <24 <<
40 #cooling-cells = <2>; <<
41 }; 30 };
42 31
43 cpu3: cpu@3 { 32 cpu3: cpu@3 {
44 compatible = "arm,cort 33 compatible = "arm,cortex-a53";
45 device_type = "cpu"; 34 device_type = "cpu";
46 reg = <3>; 35 reg = <3>;
47 enable-method = "psci" 36 enable-method = "psci";
48 clocks = <&ccu CLK_CPU <<
49 clock-latency-ns = <24 <<
50 #cooling-cells = <2>; <<
51 }; 37 };
52 }; 38 };
53 39
54 pmu { 40 pmu {
55 compatible = "arm,cortex-a53-p 41 compatible = "arm,cortex-a53-pmu";
56 interrupts = <GIC_SPI 116 IRQ_ 42 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 117 IRQ_ 43 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 118 IRQ_ 44 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 119 IRQ_ 45 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
60 interrupt-affinity = <&cpu0>, 46 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
61 }; 47 };
62 48
63 psci { 49 psci {
64 compatible = "arm,psci-0.2"; 50 compatible = "arm,psci-0.2";
65 method = "smc"; 51 method = "smc";
66 }; 52 };
67 53
68 timer { 54 timer {
69 compatible = "arm,armv8-timer" 55 compatible = "arm,armv8-timer";
70 arm,no-tick-in-suspend; <<
71 interrupts = <GIC_PPI 13 56 interrupts = <GIC_PPI 13
72 (GIC_CPU_MASK_ 57 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 58 <GIC_PPI 14
74 (GIC_CPU_MASK_ 59 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 11 60 <GIC_PPI 11
76 (GIC_CPU_MASK_ 61 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 62 <GIC_PPI 10
78 (GIC_CPU_MASK_ 63 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
79 }; 64 };
80 65
81 soc { 66 soc {
82 syscon: system-control@1c00000 67 syscon: system-control@1c00000 {
83 compatible = "allwinne 68 compatible = "allwinner,sun50i-h5-system-control";
84 reg = <0x01c00000 0x10 69 reg = <0x01c00000 0x1000>;
85 #address-cells = <1>; 70 #address-cells = <1>;
86 #size-cells = <1>; 71 #size-cells = <1>;
87 ranges; 72 ranges;
88 73
89 sram_c1: sram@18000 { 74 sram_c1: sram@18000 {
90 compatible = " 75 compatible = "mmio-sram";
91 reg = <0x00018 76 reg = <0x00018000 0x1c000>;
92 #address-cells 77 #address-cells = <1>;
93 #size-cells = 78 #size-cells = <1>;
94 ranges = <0 0x 79 ranges = <0 0x00018000 0x1c000>;
95 80
96 ve_sram: sram- 81 ve_sram: sram-section@0 {
97 compat 82 compatible = "allwinner,sun50i-h5-sram-c1",
98 83 "allwinner,sun4i-a10-sram-c1";
99 reg = 84 reg = <0x000000 0x1c000>;
100 }; 85 };
101 }; 86 };
102 }; 87 };
103 88
104 video-codec@1c0e000 { 89 video-codec@1c0e000 {
105 compatible = "allwinne 90 compatible = "allwinner,sun50i-h5-video-engine";
106 reg = <0x01c0e000 0x10 91 reg = <0x01c0e000 0x1000>;
107 clocks = <&ccu CLK_BUS 92 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
108 <&ccu CLK_DRA 93 <&ccu CLK_DRAM_VE>;
109 clock-names = "ahb", " 94 clock-names = "ahb", "mod", "ram";
110 resets = <&ccu RST_BUS 95 resets = <&ccu RST_BUS_VE>;
111 interrupts = <GIC_SPI 96 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
112 allwinner,sram = <&ve_ 97 allwinner,sram = <&ve_sram 1>;
113 }; 98 };
114 99
115 crypto: crypto@1c15000 { 100 crypto: crypto@1c15000 {
116 compatible = "allwinne 101 compatible = "allwinner,sun50i-h5-crypto";
117 reg = <0x01c15000 0x10 102 reg = <0x01c15000 0x1000>;
118 interrupts = <GIC_SPI 103 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&ccu CLK_BUS 104 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
120 clock-names = "bus", " 105 clock-names = "bus", "mod";
121 resets = <&ccu RST_BUS 106 resets = <&ccu RST_BUS_CE>;
122 }; 107 };
123 108
124 deinterlace: deinterlace@1e000 <<
125 compatible = "allwinne <<
126 reg = <0x01e00000 0x20 <<
127 clocks = <&ccu CLK_BUS <<
128 <&ccu CLK_DEI <<
129 <&ccu CLK_DRA <<
130 clock-names = "bus", " <<
131 resets = <&ccu RST_BUS <<
132 interrupts = <GIC_SPI <<
133 interconnects = <&mbus <<
134 interconnect-names = " <<
135 }; <<
136 <<
137 mali: gpu@1e80000 { 109 mali: gpu@1e80000 {
138 compatible = "allwinne 110 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
139 reg = <0x01e80000 0x30 111 reg = <0x01e80000 0x30000>;
140 /* 112 /*
141 * While the datasheet 113 * While the datasheet lists an interrupt for the
142 * PMU, the actual sil 114 * PMU, the actual silicon does not have the PMU
143 * block. Reads all re 115 * block. Reads all return zero, and writes are
144 * ignored. 116 * ignored.
145 */ 117 */
146 interrupts = <GIC_SPI 118 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 119 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 120 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 121 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 122 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 123 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 124 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 125 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 126 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 127 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 128 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-names = "gp" 129 interrupt-names = "gp",
158 "gpm 130 "gpmmu",
159 "pp" 131 "pp",
160 "pp0 132 "pp0",
161 "ppm 133 "ppmmu0",
162 "pp1 134 "pp1",
163 "ppm 135 "ppmmu1",
164 "pp2 136 "pp2",
165 "ppm 137 "ppmmu2",
166 "pp3 138 "pp3",
167 "ppm 139 "ppmmu3";
168 clocks = <&ccu CLK_BUS 140 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
169 clock-names = "bus", " 141 clock-names = "bus", "core";
170 resets = <&ccu RST_BUS 142 resets = <&ccu RST_BUS_GPU>;
171 143
172 assigned-clocks = <&cc 144 assigned-clocks = <&ccu CLK_GPU>;
173 assigned-clock-rates = 145 assigned-clock-rates = <384000000>;
174 }; 146 };
175 147
176 ths: thermal-sensor@1c25000 { 148 ths: thermal-sensor@1c25000 {
177 compatible = "allwinne 149 compatible = "allwinner,sun50i-h5-ths";
178 reg = <0x01c25000 0x40 150 reg = <0x01c25000 0x400>;
179 interrupts = <GIC_SPI 151 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
180 resets = <&ccu RST_BUS 152 resets = <&ccu RST_BUS_THS>;
181 clocks = <&ccu CLK_BUS 153 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
182 clock-names = "bus", " 154 clock-names = "bus", "mod";
183 nvmem-cells = <&ths_ca 155 nvmem-cells = <&ths_calibration>;
184 nvmem-cell-names = "ca 156 nvmem-cell-names = "calibration";
185 #thermal-sensor-cells 157 #thermal-sensor-cells = <1>;
186 }; 158 };
187 }; 159 };
188 160
189 thermal-zones { 161 thermal-zones {
190 cpu_thermal: cpu-thermal { 162 cpu_thermal: cpu-thermal {
191 polling-delay-passive 163 polling-delay-passive = <0>;
192 polling-delay = <0>; 164 polling-delay = <0>;
193 thermal-sensors = <&th 165 thermal-sensors = <&ths 0>;
194 <<
195 trips { <<
196 cpu_hot_trip: <<
197 temper <<
198 hyster <<
199 type = <<
200 }; <<
201 <<
202 cpu_very_hot_t <<
203 temper <<
204 hyster <<
205 type = <<
206 }; <<
207 }; <<
208 <<
209 cooling-maps { <<
210 cpu-hot-limit <<
211 trip = <<
212 coolin <<
213 <<
214 <<
215 <<
216 }; <<
217 }; <<
218 }; 166 };
219 167
220 gpu-thermal { !! 168 gpu_thermal {
221 polling-delay-passive 169 polling-delay-passive = <0>;
222 polling-delay = <0>; 170 polling-delay = <0>;
223 thermal-sensors = <&th 171 thermal-sensors = <&ths 1>;
224 }; 172 };
225 }; 173 };
226 }; 174 };
227 175
228 &ccu { 176 &ccu {
229 compatible = "allwinner,sun50i-h5-ccu" 177 compatible = "allwinner,sun50i-h5-ccu";
230 }; 178 };
231 179
232 &display_clocks { 180 &display_clocks {
233 compatible = "allwinner,sun50i-h5-de2- 181 compatible = "allwinner,sun50i-h5-de2-clk";
234 }; <<
235 <<
236 &mbus { <<
237 compatible = "allwinner,sun50i-h5-mbus <<
238 }; 182 };
239 183
240 &mmc0 { 184 &mmc0 {
241 compatible = "allwinner,sun50i-h5-mmc" 185 compatible = "allwinner,sun50i-h5-mmc",
242 "allwinner,sun50i-a64-mmc 186 "allwinner,sun50i-a64-mmc";
243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CL 187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
244 clock-names = "ahb", "mmc"; 188 clock-names = "ahb", "mmc";
245 }; 189 };
246 190
247 &mmc1 { 191 &mmc1 {
248 compatible = "allwinner,sun50i-h5-mmc" 192 compatible = "allwinner,sun50i-h5-mmc",
249 "allwinner,sun50i-a64-mmc 193 "allwinner,sun50i-a64-mmc";
250 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CL 194 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
251 clock-names = "ahb", "mmc"; 195 clock-names = "ahb", "mmc";
252 }; 196 };
253 197
254 &mmc2 { 198 &mmc2 {
255 compatible = "allwinner,sun50i-h5-emmc 199 compatible = "allwinner,sun50i-h5-emmc",
256 "allwinner,sun50i-a64-emm 200 "allwinner,sun50i-a64-emmc";
257 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CL 201 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
258 clock-names = "ahb", "mmc"; 202 clock-names = "ahb", "mmc";
259 }; 203 };
260 204
261 &pio { 205 &pio {
262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVE 206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 17 IRQ_TYPE_LEVE 207 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 23 IRQ_TYPE_LEVE 208 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
265 compatible = "allwinner,sun50i-h5-pinc 209 compatible = "allwinner,sun50i-h5-pinctrl";
266 }; 210 };
267 211
268 &rtc { 212 &rtc {
269 compatible = "allwinner,sun50i-h5-rtc" 213 compatible = "allwinner,sun50i-h5-rtc";
270 }; 214 };
271 215
272 &sid { 216 &sid {
273 compatible = "allwinner,sun50i-h5-sid" 217 compatible = "allwinner,sun50i-h5-sid";
274 }; 218 };
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