1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright Altera Corporation (C) 2015. All 3 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h 7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h> 9 #include <dt-bindings/clock/stratix10-clock.h>
10 10
11 / { 11 / {
12 compatible = "altr,socfpga-stratix10"; 12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 reserved-memory { 16 reserved-memory {
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 ranges; 19 ranges;
20 20
21 service_reserved: svcbuffer@0 21 service_reserved: svcbuffer@0 {
22 compatible = "shared-d 22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1 23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>; 24 alignment = <0x1000>;
25 no-map; 25 no-map;
26 }; 26 };
27 }; 27 };
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu0: cpu@0 { 33 cpu0: cpu@0 {
34 compatible = "arm,cort 34 compatible = "arm,cortex-a53";
35 device_type = "cpu"; 35 device_type = "cpu";
36 enable-method = "psci" 36 enable-method = "psci";
37 next-level-cache = <&l 37 next-level-cache = <&l2_shared>;
38 reg = <0x0>; 38 reg = <0x0>;
39 }; 39 };
40 40
41 cpu1: cpu@1 { 41 cpu1: cpu@1 {
42 compatible = "arm,cort 42 compatible = "arm,cortex-a53";
43 device_type = "cpu"; 43 device_type = "cpu";
44 enable-method = "psci" 44 enable-method = "psci";
45 next-level-cache = <&l 45 next-level-cache = <&l2_shared>;
46 reg = <0x1>; 46 reg = <0x1>;
47 }; 47 };
48 48
49 cpu2: cpu@2 { 49 cpu2: cpu@2 {
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 51 device_type = "cpu";
52 enable-method = "psci" 52 enable-method = "psci";
53 next-level-cache = <&l 53 next-level-cache = <&l2_shared>;
54 reg = <0x2>; 54 reg = <0x2>;
55 }; 55 };
56 56
57 cpu3: cpu@3 { 57 cpu3: cpu@3 {
58 compatible = "arm,cort 58 compatible = "arm,cortex-a53";
59 device_type = "cpu"; 59 device_type = "cpu";
60 enable-method = "psci" 60 enable-method = "psci";
61 next-level-cache = <&l 61 next-level-cache = <&l2_shared>;
62 reg = <0x3>; 62 reg = <0x3>;
63 }; 63 };
64 64
65 l2_shared: cache { 65 l2_shared: cache {
66 compatible = "cache"; 66 compatible = "cache";
67 cache-level = <2>; 67 cache-level = <2>;
68 cache-unified; 68 cache-unified;
69 }; 69 };
70 }; 70 };
71 71
72 firmware { 72 firmware {
73 svc { 73 svc {
74 compatible = "intel,st 74 compatible = "intel,stratix10-svc";
75 method = "smc"; 75 method = "smc";
76 memory-region = <&serv 76 memory-region = <&service_reserved>;
77 77
78 fpga_mgr: fpga-mgr { 78 fpga_mgr: fpga-mgr {
79 compatible = " 79 compatible = "intel,stratix10-soc-fpga-mgr";
80 }; 80 };
81 }; 81 };
82 }; 82 };
83 83
84 fpga-region { 84 fpga-region {
85 compatible = "fpga-region"; 85 compatible = "fpga-region";
86 #address-cells = <0x2>; 86 #address-cells = <0x2>;
87 #size-cells = <0x2>; 87 #size-cells = <0x2>;
88 fpga-mgr = <&fpga_mgr>; 88 fpga-mgr = <&fpga_mgr>;
89 }; 89 };
90 90
91 pmu { 91 pmu {
92 compatible = "arm,cortex-a53-p 92 compatible = "arm,cortex-a53-pmu";
93 interrupts = <0 170 4>, 93 interrupts = <0 170 4>,
94 <0 171 4>, 94 <0 171 4>,
95 <0 172 4>, 95 <0 172 4>,
96 <0 173 4>; 96 <0 173 4>;
97 interrupt-affinity = <&cpu0>, 97 interrupt-affinity = <&cpu0>,
98 <&cpu1>, 98 <&cpu1>,
99 <&cpu2>, 99 <&cpu2>,
100 <&cpu3>; 100 <&cpu3>;
101 interrupt-parent = <&intc>; 101 interrupt-parent = <&intc>;
102 }; 102 };
103 103
104 psci { 104 psci {
105 compatible = "arm,psci-0.2"; 105 compatible = "arm,psci-0.2";
106 method = "smc"; 106 method = "smc";
107 }; 107 };
108 108
109 /* Local timer */ 109 /* Local timer */
110 timer { 110 timer {
111 compatible = "arm,armv8-timer" 111 compatible = "arm,armv8-timer";
112 interrupts = <1 13 0xf08>, 112 interrupts = <1 13 0xf08>,
113 <1 14 0xf08>, 113 <1 14 0xf08>,
114 <1 11 0xf08>, 114 <1 11 0xf08>,
115 <1 10 0xf08>; 115 <1 10 0xf08>;
116 interrupt-parent = <&intc>; 116 interrupt-parent = <&intc>;
117 }; 117 };
118 118
119 intc: interrupt-controller@fffc1000 { 119 intc: interrupt-controller@fffc1000 {
120 compatible = "arm,gic-400", "a 120 compatible = "arm,gic-400", "arm,cortex-a15-gic";
121 #interrupt-cells = <3>; 121 #interrupt-cells = <3>;
122 interrupt-controller; 122 interrupt-controller;
123 reg = <0x0 0xfffc1000 0x0 0x10 123 reg = <0x0 0xfffc1000 0x0 0x1000>,
124 <0x0 0xfffc2000 0x0 0x20 124 <0x0 0xfffc2000 0x0 0x2000>,
125 <0x0 0xfffc4000 0x0 0x20 125 <0x0 0xfffc4000 0x0 0x2000>,
126 <0x0 0xfffc6000 0x0 0x20 126 <0x0 0xfffc6000 0x0 0x2000>;
127 }; 127 };
128 128
129 clocks { 129 clocks {
130 cb_intosc_hs_div2_clk: cb-into 130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
131 #clock-cells = <0>; 131 #clock-cells = <0>;
132 compatible = "fixed-cl 132 compatible = "fixed-clock";
133 }; 133 };
134 134
135 cb_intosc_ls_clk: cb-intosc-ls 135 cb_intosc_ls_clk: cb-intosc-ls-clk {
136 #clock-cells = <0>; 136 #clock-cells = <0>;
137 compatible = "fixed-cl 137 compatible = "fixed-clock";
138 }; 138 };
139 139
140 f2s_free_clk: f2s-free-clk { 140 f2s_free_clk: f2s-free-clk {
141 #clock-cells = <0>; 141 #clock-cells = <0>;
142 compatible = "fixed-cl 142 compatible = "fixed-clock";
143 }; 143 };
144 144
145 osc1: osc1 { 145 osc1: osc1 {
146 #clock-cells = <0>; 146 #clock-cells = <0>;
147 compatible = "fixed-cl 147 compatible = "fixed-clock";
148 }; 148 };
149 149
150 qspi_clk: qspi-clk { 150 qspi_clk: qspi-clk {
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 compatible = "fixed-cl 152 compatible = "fixed-clock";
153 clock-frequency = <200 153 clock-frequency = <200000000>;
154 }; 154 };
155 }; 155 };
156 156
157 soc@0 { 157 soc@0 {
158 #address-cells = <1>; 158 #address-cells = <1>;
159 #size-cells = <1>; 159 #size-cells = <1>;
160 compatible = "simple-bus"; 160 compatible = "simple-bus";
161 device_type = "soc"; 161 device_type = "soc";
162 interrupt-parent = <&intc>; 162 interrupt-parent = <&intc>;
163 ranges = <0 0 0 0xffffffff>; 163 ranges = <0 0 0 0xffffffff>;
164 164
165 clkmgr: clock-controller@ffd10 165 clkmgr: clock-controller@ffd10000 {
166 compatible = "intel,st 166 compatible = "intel,stratix10-clkmgr";
167 reg = <0xffd10000 0x10 167 reg = <0xffd10000 0x1000>;
168 #clock-cells = <1>; 168 #clock-cells = <1>;
169 }; 169 };
170 170
171 gmac0: ethernet@ff800000 { 171 gmac0: ethernet@ff800000 {
172 compatible = "altr,soc 172 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
173 reg = <0xff800000 0x20 173 reg = <0xff800000 0x2000>;
174 interrupts = <0 90 4>; 174 interrupts = <0 90 4>;
175 interrupt-names = "mac 175 interrupt-names = "macirq";
176 mac-address = [00 00 0 176 mac-address = [00 00 00 00 00 00];
177 resets = <&rst EMAC0_R 177 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
178 reset-names = "stmmace 178 reset-names = "stmmaceth", "ahb";
179 clocks = <&clkmgr STRA 179 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
180 clock-names = "stmmace 180 clock-names = "stmmaceth", "ptp_ref";
181 tx-fifo-depth = <16384 181 tx-fifo-depth = <16384>;
182 rx-fifo-depth = <16384 182 rx-fifo-depth = <16384>;
183 snps,multicast-filter- 183 snps,multicast-filter-bins = <256>;
184 iommus = <&smmu 1>; 184 iommus = <&smmu 1>;
185 altr,sysmgr-syscon = < 185 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
186 status = "disabled"; 186 status = "disabled";
187 }; 187 };
188 188
189 gmac1: ethernet@ff802000 { 189 gmac1: ethernet@ff802000 {
190 compatible = "altr,soc 190 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
191 reg = <0xff802000 0x20 191 reg = <0xff802000 0x2000>;
192 interrupts = <0 91 4>; 192 interrupts = <0 91 4>;
193 interrupt-names = "mac 193 interrupt-names = "macirq";
194 mac-address = [00 00 0 194 mac-address = [00 00 00 00 00 00];
195 resets = <&rst EMAC1_R 195 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
196 reset-names = "stmmace 196 reset-names = "stmmaceth", "ahb";
197 clocks = <&clkmgr STRA 197 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
198 clock-names = "stmmace 198 clock-names = "stmmaceth", "ptp_ref";
199 tx-fifo-depth = <16384 199 tx-fifo-depth = <16384>;
200 rx-fifo-depth = <16384 200 rx-fifo-depth = <16384>;
201 snps,multicast-filter- 201 snps,multicast-filter-bins = <256>;
202 iommus = <&smmu 2>; 202 iommus = <&smmu 2>;
203 altr,sysmgr-syscon = < 203 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
204 status = "disabled"; 204 status = "disabled";
205 }; 205 };
206 206
207 gmac2: ethernet@ff804000 { 207 gmac2: ethernet@ff804000 {
208 compatible = "altr,soc 208 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
209 reg = <0xff804000 0x20 209 reg = <0xff804000 0x2000>;
210 interrupts = <0 92 4>; 210 interrupts = <0 92 4>;
211 interrupt-names = "mac 211 interrupt-names = "macirq";
212 mac-address = [00 00 0 212 mac-address = [00 00 00 00 00 00];
213 resets = <&rst EMAC2_R 213 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
214 reset-names = "stmmace 214 reset-names = "stmmaceth", "ahb";
215 clocks = <&clkmgr STRA 215 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
216 clock-names = "stmmace 216 clock-names = "stmmaceth", "ptp_ref";
217 tx-fifo-depth = <16384 217 tx-fifo-depth = <16384>;
218 rx-fifo-depth = <16384 218 rx-fifo-depth = <16384>;
219 snps,multicast-filter- 219 snps,multicast-filter-bins = <256>;
220 iommus = <&smmu 3>; 220 iommus = <&smmu 3>;
221 altr,sysmgr-syscon = < 221 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
222 status = "disabled"; 222 status = "disabled";
223 }; 223 };
224 224
225 gpio0: gpio@ffc03200 { 225 gpio0: gpio@ffc03200 {
226 #address-cells = <1>; 226 #address-cells = <1>;
227 #size-cells = <0>; 227 #size-cells = <0>;
228 compatible = "snps,dw- 228 compatible = "snps,dw-apb-gpio";
229 reg = <0xffc03200 0x10 229 reg = <0xffc03200 0x100>;
230 resets = <&rst GPIO0_R 230 resets = <&rst GPIO0_RESET>;
231 status = "disabled"; 231 status = "disabled";
232 232
233 porta: gpio-controller 233 porta: gpio-controller@0 {
234 compatible = " 234 compatible = "snps,dw-apb-gpio-port";
235 gpio-controlle 235 gpio-controller;
236 #gpio-cells = 236 #gpio-cells = <2>;
237 ngpios = <24>; 237 ngpios = <24>;
238 reg = <0>; 238 reg = <0>;
239 interrupt-cont 239 interrupt-controller;
240 #interrupt-cel 240 #interrupt-cells = <2>;
241 interrupts = < 241 interrupts = <0 110 4>;
242 }; 242 };
243 }; 243 };
244 244
245 gpio1: gpio@ffc03300 { 245 gpio1: gpio@ffc03300 {
246 #address-cells = <1>; 246 #address-cells = <1>;
247 #size-cells = <0>; 247 #size-cells = <0>;
248 compatible = "snps,dw- 248 compatible = "snps,dw-apb-gpio";
249 reg = <0xffc03300 0x10 249 reg = <0xffc03300 0x100>;
250 resets = <&rst GPIO1_R 250 resets = <&rst GPIO1_RESET>;
251 status = "disabled"; 251 status = "disabled";
252 252
253 portb: gpio-controller 253 portb: gpio-controller@0 {
254 compatible = " 254 compatible = "snps,dw-apb-gpio-port";
255 gpio-controlle 255 gpio-controller;
256 #gpio-cells = 256 #gpio-cells = <2>;
257 ngpios = <24>; 257 ngpios = <24>;
258 reg = <0>; 258 reg = <0>;
259 interrupt-cont 259 interrupt-controller;
260 #interrupt-cel 260 #interrupt-cells = <2>;
261 interrupts = < 261 interrupts = <0 111 4>;
262 }; 262 };
263 }; 263 };
264 264
265 i2c0: i2c@ffc02800 { 265 i2c0: i2c@ffc02800 {
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <0>; 267 #size-cells = <0>;
268 compatible = "snps,des 268 compatible = "snps,designware-i2c";
269 reg = <0xffc02800 0x10 269 reg = <0xffc02800 0x100>;
270 interrupts = <0 103 4> 270 interrupts = <0 103 4>;
271 resets = <&rst I2C0_RE 271 resets = <&rst I2C0_RESET>;
272 clocks = <&clkmgr STRA 272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
273 status = "disabled"; 273 status = "disabled";
274 }; 274 };
275 275
276 i2c1: i2c@ffc02900 { 276 i2c1: i2c@ffc02900 {
277 #address-cells = <1>; 277 #address-cells = <1>;
278 #size-cells = <0>; 278 #size-cells = <0>;
279 compatible = "snps,des 279 compatible = "snps,designware-i2c";
280 reg = <0xffc02900 0x10 280 reg = <0xffc02900 0x100>;
281 interrupts = <0 104 4> 281 interrupts = <0 104 4>;
282 resets = <&rst I2C1_RE 282 resets = <&rst I2C1_RESET>;
283 clocks = <&clkmgr STRA 283 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
284 status = "disabled"; 284 status = "disabled";
285 }; 285 };
286 286
287 i2c2: i2c@ffc02a00 { 287 i2c2: i2c@ffc02a00 {
288 #address-cells = <1>; 288 #address-cells = <1>;
289 #size-cells = <0>; 289 #size-cells = <0>;
290 compatible = "snps,des 290 compatible = "snps,designware-i2c";
291 reg = <0xffc02a00 0x10 291 reg = <0xffc02a00 0x100>;
292 interrupts = <0 105 4> 292 interrupts = <0 105 4>;
293 resets = <&rst I2C2_RE 293 resets = <&rst I2C2_RESET>;
294 clocks = <&clkmgr STRA 294 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
295 status = "disabled"; 295 status = "disabled";
296 }; 296 };
297 297
298 i2c3: i2c@ffc02b00 { 298 i2c3: i2c@ffc02b00 {
299 #address-cells = <1>; 299 #address-cells = <1>;
300 #size-cells = <0>; 300 #size-cells = <0>;
301 compatible = "snps,des 301 compatible = "snps,designware-i2c";
302 reg = <0xffc02b00 0x10 302 reg = <0xffc02b00 0x100>;
303 interrupts = <0 106 4> 303 interrupts = <0 106 4>;
304 resets = <&rst I2C3_RE 304 resets = <&rst I2C3_RESET>;
305 clocks = <&clkmgr STRA 305 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
306 status = "disabled"; 306 status = "disabled";
307 }; 307 };
308 308
309 i2c4: i2c@ffc02c00 { 309 i2c4: i2c@ffc02c00 {
310 #address-cells = <1>; 310 #address-cells = <1>;
311 #size-cells = <0>; 311 #size-cells = <0>;
312 compatible = "snps,des 312 compatible = "snps,designware-i2c";
313 reg = <0xffc02c00 0x10 313 reg = <0xffc02c00 0x100>;
314 interrupts = <0 107 4> 314 interrupts = <0 107 4>;
315 resets = <&rst I2C4_RE 315 resets = <&rst I2C4_RESET>;
316 clocks = <&clkmgr STRA 316 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
317 status = "disabled"; 317 status = "disabled";
318 }; 318 };
319 319
320 mmc: mmc@ff808000 { 320 mmc: mmc@ff808000 {
321 #address-cells = <1>; 321 #address-cells = <1>;
322 #size-cells = <0>; 322 #size-cells = <0>;
323 compatible = "altr,soc 323 compatible = "altr,socfpga-dw-mshc";
324 reg = <0xff808000 0x10 324 reg = <0xff808000 0x1000>;
325 interrupts = <0 96 4>; 325 interrupts = <0 96 4>;
326 fifo-depth = <0x400>; 326 fifo-depth = <0x400>;
327 resets = <&rst SDMMC_R 327 resets = <&rst SDMMC_RESET>;
328 reset-names = "reset"; 328 reset-names = "reset";
329 clocks = <&clkmgr STRA 329 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
330 <&clkmgr STRA 330 <&clkmgr STRATIX10_SDMMC_CLK>;
331 clock-names = "biu", " 331 clock-names = "biu", "ciu";
332 iommus = <&smmu 5>; 332 iommus = <&smmu 5>;
333 altr,sysmgr-syscon = < 333 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
334 status = "disabled"; 334 status = "disabled";
335 }; 335 };
336 336
337 nand: nand-controller@ffb90000 337 nand: nand-controller@ffb90000 {
338 #address-cells = <1>; 338 #address-cells = <1>;
339 #size-cells = <0>; 339 #size-cells = <0>;
340 compatible = "altr,soc 340 compatible = "altr,socfpga-denali-nand";
341 reg = <0xffb90000 0x10 341 reg = <0xffb90000 0x10000>,
342 <0xffb80000 0x10 342 <0xffb80000 0x1000>;
343 reg-names = "nand_data 343 reg-names = "nand_data", "denali_reg";
344 interrupts = <0 97 4>; 344 interrupts = <0 97 4>;
345 clocks = <&clkmgr STRA 345 clocks = <&clkmgr STRATIX10_NAND_CLK>,
346 <&clkmgr STRA 346 <&clkmgr STRATIX10_NAND_X_CLK>,
347 <&clkmgr STRA 347 <&clkmgr STRATIX10_NAND_ECC_CLK>;
348 clock-names = "nand", 348 clock-names = "nand", "nand_x", "ecc";
349 resets = <&rst NAND_RE 349 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
350 status = "disabled"; 350 status = "disabled";
351 }; 351 };
352 352
353 ocram: sram@ffe00000 { 353 ocram: sram@ffe00000 {
354 compatible = "mmio-sra 354 compatible = "mmio-sram";
355 reg = <0xffe00000 0x10 355 reg = <0xffe00000 0x100000>;
356 #address-cells = <1>; 356 #address-cells = <1>;
357 #size-cells = <1>; 357 #size-cells = <1>;
358 ranges = <0 0xffe00000 358 ranges = <0 0xffe00000 0x100000>;
359 }; 359 };
360 360
361 pdma: dma-controller@ffda0000 361 pdma: dma-controller@ffda0000 {
362 compatible = "arm,pl33 362 compatible = "arm,pl330", "arm,primecell";
363 reg = <0xffda0000 0x10 363 reg = <0xffda0000 0x1000>;
364 interrupts = <0 81 4>, 364 interrupts = <0 81 4>,
365 <0 82 4>, 365 <0 82 4>,
366 <0 83 4>, 366 <0 83 4>,
367 <0 84 4>, 367 <0 84 4>,
368 <0 85 4>, 368 <0 85 4>,
369 <0 86 4>, 369 <0 86 4>,
370 <0 87 4>, 370 <0 87 4>,
371 <0 88 4>, 371 <0 88 4>,
372 <0 89 4>; 372 <0 89 4>;
373 #dma-cells = <1>; 373 #dma-cells = <1>;
374 clocks = <&clkmgr STRA 374 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
375 clock-names = "apb_pcl 375 clock-names = "apb_pclk";
376 resets = <&rst DMA_RES 376 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
377 reset-names = "dma", " 377 reset-names = "dma", "dma-ocp";
378 }; 378 };
379 379
380 pinctrl0: pinctrl@ffd13000 { 380 pinctrl0: pinctrl@ffd13000 {
381 compatible = "pinctrl- 381 compatible = "pinctrl-single";
382 reg = <0xffd13000 0xA0 382 reg = <0xffd13000 0xA0>;
383 #pinctrl-cells = <1>; 383 #pinctrl-cells = <1>;
384 pinctrl-single,registe 384 pinctrl-single,register-width = <32>;
385 pinctrl-single,functio 385 pinctrl-single,function-mask = <0x0000000f>;
386 }; 386 };
387 387
388 pinctrl1: pinctrl@ffd13100 { 388 pinctrl1: pinctrl@ffd13100 {
389 compatible = "pinctrl- 389 compatible = "pinctrl-single";
390 reg = <0xffd13100 0x20 390 reg = <0xffd13100 0x20>;
391 #pinctrl-cells = <1>; 391 #pinctrl-cells = <1>;
392 pinctrl-single,registe 392 pinctrl-single,register-width = <32>;
393 pinctrl-single,functio 393 pinctrl-single,function-mask = <0x0000000f>;
394 }; 394 };
395 395
396 rst: rstmgr@ffd11000 { 396 rst: rstmgr@ffd11000 {
397 #reset-cells = <1>; 397 #reset-cells = <1>;
398 compatible = "altr,str 398 compatible = "altr,stratix10-rst-mgr";
399 reg = <0xffd11000 0x10 399 reg = <0xffd11000 0x1000>;
400 }; 400 };
401 401
402 smmu: iommu@fa000000 { 402 smmu: iommu@fa000000 {
403 compatible = "arm,mmu- 403 compatible = "arm,mmu-500", "arm,smmu-v2";
404 reg = <0xfa000000 0x40 404 reg = <0xfa000000 0x40000>;
405 #global-interrupts = < 405 #global-interrupts = <2>;
406 #iommu-cells = <1>; 406 #iommu-cells = <1>;
407 clocks = <&clkmgr STRA 407 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
408 clock-names = "iommu"; 408 clock-names = "iommu";
409 interrupt-parent = <&i 409 interrupt-parent = <&intc>;
410 interrupts = <0 128 4> 410 interrupts = <0 128 4>, /* Global Secure Fault */
411 <0 129 4>, /* 411 <0 129 4>, /* Global Non-secure Fault */
412 /* Non-secure 412 /* Non-secure Context Interrupts (32) */
413 <0 138 4>, <0 413 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
414 <0 142 4>, <0 414 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
415 <0 146 4>, <0 415 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
416 <0 150 4>, <0 416 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
417 <0 154 4>, <0 417 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
418 <0 158 4>, <0 418 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
419 <0 162 4>, <0 419 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
420 <0 166 4>, <0 420 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
421 stream-match-mask = <0 421 stream-match-mask = <0x7ff0>;
422 status = "disabled"; 422 status = "disabled";
423 }; 423 };
424 424
425 spi0: spi@ffda4000 { 425 spi0: spi@ffda4000 {
426 compatible = "snps,dw- 426 compatible = "snps,dw-apb-ssi";
427 #address-cells = <1>; 427 #address-cells = <1>;
428 #size-cells = <0>; 428 #size-cells = <0>;
429 reg = <0xffda4000 0x10 429 reg = <0xffda4000 0x1000>;
430 interrupts = <0 99 4>; 430 interrupts = <0 99 4>;
431 resets = <&rst SPIM0_R 431 resets = <&rst SPIM0_RESET>;
432 reset-names = "spi"; 432 reset-names = "spi";
433 reg-io-width = <4>; 433 reg-io-width = <4>;
434 num-cs = <4>; 434 num-cs = <4>;
435 clocks = <&clkmgr STRA 435 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
436 status = "disabled"; 436 status = "disabled";
437 }; 437 };
438 438
439 spi1: spi@ffda5000 { 439 spi1: spi@ffda5000 {
440 compatible = "snps,dw- 440 compatible = "snps,dw-apb-ssi";
441 #address-cells = <1>; 441 #address-cells = <1>;
442 #size-cells = <0>; 442 #size-cells = <0>;
443 reg = <0xffda5000 0x10 443 reg = <0xffda5000 0x1000>;
444 interrupts = <0 100 4> 444 interrupts = <0 100 4>;
445 resets = <&rst SPIM1_R 445 resets = <&rst SPIM1_RESET>;
446 reset-names = "spi"; 446 reset-names = "spi";
447 reg-io-width = <4>; 447 reg-io-width = <4>;
448 num-cs = <4>; 448 num-cs = <4>;
449 clocks = <&clkmgr STRA 449 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
450 status = "disabled"; 450 status = "disabled";
451 }; 451 };
452 452
453 sysmgr: sysmgr@ffd12000 { 453 sysmgr: sysmgr@ffd12000 {
454 compatible = "altr,sys 454 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
455 reg = <0xffd12000 0x22 455 reg = <0xffd12000 0x228>;
456 }; 456 };
457 457
458 timer0: timer0@ffc03000 { 458 timer0: timer0@ffc03000 {
459 compatible = "snps,dw- 459 compatible = "snps,dw-apb-timer";
460 interrupts = <0 113 4> 460 interrupts = <0 113 4>;
461 reg = <0xffc03000 0x10 461 reg = <0xffc03000 0x100>;
462 clocks = <&clkmgr STRA 462 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
463 clock-names = "timer"; 463 clock-names = "timer";
464 }; 464 };
465 465
466 timer1: timer1@ffc03100 { 466 timer1: timer1@ffc03100 {
467 compatible = "snps,dw- 467 compatible = "snps,dw-apb-timer";
468 interrupts = <0 114 4> 468 interrupts = <0 114 4>;
469 reg = <0xffc03100 0x10 469 reg = <0xffc03100 0x100>;
470 clocks = <&clkmgr STRA 470 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
471 clock-names = "timer"; 471 clock-names = "timer";
472 }; 472 };
473 473
474 timer2: timer2@ffd00000 { 474 timer2: timer2@ffd00000 {
475 compatible = "snps,dw- 475 compatible = "snps,dw-apb-timer";
476 interrupts = <0 115 4> 476 interrupts = <0 115 4>;
477 reg = <0xffd00000 0x10 477 reg = <0xffd00000 0x100>;
478 clocks = <&clkmgr STRA 478 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
479 clock-names = "timer"; 479 clock-names = "timer";
480 }; 480 };
481 481
482 timer3: timer3@ffd00100 { 482 timer3: timer3@ffd00100 {
483 compatible = "snps,dw- 483 compatible = "snps,dw-apb-timer";
484 interrupts = <0 116 4> 484 interrupts = <0 116 4>;
485 reg = <0xffd00100 0x10 485 reg = <0xffd00100 0x100>;
486 clocks = <&clkmgr STRA 486 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
487 clock-names = "timer"; 487 clock-names = "timer";
488 }; 488 };
489 489
490 uart0: serial@ffc02000 { 490 uart0: serial@ffc02000 {
491 compatible = "snps,dw- 491 compatible = "snps,dw-apb-uart";
492 reg = <0xffc02000 0x10 492 reg = <0xffc02000 0x100>;
493 interrupts = <0 108 4> 493 interrupts = <0 108 4>;
494 reg-shift = <2>; 494 reg-shift = <2>;
495 reg-io-width = <4>; 495 reg-io-width = <4>;
496 resets = <&rst UART0_R 496 resets = <&rst UART0_RESET>;
497 clocks = <&clkmgr STRA 497 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
498 status = "disabled"; 498 status = "disabled";
499 }; 499 };
500 500
501 uart1: serial@ffc02100 { 501 uart1: serial@ffc02100 {
502 compatible = "snps,dw- 502 compatible = "snps,dw-apb-uart";
503 reg = <0xffc02100 0x10 503 reg = <0xffc02100 0x100>;
504 interrupts = <0 109 4> 504 interrupts = <0 109 4>;
505 reg-shift = <2>; 505 reg-shift = <2>;
506 reg-io-width = <4>; 506 reg-io-width = <4>;
507 resets = <&rst UART1_R 507 resets = <&rst UART1_RESET>;
508 clocks = <&clkmgr STRA 508 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
509 status = "disabled"; 509 status = "disabled";
510 }; 510 };
511 511
512 usb0: usb@ffb00000 { 512 usb0: usb@ffb00000 {
513 compatible = "snps,dwc 513 compatible = "snps,dwc2";
514 reg = <0xffb00000 0x40 514 reg = <0xffb00000 0x40000>;
515 interrupts = <0 93 4>; 515 interrupts = <0 93 4>;
516 phys = <&usbphy0>; 516 phys = <&usbphy0>;
517 phy-names = "usb2-phy" 517 phy-names = "usb2-phy";
518 resets = <&rst USB0_RE 518 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
519 reset-names = "dwc2", 519 reset-names = "dwc2", "dwc2-ecc";
520 clocks = <&clkmgr STRA 520 clocks = <&clkmgr STRATIX10_USB_CLK>;
521 clock-names = "otg"; 521 clock-names = "otg";
522 iommus = <&smmu 6>; 522 iommus = <&smmu 6>;
523 status = "disabled"; 523 status = "disabled";
524 }; 524 };
525 525
526 usb1: usb@ffb40000 { 526 usb1: usb@ffb40000 {
527 compatible = "snps,dwc 527 compatible = "snps,dwc2";
528 reg = <0xffb40000 0x40 528 reg = <0xffb40000 0x40000>;
529 interrupts = <0 94 4>; 529 interrupts = <0 94 4>;
530 phys = <&usbphy0>; 530 phys = <&usbphy0>;
531 phy-names = "usb2-phy" 531 phy-names = "usb2-phy";
532 resets = <&rst USB1_RE 532 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
533 reset-names = "dwc2", 533 reset-names = "dwc2", "dwc2-ecc";
534 clocks = <&clkmgr STRA 534 clocks = <&clkmgr STRATIX10_USB_CLK>;
535 clock-names = "otg"; 535 clock-names = "otg";
536 iommus = <&smmu 7>; 536 iommus = <&smmu 7>;
537 status = "disabled"; 537 status = "disabled";
538 }; 538 };
539 539
540 watchdog0: watchdog@ffd00200 { 540 watchdog0: watchdog@ffd00200 {
541 compatible = "snps,dw- 541 compatible = "snps,dw-wdt";
542 reg = <0xffd00200 0x10 542 reg = <0xffd00200 0x100>;
543 interrupts = <0 117 4> 543 interrupts = <0 117 4>;
544 resets = <&rst WATCHDO 544 resets = <&rst WATCHDOG0_RESET>;
545 clocks = <&clkmgr STRA 545 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
546 status = "disabled"; 546 status = "disabled";
547 }; 547 };
548 548
549 watchdog1: watchdog@ffd00300 { 549 watchdog1: watchdog@ffd00300 {
550 compatible = "snps,dw- 550 compatible = "snps,dw-wdt";
551 reg = <0xffd00300 0x10 551 reg = <0xffd00300 0x100>;
552 interrupts = <0 118 4> 552 interrupts = <0 118 4>;
553 resets = <&rst WATCHDO 553 resets = <&rst WATCHDOG1_RESET>;
554 clocks = <&clkmgr STRA 554 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
555 status = "disabled"; 555 status = "disabled";
556 }; 556 };
557 557
558 watchdog2: watchdog@ffd00400 { 558 watchdog2: watchdog@ffd00400 {
559 compatible = "snps,dw- 559 compatible = "snps,dw-wdt";
560 reg = <0xffd00400 0x10 560 reg = <0xffd00400 0x100>;
561 interrupts = <0 125 4> 561 interrupts = <0 125 4>;
562 resets = <&rst WATCHDO 562 resets = <&rst WATCHDOG2_RESET>;
563 clocks = <&clkmgr STRA 563 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
564 status = "disabled"; 564 status = "disabled";
565 }; 565 };
566 566
567 watchdog3: watchdog@ffd00500 { 567 watchdog3: watchdog@ffd00500 {
568 compatible = "snps,dw- 568 compatible = "snps,dw-wdt";
569 reg = <0xffd00500 0x10 569 reg = <0xffd00500 0x100>;
570 interrupts = <0 126 4> 570 interrupts = <0 126 4>;
571 resets = <&rst WATCHDO 571 resets = <&rst WATCHDOG3_RESET>;
572 clocks = <&clkmgr STRA 572 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
573 status = "disabled"; 573 status = "disabled";
574 }; 574 };
575 575
576 sdr: sdr@f8011100 { 576 sdr: sdr@f8011100 {
577 compatible = "altr,sdr 577 compatible = "altr,sdr-ctl", "syscon";
578 reg = <0xf8011100 0xc0 578 reg = <0xf8011100 0xc0>;
579 }; 579 };
580 580
581 eccmgr { 581 eccmgr {
582 compatible = "altr,soc 582 compatible = "altr,socfpga-s10-ecc-manager",
583 "altr,soc 583 "altr,socfpga-a10-ecc-manager";
584 altr,sysmgr-syscon = < 584 altr,sysmgr-syscon = <&sysmgr>;
585 #address-cells = <1>; 585 #address-cells = <1>;
586 #size-cells = <1>; 586 #size-cells = <1>;
587 interrupts = <0 15 4>; 587 interrupts = <0 15 4>;
588 interrupt-controller; 588 interrupt-controller;
589 #interrupt-cells = <2> 589 #interrupt-cells = <2>;
590 ranges; 590 ranges;
591 591
592 sdramedac { 592 sdramedac {
593 compatible = " 593 compatible = "altr,sdram-edac-s10";
594 altr,sdr-sysco 594 altr,sdr-syscon = <&sdr>;
595 interrupts = < 595 interrupts = <16 4>;
596 }; 596 };
597 597
598 ocram-ecc@ff8cc000 { 598 ocram-ecc@ff8cc000 {
599 compatible = " 599 compatible = "altr,socfpga-s10-ocram-ecc",
600 " 600 "altr,socfpga-a10-ocram-ecc";
601 reg = <0xff8cc 601 reg = <0xff8cc000 0x100>;
602 altr,ecc-paren 602 altr,ecc-parent = <&ocram>;
603 interrupts = < 603 interrupts = <1 4>;
604 }; 604 };
605 605
606 usb0-ecc@ff8c4000 { 606 usb0-ecc@ff8c4000 {
607 compatible = " 607 compatible = "altr,socfpga-s10-usb-ecc",
608 " 608 "altr,socfpga-usb-ecc";
609 reg = <0xff8c4 609 reg = <0xff8c4000 0x100>;
610 altr,ecc-paren 610 altr,ecc-parent = <&usb0>;
611 interrupts = < 611 interrupts = <2 4>;
612 }; 612 };
613 613
614 emac0-rx-ecc@ff8c0000 614 emac0-rx-ecc@ff8c0000 {
615 compatible = " 615 compatible = "altr,socfpga-s10-eth-mac-ecc",
616 " 616 "altr,socfpga-eth-mac-ecc";
617 reg = <0xff8c0 617 reg = <0xff8c0000 0x100>;
618 altr,ecc-paren 618 altr,ecc-parent = <&gmac0>;
619 interrupts = < 619 interrupts = <4 4>;
620 }; 620 };
621 621
622 emac0-tx-ecc@ff8c0400 622 emac0-tx-ecc@ff8c0400 {
623 compatible = " 623 compatible = "altr,socfpga-s10-eth-mac-ecc",
624 " 624 "altr,socfpga-eth-mac-ecc";
625 reg = <0xff8c0 625 reg = <0xff8c0400 0x100>;
626 altr,ecc-paren 626 altr,ecc-parent = <&gmac0>;
627 interrupts = < 627 interrupts = <5 4>;
628 }; 628 };
629 629
630 }; 630 };
631 631
632 qspi: spi@ff8d2000 { 632 qspi: spi@ff8d2000 {
633 compatible = "intel,so 633 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
634 #address-cells = <1>; 634 #address-cells = <1>;
635 #size-cells = <0>; 635 #size-cells = <0>;
636 reg = <0xff8d2000 0x10 636 reg = <0xff8d2000 0x100>,
637 <0xff900000 0x10 637 <0xff900000 0x100000>;
638 interrupts = <0 3 4>; 638 interrupts = <0 3 4>;
639 cdns,fifo-depth = <128 639 cdns,fifo-depth = <128>;
640 cdns,fifo-width = <4>; 640 cdns,fifo-width = <4>;
641 cdns,trigger-address = 641 cdns,trigger-address = <0x00000000>;
642 clocks = <&qspi_clk>; 642 clocks = <&qspi_clk>;
643 643
644 status = "disabled"; 644 status = "disabled";
645 }; 645 };
646 }; 646 };
647 647
648 usbphy0: usbphy0 { 648 usbphy0: usbphy0 {
649 compatible = "usb-nop-xceiv"; 649 compatible = "usb-nop-xceiv";
650 #phy-cells = <0>; 650 #phy-cells = <0>;
651 }; 651 };
652 }; 652 };
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