1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 Amlogic, Inc. All rights 3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/irq 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h 9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clk 10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-cl 11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-periphe 12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h> 13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h> 14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
15 15
16 / { 16 / {
17 cpus { 17 cpus {
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <0>; 19 #size-cells = <0>;
20 20
21 cpu0: cpu@0 { 21 cpu0: cpu@0 {
22 device_type = "cpu"; 22 device_type = "cpu";
23 compatible = "arm,cort 23 compatible = "arm,cortex-a35";
24 reg = <0x0 0x0>; 24 reg = <0x0 0x0>;
25 enable-method = "psci" 25 enable-method = "psci";
26 }; 26 };
27 27
28 cpu1: cpu@1 { 28 cpu1: cpu@1 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 compatible = "arm,cort 30 compatible = "arm,cortex-a35";
31 reg = <0x0 0x1>; 31 reg = <0x0 0x1>;
32 enable-method = "psci" 32 enable-method = "psci";
33 }; 33 };
34 }; 34 };
35 35
36 timer { 36 timer {
37 compatible = "arm,armv8-timer" 37 compatible = "arm,armv8-timer";
38 interrupts = <GIC_PPI 13 (GIC_ 38 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
39 <GIC_PPI 14 (GIC_ 39 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
40 <GIC_PPI 11 (GIC_ 40 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
41 <GIC_PPI 10 (GIC_ 41 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
42 }; 42 };
43 43
44 psci { 44 psci {
45 compatible = "arm,psci-1.0"; 45 compatible = "arm,psci-1.0";
46 method = "smc"; 46 method = "smc";
47 }; 47 };
48 48
49 xtal: xtal-clk { 49 xtal: xtal-clk {
50 compatible = "fixed-clock"; 50 compatible = "fixed-clock";
51 clock-frequency = <24000000>; 51 clock-frequency = <24000000>;
52 clock-output-names = "xtal"; 52 clock-output-names = "xtal";
53 #clock-cells = <0>; 53 #clock-cells = <0>;
54 }; 54 };
55 55
56 sm: secure-monitor { 56 sm: secure-monitor {
57 compatible = "amlogic,meson-gx 57 compatible = "amlogic,meson-gxbb-sm";
58 58
59 pwrc: power-controller { 59 pwrc: power-controller {
60 compatible = "amlogic, 60 compatible = "amlogic,c3-pwrc";
61 #power-domain-cells = 61 #power-domain-cells = <1>;
62 }; 62 };
63 }; 63 };
64 64
65 sram@7f50e00 { 65 sram@7f50e00 {
66 compatible = "mmio-sram"; 66 compatible = "mmio-sram";
67 reg = <0x0 0x07f50e00 0x0 0x10 67 reg = <0x0 0x07f50e00 0x0 0x100>;
68 #address-cells = <1>; 68 #address-cells = <1>;
69 #size-cells = <1>; 69 #size-cells = <1>;
70 ranges = <0 0x0 0x07f50e00 0x1 70 ranges = <0 0x0 0x07f50e00 0x100>;
71 71
72 scmi_shmem: sram@0 { 72 scmi_shmem: sram@0 {
73 compatible = "arm,scmi 73 compatible = "arm,scmi-shmem";
74 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
75 }; 75 };
76 }; 76 };
77 77
78 firmware { 78 firmware {
79 scmi: scmi { 79 scmi: scmi {
80 compatible = "arm,scmi 80 compatible = "arm,scmi-smc";
81 arm,smc-id = <0x820000 81 arm,smc-id = <0x820000C1>;
82 shmem = <&scmi_shmem>; 82 shmem = <&scmi_shmem>;
83 #address-cells = <1>; 83 #address-cells = <1>;
84 #size-cells = <0>; 84 #size-cells = <0>;
85 85
86 scmi_clk: protocol@14 86 scmi_clk: protocol@14 {
87 reg = <0x14>; 87 reg = <0x14>;
88 #clock-cells = 88 #clock-cells = <1>;
89 }; 89 };
90 }; 90 };
91 }; 91 };
92 92
93 soc { 93 soc {
94 compatible = "simple-bus"; 94 compatible = "simple-bus";
95 #address-cells = <2>; 95 #address-cells = <2>;
96 #size-cells = <2>; 96 #size-cells = <2>;
97 ranges; 97 ranges;
98 98
99 gic: interrupt-controller@fff0 99 gic: interrupt-controller@fff01000 {
100 compatible = "arm,gic- 100 compatible = "arm,gic-400";
101 #interrupt-cells = <3> 101 #interrupt-cells = <3>;
102 #address-cells = <0>; 102 #address-cells = <0>;
103 interrupt-controller; 103 interrupt-controller;
104 reg = <0x0 0xfff01000 104 reg = <0x0 0xfff01000 0 0x1000>,
105 <0x0 0xfff02000 105 <0x0 0xfff02000 0 0x2000>,
106 <0x0 0xfff04000 106 <0x0 0xfff04000 0 0x2000>,
107 <0x0 0xfff06000 107 <0x0 0xfff06000 0 0x2000>;
108 interrupts = <GIC_PPI 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 }; 109 };
110 110
111 apb4: bus@fe000000 { 111 apb4: bus@fe000000 {
112 compatible = "simple-b 112 compatible = "simple-bus";
113 reg = <0x0 0xfe000000 113 reg = <0x0 0xfe000000 0x0 0x480000>;
114 #address-cells = <2>; 114 #address-cells = <2>;
115 #size-cells = <2>; 115 #size-cells = <2>;
116 ranges = <0x0 0x0 0x0 116 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
117 117
118 clkc_periphs: clock-co 118 clkc_periphs: clock-controller@0 {
119 compatible = " 119 compatible = "amlogic,c3-peripherals-clkc";
120 reg = <0x0 0x0 120 reg = <0x0 0x0 0x0 0x49c>;
121 #clock-cells = 121 #clock-cells = <1>;
122 clocks = <&xta 122 clocks = <&xtal>,
123 <&scm 123 <&scmi_clk CLKID_OSC>,
124 <&scm 124 <&scmi_clk CLKID_FIXED_PLL_OSC>,
125 <&clk 125 <&clkc_pll CLKID_FCLK_DIV2>,
126 <&clk 126 <&clkc_pll CLKID_FCLK_DIV2P5>,
127 <&clk 127 <&clkc_pll CLKID_FCLK_DIV3>,
128 <&clk 128 <&clkc_pll CLKID_FCLK_DIV4>,
129 <&clk 129 <&clkc_pll CLKID_FCLK_DIV5>,
130 <&clk 130 <&clkc_pll CLKID_FCLK_DIV7>,
131 <&clk 131 <&clkc_pll CLKID_GP0_PLL>,
132 <&scm 132 <&scmi_clk CLKID_GP1_PLL_OSC>,
133 <&clk 133 <&clkc_pll CLKID_HIFI_PLL>,
134 <&scm 134 <&scmi_clk CLKID_SYS_CLK>,
135 <&scm 135 <&scmi_clk CLKID_AXI_CLK>,
136 <&scm 136 <&scmi_clk CLKID_SYS_PLL_DIV16>,
137 <&scm 137 <&scmi_clk CLKID_CPU_CLK_DIV16>;
138 clock-names = 138 clock-names = "xtal_24m",
139 139 "oscin",
140 140 "fix",
141 141 "fdiv2",
142 142 "fdiv2p5",
143 143 "fdiv3",
144 144 "fdiv4",
145 145 "fdiv5",
146 146 "fdiv7",
147 147 "gp0",
148 148 "gp1",
149 149 "hifi",
150 150 "sysclk",
151 151 "axiclk",
152 152 "sysplldiv16",
153 153 "cpudiv16";
154 }; 154 };
155 155
156 reset: reset-controlle 156 reset: reset-controller@2000 {
157 compatible = " 157 compatible = "amlogic,c3-reset";
158 reg = <0x0 0x2 158 reg = <0x0 0x2000 0x0 0x98>;
159 #reset-cells = 159 #reset-cells = <1>;
160 }; 160 };
161 161
162 watchdog@2100 { 162 watchdog@2100 {
163 compatible = " 163 compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
164 reg = <0x0 0x2 164 reg = <0x0 0x2100 0x0 0x10>;
165 clocks = <&xta 165 clocks = <&xtal>;
166 }; 166 };
167 167
168 periphs_pinctrl: pinct 168 periphs_pinctrl: pinctrl@4000 {
169 compatible = " 169 compatible = "amlogic,c3-periphs-pinctrl";
170 #address-cells 170 #address-cells = <2>;
171 #size-cells = 171 #size-cells = <2>;
172 ranges = <0x0 172 ranges = <0x0 0x0 0x0 0x4000 0x0 0x02de>;
173 173
174 gpio: bank@0 { 174 gpio: bank@0 {
175 reg = 175 reg = <0x0 0x0 0x0 0x004c>,
176 176 <0x0 0x100 0x0 0x01de>;
177 reg-na 177 reg-names = "mux", "gpio";
178 gpio-c 178 gpio-controller;
179 #gpio- 179 #gpio-cells = <2>;
180 gpio-r 180 gpio-ranges = <&periphs_pinctrl 0 0 55>;
181 }; 181 };
182 182
183 i2c0_pins1: i2 183 i2c0_pins1: i2c0-pins1 {
184 mux { 184 mux {
185 185 groups = "i2c0_sda_e",
186 186 "i2c0_scl_e";
187 187 function = "i2c0";
188 188 bias-disable;
189 189 drive-strength-microamp = <3000>;
190 }; 190 };
191 }; 191 };
192 192
193 i2c0_pins2: i2 193 i2c0_pins2: i2c0-pins2 {
194 mux { 194 mux {
195 195 groups = "i2c0_sda_d",
196 196 "i2c0_scl_d";
197 197 function = "i2c0";
198 198 bias-disable;
199 199 drive-strength-microamp = <3000>;
200 }; 200 };
201 }; 201 };
202 202
203 i2c1_pins1: i2 203 i2c1_pins1: i2c1-pins1 {
204 mux { 204 mux {
205 205 groups = "i2c1_sda_x",
206 206 "i2c1_scl_x";
207 207 function = "i2c1";
208 208 bias-disable;
209 209 drive-strength-microamp = <3000>;
210 }; 210 };
211 }; 211 };
212 212
213 i2c1_pins2: i2 213 i2c1_pins2: i2c1-pins2 {
214 mux { 214 mux {
215 215 groups = "i2c1_sda_d",
216 216 "i2c1_scl_d";
217 217 function = "i2c1";
218 218 bias-disable;
219 219 drive-strength-microamp = <3000>;
220 }; 220 };
221 }; 221 };
222 222
223 i2c1_pins3: i2 223 i2c1_pins3: i2c1-pins3 {
224 mux { 224 mux {
225 225 groups = "i2c1_sda_a",
226 226 "i2c1_scl_a";
227 227 function = "i2c1";
228 228 bias-disable;
229 229 drive-strength-microamp = <3000>;
230 }; 230 };
231 }; 231 };
232 232
233 i2c1_pins4: i2 233 i2c1_pins4: i2c1-pins4 {
234 mux { 234 mux {
235 235 groups = "i2c1_sda_b",
236 236 "i2c1_scl_b";
237 237 function = "i2c1";
238 238 bias-disable;
239 239 drive-strength-microamp = <3000>;
240 }; 240 };
241 }; 241 };
242 242
243 i2c2_pins1: i2 243 i2c2_pins1: i2c2-pins1 {
244 mux { 244 mux {
245 245 groups = "i2c2_sda",
246 246 "i2c2_scl";
247 247 function = "i2c2";
248 248 bias-disable;
249 249 drive-strength-microamp = <3000>;
250 }; 250 };
251 }; 251 };
252 252
253 i2c3_pins1: i2 253 i2c3_pins1: i2c3-pins1 {
254 mux { 254 mux {
255 255 groups = "i2c3_sda_c",
256 256 "i2c3_scl_c";
257 257 function = "i2c3";
258 258 bias-disable;
259 259 drive-strength-microamp = <3000>;
260 }; 260 };
261 }; 261 };
262 262
263 i2c3_pins2: i2 263 i2c3_pins2: i2c3-pins2 {
264 mux { 264 mux {
265 265 groups = "i2c3_sda_x",
266 266 "i2c3_scl_x";
267 267 function = "i2c3";
268 268 bias-disable;
269 269 drive-strength-microamp = <3000>;
270 }; 270 };
271 }; 271 };
272 272
273 i2c3_pins3: i2 273 i2c3_pins3: i2c3-pins3 {
274 mux { 274 mux {
275 275 groups = "i2c3_sda_d",
276 276 "i2c3_scl_d";
277 277 function = "i2c3";
278 278 bias-disable;
279 279 drive-strength-microamp = <3000>;
280 }; 280 };
281 }; 281 };
282 282
283 nand_pins: nan 283 nand_pins: nand-pins {
284 mux { 284 mux {
285 285 groups = "emmc_nand_d0",
286 286 "emmc_nand_d1",
287 287 "emmc_nand_d2",
288 288 "emmc_nand_d3",
289 289 "emmc_nand_d4",
290 290 "emmc_nand_d5",
291 291 "emmc_nand_d6",
292 292 "emmc_nand_d7",
293 293 "nand_ce0",
294 294 "nand_ale",
295 295 "nand_cle",
296 296 "nand_wen_clk",
297 297 "nand_ren_wr";
298 298 function = "nand";
299 299 input-enable;
300 }; 300 };
301 }; 301 };
302 302
303 sdcard_pins: s 303 sdcard_pins: sdcard-pins {
304 mux { 304 mux {
305 305 groups = "sdcard_d0",
306 306 "sdcard_d1",
307 307 "sdcard_d2",
308 308 "sdcard_d3",
309 309 "sdcard_clk",
310 310 "sdcard_cmd";
311 311 function = "sdcard";
312 312 bias-pull-up;
313 313 drive-strength-microamp = <4000>;
314 }; 314 };
315 }; 315 };
316 316
317 sdcard_clk_gat 317 sdcard_clk_gate_pins: sdcard-clk-cmd-pins {
318 mux { 318 mux {
319 319 groups = "GPIOC_4";
320 320 function = "gpio_periphs";
321 321 bias-pull-down;
322 322 drive-strength-microamp = <4000>;
323 }; 323 };
324 }; 324 };
325 325
326 sdio_m_clk_gat 326 sdio_m_clk_gate_pins: sdio-m-clk-cmd-pins {
327 mux { 327 mux {
328 328 groups = "sdio_clk";
329 329 function = "sdio";
330 330 bias-pull-down;
331 331 drive-strength-microamp = <4000>;
332 }; 332 };
333 }; 333 };
334 334
335 sdio_m_pins: s 335 sdio_m_pins: sdio-m-all-pins {
336 mux { 336 mux {
337 337 groups = "sdio_d0",
338 338 "sdio_d1",
339 339 "sdio_d2",
340 340 "sdio_d3",
341 341 "sdio_clk",
342 342 "sdio_cmd";
343 343 function = "sdio";
344 344 input-enable;
345 345 bias-pull-up;
346 346 drive-strength-microamp = <4000>;
347 }; 347 };
348 }; 348 };
349 349
350 spicc0_pins1: 350 spicc0_pins1: spicc0-pins1 {
351 mux { 351 mux {
352 352 groups = "spi_a_mosi_b",
353 353 "spi_a_miso_b",
354 354 "spi_a_clk_b";
355 355 function = "spi_a";
356 356 drive-strength-microamp = <3000>;
357 }; 357 };
358 }; 358 };
359 359
360 spicc0_pins2: 360 spicc0_pins2: spicc0-pins2 {
361 mux { 361 mux {
362 362 groups = "spi_a_mosi_c",
363 363 "spi_a_miso_c",
364 364 "spi_a_clk_c";
365 365 function = "spi_a";
366 366 drive-strength-microamp = <3000>;
367 }; 367 };
368 }; 368 };
369 369
370 spicc0_pins3: 370 spicc0_pins3: spicc0-pins3 {
371 mux { 371 mux {
372 372 groups = "spi_a_mosi_x",
373 373 "spi_a_miso_x",
374 374 "spi_a_clk_x";
375 375 function = "spi_a";
376 376 drive-strength-microamp = <3000>;
377 }; 377 };
378 }; 378 };
379 379
380 spicc1_pins1: 380 spicc1_pins1: spicc1-pins1 {
381 mux { 381 mux {
382 382 groups = "spi_b_mosi_d",
383 383 "spi_b_miso_d",
384 384 "spi_b_clk_d";
385 385 function = "spi_b";
386 386 drive-strength-microamp = <3000>;
387 }; 387 };
388 }; 388 };
389 389
390 spicc1_pins2: 390 spicc1_pins2: spicc1-pins2 {
391 mux { 391 mux {
392 392 groups = "spi_b_mosi_x",
393 393 "spi_b_miso_x",
394 394 "spi_b_clk_x";
395 395 function = "spi_b";
396 396 drive-strength-microamp = <3000>;
397 }; 397 };
398 }; 398 };
399 399
400 spifc_pins: sp 400 spifc_pins: spifc-pins {
401 mux { 401 mux {
402 402 groups = "spif_mo",
403 403 "spif_mi",
404 404 "spif_clk",
405 405 "spif_cs",
406 406 "spif_hold",
407 407 "spif_wp",
408 408 "spif_clk_loop";
409 409 function = "spif";
410 410 drive-strength-microamp = <4000>;
411 }; 411 };
412 }; 412 };
413 }; 413 };
414 414
415 gpio_intc: interrupt-c 415 gpio_intc: interrupt-controller@4080 {
416 compatible = " 416 compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";
417 reg = <0x0 0x4 417 reg = <0x0 0x4080 0x0 0x0020>;
418 interrupt-cont 418 interrupt-controller;
419 #interrupt-cel 419 #interrupt-cells = <2>;
420 amlogic,channe 420 amlogic,channel-interrupts =
421 <10 11 421 <10 11 12 13 14 15 16 17 18 19 20 21>;
422 }; 422 };
423 423
424 clkc_pll: clock-contro 424 clkc_pll: clock-controller@8000 {
425 compatible = " 425 compatible = "amlogic,c3-pll-clkc";
426 reg = <0x0 0x8 426 reg = <0x0 0x8000 0x0 0x1a4>;
427 #clock-cells = 427 #clock-cells = <1>;
428 clocks = <&scm 428 clocks = <&scmi_clk CLKID_TOP_PLL_OSC>,
429 <&scm 429 <&scmi_clk CLKID_MCLK_PLL_OSC>,
430 <&scm 430 <&scmi_clk CLKID_FIXED_PLL_OSC>;
431 clock-names = 431 clock-names = "top",
432 432 "mclk",
433 433 "fix";
434 }; 434 };
435 435
436 eth_phy: mdio-multiple 436 eth_phy: mdio-multiplexer@28000 {
437 compatible = " 437 compatible = "amlogic,g12a-mdio-mux";
438 reg = <0x0 0x2 438 reg = <0x0 0x28000 0x0 0xa4>;
439 439
440 clocks = <&clk 440 clocks = <&clkc_periphs CLKID_SYS_ETH_PHY>,
441 <&xta 441 <&xtal>,
442 <&clk 442 <&clkc_pll CLKID_FCLK_50M>;
443 clock-names = 443 clock-names = "pclk", "clkin0", "clkin1";
444 mdio-parent-bu 444 mdio-parent-bus = <&mdio0>;
445 #address-cells 445 #address-cells = <1>;
446 #size-cells = 446 #size-cells = <0>;
447 447
448 ext_mdio: mdio 448 ext_mdio: mdio@0 {
449 reg = 449 reg = <0>;
450 #addre 450 #address-cells = <1>;
451 #size- 451 #size-cells = <0>;
452 }; 452 };
453 453
454 int_mdio: mdio 454 int_mdio: mdio@1 {
455 reg = 455 reg = <1>;
456 #addre 456 #address-cells = <1>;
457 #size- 457 #size-cells = <0>;
458 458
459 intern 459 internal_ephy: ethernet_phy@8 {
460 460 compatible = "ethernet-phy-id0180.3301",
461 461 "ethernet-phy-ieee802.3-c22";
462 462 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
463 463 reg = <8>;
464 464 max-speed = <100>;
465 }; 465 };
466 }; 466 };
467 }; 467 };
468 468
469 spicc0: spi@50000 { 469 spicc0: spi@50000 {
470 compatible = " 470 compatible = "amlogic,meson-g12a-spicc";
471 reg = <0x0 0x5 471 reg = <0x0 0x50000 0x0 0x44>;
472 interrupts = < 472 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clk 473 clocks = <&clkc_periphs CLKID_SYS_SPICC_0>,
474 <&clk 474 <&clkc_periphs CLKID_SPICC_A>;
475 clock-names = 475 clock-names = "core", "pclk";
476 #address-cells 476 #address-cells = <1>;
477 #size-cells = 477 #size-cells = <0>;
478 status = "disa 478 status = "disabled";
479 }; 479 };
480 480
481 spicc1: spi@52000 { 481 spicc1: spi@52000 {
482 compatible = " 482 compatible = "amlogic,meson-g12a-spicc";
483 reg = <0x0 0x5 483 reg = <0x0 0x52000 0x0 0x44>;
484 interrupts = < 484 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clk 485 clocks = <&clkc_periphs CLKID_SYS_SPICC_1>,
486 <&clk 486 <&clkc_periphs CLKID_SPICC_B>;
487 clock-names = 487 clock-names = "core", "pclk";
488 #address-cells 488 #address-cells = <1>;
489 #size-cells = 489 #size-cells = <0>;
490 status = "disa 490 status = "disabled";
491 }; 491 };
492 492
493 spifc: spi@56000 { 493 spifc: spi@56000 {
494 compatible = " 494 compatible = "amlogic,a1-spifc";
495 reg = <0x0 0x5 495 reg = <0x0 0x56000 0x0 0x290>;
496 interrupts = < 496 interrupts = <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>;
497 clocks = <&clk 497 clocks = <&clkc_periphs CLKID_SPIFC>;
498 clock-names = 498 clock-names = "core";
499 status = "disa 499 status = "disabled";
500 }; 500 };
501 501
502 i2c0: i2c@66000 { 502 i2c0: i2c@66000 {
503 compatible = " 503 compatible = "amlogic,meson-axg-i2c";
504 reg = <0x0 0x6 504 reg = <0x0 0x66000 0x0 0x24>;
505 interrupts = < 505 interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
506 #address-cells 506 #address-cells = <1>;
507 #size-cells = 507 #size-cells = <0>;
508 clocks = <&clk 508 clocks = <&clkc_periphs CLKID_SYS_I2C_M_A>;
509 status = "disa 509 status = "disabled";
510 }; 510 };
511 511
512 i2c1: i2c@68000 { 512 i2c1: i2c@68000 {
513 compatible = " 513 compatible = "amlogic,meson-axg-i2c";
514 reg = <0x0 0x6 514 reg = <0x0 0x68000 0x0 0x24>;
515 interrupts = < 515 interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
516 #address-cells 516 #address-cells = <1>;
517 #size-cells = 517 #size-cells = <0>;
518 clocks = <&clk 518 clocks = <&clkc_periphs CLKID_SYS_I2C_M_B>;
519 status = "disa 519 status = "disabled";
520 }; 520 };
521 521
522 i2c2: i2c@6a000 { 522 i2c2: i2c@6a000 {
523 compatible = " 523 compatible = "amlogic,meson-axg-i2c";
524 reg = <0x0 0x6 524 reg = <0x0 0x6a000 0x0 0x24>;
525 interrupts = < 525 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
526 #address-cells 526 #address-cells = <1>;
527 #size-cells = 527 #size-cells = <0>;
528 clocks = <&clk 528 clocks = <&clkc_periphs CLKID_SYS_I2C_M_C>;
529 status = "disa 529 status = "disabled";
530 }; 530 };
531 531
532 i2c3: i2c@6c000 { 532 i2c3: i2c@6c000 {
533 compatible = " 533 compatible = "amlogic,meson-axg-i2c";
534 reg = <0x0 0x6 534 reg = <0x0 0x6c000 0x0 0x24>;
535 interrupts = < 535 interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
536 #address-cells 536 #address-cells = <1>;
537 #size-cells = 537 #size-cells = <0>;
538 clocks = <&clk 538 clocks = <&clkc_periphs CLKID_SYS_I2C_M_D>;
539 status = "disa 539 status = "disabled";
540 }; 540 };
541 541
542 uart_b: serial@7a000 { 542 uart_b: serial@7a000 {
543 compatible = " 543 compatible = "amlogic,meson-s4-uart",
544 "am 544 "amlogic,meson-ao-uart";
545 reg = <0x0 0x7 545 reg = <0x0 0x7a000 0x0 0x18>;
546 interrupts = < 546 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
547 status = "disa 547 status = "disabled";
548 clocks = <&xta 548 clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
549 clock-names = 549 clock-names = "xtal", "pclk", "baud";
550 }; 550 };
551 551
552 sec_ao: ao-secure@1022 552 sec_ao: ao-secure@10220 {
553 compatible = " 553 compatible = "amlogic,c3-ao-secure",
554 " 554 "amlogic,meson-gx-ao-secure",
555 " 555 "syscon";
556 reg = <0x0 0x1 556 reg = <0x0 0x10220 0x0 0x140>;
557 amlogic,has-ch 557 amlogic,has-chip-id;
558 }; 558 };
559 559
560 sdio: mmc@88000 { 560 sdio: mmc@88000 {
561 compatible = " 561 compatible = "amlogic,meson-axg-mmc";
562 reg = <0x0 0x8 562 reg = <0x0 0x88000 0x0 0x800>;
563 interrupts = < 563 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
564 power-domains 564 power-domains = <&pwrc PWRC_C3_SDIOA_ID>;
565 clocks = <&clk 565 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
566 <&cl 566 <&clkc_periphs CLKID_SD_EMMC_A>,
567 <&cl 567 <&clkc_pll CLKID_FCLK_DIV2>;
568 clock-names = 568 clock-names = "core","clkin0", "clkin1";
569 no-mmc; 569 no-mmc;
570 no-sd; 570 no-sd;
571 resets = <&res 571 resets = <&reset RESET_SD_EMMC_A>;
572 status = "disa 572 status = "disabled";
573 }; 573 };
574 574
575 sd: mmc@8a000 { 575 sd: mmc@8a000 {
576 compatible = " 576 compatible = "amlogic,meson-axg-mmc";
577 reg = <0x0 0x8 577 reg = <0x0 0x8a000 0x0 0x800>;
578 interrupts = < 578 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
579 power-domains 579 power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
580 clocks = <&clk 580 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
581 <&clkc 581 <&clkc_periphs CLKID_SD_EMMC_B>,
582 <&clkc 582 <&clkc_pll CLKID_FCLK_DIV2>;
583 clock-names = 583 clock-names = "core", "clkin0", "clkin1";
584 no-mmc; 584 no-mmc;
585 no-sdio; 585 no-sdio;
586 resets = <&res 586 resets = <&reset RESET_SD_EMMC_B>;
587 status = "disa 587 status = "disabled";
588 }; 588 };
589 589
590 nand: nand-controller@ 590 nand: nand-controller@8d000 {
591 compatible = " 591 compatible = "amlogic,meson-axg-nfc";
592 reg = <0x0 0x8 592 reg = <0x0 0x8d000 0x0 0x200>,
593 <0x0 0 593 <0x0 0x8C000 0x0 0x4>;
594 reg-names = "n 594 reg-names = "nfc", "emmc";
595 interrupts = < 595 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
596 clocks = <&clk 596 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
597 <&clkc 597 <&clkc_pll CLKID_FCLK_DIV2>;
598 clock-names = 598 clock-names = "core", "device";
599 status = "disa 599 status = "disabled";
600 }; 600 };
601 }; 601 };
602 602
603 ethmac: ethernet@fdc00000 { 603 ethmac: ethernet@fdc00000 {
604 compatible = "amlogic, 604 compatible = "amlogic,meson-g12a-dwmac",
605 "snps,dwm 605 "snps,dwmac-3.70a",
606 "snps,dwm 606 "snps,dwmac";
607 reg = <0x0 0xfdc00000 607 reg = <0x0 0xfdc00000 0x0 0x10000>,
608 <0x0 0xfe024000 608 <0x0 0xfe024000 0x0 0x8>;
609 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-names = "mac 610 interrupt-names = "macirq";
611 power-domains = <&pwrc 611 power-domains = <&pwrc PWRC_C3_ETH_ID>;
612 clocks = <&clkc_periph 612 clocks = <&clkc_periphs CLKID_SYS_ETH_MAC>,
613 <&clkc_pll CL 613 <&clkc_pll CLKID_FCLK_DIV2>,
614 <&clkc_pll CL 614 <&clkc_pll CLKID_FCLK_50M>;
615 clock-names = "stmmace 615 clock-names = "stmmaceth", "clkin0", "clkin1";
616 rx-fifo-depth = <4096> 616 rx-fifo-depth = <4096>;
617 tx-fifo-depth = <2048> 617 tx-fifo-depth = <2048>;
618 status = "disabled"; 618 status = "disabled";
619 619
620 mdio0: mdio { 620 mdio0: mdio {
621 compatible = " 621 compatible = "snps,dwmac-mdio";
622 #address-cells 622 #address-cells = <1>;
623 #size-cells = 623 #size-cells = <0>;
624 }; 624 };
625 }; 625 };
626 }; 626 };
627 }; 627 };
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