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Linux/scripts/dtc/include-prefixes/arm64/amlogic/amlogic-t7-reset.h

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/amlogic/amlogic-t7-reset.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/amlogic/amlogic-t7-reset.h (Version linux-6.0.19)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR M      1 
  2 /*                                                
  3  * Copyright (c) 2024 Amlogic, Inc. All rights    
  4  */                                               
  5                                                   
  6 #ifndef __DTS_AMLOGIC_T7_RESET_H                  
  7 #define __DTS_AMLOGIC_T7_RESET_H                  
  8                                                   
  9 /* RESET0 */                                      
 10 /*                                      0-3       
 11 #define RESET_USB                       4         
 12 #define RESET_U2DRD                     5         
 13 #define RESET_U3DRD                     6         
 14 #define RESET_U3DRD_PIPE0               7         
 15 #define RESET_U2PHY20                   8         
 16 #define RESET_U2PHY21                   9         
 17 #define RESET_GDC                       10        
 18 #define RESET_HDMI20_AES                11        
 19 #define RESET_HDMIRX                    12        
 20 #define RESET_HDMIRX_APB                13        
 21 #define RESET_DEWARP                    14        
 22 /*                                      15        
 23 #define RESET_HDMITX_CAPB3              16        
 24 #define RESET_BRG_VCBUG_DEC             17        
 25 #define RESET_VCBUS                     18        
 26 #define RESET_VID_PLL_DIV               19        
 27 #define RESET_VDI6                      20        
 28 #define RESET_GE2D                      21        
 29 #define RESET_HDMITXPHY                 22        
 30 #define RESET_VID_LOCK                  23        
 31 #define RESET_VENC0                     24        
 32 #define RESET_VDAC                      25        
 33 #define RESET_VENC2                     26        
 34 #define RESET_VENC1                     27        
 35 #define RESET_RDMA                      28        
 36 #define RESET_HDMITX                    29        
 37 #define RESET_VIU                       30        
 38 #define RESET_VENC                      31        
 39                                                   
 40 /* RESET1 */                                      
 41 #define RESET_AUDIO                     32        
 42 #define RESET_MALI_CAPB3                33        
 43 #define RESET_MALI                      34        
 44 #define RESET_DDR_APB                   35        
 45 #define RESET_DDR                       36        
 46 #define RESET_DOS_CAPB3                 37        
 47 #define RESET_DOS                       38        
 48 #define RESET_COMBO_DPHY_CHAN2          39        
 49 #define RESET_DEBUG_B                   40        
 50 #define RESET_DEBUG_A                   41        
 51 #define RESET_DSP_B                     42        
 52 #define RESET_DSP_A                     43        
 53 #define RESET_PCIE_A                    44        
 54 #define RESET_PCIE_PHY                  45        
 55 #define RESET_PCIE_APB                  46        
 56 #define RESET_ANAKIN                    47        
 57 #define RESET_ETH                       48        
 58 #define RESET_EDP0_CTRL                 49        
 59 #define RESET_EDP1_CTRL                 50        
 60 #define RESET_COMBO_DPHY_CHAN0          51        
 61 #define RESET_COMBO_DPHY_CHAN1          52        
 62 #define RESET_DSI_LVDS_EDP_TOP          53        
 63 #define RESET_PCIE1_PHY                 54        
 64 #define RESET_PCIE1_APB                 55        
 65 #define RESET_DDR_1                     56        
 66 /*                                      57        
 67 #define RESET_EDP1_PIPELINE             58        
 68 #define RESET_EDP0_PIPELINE             59        
 69 #define RESET_MIPI_DSI1_PHY             60        
 70 #define RESET_MIPI_DSI0_PHY             61        
 71 #define RESET_MIPI_DSI_A_HOST           62        
 72 #define RESET_MIPI_DSI_B_HOST           63        
 73                                                   
 74 /* RESET2 */                                      
 75 #define RESET_DEVICE_MMC_ARB            64        
 76 #define RESET_IR_CTRL                   65        
 77 #define RESET_TS_A73                    66        
 78 #define RESET_TS_A53                    67        
 79 #define RESET_SPICC_2                   68        
 80 #define RESET_SPICC_3                   69        
 81 #define RESET_SPICC_4                   70        
 82 #define RESET_SPICC_5                   71        
 83 #define RESET_SMART_CARD                72        
 84 #define RESET_SPICC_0                   73        
 85 #define RESET_SPICC_1                   74        
 86 #define RESET_RSA                       75        
 87 /*                                      76-79     
 88 #define RESET_MSR_CLK                   80        
 89 #define RESET_SPIFC                     81        
 90 #define RESET_SAR_ADC                   82        
 91 #define RESET_BT                        83        
 92 /*                                      84-87     
 93 #define RESET_ACODEC                    88        
 94 #define RESET_CEC                       89        
 95 #define RESET_AFIFO                     90        
 96 #define RESET_WATCHDOG                  91        
 97 /*                                      92-95     
 98                                                   
 99 /* RESET3 */                                      
100 #define RESET_BRG_NIC1_GPV              96        
101 #define RESET_BRG_NIC2_GPV              97        
102 #define RESET_BRG_NIC3_GPV              98        
103 #define RESET_BRG_NIC4_GPV              99        
104 #define RESET_BRG_NIC5_GPV              100       
105 /*                                      101-12    
106 #define RESET_MIPI_ISP                  122       
107 #define RESET_BRG_ADB_MALI_1            123       
108 #define RESET_BRG_ADB_MALI_0            124       
109 #define RESET_BRG_ADB_A73               125       
110 #define RESET_BRG_ADB_A53               126       
111 #define RESET_BRG_CCI                   127       
112                                                   
113 /* RESET4 */                                      
114 #define RESET_PWM_AO_AB                 128       
115 #define RESET_PWM_AO_CD                 129       
116 #define RESET_PWM_AO_EF                 130       
117 #define RESET_PWM_AO_GH                 131       
118 #define RESET_PWM_AB                    132       
119 #define RESET_PWM_CD                    133       
120 #define RESET_PWM_EF                    134       
121 /*                                      135-13    
122 #define RESET_UART_A                    138       
123 #define RESET_UART_B                    139       
124 #define RESET_UART_C                    140       
125 #define RESET_UART_D                    141       
126 #define RESET_UART_E                    142       
127 #define RESET_UART_F                    143       
128 #define RESET_I2C_S_A                   144       
129 #define RESET_I2C_M_A                   145       
130 #define RESET_I2C_M_B                   146       
131 #define RESET_I2C_M_C                   147       
132 #define RESET_I2C_M_D                   148       
133 #define RESET_I2C_M_E                   149       
134 #define RESET_I2C_M_F                   150       
135 #define RESET_I2C_M_AO_A                151       
136 #define RESET_SD_EMMC_A                 152       
137 #define RESET_SD_EMMC_B                 153       
138 #define RESET_SD_EMMC_C                 154       
139 #define RESET_I2C_M_AO_B                155       
140 #define RESET_TS_GPU                    156       
141 #define RESET_TS_NNA                    157       
142 #define RESET_TS_VPN                    158       
143 #define RESET_TS_HEVC                   159       
144                                                   
145 /* RESET5 */                                      
146 #define RESET_BRG_NOC_DDR_1             160       
147 #define RESET_BRG_NOC_DDR_0             161       
148 #define RESET_BRG_NOC_MAIN              162       
149 #define RESET_BRG_NOC_ALL               163       
150 /*                                      164-16    
151 #define RESET_BRG_NIC2_SYS              168       
152 #define RESET_BRG_NIC2_MAIN             169       
153 #define RESET_BRG_NIC2_HDMI             170       
154 #define RESET_BRG_NIC2_ALL              171       
155 #define RESET_BRG_NIC3_WAVE             172       
156 #define RESET_BRG_NIC3_VDEC             173       
157 #define RESET_BRG_NIC3_HEVCF            174       
158 #define RESET_BRG_NIC3_HEVCB            175       
159 #define RESET_BRG_NIC3_HCODEC           176       
160 #define RESET_BRG_NIC3_GE2D             177       
161 #define RESET_BRG_NIC3_GDC              178       
162 #define RESET_BRG_NIC3_AMLOGIC          179       
163 #define RESET_BRG_NIC3_MAIN             180       
164 #define RESET_BRG_NIC3_ALL              181       
165 #define RESET_BRG_NIC5_VPU              182       
166 /*                                      183-18    
167 #define RESET_BRG_NIC4_DSPB             186       
168 #define RESET_BRG_NIC4_DSPA             187       
169 #define RESET_BRG_NIC4_VAPB             188       
170 #define RESET_BRG_NIC4_CLK81            189       
171 #define RESET_BRG_NIC4_MAIN             190       
172 #define RESET_BRG_NIC4_ALL              191       
173                                                   
174 /* RESET6 */                                      
175 #define RESET_BRG_VDEC_PIPEL            192       
176 #define RESET_BRG_HEVCF_DMC_PIPEL       193       
177 #define RESET_BRG_NIC2TONIC4_PIPEL      194       
178 #define RESET_BRG_HDMIRXTONIC2_PIPEL    195       
179 #define RESET_BRG_SECTONIC4_PIPEL       196       
180 #define RESET_BRG_VPUTONOC_PIPEL        197       
181 #define RESET_BRG_NIC4TONOC_PIPEL       198       
182 #define RESET_BRG_NIC3TONOC_PIPEL       199       
183 #define RESET_BRG_NIC2TONOC_PIPEL       200       
184 #define RESET_BRG_NNATONOC_PIPEL        201       
185 #define RESET_BRG_FRISP3_PIPEL          202       
186 #define RESET_BRG_FRISP2_PIPEL          203       
187 #define RESET_BRG_FRISP1_PIPEL          204       
188 #define RESET_BRG_FRISP0_PIPEL          205       
189 /*                                      206-21    
190 #define RESET_BRG_AMPIPE_NAND           218       
191 #define RESET_BRG_AMPIPE_ETH            219       
192 /*                                      220       
193 #define RESET_BRG_AM2AXI0               221       
194 #define RESET_BRG_AM2AXI1               222       
195 #define RESET_BRG_AM2AXI2               223       
196                                                   
197 #endif /* ___DTS_AMLOGIC_T7_RESET_H */            
198                                                   

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