1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights
4 */
5
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/reset/amlogic,meson-axg-
14 #include <dt-bindings/reset/amlogic,meson-axg-
15 #include <dt-bindings/power/meson-axg-power.h>
16
17 / {
18 compatible = "amlogic,meson-axg";
19
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm-
26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI
29 <&clkc_audio AUD_CLKI
30 <&clkc_audio AUD_CLKI
31 clock-names = "sclk", "lrclk",
32 status = "disabled";
33 };
34
35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm-
37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI
40 <&clkc_audio AUD_CLKI
41 <&clkc_audio AUD_CLKI
42 clock-names = "sclk", "lrclk",
43 status = "disabled";
44 };
45
46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm-
48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI
51 <&clkc_audio AUD_CLKI
52 <&clkc_audio AUD_CLKI
53 clock-names = "sclk", "lrclk",
54 status = "disabled";
55 };
56
57 arm-pmu {
58 compatible = "arm,cortex-a53-p
59 interrupts = <GIC_SPI 137 IRQ_
60 <GIC_SPI 138 IRQ_
61 <GIC_SPI 153 IRQ_
62 <GIC_SPI 154 IRQ_
63 interrupt-affinity = <&cpu0>,
64 };
65
66 cpus {
67 #address-cells = <0x2>;
68 #size-cells = <0x0>;
69
70 cpu0: cpu@0 {
71 device_type = "cpu";
72 compatible = "arm,cort
73 reg = <0x0 0x0>;
74 enable-method = "psci"
75 next-level-cache = <&l
76 clocks = <&scpi_dvfs 0
77 dynamic-power-coeffici
78 #cooling-cells = <2>;
79 };
80
81 cpu1: cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cort
84 reg = <0x0 0x1>;
85 enable-method = "psci"
86 next-level-cache = <&l
87 clocks = <&scpi_dvfs 0
88 dynamic-power-coeffici
89 #cooling-cells = <2>;
90 };
91
92 cpu2: cpu@2 {
93 device_type = "cpu";
94 compatible = "arm,cort
95 reg = <0x0 0x2>;
96 enable-method = "psci"
97 next-level-cache = <&l
98 clocks = <&scpi_dvfs 0
99 dynamic-power-coeffici
100 #cooling-cells = <2>;
101 };
102
103 cpu3: cpu@3 {
104 device_type = "cpu";
105 compatible = "arm,cort
106 reg = <0x0 0x3>;
107 enable-method = "psci"
108 next-level-cache = <&l
109 clocks = <&scpi_dvfs 0
110 dynamic-power-coeffici
111 #cooling-cells = <2>;
112 };
113
114 l2: l2-cache0 {
115 compatible = "cache";
116 cache-level = <2>;
117 cache-unified;
118 };
119 };
120
121 sm: secure-monitor {
122 compatible = "amlogic,meson-gx
123 };
124
125 efuse: efuse {
126 compatible = "amlogic,meson-gx
127 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>;
129 #size-cells = <1>;
130 read-only;
131 secure-monitor = <&sm>;
132 };
133
134 psci {
135 compatible = "arm,psci-1.0";
136 method = "smc";
137 };
138
139 reserved-memory {
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 /* 16 MiB reserved for Hardwar
145 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1
147 no-map;
148 };
149
150 /* Alternate 3 MiB reserved fo
151 secmon_reserved: secmon@500000
152 reg = <0x0 0x05000000
153 no-map;
154 };
155 };
156
157 scpi {
158 compatible = "arm,scpi-pre-1.0
159 mboxes = <&mailbox 1 &mailbox
160 shmem = <&cpu_scp_lpri &cpu_sc
161
162 scpi_clocks: clocks {
163 compatible = "arm,scpi
164
165 scpi_dvfs: clocks-0 {
166 compatible = "
167 #clock-cells =
168 clock-indices
169 clock-output-n
170 };
171 };
172
173 scpi_sensors: sensors {
174 compatible = "amlogic,
175 #thermal-sensor-cells
176 };
177 };
178
179 soc {
180 compatible = "simple-bus";
181 #address-cells = <2>;
182 #size-cells = <2>;
183 ranges;
184
185 pcieA: pcie@f9800000 {
186 compatible = "amlogic,
187 reg = <0x0 0xf9800000
188 <0x0 0xff646000
189 <0x0 0xf9f00000
190 reg-names = "elbi", "c
191 interrupts = <GIC_SPI
192 #interrupt-cells = <1>
193 interrupt-map-mask = <
194 interrupt-map = <0 0 0
195 bus-range = <0x0 0xff>
196 #address-cells = <3>;
197 #size-cells = <2>;
198 device_type = "pci";
199 ranges = <0x82000000 0
200
201 clocks = <&clkc CLKID_
202 clock-names = "general
203 resets = <&reset RESET
204 reset-names = "port",
205 num-lanes = <1>;
206 phys = <&pcie_phy>;
207 phy-names = "pcie";
208 status = "disabled";
209 };
210
211 pcieB: pcie@fa000000 {
212 compatible = "amlogic,
213 reg = <0x0 0xfa000000
214 <0x0 0xff648000
215 <0x0 0xfa400000
216 reg-names = "elbi", "c
217 interrupts = <GIC_SPI
218 #interrupt-cells = <1>
219 interrupt-map-mask = <
220 interrupt-map = <0 0 0
221 bus-range = <0x0 0xff>
222 #address-cells = <3>;
223 #size-cells = <2>;
224 device_type = "pci";
225 ranges = <0x82000000 0
226
227 clocks = <&clkc CLKID_
228 clock-names = "general
229 resets = <&reset RESET
230 reset-names = "port",
231 num-lanes = <1>;
232 phys = <&pcie_phy>;
233 phy-names = "pcie";
234 status = "disabled";
235 };
236
237 usb: usb@ffe09080 {
238 compatible = "amlogic,
239 reg = <0x0 0xffe09080
240 interrupts = <GIC_SPI
241 #address-cells = <2>;
242 #size-cells = <2>;
243 ranges;
244
245 clocks = <&clkc CLKID_
246 clock-names = "usb_ctr
247 resets = <&reset RESET
248
249 dr_mode = "otg";
250
251 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1
253
254 dwc2: usb@ff400000 {
255 compatible = "
256 reg = <0x0 0xf
257 interrupts = <
258 clocks = <&clk
259 clock-names =
260 phys = <&usb2_
261 dr_mode = "per
262 g-rx-fifo-size
263 g-np-tx-fifo-s
264 g-tx-fifo-size
265 };
266
267 dwc3: usb@ff500000 {
268 compatible = "
269 reg = <0x0 0xf
270 interrupts = <
271 dr_mode = "hos
272 maximum-speed
273 snps,dis_u2_su
274 };
275 };
276
277 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic,
279 "snps,dwm
280 "snps,dwm
281 reg = <0x0 0xff3f0000
282 <0x0 0xff634540
283 interrupts = <GIC_SPI
284 interrupt-names = "mac
285 clocks = <&clkc CLKID_
286 <&clkc CLKID_
287 <&clkc CLKID_
288 <&clkc CLKID_
289 clock-names = "stmmace
290 "timing-
291 rx-fifo-depth = <4096>
292 tx-fifo-depth = <2048>
293 power-domains = <&pwrc
294 status = "disabled";
295 };
296
297 pcie_phy: phy@ff644000 {
298 compatible = "amlogic,
299 reg = <0x0 0xff644000
300 resets = <&reset RESET
301 phys = <&mipi_pcie_ana
302 phy-names = "analog";
303 #phy-cells = <0>;
304 };
305
306 pdm: audio-controller@ff632000
307 compatible = "amlogic,
308 reg = <0x0 0xff632000
309 #sound-dai-cells = <0>
310 sound-name-prefix = "P
311 clocks = <&clkc_audio
312 <&clkc_audio
313 <&clkc_audio
314 clock-names = "pclk",
315 status = "disabled";
316 };
317
318 periphs: bus@ff634000 {
319 compatible = "simple-b
320 reg = <0x0 0xff634000
321 #address-cells = <2>;
322 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0
324
325 hwrng: rng@18 {
326 compatible = "
327 reg = <0x0 0x1
328 clocks = <&clk
329 clock-names =
330 };
331
332 pinctrl_periphs: pinct
333 compatible = "
334 #address-cells
335 #size-cells =
336 ranges;
337
338 gpio: bank@480
339 reg =
340
341
342
343 reg-na
344 gpio-c
345 #gpio-
346 gpio-r
347 };
348
349 i2c0_pins: i2c
350 mux {
351
352
353
354
355 };
356 };
357
358 i2c1_x_pins: i
359 mux {
360
361
362
363
364 };
365 };
366
367 i2c1_z_pins: i
368 mux {
369
370
371
372
373 };
374 };
375
376 i2c2_a_pins: i
377 mux {
378
379
380
381
382 };
383 };
384
385 i2c2_x_pins: i
386 mux {
387
388
389
390
391 };
392 };
393
394 i2c3_a6_pins:
395 mux {
396
397
398
399
400 };
401 };
402
403 i2c3_a12_pins:
404 mux {
405
406
407
408
409 };
410 };
411
412 i2c3_a19_pins:
413 mux {
414
415
416
417
418 };
419 };
420
421 emmc_pins: emm
422 mux-0
423
424
425
426
427
428
429
430
431
432
433
434 };
435
436 mux-1
437
438
439
440 };
441 };
442
443 nand_all_pins:
444 mux {
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461 };
462 };
463
464 emmc_ds_pins:
465 mux {
466
467
468
469 };
470 };
471
472 emmc_clk_gate_
473 mux {
474
475
476
477 };
478 };
479
480 eth_rgmii_x_pi
481 mux {
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498 };
499 };
500
501 eth_rgmii_y_pi
502 mux {
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519 };
520 };
521
522 eth_rmii_x_pin
523 mux {
524
525
526
527
528
529
530
531
532
533
534
535 };
536 };
537
538 eth_rmii_y_pin
539 mux {
540
541
542
543
544
545
546
547
548
549
550
551 };
552 };
553
554 mclk_b_pins: m
555 mux {
556
557
558
559 };
560 };
561
562 mclk_c_pins: m
563 mux {
564
565
566
567 };
568 };
569
570 pdm_dclk_a14_p
571 mux {
572
573
574
575 };
576 };
577
578 pdm_dclk_a19_p
579 mux {
580
581
582
583 };
584 };
585
586 pdm_din0_pins:
587 mux {
588
589
590
591 };
592 };
593
594 pdm_din1_pins:
595 mux {
596
597
598
599 };
600 };
601
602 pdm_din2_pins:
603 mux {
604
605
606
607 };
608 };
609
610 pdm_din3_pins:
611 mux {
612
613
614
615 };
616 };
617
618 pwm_a_a_pins:
619 mux {
620
621
622
623 };
624 };
625
626 pwm_a_x18_pins
627 mux {
628
629
630
631 };
632 };
633
634 pwm_a_x20_pins
635 mux {
636
637
638
639 };
640 };
641
642 pwm_a_z_pins:
643 mux {
644
645
646
647 };
648 };
649
650 pwm_b_a_pins:
651 mux {
652
653
654
655 };
656 };
657
658 pwm_b_x_pins:
659 mux {
660
661
662
663 };
664 };
665
666 pwm_b_z_pins:
667 mux {
668
669
670
671 };
672 };
673
674 pwm_c_a_pins:
675 mux {
676
677
678
679 };
680 };
681
682 pwm_c_x10_pins
683 mux {
684
685
686
687 };
688 };
689
690 pwm_c_x17_pins
691 mux {
692
693
694
695 };
696 };
697
698 pwm_d_x11_pins
699 mux {
700
701
702
703 };
704 };
705
706 pwm_d_x16_pins
707 mux {
708
709
710
711 };
712 };
713
714 sdio_pins: sdi
715 mux-0
716
717
718
719
720
721
722
723 };
724
725 mux-1
726
727
728
729 };
730 };
731
732 sdio_clk_gate_
733 mux {
734
735
736
737 };
738 };
739
740 spdif_in_z_pin
741 mux {
742
743
744
745 };
746 };
747
748 spdif_in_a1_pi
749 mux {
750
751
752
753 };
754 };
755
756 spdif_in_a7_pi
757 mux {
758
759
760
761 };
762 };
763
764 spdif_in_a19_p
765 mux {
766
767
768
769 };
770 };
771
772 spdif_in_a20_p
773 mux {
774
775
776
777 };
778 };
779
780 spdif_out_a1_p
781 mux {
782
783
784
785 };
786 };
787
788 spdif_out_a11_
789 mux {
790
791
792
793 };
794 };
795
796 spdif_out_a19_
797 mux {
798
799
800
801 };
802 };
803
804 spdif_out_a20_
805 mux {
806
807
808
809 };
810 };
811
812 spdif_out_z_pi
813 mux {
814
815
816
817 };
818 };
819
820 spi0_pins: spi
821 mux {
822
823
824
825
826
827 };
828 };
829
830 spi0_ss0_pins:
831 mux {
832
833
834
835 };
836 };
837
838 spi0_ss1_pins:
839 mux {
840
841
842
843 };
844 };
845
846 spi0_ss2_pins:
847 mux {
848
849
850
851 };
852 };
853
854 spi1_a_pins: s
855 mux {
856
857
858
859
860
861 };
862 };
863
864 spi1_ss0_a_pin
865 mux {
866
867
868
869 };
870 };
871
872 spi1_ss1_pins:
873 mux {
874
875
876
877 };
878 };
879
880 spi1_x_pins: s
881 mux {
882
883
884
885
886
887 };
888 };
889
890 spi1_ss0_x_pin
891 mux {
892
893
894
895 };
896 };
897
898 tdma_din0_pins
899 mux {
900
901
902
903 };
904 };
905
906 tdma_dout0_x14
907 mux {
908
909
910
911 };
912 };
913
914 tdma_dout0_x15
915 mux {
916
917
918
919 };
920 };
921
922 tdma_dout1_pin
923 mux {
924
925
926
927 };
928 };
929
930 tdma_din1_pins
931 mux {
932
933
934
935 };
936 };
937
938 tdma_fs_pins:
939 mux {
940
941
942
943 };
944 };
945
946 tdma_fs_slv_pi
947 mux {
948
949
950
951 };
952 };
953
954 tdma_sclk_pins
955 mux {
956
957
958
959 };
960 };
961
962 tdma_sclk_slv_
963 mux {
964
965
966
967 };
968 };
969
970 tdmb_din0_pins
971 mux {
972
973
974
975 };
976 };
977
978 tdmb_din1_pins
979 mux {
980
981
982
983 };
984 };
985
986 tdmb_din2_pins
987 mux {
988
989
990
991 };
992 };
993
994 tdmb_din3_pins
995 mux {
996
997
998
999 };
1000 };
1001
1002 tdmb_dout0_pi
1003 mux {
1004
1005
1006
1007 };
1008 };
1009
1010 tdmb_dout1_pi
1011 mux {
1012
1013
1014
1015 };
1016 };
1017
1018 tdmb_dout2_pi
1019 mux {
1020
1021
1022
1023 };
1024 };
1025
1026 tdmb_dout3_pi
1027 mux {
1028
1029
1030
1031 };
1032 };
1033
1034 tdmb_fs_pins:
1035 mux {
1036
1037
1038
1039 };
1040 };
1041
1042 tdmb_fs_slv_p
1043 mux {
1044
1045
1046
1047 };
1048 };
1049
1050 tdmb_sclk_pin
1051 mux {
1052
1053
1054
1055 };
1056 };
1057
1058 tdmb_sclk_slv
1059 mux {
1060
1061
1062
1063 };
1064 };
1065
1066 tdmc_fs_pins:
1067 mux {
1068
1069
1070
1071 };
1072 };
1073
1074 tdmc_fs_slv_p
1075 mux {
1076
1077
1078
1079 };
1080 };
1081
1082 tdmc_sclk_pin
1083 mux {
1084
1085
1086
1087 };
1088 };
1089
1090 tdmc_sclk_slv
1091 mux {
1092
1093
1094
1095 };
1096 };
1097
1098 tdmc_din0_pin
1099 mux {
1100
1101
1102
1103 };
1104 };
1105
1106 tdmc_din1_pin
1107 mux {
1108
1109
1110
1111 };
1112 };
1113
1114 tdmc_din2_pin
1115 mux {
1116
1117
1118
1119 };
1120 };
1121
1122 tdmc_din3_pin
1123 mux {
1124
1125
1126
1127 };
1128 };
1129
1130 tdmc_dout0_pi
1131 mux {
1132
1133
1134
1135 };
1136 };
1137
1138 tdmc_dout1_pi
1139 mux {
1140
1141
1142
1143 };
1144 };
1145
1146 tdmc_dout2_pi
1147 mux {
1148
1149
1150
1151 };
1152 };
1153
1154 tdmc_dout3_pi
1155 mux {
1156
1157
1158
1159 };
1160 };
1161
1162 uart_a_pins:
1163 mux {
1164
1165
1166
1167
1168 };
1169 };
1170
1171 uart_a_cts_rt
1172 mux {
1173
1174
1175
1176
1177 };
1178 };
1179
1180 uart_b_x_pins
1181 mux {
1182
1183
1184
1185
1186 };
1187 };
1188
1189 uart_b_x_cts_
1190 mux {
1191
1192
1193
1194
1195 };
1196 };
1197
1198 uart_b_z_pins
1199 mux {
1200
1201
1202
1203
1204 };
1205 };
1206
1207 uart_b_z_cts_
1208 mux {
1209
1210
1211
1212
1213 };
1214 };
1215
1216 uart_ao_b_z_p
1217 mux {
1218
1219
1220
1221
1222 };
1223 };
1224
1225 uart_ao_b_z_c
1226 mux {
1227
1228
1229
1230
1231 };
1232 };
1233 };
1234 };
1235
1236 hiubus: bus@ff63c000 {
1237 compatible = "simple-
1238 reg = <0x0 0xff63c000
1239 #address-cells = <2>;
1240 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0
1242
1243 sysctrl: system-contr
1244 compatible =
1245
1246 reg = <0 0 0
1247
1248 clkc: clock-c
1249 compa
1250 #cloc
1251 clock
1252 clock
1253 };
1254
1255 pwrc: power-c
1256 compa
1257 #powe
1258 amlog
1259 reset
1260
1261
1262
1263
1264 reset
1265
1266 clock
1267
1268 clock
1269 /*
1270 * VP
1271 * VP
1272 * fr
1273 * Sa
1274 */
1275 assig
1276
1277
1278
1279
1280
1281 assig
1282
1283
1284
1285
1286
1287 assig
1288
1289
1290
1291
1292
1293 };
1294
1295 mipi_pcie_ana
1296 compa
1297 #phy-
1298 statu
1299 };
1300 };
1301 };
1302
1303 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic
1305 reg = <0 0xff63c404 0
1306 interrupts = <GIC_SPI
1307 <GIC_SPI
1308 <GIC_SPI
1309 #mbox-cells = <1>;
1310 };
1311
1312 mipi_dphy: phy@ff640000 {
1313 compatible = "amlogic
1314 reg = <0x0 0xff640000
1315 clocks = <&clkc CLKID
1316 clock-names = "pclk";
1317 resets = <&reset RESE
1318 reset-names = "phy";
1319 phys = <&mipi_pcie_an
1320 phy-names = "analog";
1321 #phy-cells = <0>;
1322 status = "disabled";
1323 };
1324
1325 audio: bus@ff642000 {
1326 compatible = "simple-
1327 reg = <0x0 0xff642000
1328 #address-cells = <2>;
1329 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0
1331
1332 clkc_audio: clock-con
1333 compatible =
1334 reg = <0x0 0x
1335 #clock-cells
1336
1337 clocks = <&cl
1338 <&cl
1339 <&cl
1340 <&cl
1341 <&cl
1342 <&cl
1343 <&cl
1344 <&cl
1345 <&cl
1346 clock-names =
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356 resets = <&re
1357 };
1358
1359 toddr_a: audio-contro
1360 compatible =
1361 reg = <0x0 0x
1362 #sound-dai-ce
1363 sound-name-pr
1364 interrupts =
1365 clocks = <&cl
1366 resets = <&ar
1367 amlogic,fifo-
1368 status = "dis
1369 };
1370
1371 toddr_b: audio-contro
1372 compatible =
1373 reg = <0x0 0x
1374 #sound-dai-ce
1375 sound-name-pr
1376 interrupts =
1377 clocks = <&cl
1378 resets = <&ar
1379 amlogic,fifo-
1380 status = "dis
1381 };
1382
1383 toddr_c: audio-contro
1384 compatible =
1385 reg = <0x0 0x
1386 #sound-dai-ce
1387 sound-name-pr
1388 interrupts =
1389 clocks = <&cl
1390 resets = <&ar
1391 amlogic,fifo-
1392 status = "dis
1393 };
1394
1395 frddr_a: audio-contro
1396 compatible =
1397 reg = <0x0 0x
1398 #sound-dai-ce
1399 sound-name-pr
1400 interrupts =
1401 clocks = <&cl
1402 resets = <&ar
1403 amlogic,fifo-
1404 status = "dis
1405 };
1406
1407 frddr_b: audio-contro
1408 compatible =
1409 reg = <0x0 0x
1410 #sound-dai-ce
1411 sound-name-pr
1412 interrupts =
1413 clocks = <&cl
1414 resets = <&ar
1415 amlogic,fifo-
1416 status = "dis
1417 };
1418
1419 frddr_c: audio-contro
1420 compatible =
1421 reg = <0x0 0x
1422 #sound-dai-ce
1423 sound-name-pr
1424 interrupts =
1425 clocks = <&cl
1426 resets = <&ar
1427 amlogic,fifo-
1428 status = "dis
1429 };
1430
1431 arb: reset-controller
1432 compatible =
1433 reg = <0x0 0x
1434 #reset-cells
1435 clocks = <&cl
1436 };
1437
1438 tdmin_a: audio-contro
1439 compatible =
1440 reg = <0x0 0x
1441 sound-name-pr
1442 clocks = <&cl
1443 <&cl
1444 <&cl
1445 <&cl
1446 <&cl
1447 clock-names =
1448
1449 status = "dis
1450 };
1451
1452 tdmin_b: audio-contro
1453 compatible =
1454 reg = <0x0 0x
1455 sound-name-pr
1456 clocks = <&cl
1457 <&cl
1458 <&cl
1459 <&cl
1460 <&cl
1461 clock-names =
1462
1463 status = "dis
1464 };
1465
1466 tdmin_c: audio-contro
1467 compatible =
1468 reg = <0x0 0x
1469 sound-name-pr
1470 clocks = <&cl
1471 <&cl
1472 <&cl
1473 <&cl
1474 <&cl
1475 clock-names =
1476
1477 status = "dis
1478 };
1479
1480 tdmin_lb: audio-contr
1481 compatible =
1482 reg = <0x0 0x
1483 sound-name-pr
1484 clocks = <&cl
1485 <&cl
1486 <&cl
1487 <&cl
1488 <&cl
1489 clock-names =
1490
1491 status = "dis
1492 };
1493
1494 spdifin: audio-contro
1495 compatible =
1496 reg = <0x0 0x
1497 #sound-dai-ce
1498 sound-name-pr
1499 interrupts =
1500 clocks = <&cl
1501 <&cl
1502 clock-names =
1503 status = "dis
1504 };
1505
1506 spdifout: audio-contr
1507 compatible =
1508 reg = <0x0 0x
1509 #sound-dai-ce
1510 sound-name-pr
1511 clocks = <&cl
1512 <&cl
1513 clock-names =
1514 status = "dis
1515 };
1516
1517 tdmout_a: audio-contr
1518 compatible =
1519 reg = <0x0 0x
1520 sound-name-pr
1521 clocks = <&cl
1522 <&cl
1523 <&cl
1524 <&cl
1525 <&cl
1526 clock-names =
1527
1528 status = "dis
1529 };
1530
1531 tdmout_b: audio-contr
1532 compatible =
1533 reg = <0x0 0x
1534 sound-name-pr
1535 clocks = <&cl
1536 <&cl
1537 <&cl
1538 <&cl
1539 <&cl
1540 clock-names =
1541
1542 status = "dis
1543 };
1544
1545 tdmout_c: audio-contr
1546 compatible =
1547 reg = <0x0 0x
1548 sound-name-pr
1549 clocks = <&cl
1550 <&cl
1551 <&cl
1552 <&cl
1553 <&cl
1554 clock-names =
1555
1556 status = "dis
1557 };
1558 };
1559
1560 aobus: bus@ff800000 {
1561 compatible = "simple-
1562 reg = <0x0 0xff800000
1563 #address-cells = <2>;
1564 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0
1566
1567 sysctrl_AO: sys-ctrl@
1568 compatible =
1569 reg = <0x0 0x
1570
1571 clkc_AO: cloc
1572 compa
1573 #cloc
1574 #rese
1575 clock
1576 clock
1577 };
1578 };
1579
1580 pinctrl_aobus: pinctr
1581 compatible =
1582 #address-cell
1583 #size-cells =
1584 ranges;
1585
1586 gpio_ao: bank
1587 reg =
1588
1589
1590 reg-n
1591 gpio-
1592 #gpio
1593 gpio-
1594 };
1595
1596 i2c_ao_sck_4_
1597 mux {
1598
1599
1600
1601 };
1602 };
1603
1604 i2c_ao_sck_8_
1605 mux {
1606
1607
1608
1609 };
1610 };
1611
1612 i2c_ao_sck_10
1613 mux {
1614
1615
1616
1617 };
1618 };
1619
1620 i2c_ao_sda_5_
1621 mux {
1622
1623
1624
1625 };
1626 };
1627
1628 i2c_ao_sda_9_
1629 mux {
1630
1631
1632
1633 };
1634 };
1635
1636 i2c_ao_sda_11
1637 mux {
1638
1639
1640
1641 };
1642 };
1643
1644 remote_input_
1645 mux {
1646
1647
1648
1649 };
1650 };
1651
1652 uart_ao_a_pin
1653 mux {
1654
1655
1656
1657
1658 };
1659 };
1660
1661 uart_ao_a_cts
1662 mux {
1663
1664
1665
1666
1667 };
1668 };
1669
1670 uart_ao_b_pin
1671 mux {
1672
1673
1674
1675
1676 };
1677 };
1678
1679 uart_ao_b_cts
1680 mux {
1681
1682
1683
1684
1685 };
1686 };
1687 };
1688
1689 sec_AO: ao-secure@140
1690 compatible =
1691 reg = <0x0 0x
1692 amlogic,has-c
1693 };
1694
1695 pwm_AO_cd: pwm@2000 {
1696 compatible =
1697 reg = <0x0 0x
1698 #pwm-cells =
1699 status = "dis
1700 };
1701
1702 uart_AO: serial@3000
1703 compatible =
1704 reg = <0x0 0x
1705 interrupts =
1706 clocks = <&xt
1707 clock-names =
1708 status = "dis
1709 };
1710
1711 uart_AO_B: serial@400
1712 compatible =
1713 reg = <0x0 0x
1714 interrupts =
1715 clocks = <&xt
1716 clock-names =
1717 status = "dis
1718 };
1719
1720 i2c_AO: i2c@5000 {
1721 compatible =
1722 reg = <0x0 0x
1723 interrupts =
1724 clocks = <&cl
1725 #address-cell
1726 #size-cells =
1727 status = "dis
1728 };
1729
1730 pwm_AO_ab: pwm@7000 {
1731 compatible =
1732 reg = <0x0 0x
1733 #pwm-cells =
1734 status = "dis
1735 };
1736
1737 ir: ir@8000 {
1738 compatible =
1739 reg = <0x0 0x
1740 interrupts =
1741 status = "dis
1742 };
1743
1744 saradc: adc@9000 {
1745 compatible =
1746 "amlo
1747 reg = <0x0 0x
1748 #io-channel-c
1749 interrupts =
1750 clocks = <&xt
1751 <&cl
1752 <&cl
1753 <&cl
1754 clock-names =
1755 status = "dis
1756 };
1757 };
1758
1759 ge2d: ge2d@ff940000 {
1760 compatible = "amlogic
1761 reg = <0x0 0xff940000
1762 interrupts = <GIC_SPI
1763 clocks = <&clkc CLKID
1764 resets = <&reset RESE
1765 };
1766
1767 gic: interrupt-controller@ffc
1768 compatible = "arm,gic
1769 reg = <0x0 0xffc01000
1770 <0x0 0xffc02000
1771 <0x0 0xffc04000
1772 <0x0 0xffc06000
1773 interrupt-controller;
1774 interrupts = <GIC_PPI
1775 (GIC_CPU_MASK
1776 #interrupt-cells = <3
1777 #address-cells = <0>;
1778 };
1779
1780 cbus: bus@ffd00000 {
1781 compatible = "simple-
1782 reg = <0x0 0xffd00000
1783 #address-cells = <2>;
1784 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0
1786
1787 reset: reset-controll
1788 compatible =
1789 reg = <0x0 0x
1790 #reset-cells
1791 };
1792
1793 gpio_intc: interrupt-
1794 compatible =
1795
1796 reg = <0x0 0x
1797 interrupt-con
1798 #interrupt-ce
1799 amlogic,chann
1800 };
1801
1802 watchdog@f0d0 {
1803 compatible =
1804 reg = <0x0 0x
1805 clocks = <&xt
1806 };
1807
1808 pwm_ab: pwm@1b000 {
1809 compatible =
1810 reg = <0x0 0x
1811 #pwm-cells =
1812 status = "dis
1813 };
1814
1815 pwm_cd: pwm@1a000 {
1816 compatible =
1817 reg = <0x0 0x
1818 #pwm-cells =
1819 status = "dis
1820 };
1821
1822 spicc0: spi@13000 {
1823 compatible =
1824 reg = <0x0 0x
1825 interrupts =
1826 clocks = <&cl
1827 clock-names =
1828 #address-cell
1829 #size-cells =
1830 status = "dis
1831 };
1832
1833 spicc1: spi@15000 {
1834 compatible =
1835 reg = <0x0 0x
1836 interrupts =
1837 clocks = <&cl
1838 clock-names =
1839 #address-cell
1840 #size-cells =
1841 status = "dis
1842 };
1843
1844 clk_msr: clock-measur
1845 compatible =
1846 reg = <0x0 0x
1847 };
1848
1849 i2c3: i2c@1c000 {
1850 compatible =
1851 reg = <0x0 0x
1852 interrupts =
1853 clocks = <&cl
1854 #address-cell
1855 #size-cells =
1856 status = "dis
1857 };
1858
1859 i2c2: i2c@1d000 {
1860 compatible =
1861 reg = <0x0 0x
1862 interrupts =
1863 clocks = <&cl
1864 #address-cell
1865 #size-cells =
1866 status = "dis
1867 };
1868
1869 i2c1: i2c@1e000 {
1870 compatible =
1871 reg = <0x0 0x
1872 interrupts =
1873 clocks = <&cl
1874 #address-cell
1875 #size-cells =
1876 status = "dis
1877 };
1878
1879 i2c0: i2c@1f000 {
1880 compatible =
1881 reg = <0x0 0x
1882 interrupts =
1883 clocks = <&cl
1884 #address-cell
1885 #size-cells =
1886 status = "dis
1887 };
1888
1889 uart_B: serial@23000
1890 compatible =
1891 reg = <0x0 0x
1892 interrupts =
1893 status = "dis
1894 clocks = <&xt
1895 clock-names =
1896 };
1897
1898 uart_A: serial@24000
1899 compatible =
1900 reg = <0x0 0x
1901 interrupts =
1902 status = "dis
1903 clocks = <&xt
1904 clock-names =
1905 fifo-size = <
1906 };
1907 };
1908
1909 apb: bus@ffe00000 {
1910 compatible = "simple-
1911 reg = <0x0 0xffe00000
1912 #address-cells = <2>;
1913 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0
1915
1916 sd_emmc_b: mmc@5000 {
1917 compatible =
1918 reg = <0x0 0x
1919 interrupts =
1920 status = "dis
1921 clocks = <&cl
1922 <&clk
1923 <&clk
1924 clock-names =
1925 resets = <&re
1926 };
1927
1928 sd_emmc_c: mmc@7000 {
1929 compatible =
1930 reg = <0x0 0x
1931 interrupts =
1932 status = "dis
1933 clocks = <&cl
1934 <&clk
1935 <&clk
1936 clock-names =
1937 resets = <&re
1938 };
1939
1940 nfc: nand-controller@
1941 compatible =
1942 reg = <0x0 0x
1943 <0x0 0x
1944 reg-names = "
1945 pinctrl-0 = <
1946 pinctrl-names
1947 #address-cell
1948 #size-cells =
1949 interrupts =
1950 clocks = <&cl
1951 <&cl
1952 clock-names =
1953 };
1954
1955 usb2_phy1: phy@9020 {
1956 compatible =
1957 #phy-cells =
1958 reg = <0x0 0x
1959 clocks = <&cl
1960 clock-names =
1961 resets = <&re
1962 reset-names =
1963 };
1964 };
1965
1966 sram: sram@fffc0000 {
1967 compatible = "mmio-sr
1968 reg = <0x0 0xfffc0000
1969 #address-cells = <1>;
1970 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff
1972
1973 cpu_scp_lpri: scp-sra
1974 compatible =
1975 reg = <0x1300
1976 };
1977
1978 cpu_scp_hpri: scp-sra
1979 compatible =
1980 reg = <0x1340
1981 };
1982 };
1983 };
1984
1985 timer {
1986 compatible = "arm,armv8-timer
1987 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf
1989 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf
1991 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf
1993 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf
1995 };
1996
1997 xtal: xtal-clk {
1998 compatible = "fixed-clock";
1999 clock-frequency = <24000000>;
2000 clock-output-names = "xtal";
2001 #clock-cells = <0>;
2002 };
2003 };
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