1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
>> 3 *
>> 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 */ 5 */
5 6
6 #include <dt-bindings/clock/axg-aoclkc.h> <<
7 #include <dt-bindings/clock/axg-audio-clkc.h> <<
8 #include <dt-bindings/clock/axg-clkc.h> <<
9 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> <<
11 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- !! 10 #include <dt-bindings/clock/axg-clkc.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- <<
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 11
17 / { 12 / {
18 compatible = "amlogic,meson-axg"; 13 compatible = "amlogic,meson-axg";
19 14
20 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 tdmif_a: audio-controller-0 { !! 19 reserved-memory {
25 compatible = "amlogic,axg-tdm- !! 20 #address-cells = <2>;
26 #sound-dai-cells = <0>; !! 21 #size-cells = <2>;
27 sound-name-prefix = "TDM_A"; !! 22 ranges;
28 clocks = <&clkc_audio AUD_CLKI <<
29 <&clkc_audio AUD_CLKI <<
30 <&clkc_audio AUD_CLKI <<
31 clock-names = "sclk", "lrclk", <<
32 status = "disabled"; <<
33 }; <<
34 <<
35 tdmif_b: audio-controller-1 { <<
36 compatible = "amlogic,axg-tdm- <<
37 #sound-dai-cells = <0>; <<
38 sound-name-prefix = "TDM_B"; <<
39 clocks = <&clkc_audio AUD_CLKI <<
40 <&clkc_audio AUD_CLKI <<
41 <&clkc_audio AUD_CLKI <<
42 clock-names = "sclk", "lrclk", <<
43 status = "disabled"; <<
44 }; <<
45 23
46 tdmif_c: audio-controller-2 { !! 24 /* 16 MiB reserved for Hardware ROM Firmware */
47 compatible = "amlogic,axg-tdm- !! 25 hwrom_reserved: hwrom@0 {
48 #sound-dai-cells = <0>; !! 26 reg = <0x0 0x0 0x0 0x1000000>;
49 sound-name-prefix = "TDM_C"; !! 27 no-map;
50 clocks = <&clkc_audio AUD_CLKI !! 28 };
51 <&clkc_audio AUD_CLKI <<
52 <&clkc_audio AUD_CLKI <<
53 clock-names = "sclk", "lrclk", <<
54 status = "disabled"; <<
55 }; <<
56 29
57 arm-pmu { !! 30 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
58 compatible = "arm,cortex-a53-p !! 31 secmon_reserved: secmon@5000000 {
59 interrupts = <GIC_SPI 137 IRQ_ !! 32 reg = <0x0 0x05000000 0x0 0x300000>;
60 <GIC_SPI 138 IRQ_ !! 33 no-map;
61 <GIC_SPI 153 IRQ_ !! 34 };
62 <GIC_SPI 154 IRQ_ <<
63 interrupt-affinity = <&cpu0>, <<
64 }; 35 };
65 36
66 cpus { 37 cpus {
67 #address-cells = <0x2>; 38 #address-cells = <0x2>;
68 #size-cells = <0x0>; 39 #size-cells = <0x0>;
69 40
70 cpu0: cpu@0 { 41 cpu0: cpu@0 {
71 device_type = "cpu"; 42 device_type = "cpu";
72 compatible = "arm,cort !! 43 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
74 enable-method = "psci" 45 enable-method = "psci";
75 next-level-cache = <&l 46 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 <<
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 47 };
80 48
81 cpu1: cpu@1 { 49 cpu1: cpu@1 {
82 device_type = "cpu"; 50 device_type = "cpu";
83 compatible = "arm,cort !! 51 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>; 52 reg = <0x0 0x1>;
85 enable-method = "psci" 53 enable-method = "psci";
86 next-level-cache = <&l 54 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 <<
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 55 };
91 56
92 cpu2: cpu@2 { 57 cpu2: cpu@2 {
93 device_type = "cpu"; 58 device_type = "cpu";
94 compatible = "arm,cort !! 59 compatible = "arm,cortex-a53", "arm,armv8";
95 reg = <0x0 0x2>; 60 reg = <0x0 0x2>;
96 enable-method = "psci" 61 enable-method = "psci";
97 next-level-cache = <&l 62 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 <<
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 63 };
102 64
103 cpu3: cpu@3 { 65 cpu3: cpu@3 {
104 device_type = "cpu"; 66 device_type = "cpu";
105 compatible = "arm,cort !! 67 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x3>; 68 reg = <0x0 0x3>;
107 enable-method = "psci" 69 enable-method = "psci";
108 next-level-cache = <&l 70 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 <<
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 71 };
113 72
114 l2: l2-cache0 { 73 l2: l2-cache0 {
115 compatible = "cache"; 74 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 75 };
119 }; 76 };
120 77
121 sm: secure-monitor { !! 78 arm-pmu {
122 compatible = "amlogic,meson-gx !! 79 compatible = "arm,cortex-a53-pmu";
123 }; !! 80 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
124 !! 81 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
125 efuse: efuse { !! 82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
126 compatible = "amlogic,meson-gx !! 83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&clkc CLKID_EFUSE>; !! 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
128 #address-cells = <1>; <<
129 #size-cells = <1>; <<
130 read-only; <<
131 secure-monitor = <&sm>; <<
132 }; 85 };
133 86
134 psci { 87 psci {
135 compatible = "arm,psci-1.0"; 88 compatible = "arm,psci-1.0";
136 method = "smc"; 89 method = "smc";
137 }; 90 };
138 91
139 reserved-memory { !! 92 timer {
140 #address-cells = <2>; !! 93 compatible = "arm,armv8-timer";
141 #size-cells = <2>; !! 94 interrupts = <GIC_PPI 13
142 ranges; !! 95 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
143 !! 96 <GIC_PPI 14
144 /* 16 MiB reserved for Hardwar !! 97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
145 hwrom_reserved: hwrom@0 { !! 98 <GIC_PPI 11
146 reg = <0x0 0x0 0x0 0x1 !! 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
147 no-map; !! 100 <GIC_PPI 10
148 }; !! 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
149 <<
150 /* Alternate 3 MiB reserved fo <<
151 secmon_reserved: secmon@500000 <<
152 reg = <0x0 0x05000000 <<
153 no-map; <<
154 }; <<
155 }; 102 };
156 103
157 scpi { !! 104 xtal: xtal-clk {
158 compatible = "arm,scpi-pre-1.0 !! 105 compatible = "fixed-clock";
159 mboxes = <&mailbox 1 &mailbox !! 106 clock-frequency = <24000000>;
160 shmem = <&cpu_scp_lpri &cpu_sc !! 107 clock-output-names = "xtal";
161 !! 108 #clock-cells = <0>;
162 scpi_clocks: clocks { <<
163 compatible = "arm,scpi <<
164 <<
165 scpi_dvfs: clocks-0 { <<
166 compatible = " <<
167 #clock-cells = <<
168 clock-indices <<
169 clock-output-n <<
170 }; <<
171 }; <<
172 <<
173 scpi_sensors: sensors { <<
174 compatible = "amlogic, <<
175 #thermal-sensor-cells <<
176 }; <<
177 }; 109 };
178 110
179 soc { 111 soc {
180 compatible = "simple-bus"; 112 compatible = "simple-bus";
181 #address-cells = <2>; 113 #address-cells = <2>;
182 #size-cells = <2>; 114 #size-cells = <2>;
183 ranges; 115 ranges;
184 116
185 pcieA: pcie@f9800000 { !! 117 cbus: bus@ffd00000 {
186 compatible = "amlogic, !! 118 compatible = "simple-bus";
187 reg = <0x0 0xf9800000 !! 119 reg = <0x0 0xffd00000 0x0 0x25000>;
188 <0x0 0xff646000 !! 120 #address-cells = <2>;
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; 121 #size-cells = <2>;
198 device_type = "pci"; !! 122 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
199 ranges = <0x82000000 0 <<
200 123
201 clocks = <&clkc CLKID_ !! 124 pwm_ab: pwm@1b000 {
202 clock-names = "general !! 125 compatible = "amlogic,meson-axg-ee-pwm";
203 resets = <&reset RESET !! 126 reg = <0x0 0x1b000 0x0 0x20>;
204 reset-names = "port", !! 127 #pwm-cells = <3>;
205 num-lanes = <1>; !! 128 status = "disabled";
206 phys = <&pcie_phy>; !! 129 };
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 130
211 pcieB: pcie@fa000000 { !! 131 pwm_cd: pwm@1a000 {
212 compatible = "amlogic, !! 132 compatible = "amlogic,meson-axg-ee-pwm";
213 reg = <0x0 0xfa000000 !! 133 reg = <0x0 0x1a000 0x0 0x20>;
214 <0x0 0xff648000 !! 134 #pwm-cells = <3>;
215 <0x0 0xfa400000 !! 135 status = "disabled";
216 reg-names = "elbi", "c !! 136 };
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 137
227 clocks = <&clkc CLKID_ !! 138 reset: reset-controller@1004 {
228 clock-names = "general !! 139 compatible = "amlogic,meson-axg-reset";
229 resets = <&reset RESET !! 140 reg = <0x0 0x01004 0x0 0x9c>;
230 reset-names = "port", !! 141 #reset-cells = <1>;
231 num-lanes = <1>; !! 142 };
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 143
237 usb: usb@ffe09080 { !! 144 spicc0: spi@13000 {
238 compatible = "amlogic, !! 145 compatible = "amlogic,meson-axg-spicc";
239 reg = <0x0 0xffe09080 !! 146 reg = <0x0 0x13000 0x0 0x3c>;
240 interrupts = <GIC_SPI !! 147 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; !! 148 clocks = <&clkc CLKID_SPICC0>;
242 #size-cells = <2>; !! 149 clock-names = "core";
243 ranges; !! 150 #address-cells = <1>;
>> 151 #size-cells = <0>;
>> 152 status = "disabled";
>> 153 };
>> 154
>> 155 spicc1: spi@15000 {
>> 156 compatible = "amlogic,meson-axg-spicc";
>> 157 reg = <0x0 0x15000 0x0 0x3c>;
>> 158 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
>> 159 clocks = <&clkc CLKID_SPICC1>;
>> 160 clock-names = "core";
>> 161 #address-cells = <1>;
>> 162 #size-cells = <0>;
>> 163 status = "disabled";
>> 164 };
244 165
245 clocks = <&clkc CLKID_ !! 166 uart_A: serial@24000 {
246 clock-names = "usb_ctr !! 167 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
247 resets = <&reset RESET !! 168 reg = <0x0 0x24000 0x0 0x18>;
248 !! 169 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
249 dr_mode = "otg"; !! 170 status = "disabled";
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; 171 };
266 172
267 dwc3: usb@ff500000 { !! 173 uart_B: serial@23000 {
268 compatible = " !! 174 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
269 reg = <0x0 0xf !! 175 reg = <0x0 0x23000 0x0 0x18>;
270 interrupts = < !! 176 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
271 dr_mode = "hos !! 177 status = "disabled";
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; 178 };
275 }; 179 };
276 180
277 ethmac: ethernet@ff3f0000 { 181 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, !! 182 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
279 "snps,dwm !! 183 reg = <0x0 0xff3f0000 0x0 0x10000
280 "snps,dwm !! 184 0x0 0xff634540 0x0 0x8>;
281 reg = <0x0 0xff3f0000 !! 185 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
282 <0x0 0xff634540 <<
283 interrupts = <GIC_SPI <<
284 interrupt-names = "mac 186 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 187 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 188 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 189 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 190 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 191 status = "disabled";
295 }; 192 };
296 193
297 pcie_phy: phy@ff644000 { !! 194 gic: interrupt-controller@ffc01000 {
298 compatible = "amlogic, !! 195 compatible = "arm,gic-400";
299 reg = <0x0 0xff644000 !! 196 reg = <0x0 0xffc01000 0 0x1000>,
300 resets = <&reset RESET !! 197 <0x0 0xffc02000 0 0x2000>,
301 phys = <&mipi_pcie_ana !! 198 <0x0 0xffc04000 0 0x2000>,
302 phy-names = "analog"; !! 199 <0x0 0xffc06000 0 0x2000>;
303 #phy-cells = <0>; !! 200 interrupt-controller;
>> 201 interrupts = <GIC_PPI 9
>> 202 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>> 203 #interrupt-cells = <3>;
>> 204 #address-cells = <0>;
304 }; 205 };
305 206
306 pdm: audio-controller@ff632000 !! 207 hiubus: bus@ff63c000 {
307 compatible = "amlogic, !! 208 compatible = "simple-bus";
308 reg = <0x0 0xff632000 !! 209 reg = <0x0 0xff63c000 0x0 0x1c00>;
309 #sound-dai-cells = <0> !! 210 #address-cells = <2>;
310 sound-name-prefix = "P !! 211 #size-cells = <2>;
311 clocks = <&clkc_audio !! 212 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
312 <&clkc_audio !! 213
313 <&clkc_audio !! 214 clkc: clock-controller@0 {
314 clock-names = "pclk", !! 215 compatible = "amlogic,axg-clkc";
315 status = "disabled"; !! 216 #clock-cells = <1>;
>> 217 reg = <0x0 0x0 0x0 0x320>;
>> 218 };
>> 219 };
>> 220
>> 221 mailbox: mailbox@ff63dc00 {
>> 222 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
>> 223 reg = <0 0xff63dc00 0 0x400>;
>> 224 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
>> 225 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
>> 226 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
>> 227 #mbox-cells = <1>;
316 }; 228 };
317 229
318 periphs: bus@ff634000 { !! 230 periphs: periphs@ff634000 {
319 compatible = "simple-b 231 compatible = "simple-bus";
320 reg = <0x0 0xff634000 232 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 233 #address-cells = <2>;
322 #size-cells = <2>; 234 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 235 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 236
325 hwrng: rng@18 { <<
326 compatible = " <<
327 reg = <0x0 0x1 <<
328 clocks = <&clk <<
329 clock-names = <<
330 }; <<
331 <<
332 pinctrl_periphs: pinct 237 pinctrl_periphs: pinctrl@480 {
333 compatible = " 238 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 239 #address-cells = <2>;
335 #size-cells = 240 #size-cells = <2>;
336 ranges; 241 ranges;
337 242
338 gpio: bank@480 243 gpio: bank@480 {
339 reg = 244 reg = <0x0 0x00480 0x0 0x40>,
340 !! 245 <0x0 0x004e8 0x0 0x14>,
341 !! 246 <0x0 0x00520 0x0 0x14>,
342 !! 247 <0x0 0x00430 0x0 0x3c>;
343 reg-na 248 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 249 gpio-controller;
345 #gpio- 250 #gpio-cells = <2>;
346 gpio-r 251 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 252 };
348 253
349 i2c0_pins: i2c <<
350 mux { <<
351 <<
352 <<
353 <<
354 <<
355 }; <<
356 }; <<
357 <<
358 i2c1_x_pins: i <<
359 mux { <<
360 <<
361 <<
362 <<
363 <<
364 }; <<
365 }; <<
366 <<
367 i2c1_z_pins: i <<
368 mux { <<
369 <<
370 <<
371 <<
372 <<
373 }; <<
374 }; <<
375 <<
376 i2c2_a_pins: i <<
377 mux { <<
378 <<
379 <<
380 <<
381 <<
382 }; <<
383 }; <<
384 <<
385 i2c2_x_pins: i <<
386 mux { <<
387 <<
388 <<
389 <<
390 <<
391 }; <<
392 }; <<
393 <<
394 i2c3_a6_pins: <<
395 mux { <<
396 <<
397 <<
398 <<
399 <<
400 }; <<
401 }; <<
402 <<
403 i2c3_a12_pins: <<
404 mux { <<
405 <<
406 <<
407 <<
408 <<
409 }; <<
410 }; <<
411 <<
412 i2c3_a19_pins: <<
413 mux { <<
414 <<
415 <<
416 <<
417 <<
418 }; <<
419 }; <<
420 <<
421 emmc_pins: emm <<
422 mux-0 <<
423 <<
424 <<
425 <<
426 <<
427 <<
428 <<
429 <<
430 <<
431 <<
432 <<
433 <<
434 }; <<
435 <<
436 mux-1 <<
437 <<
438 <<
439 <<
440 }; <<
441 }; <<
442 <<
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: <<
465 mux { <<
466 <<
467 <<
468 <<
469 }; <<
470 }; <<
471 <<
472 emmc_clk_gate_ <<
473 mux { <<
474 <<
475 <<
476 <<
477 }; <<
478 }; <<
479 <<
480 eth_rgmii_x_pi 254 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 255 mux {
482 256 groups = "eth_mdio_x",
483 !! 257 "eth_mdc_x",
484 !! 258 "eth_rgmii_rx_clk_x",
485 !! 259 "eth_rx_dv_x",
486 !! 260 "eth_rxd0_x",
487 !! 261 "eth_rxd1_x",
488 !! 262 "eth_rxd2_rgmii",
489 !! 263 "eth_rxd3_rgmii",
490 !! 264 "eth_rgmii_tx_clk",
491 !! 265 "eth_txen_x",
492 !! 266 "eth_txd0_x",
493 !! 267 "eth_txd1_x",
494 !! 268 "eth_txd2_rgmii",
495 !! 269 "eth_txd3_rgmii";
496 270 function = "eth";
497 <<
498 }; 271 };
499 }; 272 };
500 273
501 eth_rgmii_y_pi 274 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 275 mux {
503 276 groups = "eth_mdio_y",
504 !! 277 "eth_mdc_y",
505 !! 278 "eth_rgmii_rx_clk_y",
506 !! 279 "eth_rx_dv_y",
507 !! 280 "eth_rxd0_y",
508 !! 281 "eth_rxd1_y",
509 !! 282 "eth_rxd2_rgmii",
510 !! 283 "eth_rxd3_rgmii",
511 !! 284 "eth_rgmii_tx_clk",
512 !! 285 "eth_txen_y",
513 !! 286 "eth_txd0_y",
514 !! 287 "eth_txd1_y",
515 !! 288 "eth_txd2_rgmii",
516 !! 289 "eth_txd3_rgmii";
517 <<
518 <<
519 }; <<
520 }; <<
521 <<
522 eth_rmii_x_pin <<
523 mux { <<
524 <<
525 <<
526 <<
527 <<
528 <<
529 <<
530 <<
531 <<
532 <<
533 <<
534 <<
535 }; <<
536 }; <<
537 <<
538 eth_rmii_y_pin <<
539 mux { <<
540 <<
541 <<
542 <<
543 <<
544 <<
545 <<
546 <<
547 <<
548 <<
549 290 function = "eth";
550 <<
551 }; <<
552 }; <<
553 <<
554 mclk_b_pins: m <<
555 mux { <<
556 <<
557 <<
558 <<
559 }; <<
560 }; <<
561 <<
562 mclk_c_pins: m <<
563 mux { <<
564 <<
565 <<
566 <<
567 }; <<
568 }; <<
569 <<
570 pdm_dclk_a14_p <<
571 mux { <<
572 <<
573 <<
574 <<
575 }; <<
576 }; <<
577 <<
578 pdm_dclk_a19_p <<
579 mux { <<
580 <<
581 <<
582 <<
583 }; <<
584 }; <<
585 <<
586 pdm_din0_pins: <<
587 mux { <<
588 <<
589 <<
590 <<
591 }; <<
592 }; <<
593 <<
594 pdm_din1_pins: <<
595 mux { <<
596 <<
597 <<
598 <<
599 }; <<
600 }; <<
601 <<
602 pdm_din2_pins: <<
603 mux { <<
604 <<
605 <<
606 <<
607 }; <<
608 }; <<
609 <<
610 pdm_din3_pins: <<
611 mux { <<
612 <<
613 <<
614 <<
615 }; 291 };
616 }; 292 };
617 293
618 pwm_a_a_pins: 294 pwm_a_a_pins: pwm_a_a {
619 mux { 295 mux {
620 296 groups = "pwm_a_a";
621 297 function = "pwm_a";
622 <<
623 }; 298 };
624 }; 299 };
625 300
626 pwm_a_x18_pins 301 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 302 mux {
628 303 groups = "pwm_a_x18";
629 304 function = "pwm_a";
630 <<
631 }; 305 };
632 }; 306 };
633 307
634 pwm_a_x20_pins 308 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 309 mux {
636 310 groups = "pwm_a_x20";
637 311 function = "pwm_a";
638 <<
639 }; 312 };
640 }; 313 };
641 314
642 pwm_a_z_pins: 315 pwm_a_z_pins: pwm_a_z {
643 mux { 316 mux {
644 317 groups = "pwm_a_z";
645 318 function = "pwm_a";
646 <<
647 }; 319 };
648 }; 320 };
649 321
650 pwm_b_a_pins: 322 pwm_b_a_pins: pwm_b_a {
651 mux { 323 mux {
652 324 groups = "pwm_b_a";
653 325 function = "pwm_b";
654 <<
655 }; 326 };
656 }; 327 };
657 328
658 pwm_b_x_pins: 329 pwm_b_x_pins: pwm_b_x {
659 mux { 330 mux {
660 331 groups = "pwm_b_x";
661 332 function = "pwm_b";
662 <<
663 }; 333 };
664 }; 334 };
665 335
666 pwm_b_z_pins: 336 pwm_b_z_pins: pwm_b_z {
667 mux { 337 mux {
668 338 groups = "pwm_b_z";
669 339 function = "pwm_b";
670 <<
671 }; 340 };
672 }; 341 };
673 342
674 pwm_c_a_pins: 343 pwm_c_a_pins: pwm_c_a {
675 mux { 344 mux {
676 345 groups = "pwm_c_a";
677 346 function = "pwm_c";
678 <<
679 }; 347 };
680 }; 348 };
681 349
682 pwm_c_x10_pins 350 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 351 mux {
684 352 groups = "pwm_c_x10";
685 353 function = "pwm_c";
686 <<
687 }; 354 };
688 }; 355 };
689 356
690 pwm_c_x17_pins 357 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 358 mux {
692 359 groups = "pwm_c_x17";
693 360 function = "pwm_c";
694 <<
695 }; 361 };
696 }; 362 };
697 363
698 pwm_d_x11_pins 364 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 365 mux {
700 366 groups = "pwm_d_x11";
701 367 function = "pwm_d";
702 <<
703 }; 368 };
704 }; 369 };
705 370
706 pwm_d_x16_pins 371 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 372 mux {
708 373 groups = "pwm_d_x16";
709 374 function = "pwm_d";
710 <<
711 }; <<
712 }; <<
713 <<
714 sdio_pins: sdi <<
715 mux-0 <<
716 <<
717 <<
718 <<
719 <<
720 <<
721 <<
722 <<
723 }; <<
724 <<
725 mux-1 <<
726 <<
727 <<
728 <<
729 }; <<
730 }; <<
731 <<
732 sdio_clk_gate_ <<
733 mux { <<
734 <<
735 <<
736 <<
737 }; <<
738 }; <<
739 <<
740 spdif_in_z_pin <<
741 mux { <<
742 <<
743 <<
744 <<
745 }; <<
746 }; <<
747 <<
748 spdif_in_a1_pi <<
749 mux { <<
750 <<
751 <<
752 <<
753 }; <<
754 }; <<
755 <<
756 spdif_in_a7_pi <<
757 mux { <<
758 <<
759 <<
760 <<
761 }; <<
762 }; <<
763 <<
764 spdif_in_a19_p <<
765 mux { <<
766 <<
767 <<
768 <<
769 }; <<
770 }; <<
771 <<
772 spdif_in_a20_p <<
773 mux { <<
774 <<
775 <<
776 <<
777 }; <<
778 }; <<
779 <<
780 spdif_out_a1_p <<
781 mux { <<
782 <<
783 <<
784 <<
785 }; <<
786 }; <<
787 <<
788 spdif_out_a11_ <<
789 mux { <<
790 <<
791 <<
792 <<
793 }; <<
794 }; <<
795 <<
796 spdif_out_a19_ <<
797 mux { <<
798 <<
799 <<
800 <<
801 }; <<
802 }; <<
803 <<
804 spdif_out_a20_ <<
805 mux { <<
806 <<
807 <<
808 <<
809 }; <<
810 }; <<
811 <<
812 spdif_out_z_pi <<
813 mux { <<
814 <<
815 <<
816 <<
817 }; 375 };
818 }; 376 };
819 377
820 spi0_pins: spi 378 spi0_pins: spi0 {
821 mux { 379 mux {
822 380 groups = "spi0_miso",
823 !! 381 "spi0_mosi",
824 !! 382 "spi0_clk";
825 383 function = "spi0";
826 <<
827 }; 384 };
828 }; 385 };
829 386
830 spi0_ss0_pins: 387 spi0_ss0_pins: spi0_ss0 {
831 mux { 388 mux {
832 389 groups = "spi0_ss0";
833 390 function = "spi0";
834 <<
835 }; 391 };
836 }; 392 };
837 393
838 spi0_ss1_pins: 394 spi0_ss1_pins: spi0_ss1 {
839 mux { 395 mux {
840 396 groups = "spi0_ss1";
841 397 function = "spi0";
842 <<
843 }; 398 };
844 }; 399 };
845 400
846 spi0_ss2_pins: 401 spi0_ss2_pins: spi0_ss2 {
847 mux { 402 mux {
848 403 groups = "spi0_ss2";
849 404 function = "spi0";
850 <<
851 }; 405 };
852 }; 406 };
853 407
>> 408
854 spi1_a_pins: s 409 spi1_a_pins: spi1_a {
855 mux { 410 mux {
856 411 groups = "spi1_miso_a",
857 !! 412 "spi1_mosi_a",
858 !! 413 "spi1_clk_a";
859 414 function = "spi1";
860 <<
861 }; 415 };
862 }; 416 };
863 417
864 spi1_ss0_a_pin 418 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 419 mux {
866 420 groups = "spi1_ss0_a";
867 421 function = "spi1";
868 <<
869 }; 422 };
870 }; 423 };
871 424
872 spi1_ss1_pins: 425 spi1_ss1_pins: spi1_ss1 {
873 mux { 426 mux {
874 427 groups = "spi1_ss1";
875 428 function = "spi1";
876 <<
877 }; 429 };
878 }; 430 };
879 431
880 spi1_x_pins: s 432 spi1_x_pins: spi1_x {
881 mux { 433 mux {
882 434 groups = "spi1_miso_x",
883 !! 435 "spi1_mosi_x",
884 !! 436 "spi1_clk_x";
885 437 function = "spi1";
886 <<
887 }; 438 };
888 }; 439 };
889 440
890 spi1_ss0_x_pin 441 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 442 mux {
892 443 groups = "spi1_ss0_x";
893 444 function = "spi1";
894 <<
895 }; <<
896 }; <<
897 <<
898 tdma_din0_pins <<
899 mux { <<
900 <<
901 <<
902 <<
903 }; <<
904 }; <<
905 <<
906 tdma_dout0_x14 <<
907 mux { <<
908 <<
909 <<
910 <<
911 }; <<
912 }; <<
913 <<
914 tdma_dout0_x15 <<
915 mux { <<
916 <<
917 <<
918 <<
919 }; <<
920 }; <<
921 <<
922 tdma_dout1_pin <<
923 mux { <<
924 <<
925 <<
926 <<
927 }; <<
928 }; <<
929 <<
930 tdma_din1_pins <<
931 mux { <<
932 <<
933 <<
934 <<
935 }; <<
936 }; <<
937 <<
938 tdma_fs_pins: <<
939 mux { <<
940 <<
941 <<
942 <<
943 }; <<
944 }; <<
945 <<
946 tdma_fs_slv_pi <<
947 mux { <<
948 <<
949 <<
950 <<
951 }; <<
952 }; <<
953 <<
954 tdma_sclk_pins <<
955 mux { <<
956 <<
957 <<
958 <<
959 }; <<
960 }; <<
961 <<
962 tdma_sclk_slv_ <<
963 mux { <<
964 <<
965 <<
966 <<
967 }; <<
968 }; <<
969 <<
970 tdmb_din0_pins <<
971 mux { <<
972 <<
973 <<
974 <<
975 }; <<
976 }; <<
977 <<
978 tdmb_din1_pins <<
979 mux { <<
980 <<
981 <<
982 <<
983 }; <<
984 }; <<
985 <<
986 tdmb_din2_pins <<
987 mux { <<
988 <<
989 <<
990 <<
991 }; <<
992 }; <<
993 <<
994 tdmb_din3_pins <<
995 mux { <<
996 <<
997 <<
998 <<
999 }; <<
1000 }; <<
1001 <<
1002 tdmb_dout0_pi <<
1003 mux { <<
1004 <<
1005 <<
1006 <<
1007 }; <<
1008 }; <<
1009 <<
1010 tdmb_dout1_pi <<
1011 mux { <<
1012 <<
1013 <<
1014 <<
1015 }; <<
1016 }; <<
1017 <<
1018 tdmb_dout2_pi <<
1019 mux { <<
1020 <<
1021 <<
1022 <<
1023 }; <<
1024 }; <<
1025 <<
1026 tdmb_dout3_pi <<
1027 mux { <<
1028 <<
1029 <<
1030 <<
1031 }; <<
1032 }; <<
1033 <<
1034 tdmb_fs_pins: <<
1035 mux { <<
1036 <<
1037 <<
1038 <<
1039 }; <<
1040 }; <<
1041 <<
1042 tdmb_fs_slv_p <<
1043 mux { <<
1044 <<
1045 <<
1046 <<
1047 }; <<
1048 }; <<
1049 <<
1050 tdmb_sclk_pin <<
1051 mux { <<
1052 <<
1053 <<
1054 <<
1055 }; 445 };
1056 }; 446 };
1057 <<
1058 tdmb_sclk_slv <<
1059 mux { <<
1060 <<
1061 <<
1062 <<
1063 }; <<
1064 }; <<
1065 <<
1066 tdmc_fs_pins: <<
1067 mux { <<
1068 <<
1069 <<
1070 <<
1071 }; <<
1072 }; <<
1073 <<
1074 tdmc_fs_slv_p <<
1075 mux { <<
1076 <<
1077 <<
1078 <<
1079 }; <<
1080 }; <<
1081 <<
1082 tdmc_sclk_pin <<
1083 mux { <<
1084 <<
1085 <<
1086 <<
1087 }; <<
1088 }; <<
1089 <<
1090 tdmc_sclk_slv <<
1091 mux { <<
1092 <<
1093 <<
1094 <<
1095 }; <<
1096 }; <<
1097 <<
1098 tdmc_din0_pin <<
1099 mux { <<
1100 <<
1101 <<
1102 <<
1103 }; <<
1104 }; <<
1105 <<
1106 tdmc_din1_pin <<
1107 mux { <<
1108 <<
1109 <<
1110 <<
1111 }; <<
1112 }; <<
1113 <<
1114 tdmc_din2_pin <<
1115 mux { <<
1116 <<
1117 <<
1118 <<
1119 }; <<
1120 }; <<
1121 <<
1122 tdmc_din3_pin <<
1123 mux { <<
1124 <<
1125 <<
1126 <<
1127 }; <<
1128 }; <<
1129 <<
1130 tdmc_dout0_pi <<
1131 mux { <<
1132 <<
1133 <<
1134 <<
1135 }; <<
1136 }; <<
1137 <<
1138 tdmc_dout1_pi <<
1139 mux { <<
1140 <<
1141 <<
1142 <<
1143 }; <<
1144 }; <<
1145 <<
1146 tdmc_dout2_pi <<
1147 mux { <<
1148 <<
1149 <<
1150 <<
1151 }; <<
1152 }; <<
1153 <<
1154 tdmc_dout3_pi <<
1155 mux { <<
1156 <<
1157 <<
1158 <<
1159 }; <<
1160 }; <<
1161 <<
1162 uart_a_pins: <<
1163 mux { <<
1164 <<
1165 <<
1166 <<
1167 <<
1168 }; <<
1169 }; <<
1170 <<
1171 uart_a_cts_rt <<
1172 mux { <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 }; <<
1178 }; <<
1179 <<
1180 uart_b_x_pins <<
1181 mux { <<
1182 <<
1183 <<
1184 <<
1185 <<
1186 }; <<
1187 }; <<
1188 <<
1189 uart_b_x_cts_ <<
1190 mux { <<
1191 <<
1192 <<
1193 <<
1194 <<
1195 }; <<
1196 }; <<
1197 <<
1198 uart_b_z_pins <<
1199 mux { <<
1200 <<
1201 <<
1202 <<
1203 <<
1204 }; <<
1205 }; <<
1206 <<
1207 uart_b_z_cts_ <<
1208 mux { <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 }; <<
1214 }; <<
1215 <<
1216 uart_ao_b_z_p <<
1217 mux { <<
1218 <<
1219 <<
1220 <<
1221 <<
1222 }; <<
1223 }; <<
1224 <<
1225 uart_ao_b_z_c <<
1226 mux { <<
1227 <<
1228 <<
1229 <<
1230 <<
1231 }; <<
1232 }; <<
1233 }; <<
1234 }; <<
1235 <<
1236 hiubus: bus@ff63c000 { <<
1237 compatible = "simple- <<
1238 reg = <0x0 0xff63c000 <<
1239 #address-cells = <2>; <<
1240 #size-cells = <2>; <<
1241 ranges = <0x0 0x0 0x0 <<
1242 <<
1243 sysctrl: system-contr <<
1244 compatible = <<
1245 <<
1246 reg = <0 0 0 <<
1247 <<
1248 clkc: clock-c <<
1249 compa <<
1250 #cloc <<
1251 clock <<
1252 clock <<
1253 }; <<
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 447 };
1301 }; 448 };
1302 449
1303 mailbox: mailbox@ff63c404 { !! 450 sram: sram@fffc0000 {
1304 compatible = "amlogic !! 451 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1305 reg = <0 0xff63c404 0 !! 452 reg = <0x0 0xfffc0000 0x0 0x20000>;
1306 interrupts = <GIC_SPI !! 453 #address-cells = <1>;
1307 <GIC_SPI !! 454 #size-cells = <1>;
1308 <GIC_SPI !! 455 ranges = <0 0x0 0xfffc0000 0x20000>;
1309 #mbox-cells = <1>; <<
1310 }; <<
1311 <<
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { <<
1326 compatible = "simple- <<
1327 reg = <0x0 0xff642000 <<
1328 #address-cells = <2>; <<
1329 #size-cells = <2>; <<
1330 ranges = <0x0 0x0 0x0 <<
1331 <<
1332 clkc_audio: clock-con <<
1333 compatible = <<
1334 reg = <0x0 0x <<
1335 #clock-cells <<
1336 <<
1337 clocks = <&cl <<
1338 <&cl <<
1339 <&cl <<
1340 <&cl <<
1341 <&cl <<
1342 <&cl <<
1343 <&cl <<
1344 <&cl <<
1345 <&cl <<
1346 clock-names = <<
1347 <<
1348 <<
1349 <<
1350 <<
1351 <<
1352 <<
1353 <<
1354 <<
1355 <<
1356 resets = <&re <<
1357 }; <<
1358 <<
1359 toddr_a: audio-contro <<
1360 compatible = <<
1361 reg = <0x0 0x <<
1362 #sound-dai-ce <<
1363 sound-name-pr <<
1364 interrupts = <<
1365 clocks = <&cl <<
1366 resets = <&ar <<
1367 amlogic,fifo- <<
1368 status = "dis <<
1369 }; <<
1370 <<
1371 toddr_b: audio-contro <<
1372 compatible = <<
1373 reg = <0x0 0x <<
1374 #sound-dai-ce <<
1375 sound-name-pr <<
1376 interrupts = <<
1377 clocks = <&cl <<
1378 resets = <&ar <<
1379 amlogic,fifo- <<
1380 status = "dis <<
1381 }; <<
1382 <<
1383 toddr_c: audio-contro <<
1384 compatible = <<
1385 reg = <0x0 0x <<
1386 #sound-dai-ce <<
1387 sound-name-pr <<
1388 interrupts = <<
1389 clocks = <&cl <<
1390 resets = <&ar <<
1391 amlogic,fifo- <<
1392 status = "dis <<
1393 }; <<
1394 <<
1395 frddr_a: audio-contro <<
1396 compatible = <<
1397 reg = <0x0 0x <<
1398 #sound-dai-ce <<
1399 sound-name-pr <<
1400 interrupts = <<
1401 clocks = <&cl <<
1402 resets = <&ar <<
1403 amlogic,fifo- <<
1404 status = "dis <<
1405 }; <<
1406 <<
1407 frddr_b: audio-contro <<
1408 compatible = <<
1409 reg = <0x0 0x <<
1410 #sound-dai-ce <<
1411 sound-name-pr <<
1412 interrupts = <<
1413 clocks = <&cl <<
1414 resets = <&ar <<
1415 amlogic,fifo- <<
1416 status = "dis <<
1417 }; <<
1418 <<
1419 frddr_c: audio-contro <<
1420 compatible = <<
1421 reg = <0x0 0x <<
1422 #sound-dai-ce <<
1423 sound-name-pr <<
1424 interrupts = <<
1425 clocks = <&cl <<
1426 resets = <&ar <<
1427 amlogic,fifo- <<
1428 status = "dis <<
1429 }; <<
1430 <<
1431 arb: reset-controller <<
1432 compatible = <<
1433 reg = <0x0 0x <<
1434 #reset-cells <<
1435 clocks = <&cl <<
1436 }; <<
1437 <<
1438 tdmin_a: audio-contro <<
1439 compatible = <<
1440 reg = <0x0 0x <<
1441 sound-name-pr <<
1442 clocks = <&cl <<
1443 <&cl <<
1444 <&cl <<
1445 <&cl <<
1446 <&cl <<
1447 clock-names = <<
1448 <<
1449 status = "dis <<
1450 }; <<
1451 <<
1452 tdmin_b: audio-contro <<
1453 compatible = <<
1454 reg = <0x0 0x <<
1455 sound-name-pr <<
1456 clocks = <&cl <<
1457 <&cl <<
1458 <&cl <<
1459 <&cl <<
1460 <&cl <<
1461 clock-names = <<
1462 <<
1463 status = "dis <<
1464 }; <<
1465 <<
1466 tdmin_c: audio-contro <<
1467 compatible = <<
1468 reg = <0x0 0x <<
1469 sound-name-pr <<
1470 clocks = <&cl <<
1471 <&cl <<
1472 <&cl <<
1473 <&cl <<
1474 <&cl <<
1475 clock-names = <<
1476 <<
1477 status = "dis <<
1478 }; <<
1479 <<
1480 tdmin_lb: audio-contr <<
1481 compatible = <<
1482 reg = <0x0 0x <<
1483 sound-name-pr <<
1484 clocks = <&cl <<
1485 <&cl <<
1486 <&cl <<
1487 <&cl <<
1488 <&cl <<
1489 clock-names = <<
1490 <<
1491 status = "dis <<
1492 }; <<
1493 <<
1494 spdifin: audio-contro <<
1495 compatible = <<
1496 reg = <0x0 0x <<
1497 #sound-dai-ce <<
1498 sound-name-pr <<
1499 interrupts = <<
1500 clocks = <&cl <<
1501 <&cl <<
1502 clock-names = <<
1503 status = "dis <<
1504 }; <<
1505 <<
1506 spdifout: audio-contr <<
1507 compatible = <<
1508 reg = <0x0 0x <<
1509 #sound-dai-ce <<
1510 sound-name-pr <<
1511 clocks = <&cl <<
1512 <&cl <<
1513 clock-names = <<
1514 status = "dis <<
1515 }; <<
1516 <<
1517 tdmout_a: audio-contr <<
1518 compatible = <<
1519 reg = <0x0 0x <<
1520 sound-name-pr <<
1521 clocks = <&cl <<
1522 <&cl <<
1523 <&cl <<
1524 <&cl <<
1525 <&cl <<
1526 clock-names = <<
1527 <<
1528 status = "dis <<
1529 }; <<
1530 456
1531 tdmout_b: audio-contr !! 457 cpu_scp_lpri: scp-shmem@0 {
1532 compatible = !! 458 compatible = "amlogic,meson-axg-scp-shmem";
1533 reg = <0x0 0x !! 459 reg = <0x13000 0x400>;
1534 sound-name-pr <<
1535 clocks = <&cl <<
1536 <&cl <<
1537 <&cl <<
1538 <&cl <<
1539 <&cl <<
1540 clock-names = <<
1541 <<
1542 status = "dis <<
1543 }; 460 };
1544 461
1545 tdmout_c: audio-contr !! 462 cpu_scp_hpri: scp-shmem@200 {
1546 compatible = !! 463 compatible = "amlogic,meson-axg-scp-shmem";
1547 reg = <0x0 0x !! 464 reg = <0x13400 0x400>;
1548 sound-name-pr <<
1549 clocks = <&cl <<
1550 <&cl <<
1551 <&cl <<
1552 <&cl <<
1553 <&cl <<
1554 clock-names = <<
1555 <<
1556 status = "dis <<
1557 }; 465 };
1558 }; 466 };
1559 467
1560 aobus: bus@ff800000 { 468 aobus: bus@ff800000 {
1561 compatible = "simple- 469 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 470 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 471 #address-cells = <2>;
1564 #size-cells = <2>; 472 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 473 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 474
1567 sysctrl_AO: sys-ctrl@ <<
1568 compatible = <<
1569 reg = <0x0 0x <<
1570 <<
1571 clkc_AO: cloc <<
1572 compa <<
1573 #cloc <<
1574 #rese <<
1575 clock <<
1576 clock <<
1577 }; <<
1578 }; <<
1579 <<
1580 pinctrl_aobus: pinctr 475 pinctrl_aobus: pinctrl@14 {
1581 compatible = 476 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 477 #address-cells = <2>;
1583 #size-cells = 478 #size-cells = <2>;
1584 ranges; 479 ranges;
1585 480
1586 gpio_ao: bank 481 gpio_ao: bank@14 {
1587 reg = 482 reg = <0x0 0x00014 0x0 0x8>,
1588 !! 483 <0x0 0x0002c 0x0 0x4>,
1589 !! 484 <0x0 0x00024 0x0 0x8>;
1590 reg-n 485 reg-names = "mux", "pull", "gpio";
1591 gpio- 486 gpio-controller;
1592 #gpio 487 #gpio-cells = <2>;
1593 gpio- 488 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 489 };
1595 490
1596 i2c_ao_sck_4_ <<
1597 mux { <<
1598 <<
1599 <<
1600 <<
1601 }; <<
1602 }; <<
1603 <<
1604 i2c_ao_sck_8_ <<
1605 mux { <<
1606 <<
1607 <<
1608 <<
1609 }; <<
1610 }; <<
1611 <<
1612 i2c_ao_sck_10 <<
1613 mux { <<
1614 <<
1615 <<
1616 <<
1617 }; <<
1618 }; <<
1619 <<
1620 i2c_ao_sda_5_ <<
1621 mux { <<
1622 <<
1623 <<
1624 <<
1625 }; <<
1626 }; <<
1627 <<
1628 i2c_ao_sda_9_ <<
1629 mux { <<
1630 <<
1631 <<
1632 <<
1633 }; <<
1634 }; <<
1635 <<
1636 i2c_ao_sda_11 <<
1637 mux { <<
1638 <<
1639 <<
1640 <<
1641 }; <<
1642 }; <<
1643 <<
1644 remote_input_ 491 remote_input_ao_pins: remote_input_ao {
1645 mux { 492 mux {
1646 493 groups = "remote_input_ao";
1647 494 function = "remote_input_ao";
1648 <<
1649 }; <<
1650 }; <<
1651 <<
1652 uart_ao_a_pin <<
1653 mux { <<
1654 <<
1655 <<
1656 <<
1657 <<
1658 }; <<
1659 }; <<
1660 <<
1661 uart_ao_a_cts <<
1662 mux { <<
1663 <<
1664 <<
1665 <<
1666 <<
1667 }; <<
1668 }; <<
1669 <<
1670 uart_ao_b_pin <<
1671 mux { <<
1672 <<
1673 <<
1674 <<
1675 <<
1676 }; <<
1677 }; <<
1678 <<
1679 uart_ao_b_cts <<
1680 mux { <<
1681 <<
1682 <<
1683 <<
1684 <<
1685 }; 495 };
1686 }; 496 };
1687 }; 497 };
1688 498
1689 sec_AO: ao-secure@140 !! 499 pwm_AO_ab: pwm@7000 {
1690 compatible = !! 500 compatible = "amlogic,meson-axg-ao-pwm";
1691 reg = <0x0 0x !! 501 reg = <0x0 0x07000 0x0 0x20>;
1692 amlogic,has-c !! 502 #pwm-cells = <3>;
>> 503 status = "disabled";
1693 }; 504 };
1694 505
1695 pwm_AO_cd: pwm@2000 { 506 pwm_AO_cd: pwm@2000 {
1696 compatible = !! 507 compatible = "amlogic,axg-ao-pwm";
1697 reg = <0x0 0x 508 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 509 #pwm-cells = <3>;
1699 status = "dis 510 status = "disabled";
1700 }; 511 };
1701 512
1702 uart_AO: serial@3000 513 uart_AO: serial@3000 {
1703 compatible = 514 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 515 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 516 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt !! 517 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1707 clock-names = 518 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 519 status = "disabled";
1709 }; 520 };
1710 521
1711 uart_AO_B: serial@400 522 uart_AO_B: serial@4000 {
1712 compatible = 523 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 524 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 525 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt !! 526 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1716 clock-names = 527 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 528 status = "disabled";
1718 }; 529 };
1719 530
1720 i2c_AO: i2c@5000 { <<
1721 compatible = <<
1722 reg = <0x0 0x <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 #address-cell <<
1726 #size-cells = <<
1727 status = "dis <<
1728 }; <<
1729 <<
1730 pwm_AO_ab: pwm@7000 { <<
1731 compatible = <<
1732 reg = <0x0 0x <<
1733 #pwm-cells = <<
1734 status = "dis <<
1735 }; <<
1736 <<
1737 ir: ir@8000 { 531 ir: ir@8000 {
1738 compatible = 532 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 533 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 534 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 535 status = "disabled";
1742 }; 536 };
1743 <<
1744 saradc: adc@9000 { <<
1745 compatible = <<
1746 "amlo <<
1747 reg = <0x0 0x <<
1748 #io-channel-c <<
1749 interrupts = <<
1750 clocks = <&xt <<
1751 <&cl <<
1752 <&cl <<
1753 <&cl <<
1754 clock-names = <<
1755 status = "dis <<
1756 }; <<
1757 }; <<
1758 <<
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc <<
1768 compatible = "arm,gic <<
1769 reg = <0x0 0xffc01000 <<
1770 <0x0 0xffc02000 <<
1771 <0x0 0xffc04000 <<
1772 <0x0 0xffc06000 <<
1773 interrupt-controller; <<
1774 interrupts = <GIC_PPI <<
1775 (GIC_CPU_MASK <<
1776 #interrupt-cells = <3 <<
1777 #address-cells = <0>; <<
1778 }; <<
1779 <<
1780 cbus: bus@ffd00000 { <<
1781 compatible = "simple- <<
1782 reg = <0x0 0xffd00000 <<
1783 #address-cells = <2>; <<
1784 #size-cells = <2>; <<
1785 ranges = <0x0 0x0 0x0 <<
1786 <<
1787 reset: reset-controll <<
1788 compatible = <<
1789 reg = <0x0 0x <<
1790 #reset-cells <<
1791 }; <<
1792 <<
1793 gpio_intc: interrupt- <<
1794 compatible = <<
1795 <<
1796 reg = <0x0 0x <<
1797 interrupt-con <<
1798 #interrupt-ce <<
1799 amlogic,chann <<
1800 }; <<
1801 <<
1802 watchdog@f0d0 { <<
1803 compatible = <<
1804 reg = <0x0 0x <<
1805 clocks = <&xt <<
1806 }; <<
1807 <<
1808 pwm_ab: pwm@1b000 { <<
1809 compatible = <<
1810 reg = <0x0 0x <<
1811 #pwm-cells = <<
1812 status = "dis <<
1813 }; <<
1814 <<
1815 pwm_cd: pwm@1a000 { <<
1816 compatible = <<
1817 reg = <0x0 0x <<
1818 #pwm-cells = <<
1819 status = "dis <<
1820 }; <<
1821 <<
1822 spicc0: spi@13000 { <<
1823 compatible = <<
1824 reg = <0x0 0x <<
1825 interrupts = <<
1826 clocks = <&cl <<
1827 clock-names = <<
1828 #address-cell <<
1829 #size-cells = <<
1830 status = "dis <<
1831 }; <<
1832 <<
1833 spicc1: spi@15000 { <<
1834 compatible = <<
1835 reg = <0x0 0x <<
1836 interrupts = <<
1837 clocks = <&cl <<
1838 clock-names = <<
1839 #address-cell <<
1840 #size-cells = <<
1841 status = "dis <<
1842 }; <<
1843 <<
1844 clk_msr: clock-measur <<
1845 compatible = <<
1846 reg = <0x0 0x <<
1847 }; <<
1848 <<
1849 i2c3: i2c@1c000 { <<
1850 compatible = <<
1851 reg = <0x0 0x <<
1852 interrupts = <<
1853 clocks = <&cl <<
1854 #address-cell <<
1855 #size-cells = <<
1856 status = "dis <<
1857 }; <<
1858 <<
1859 i2c2: i2c@1d000 { <<
1860 compatible = <<
1861 reg = <0x0 0x <<
1862 interrupts = <<
1863 clocks = <&cl <<
1864 #address-cell <<
1865 #size-cells = <<
1866 status = "dis <<
1867 }; <<
1868 <<
1869 i2c1: i2c@1e000 { <<
1870 compatible = <<
1871 reg = <0x0 0x <<
1872 interrupts = <<
1873 clocks = <&cl <<
1874 #address-cell <<
1875 #size-cells = <<
1876 status = "dis <<
1877 }; <<
1878 <<
1879 i2c0: i2c@1f000 { <<
1880 compatible = <<
1881 reg = <0x0 0x <<
1882 interrupts = <<
1883 clocks = <&cl <<
1884 #address-cell <<
1885 #size-cells = <<
1886 status = "dis <<
1887 }; <<
1888 <<
1889 uart_B: serial@23000 <<
1890 compatible = <<
1891 reg = <0x0 0x <<
1892 interrupts = <<
1893 status = "dis <<
1894 clocks = <&xt <<
1895 clock-names = <<
1896 }; <<
1897 <<
1898 uart_A: serial@24000 <<
1899 compatible = <<
1900 reg = <0x0 0x <<
1901 interrupts = <<
1902 status = "dis <<
1903 clocks = <&xt <<
1904 clock-names = <<
1905 fifo-size = < <<
1906 }; <<
1907 }; <<
1908 <<
1909 apb: bus@ffe00000 { <<
1910 compatible = "simple- <<
1911 reg = <0x0 0xffe00000 <<
1912 #address-cells = <2>; <<
1913 #size-cells = <2>; <<
1914 ranges = <0x0 0x0 0x0 <<
1915 <<
1916 sd_emmc_b: mmc@5000 { <<
1917 compatible = <<
1918 reg = <0x0 0x <<
1919 interrupts = <<
1920 status = "dis <<
1921 clocks = <&cl <<
1922 <&clk <<
1923 <&clk <<
1924 clock-names = <<
1925 resets = <&re <<
1926 }; <<
1927 <<
1928 sd_emmc_c: mmc@7000 { <<
1929 compatible = <<
1930 reg = <0x0 0x <<
1931 interrupts = <<
1932 status = "dis <<
1933 clocks = <&cl <<
1934 <&clk <<
1935 <&clk <<
1936 clock-names = <<
1937 resets = <&re <<
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; <<
1965 <<
1966 sram: sram@fffc0000 { <<
1967 compatible = "mmio-sr <<
1968 reg = <0x0 0xfffc0000 <<
1969 #address-cells = <1>; <<
1970 #size-cells = <1>; <<
1971 ranges = <0 0x0 0xfff <<
1972 <<
1973 cpu_scp_lpri: scp-sra <<
1974 compatible = <<
1975 reg = <0x1300 <<
1976 }; <<
1977 <<
1978 cpu_scp_hpri: scp-sra <<
1979 compatible = <<
1980 reg = <0x1340 <<
1981 }; <<
1982 }; 537 };
1983 }; <<
1984 <<
1985 timer { <<
1986 compatible = "arm,armv8-timer <<
1987 interrupts = <GIC_PPI 13 <<
1988 (GIC_CPU_MASK_RAW(0xf <<
1989 <GIC_PPI 14 <<
1990 (GIC_CPU_MASK_RAW(0xf <<
1991 <GIC_PPI 11 <<
1992 (GIC_CPU_MASK_RAW(0xf <<
1993 <GIC_PPI 10 <<
1994 (GIC_CPU_MASK_RAW(0xf <<
1995 }; <<
1996 <<
1997 xtal: xtal-clk { <<
1998 compatible = "fixed-clock"; <<
1999 clock-frequency = <24000000>; <<
2000 clock-output-names = "xtal"; <<
2001 #clock-cells = <0>; <<
2002 }; 538 };
2003 }; 539 };
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