1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> <<
7 #include <dt-bindings/clock/axg-audio-clkc.h> <<
8 #include <dt-bindings/clock/axg-clkc.h> <<
9 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> <<
11 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- !! 9 #include <dt-bindings/clock/axg-clkc.h>
>> 10 #include <dt-bindings/clock/axg-aoclkc.h>
>> 11 #include <dt-bindings/gpio/meson-axg-gpio.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 12 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 13
17 / { 14 / {
18 compatible = "amlogic,meson-axg"; 15 compatible = "amlogic,meson-axg";
19 16
20 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
21 #address-cells = <2>; 18 #address-cells = <2>;
22 #size-cells = <2>; 19 #size-cells = <2>;
23 20
24 tdmif_a: audio-controller-0 { !! 21 reserved-memory {
25 compatible = "amlogic,axg-tdm- !! 22 #address-cells = <2>;
26 #sound-dai-cells = <0>; !! 23 #size-cells = <2>;
27 sound-name-prefix = "TDM_A"; !! 24 ranges;
28 clocks = <&clkc_audio AUD_CLKI <<
29 <&clkc_audio AUD_CLKI <<
30 <&clkc_audio AUD_CLKI <<
31 clock-names = "sclk", "lrclk", <<
32 status = "disabled"; <<
33 }; <<
34 <<
35 tdmif_b: audio-controller-1 { <<
36 compatible = "amlogic,axg-tdm- <<
37 #sound-dai-cells = <0>; <<
38 sound-name-prefix = "TDM_B"; <<
39 clocks = <&clkc_audio AUD_CLKI <<
40 <&clkc_audio AUD_CLKI <<
41 <&clkc_audio AUD_CLKI <<
42 clock-names = "sclk", "lrclk", <<
43 status = "disabled"; <<
44 }; <<
45 25
46 tdmif_c: audio-controller-2 { !! 26 /* 16 MiB reserved for Hardware ROM Firmware */
47 compatible = "amlogic,axg-tdm- !! 27 hwrom_reserved: hwrom@0 {
48 #sound-dai-cells = <0>; !! 28 reg = <0x0 0x0 0x0 0x1000000>;
49 sound-name-prefix = "TDM_C"; !! 29 no-map;
50 clocks = <&clkc_audio AUD_CLKI !! 30 };
51 <&clkc_audio AUD_CLKI <<
52 <&clkc_audio AUD_CLKI <<
53 clock-names = "sclk", "lrclk", <<
54 status = "disabled"; <<
55 }; <<
56 31
57 arm-pmu { !! 32 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
58 compatible = "arm,cortex-a53-p !! 33 secmon_reserved: secmon@5000000 {
59 interrupts = <GIC_SPI 137 IRQ_ !! 34 reg = <0x0 0x05000000 0x0 0x300000>;
60 <GIC_SPI 138 IRQ_ !! 35 no-map;
61 <GIC_SPI 153 IRQ_ !! 36 };
62 <GIC_SPI 154 IRQ_ <<
63 interrupt-affinity = <&cpu0>, <<
64 }; 37 };
65 38
66 cpus { 39 cpus {
67 #address-cells = <0x2>; 40 #address-cells = <0x2>;
68 #size-cells = <0x0>; 41 #size-cells = <0x0>;
69 42
70 cpu0: cpu@0 { 43 cpu0: cpu@0 {
71 device_type = "cpu"; 44 device_type = "cpu";
72 compatible = "arm,cort !! 45 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <0x0 0x0>; 46 reg = <0x0 0x0>;
74 enable-method = "psci" 47 enable-method = "psci";
75 next-level-cache = <&l 48 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 <<
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 49 };
80 50
81 cpu1: cpu@1 { 51 cpu1: cpu@1 {
82 device_type = "cpu"; 52 device_type = "cpu";
83 compatible = "arm,cort !! 53 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>; 54 reg = <0x0 0x1>;
85 enable-method = "psci" 55 enable-method = "psci";
86 next-level-cache = <&l 56 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 <<
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 57 };
91 58
92 cpu2: cpu@2 { 59 cpu2: cpu@2 {
93 device_type = "cpu"; 60 device_type = "cpu";
94 compatible = "arm,cort !! 61 compatible = "arm,cortex-a53", "arm,armv8";
95 reg = <0x0 0x2>; 62 reg = <0x0 0x2>;
96 enable-method = "psci" 63 enable-method = "psci";
97 next-level-cache = <&l 64 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 <<
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 65 };
102 66
103 cpu3: cpu@3 { 67 cpu3: cpu@3 {
104 device_type = "cpu"; 68 device_type = "cpu";
105 compatible = "arm,cort !! 69 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x3>; 70 reg = <0x0 0x3>;
107 enable-method = "psci" 71 enable-method = "psci";
108 next-level-cache = <&l 72 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 <<
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 73 };
113 74
114 l2: l2-cache0 { 75 l2: l2-cache0 {
115 compatible = "cache"; 76 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 77 };
119 }; 78 };
120 79
121 sm: secure-monitor { !! 80 arm-pmu {
122 compatible = "amlogic,meson-gx !! 81 compatible = "arm,cortex-a53-pmu";
123 }; !! 82 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
124 !! 83 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
125 efuse: efuse { !! 84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
126 compatible = "amlogic,meson-gx !! 85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&clkc CLKID_EFUSE>; !! 86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
128 #address-cells = <1>; <<
129 #size-cells = <1>; <<
130 read-only; <<
131 secure-monitor = <&sm>; <<
132 }; 87 };
133 88
134 psci { 89 psci {
135 compatible = "arm,psci-1.0"; 90 compatible = "arm,psci-1.0";
136 method = "smc"; 91 method = "smc";
137 }; 92 };
138 93
139 reserved-memory { !! 94 timer {
140 #address-cells = <2>; !! 95 compatible = "arm,armv8-timer";
141 #size-cells = <2>; !! 96 interrupts = <GIC_PPI 13
142 ranges; !! 97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
143 !! 98 <GIC_PPI 14
144 /* 16 MiB reserved for Hardwar !! 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
145 hwrom_reserved: hwrom@0 { !! 100 <GIC_PPI 11
146 reg = <0x0 0x0 0x0 0x1 !! 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
147 no-map; !! 102 <GIC_PPI 10
148 }; !! 103 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
149 <<
150 /* Alternate 3 MiB reserved fo <<
151 secmon_reserved: secmon@500000 <<
152 reg = <0x0 0x05000000 <<
153 no-map; <<
154 }; <<
155 }; 104 };
156 105
157 scpi { !! 106 xtal: xtal-clk {
158 compatible = "arm,scpi-pre-1.0 !! 107 compatible = "fixed-clock";
159 mboxes = <&mailbox 1 &mailbox !! 108 clock-frequency = <24000000>;
160 shmem = <&cpu_scp_lpri &cpu_sc !! 109 clock-output-names = "xtal";
161 !! 110 #clock-cells = <0>;
162 scpi_clocks: clocks { !! 111 };
163 compatible = "arm,scpi <<
164 <<
165 scpi_dvfs: clocks-0 { <<
166 compatible = " <<
167 #clock-cells = <<
168 clock-indices <<
169 clock-output-n <<
170 }; <<
171 }; <<
172 112
173 scpi_sensors: sensors { !! 113 ao_alt_xtal: ao_alt_xtal-clk {
174 compatible = "amlogic, !! 114 compatible = "fixed-clock";
175 #thermal-sensor-cells !! 115 clock-frequency = <32000000>;
176 }; !! 116 clock-output-names = "ao_alt_xtal";
>> 117 #clock-cells = <0>;
177 }; 118 };
178 119
179 soc { 120 soc {
180 compatible = "simple-bus"; 121 compatible = "simple-bus";
181 #address-cells = <2>; 122 #address-cells = <2>;
182 #size-cells = <2>; 123 #size-cells = <2>;
183 ranges; 124 ranges;
184 125
185 pcieA: pcie@f9800000 { !! 126 apb: apb@ffe00000 {
186 compatible = "amlogic, !! 127 compatible = "simple-bus";
187 reg = <0x0 0xf9800000 !! 128 reg = <0x0 0xffe00000 0x0 0x200000>;
188 <0x0 0xff646000 !! 129 #address-cells = <2>;
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; 130 #size-cells = <2>;
198 device_type = "pci"; !! 131 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 132
211 pcieB: pcie@fa000000 { !! 133 sd_emmc_b: sd@5000 {
212 compatible = "amlogic, !! 134 compatible = "amlogic,meson-axg-mmc";
213 reg = <0x0 0xfa000000 !! 135 reg = <0x0 0x5000 0x0 0x800>;
214 <0x0 0xff648000 !! 136 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
215 <0x0 0xfa400000 !! 137 status = "disabled";
216 reg-names = "elbi", "c !! 138 clocks = <&clkc CLKID_SD_EMMC_B>,
217 interrupts = <GIC_SPI !! 139 <&clkc CLKID_SD_EMMC_B_CLK0>,
218 #interrupt-cells = <1> !! 140 <&clkc CLKID_FCLK_DIV2>;
219 interrupt-map-mask = < !! 141 clock-names = "core", "clkin0", "clkin1";
220 interrupt-map = <0 0 0 !! 142 resets = <&reset RESET_SD_EMMC_B>;
221 bus-range = <0x0 0xff> !! 143 };
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 144
227 clocks = <&clkc CLKID_ !! 145 sd_emmc_c: mmc@7000 {
228 clock-names = "general !! 146 compatible = "amlogic,meson-axg-mmc";
229 resets = <&reset RESET !! 147 reg = <0x0 0x7000 0x0 0x800>;
230 reset-names = "port", !! 148 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
231 num-lanes = <1>; !! 149 status = "disabled";
232 phys = <&pcie_phy>; !! 150 clocks = <&clkc CLKID_SD_EMMC_C>,
233 phy-names = "pcie"; !! 151 <&clkc CLKID_SD_EMMC_C_CLK0>,
234 status = "disabled"; !! 152 <&clkc CLKID_FCLK_DIV2>;
>> 153 clock-names = "core", "clkin0", "clkin1";
>> 154 resets = <&reset RESET_SD_EMMC_C>;
>> 155 };
235 }; 156 };
236 157
237 usb: usb@ffe09080 { !! 158 cbus: bus@ffd00000 {
238 compatible = "amlogic, !! 159 compatible = "simple-bus";
239 reg = <0x0 0xffe09080 !! 160 reg = <0x0 0xffd00000 0x0 0x25000>;
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; 161 #address-cells = <2>;
242 #size-cells = <2>; 162 #size-cells = <2>;
243 ranges; !! 163 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
>> 164
>> 165 gpio_intc: interrupt-controller@f080 {
>> 166 compatible = "amlogic,meson-gpio-intc";
>> 167 reg = <0x0 0xf080 0x0 0x10>;
>> 168 interrupt-controller;
>> 169 #interrupt-cells = <2>;
>> 170 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
>> 171 status = "disabled";
>> 172 };
>> 173
>> 174 pwm_ab: pwm@1b000 {
>> 175 compatible = "amlogic,meson-axg-ee-pwm";
>> 176 reg = <0x0 0x1b000 0x0 0x20>;
>> 177 #pwm-cells = <3>;
>> 178 status = "disabled";
>> 179 };
>> 180
>> 181 pwm_cd: pwm@1a000 {
>> 182 compatible = "amlogic,meson-axg-ee-pwm";
>> 183 reg = <0x0 0x1a000 0x0 0x20>;
>> 184 #pwm-cells = <3>;
>> 185 status = "disabled";
>> 186 };
>> 187
>> 188 reset: reset-controller@1004 {
>> 189 compatible = "amlogic,meson-axg-reset";
>> 190 reg = <0x0 0x01004 0x0 0x9c>;
>> 191 #reset-cells = <1>;
>> 192 };
>> 193
>> 194 spicc0: spi@13000 {
>> 195 compatible = "amlogic,meson-axg-spicc";
>> 196 reg = <0x0 0x13000 0x0 0x3c>;
>> 197 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> 198 clocks = <&clkc CLKID_SPICC0>;
>> 199 clock-names = "core";
>> 200 #address-cells = <1>;
>> 201 #size-cells = <0>;
>> 202 status = "disabled";
>> 203 };
244 204
245 clocks = <&clkc CLKID_ !! 205 spicc1: spi@15000 {
246 clock-names = "usb_ctr !! 206 compatible = "amlogic,meson-axg-spicc";
247 resets = <&reset RESET !! 207 reg = <0x0 0x15000 0x0 0x3c>;
248 !! 208 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
249 dr_mode = "otg"; !! 209 clocks = <&clkc CLKID_SPICC1>;
250 !! 210 clock-names = "core";
251 phys = <&usb2_phy1>; !! 211 #address-cells = <1>;
252 phy-names = "usb2-phy1 !! 212 #size-cells = <0>;
253 !! 213 status = "disabled";
254 dwc2: usb@ff400000 { !! 214 };
255 compatible = " !! 215
256 reg = <0x0 0xf !! 216 i2c0: i2c@1f000 {
257 interrupts = < !! 217 compatible = "amlogic,meson-axg-i2c";
258 clocks = <&clk !! 218 reg = <0x0 0x1f000 0x0 0x20>;
259 clock-names = !! 219 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
260 phys = <&usb2_ !! 220 clocks = <&clkc CLKID_I2C>;
261 dr_mode = "per !! 221 #address-cells = <1>;
262 g-rx-fifo-size !! 222 #size-cells = <0>;
263 g-np-tx-fifo-s !! 223 status = "disabled";
264 g-tx-fifo-size !! 224 };
265 }; !! 225
266 !! 226 i2c1: i2c@1e000 {
267 dwc3: usb@ff500000 { !! 227 compatible = "amlogic,meson-axg-i2c";
268 compatible = " !! 228 reg = <0x0 0x1e000 0x0 0x20>;
269 reg = <0x0 0xf !! 229 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
270 interrupts = < !! 230 clocks = <&clkc CLKID_I2C>;
271 dr_mode = "hos !! 231 #address-cells = <1>;
272 maximum-speed !! 232 #size-cells = <0>;
273 snps,dis_u2_su !! 233 status = "disabled";
>> 234 };
>> 235
>> 236 i2c2: i2c@1d000 {
>> 237 compatible = "amlogic,meson-axg-i2c";
>> 238 reg = <0x0 0x1d000 0x0 0x20>;
>> 239 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
>> 240 clocks = <&clkc CLKID_I2C>;
>> 241 #address-cells = <1>;
>> 242 #size-cells = <0>;
>> 243 status = "disabled";
>> 244 };
>> 245
>> 246 i2c3: i2c@1c000 {
>> 247 compatible = "amlogic,meson-axg-i2c";
>> 248 reg = <0x0 0x1c000 0x0 0x20>;
>> 249 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
>> 250 clocks = <&clkc CLKID_I2C>;
>> 251 #address-cells = <1>;
>> 252 #size-cells = <0>;
>> 253 status = "disabled";
>> 254 };
>> 255
>> 256 uart_A: serial@24000 {
>> 257 compatible = "amlogic,meson-gx-uart";
>> 258 reg = <0x0 0x24000 0x0 0x18>;
>> 259 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>> 260 status = "disabled";
>> 261 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
>> 262 clock-names = "xtal", "pclk", "baud";
>> 263 };
>> 264
>> 265 uart_B: serial@23000 {
>> 266 compatible = "amlogic,meson-gx-uart";
>> 267 reg = <0x0 0x23000 0x0 0x18>;
>> 268 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>> 269 status = "disabled";
>> 270 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
>> 271 clock-names = "xtal", "pclk", "baud";
274 }; 272 };
275 }; 273 };
276 274
277 ethmac: ethernet@ff3f0000 { 275 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, !! 276 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
279 "snps,dwm !! 277 reg = <0x0 0xff3f0000 0x0 0x10000
280 "snps,dwm !! 278 0x0 0xff634540 0x0 0x8>;
281 reg = <0x0 0xff3f0000 !! 279 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
282 <0x0 0xff634540 <<
283 interrupts = <GIC_SPI <<
284 interrupt-names = "mac 280 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 281 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 282 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 283 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 284 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 285 status = "disabled";
295 }; 286 };
296 287
297 pcie_phy: phy@ff644000 { !! 288 gic: interrupt-controller@ffc01000 {
298 compatible = "amlogic, !! 289 compatible = "arm,gic-400";
299 reg = <0x0 0xff644000 !! 290 reg = <0x0 0xffc01000 0 0x1000>,
300 resets = <&reset RESET !! 291 <0x0 0xffc02000 0 0x2000>,
301 phys = <&mipi_pcie_ana !! 292 <0x0 0xffc04000 0 0x2000>,
302 phy-names = "analog"; !! 293 <0x0 0xffc06000 0 0x2000>;
303 #phy-cells = <0>; !! 294 interrupt-controller;
>> 295 interrupts = <GIC_PPI 9
>> 296 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>> 297 #interrupt-cells = <3>;
>> 298 #address-cells = <0>;
>> 299 };
>> 300
>> 301 hiubus: bus@ff63c000 {
>> 302 compatible = "simple-bus";
>> 303 reg = <0x0 0xff63c000 0x0 0x1c00>;
>> 304 #address-cells = <2>;
>> 305 #size-cells = <2>;
>> 306 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
>> 307
>> 308 sysctrl: system-controller@0 {
>> 309 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
>> 310 reg = <0 0 0 0x400>;
>> 311
>> 312 clkc: clock-controller {
>> 313 compatible = "amlogic,axg-clkc";
>> 314 #clock-cells = <1>;
>> 315 };
>> 316 };
304 }; 317 };
305 318
306 pdm: audio-controller@ff632000 !! 319 mailbox: mailbox@ff63dc00 {
307 compatible = "amlogic, !! 320 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
308 reg = <0x0 0xff632000 !! 321 reg = <0 0xff63dc00 0 0x400>;
309 #sound-dai-cells = <0> !! 322 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
310 sound-name-prefix = "P !! 323 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
311 clocks = <&clkc_audio !! 324 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
312 <&clkc_audio !! 325 #mbox-cells = <1>;
313 <&clkc_audio <<
314 clock-names = "pclk", <<
315 status = "disabled"; <<
316 }; 326 };
317 327
318 periphs: bus@ff634000 { !! 328 periphs: periphs@ff634000 {
319 compatible = "simple-b 329 compatible = "simple-bus";
320 reg = <0x0 0xff634000 330 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 331 #address-cells = <2>;
322 #size-cells = <2>; 332 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 333 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 334
325 hwrng: rng@18 { !! 335 hwrng: rng {
326 compatible = " 336 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 337 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 338 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 339 clock-names = "core";
330 }; 340 };
331 341
332 pinctrl_periphs: pinct 342 pinctrl_periphs: pinctrl@480 {
333 compatible = " 343 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 344 #address-cells = <2>;
335 #size-cells = 345 #size-cells = <2>;
336 ranges; 346 ranges;
337 347
338 gpio: bank@480 348 gpio: bank@480 {
339 reg = 349 reg = <0x0 0x00480 0x0 0x40>,
340 !! 350 <0x0 0x004e8 0x0 0x14>,
341 !! 351 <0x0 0x00520 0x0 0x14>,
342 !! 352 <0x0 0x00430 0x0 0x3c>;
343 reg-na 353 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 354 gpio-controller;
345 #gpio- 355 #gpio-cells = <2>;
346 gpio-r 356 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 357 };
348 358
349 i2c0_pins: i2c <<
350 mux { <<
351 <<
352 <<
353 <<
354 <<
355 }; <<
356 }; <<
357 <<
358 i2c1_x_pins: i <<
359 mux { <<
360 <<
361 <<
362 <<
363 <<
364 }; <<
365 }; <<
366 <<
367 i2c1_z_pins: i <<
368 mux { <<
369 <<
370 <<
371 <<
372 <<
373 }; <<
374 }; <<
375 <<
376 i2c2_a_pins: i <<
377 mux { <<
378 <<
379 <<
380 <<
381 <<
382 }; <<
383 }; <<
384 <<
385 i2c2_x_pins: i <<
386 mux { <<
387 <<
388 <<
389 <<
390 <<
391 }; <<
392 }; <<
393 <<
394 i2c3_a6_pins: <<
395 mux { <<
396 <<
397 <<
398 <<
399 <<
400 }; <<
401 }; <<
402 <<
403 i2c3_a12_pins: <<
404 mux { <<
405 <<
406 <<
407 <<
408 <<
409 }; <<
410 }; <<
411 <<
412 i2c3_a19_pins: <<
413 mux { <<
414 <<
415 <<
416 <<
417 <<
418 }; <<
419 }; <<
420 <<
421 emmc_pins: emm 359 emmc_pins: emmc {
422 mux-0 <<
423 <<
424 <<
425 <<
426 <<
427 <<
428 <<
429 <<
430 <<
431 <<
432 <<
433 <<
434 }; <<
435 <<
436 mux-1 <<
437 <<
438 <<
439 <<
440 }; <<
441 }; <<
442 <<
443 nand_all_pins: <<
444 mux { 360 mux {
445 361 groups = "emmc_nand_d0",
446 !! 362 "emmc_nand_d1",
447 !! 363 "emmc_nand_d2",
448 !! 364 "emmc_nand_d3",
449 !! 365 "emmc_nand_d4",
450 !! 366 "emmc_nand_d5",
451 !! 367 "emmc_nand_d6",
452 !! 368 "emmc_nand_d7",
453 !! 369 "emmc_clk",
454 !! 370 "emmc_cmd",
455 !! 371 "emmc_ds";
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: <<
465 mux { <<
466 <<
467 372 function = "emmc";
468 <<
469 }; 373 };
470 }; 374 };
471 375
472 emmc_clk_gate_ 376 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 377 mux {
474 378 groups = "BOOT_8";
475 379 function = "gpio_periphs";
>> 380 };
>> 381 cfg-pull-down {
>> 382 pins = "BOOT_8";
476 383 bias-pull-down;
477 }; 384 };
478 }; 385 };
479 386
480 eth_rgmii_x_pi !! 387 sdio_pins: sdio {
481 mux { 388 mux {
482 !! 389 groups = "sdio_d0",
483 !! 390 "sdio_d1",
484 !! 391 "sdio_d2",
485 !! 392 "sdio_d3",
486 !! 393 "sdio_cmd",
487 !! 394 "sdio_clk";
488 !! 395 function = "sdio";
489 <<
490 <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 }; 396 };
499 }; 397 };
500 398
501 eth_rgmii_y_pi !! 399 sdio_clk_gate_pins: sdio_clk_gate {
502 mux { 400 mux {
503 !! 401 groups = "GPIOX_4";
504 !! 402 function = "gpio_periphs";
505 !! 403 };
506 !! 404 cfg-pull-down {
507 !! 405 pins = "GPIOX_4";
508 !! 406 bias-pull-down;
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 <<
517 <<
518 <<
519 }; 407 };
520 }; 408 };
521 409
522 eth_rmii_x_pin 410 eth_rmii_x_pins: eth-x-rmii {
523 mux { 411 mux {
524 412 groups = "eth_mdio_x",
525 !! 413 "eth_mdc_x",
526 !! 414 "eth_rgmii_rx_clk_x",
527 !! 415 "eth_rx_dv_x",
528 !! 416 "eth_rxd0_x",
529 !! 417 "eth_rxd1_x",
530 !! 418 "eth_txen_x",
531 !! 419 "eth_txd0_x",
532 !! 420 "eth_txd1_x";
533 421 function = "eth";
534 <<
535 }; 422 };
536 }; 423 };
537 424
538 eth_rmii_y_pin 425 eth_rmii_y_pins: eth-y-rmii {
539 mux { 426 mux {
540 427 groups = "eth_mdio_y",
541 !! 428 "eth_mdc_y",
542 !! 429 "eth_rgmii_rx_clk_y",
543 !! 430 "eth_rx_dv_y",
544 !! 431 "eth_rxd0_y",
545 !! 432 "eth_rxd1_y",
546 !! 433 "eth_txen_y",
547 !! 434 "eth_txd0_y",
548 !! 435 "eth_txd1_y";
549 436 function = "eth";
550 <<
551 }; <<
552 }; <<
553 <<
554 mclk_b_pins: m <<
555 mux { <<
556 <<
557 <<
558 <<
559 }; <<
560 }; <<
561 <<
562 mclk_c_pins: m <<
563 mux { <<
564 <<
565 <<
566 <<
567 }; <<
568 }; <<
569 <<
570 pdm_dclk_a14_p <<
571 mux { <<
572 <<
573 <<
574 <<
575 }; <<
576 }; <<
577 <<
578 pdm_dclk_a19_p <<
579 mux { <<
580 <<
581 <<
582 <<
583 }; <<
584 }; <<
585 <<
586 pdm_din0_pins: <<
587 mux { <<
588 <<
589 <<
590 <<
591 }; 437 };
592 }; 438 };
593 439
594 pdm_din1_pins: !! 440 eth_rgmii_x_pins: eth-x-rgmii {
595 mux { <<
596 <<
597 <<
598 <<
599 }; <<
600 }; <<
601 <<
602 pdm_din2_pins: <<
603 mux { 441 mux {
604 !! 442 groups = "eth_mdio_x",
605 !! 443 "eth_mdc_x",
606 !! 444 "eth_rgmii_rx_clk_x",
>> 445 "eth_rx_dv_x",
>> 446 "eth_rxd0_x",
>> 447 "eth_rxd1_x",
>> 448 "eth_rxd2_rgmii",
>> 449 "eth_rxd3_rgmii",
>> 450 "eth_rgmii_tx_clk",
>> 451 "eth_txen_x",
>> 452 "eth_txd0_x",
>> 453 "eth_txd1_x",
>> 454 "eth_txd2_rgmii",
>> 455 "eth_txd3_rgmii";
>> 456 function = "eth";
607 }; 457 };
608 }; 458 };
609 459
610 pdm_din3_pins: !! 460 eth_rgmii_y_pins: eth-y-rgmii {
611 mux { 461 mux {
612 !! 462 groups = "eth_mdio_y",
613 !! 463 "eth_mdc_y",
614 !! 464 "eth_rgmii_rx_clk_y",
>> 465 "eth_rx_dv_y",
>> 466 "eth_rxd0_y",
>> 467 "eth_rxd1_y",
>> 468 "eth_rxd2_rgmii",
>> 469 "eth_rxd3_rgmii",
>> 470 "eth_rgmii_tx_clk",
>> 471 "eth_txen_y",
>> 472 "eth_txd0_y",
>> 473 "eth_txd1_y",
>> 474 "eth_txd2_rgmii",
>> 475 "eth_txd3_rgmii";
>> 476 function = "eth";
615 }; 477 };
616 }; 478 };
617 479
618 pwm_a_a_pins: 480 pwm_a_a_pins: pwm_a_a {
619 mux { 481 mux {
620 482 groups = "pwm_a_a";
621 483 function = "pwm_a";
622 <<
623 }; 484 };
624 }; 485 };
625 486
626 pwm_a_x18_pins 487 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 488 mux {
628 489 groups = "pwm_a_x18";
629 490 function = "pwm_a";
630 <<
631 }; 491 };
632 }; 492 };
633 493
634 pwm_a_x20_pins 494 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 495 mux {
636 496 groups = "pwm_a_x20";
637 497 function = "pwm_a";
638 <<
639 }; 498 };
640 }; 499 };
641 500
642 pwm_a_z_pins: 501 pwm_a_z_pins: pwm_a_z {
643 mux { 502 mux {
644 503 groups = "pwm_a_z";
645 504 function = "pwm_a";
646 <<
647 }; 505 };
648 }; 506 };
649 507
650 pwm_b_a_pins: 508 pwm_b_a_pins: pwm_b_a {
651 mux { 509 mux {
652 510 groups = "pwm_b_a";
653 511 function = "pwm_b";
654 <<
655 }; 512 };
656 }; 513 };
657 514
658 pwm_b_x_pins: 515 pwm_b_x_pins: pwm_b_x {
659 mux { 516 mux {
660 517 groups = "pwm_b_x";
661 518 function = "pwm_b";
662 <<
663 }; 519 };
664 }; 520 };
665 521
666 pwm_b_z_pins: 522 pwm_b_z_pins: pwm_b_z {
667 mux { 523 mux {
668 524 groups = "pwm_b_z";
669 525 function = "pwm_b";
670 <<
671 }; 526 };
672 }; 527 };
673 528
674 pwm_c_a_pins: 529 pwm_c_a_pins: pwm_c_a {
675 mux { 530 mux {
676 531 groups = "pwm_c_a";
677 532 function = "pwm_c";
678 <<
679 }; 533 };
680 }; 534 };
681 535
682 pwm_c_x10_pins 536 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 537 mux {
684 538 groups = "pwm_c_x10";
685 539 function = "pwm_c";
686 <<
687 }; 540 };
688 }; 541 };
689 542
690 pwm_c_x17_pins 543 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 544 mux {
692 545 groups = "pwm_c_x17";
693 546 function = "pwm_c";
694 <<
695 }; 547 };
696 }; 548 };
697 549
698 pwm_d_x11_pins 550 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 551 mux {
700 552 groups = "pwm_d_x11";
701 553 function = "pwm_d";
702 <<
703 }; 554 };
704 }; 555 };
705 556
706 pwm_d_x16_pins 557 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 558 mux {
708 559 groups = "pwm_d_x16";
709 560 function = "pwm_d";
710 <<
711 }; 561 };
712 }; 562 };
713 563
714 sdio_pins: sdi !! 564 spi0_pins: spi0 {
715 mux-0 !! 565 mux {
716 !! 566 groups = "spi0_miso",
717 !! 567 "spi0_mosi",
718 !! 568 "spi0_clk";
719 !! 569 function = "spi0";
720 <<
721 <<
722 <<
723 }; 570 };
>> 571 };
724 572
725 mux-1 !! 573 spi0_ss0_pins: spi0_ss0 {
726 !! 574 mux {
727 !! 575 groups = "spi0_ss0";
728 !! 576 function = "spi0";
729 }; 577 };
730 }; 578 };
731 579
732 sdio_clk_gate_ !! 580 spi0_ss1_pins: spi0_ss1 {
733 mux { 581 mux {
734 !! 582 groups = "spi0_ss1";
735 !! 583 function = "spi0";
736 <<
737 }; 584 };
738 }; 585 };
739 586
740 spdif_in_z_pin !! 587 spi0_ss2_pins: spi0_ss2 {
741 mux { 588 mux {
742 !! 589 groups = "spi0_ss2";
743 !! 590 function = "spi0";
744 <<
745 }; 591 };
746 }; 592 };
747 593
748 spdif_in_a1_pi !! 594
>> 595 spi1_a_pins: spi1_a {
749 mux { 596 mux {
750 !! 597 groups = "spi1_miso_a",
751 !! 598 "spi1_mosi_a",
752 !! 599 "spi1_clk_a";
>> 600 function = "spi1";
753 }; 601 };
754 }; 602 };
755 603
756 spdif_in_a7_pi !! 604 spi1_ss0_a_pins: spi1_ss0_a {
757 mux { 605 mux {
758 !! 606 groups = "spi1_ss0_a";
759 !! 607 function = "spi1";
760 <<
761 }; 608 };
762 }; 609 };
763 610
764 spdif_in_a19_p !! 611 spi1_ss1_pins: spi1_ss1 {
765 mux { 612 mux {
766 !! 613 groups = "spi1_ss1";
767 !! 614 function = "spi1";
768 <<
769 }; 615 };
770 }; 616 };
771 617
772 spdif_in_a20_p !! 618 spi1_x_pins: spi1_x {
773 mux { 619 mux {
774 !! 620 groups = "spi1_miso_x",
775 !! 621 "spi1_mosi_x",
776 !! 622 "spi1_clk_x";
>> 623 function = "spi1";
777 }; 624 };
778 }; 625 };
779 626
780 spdif_out_a1_p !! 627 spi1_ss0_x_pins: spi1_ss0_x {
781 mux { 628 mux {
782 !! 629 groups = "spi1_ss0_x";
783 !! 630 function = "spi1";
784 <<
785 }; 631 };
786 }; 632 };
787 633
788 spdif_out_a11_ !! 634 i2c0_pins: i2c0 {
789 mux { 635 mux {
790 !! 636 groups = "i2c0_sck",
791 !! 637 "i2c0_sda";
792 !! 638 function = "i2c0";
793 }; 639 };
794 }; 640 };
795 641
796 spdif_out_a19_ !! 642 i2c1_z_pins: i2c1_z {
797 mux { 643 mux {
798 !! 644 groups = "i2c1_sck_z",
799 !! 645 "i2c1_sda_z";
800 !! 646 function = "i2c1";
801 }; 647 };
802 }; 648 };
803 649
804 spdif_out_a20_ !! 650 i2c1_x_pins: i2c1_x {
805 mux { 651 mux {
806 !! 652 groups = "i2c1_sck_x",
807 !! 653 "i2c1_sda_x";
808 !! 654 function = "i2c1";
809 }; 655 };
810 }; 656 };
811 657
812 spdif_out_z_pi !! 658 i2c2_x_pins: i2c2_x {
813 mux { 659 mux {
814 !! 660 groups = "i2c2_sck_x",
815 !! 661 "i2c2_sda_x";
816 !! 662 function = "i2c2";
817 }; 663 };
818 }; 664 };
819 665
820 spi0_pins: spi !! 666 i2c2_a_pins: i2c2_a {
821 mux { 667 mux {
822 !! 668 groups = "i2c2_sck_a",
823 !! 669 "i2c2_sda_a";
824 !! 670 function = "i2c2";
825 <<
826 <<
827 }; 671 };
828 }; 672 };
829 673
830 spi0_ss0_pins: !! 674 i2c3_a6_pins: i2c3_a6 {
831 mux { 675 mux {
832 !! 676 groups = "i2c3_sda_a6",
833 !! 677 "i2c3_sck_a7";
834 !! 678 function = "i2c3";
835 }; 679 };
836 }; 680 };
837 681
838 spi0_ss1_pins: !! 682 i2c3_a12_pins: i2c3_a12 {
839 mux { 683 mux {
840 !! 684 groups = "i2c3_sda_a12",
841 !! 685 "i2c3_sck_a13";
842 !! 686 function = "i2c3";
843 }; 687 };
844 }; 688 };
845 689
846 spi0_ss2_pins: !! 690 i2c3_a19_pins: i2c3_a19 {
847 mux { 691 mux {
848 !! 692 groups = "i2c3_sda_a19",
849 !! 693 "i2c3_sck_a20";
850 !! 694 function = "i2c3";
851 }; 695 };
852 }; 696 };
853 697
854 spi1_a_pins: s !! 698 uart_a_pins: uart_a {
855 mux { 699 mux {
856 !! 700 groups = "uart_tx_a",
857 !! 701 "uart_rx_a";
858 !! 702 function = "uart_a";
859 <<
860 <<
861 }; 703 };
862 }; 704 };
863 705
864 spi1_ss0_a_pin !! 706 uart_a_cts_rts_pins: uart_a_cts_rts {
865 mux { 707 mux {
866 !! 708 groups = "uart_cts_a",
867 !! 709 "uart_rts_a";
868 !! 710 function = "uart_a";
869 }; 711 };
870 }; 712 };
871 713
872 spi1_ss1_pins: !! 714 uart_b_x_pins: uart_b_x {
873 mux { 715 mux {
874 !! 716 groups = "uart_tx_b_x",
875 !! 717 "uart_rx_b_x";
876 !! 718 function = "uart_b";
877 }; 719 };
878 }; 720 };
879 721
880 spi1_x_pins: s !! 722 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
881 mux { 723 mux {
882 !! 724 groups = "uart_cts_b_x",
883 !! 725 "uart_rts_b_x";
884 !! 726 function = "uart_b";
885 <<
886 <<
887 }; 727 };
888 }; 728 };
889 729
890 spi1_ss0_x_pin !! 730 uart_b_z_pins: uart_b_z {
891 mux { 731 mux {
892 !! 732 groups = "uart_tx_b_z",
893 !! 733 "uart_rx_b_z";
894 !! 734 function = "uart_b";
895 }; 735 };
896 }; 736 };
897 737
898 tdma_din0_pins !! 738 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
899 mux { 739 mux {
900 !! 740 groups = "uart_cts_b_z",
901 !! 741 "uart_rts_b_z";
902 !! 742 function = "uart_b";
903 }; 743 };
904 }; 744 };
905 745
906 tdma_dout0_x14 !! 746 uart_ao_b_z_pins: uart_ao_b_z {
907 mux { 747 mux {
908 !! 748 groups = "uart_ao_tx_b_z",
909 !! 749 "uart_ao_rx_b_z";
910 !! 750 function = "uart_ao_b_z";
911 }; 751 };
912 }; 752 };
913 753
914 tdma_dout0_x15 !! 754 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
915 mux { 755 mux {
916 !! 756 groups = "uart_ao_cts_b_z",
917 !! 757 "uart_ao_rts_b_z";
918 !! 758 function = "uart_ao_b_z";
919 }; 759 };
920 }; 760 };
921 761
922 tdma_dout1_pin !! 762 mclk_b_pins: mclk_b {
923 mux { 763 mux {
924 !! 764 groups = "mclk_b";
>> 765 function = "mclk_b";
>> 766 };
>> 767 };
>> 768
>> 769 mclk_c_pins: mclk_c {
>> 770 mux {
>> 771 groups = "mclk_c";
>> 772 function = "mclk_c";
>> 773 };
>> 774 };
>> 775
>> 776 tdma_sclk_pins: tdma_sclk {
>> 777 mux {
>> 778 groups = "tdma_sclk";
925 779 function = "tdma";
926 <<
927 }; 780 };
928 }; 781 };
929 782
930 tdma_din1_pins !! 783 tdma_sclk_slv_pins: tdma_sclk_slv {
931 mux { 784 mux {
932 !! 785 groups = "tdma_sclk_slv";
933 786 function = "tdma";
934 <<
935 }; 787 };
936 }; 788 };
937 789
938 tdma_fs_pins: 790 tdma_fs_pins: tdma_fs {
939 mux { 791 mux {
940 792 groups = "tdma_fs";
941 793 function = "tdma";
942 <<
943 }; 794 };
944 }; 795 };
945 796
946 tdma_fs_slv_pi 797 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 798 mux {
948 799 groups = "tdma_fs_slv";
949 800 function = "tdma";
950 <<
951 }; 801 };
952 }; 802 };
953 803
954 tdma_sclk_pins !! 804 tdma_din0_pins: tdma_din0 {
955 mux { 805 mux {
956 !! 806 groups = "tdma_din0";
957 807 function = "tdma";
958 <<
959 }; 808 };
960 }; 809 };
961 810
962 tdma_sclk_slv_ !! 811 tdma_dout0_x14_pins: tdma_dout0_x14 {
963 mux { 812 mux {
964 !! 813 groups = "tdma_dout0_x14";
965 814 function = "tdma";
966 <<
967 }; 815 };
968 }; 816 };
969 817
970 tdmb_din0_pins !! 818 tdma_dout0_x15_pins: tdma_dout0_x15 {
971 mux { 819 mux {
972 !! 820 groups = "tdma_dout0_x15";
973 !! 821 function = "tdma";
974 <<
975 }; 822 };
976 }; 823 };
977 824
978 tdmb_din1_pins !! 825 tdma_dout1_pins: tdma_dout1 {
979 mux { 826 mux {
980 !! 827 groups = "tdma_dout1";
981 !! 828 function = "tdma";
982 <<
983 }; 829 };
984 }; 830 };
985 831
986 tdmb_din2_pins !! 832 tdma_din1_pins: tdma_din1 {
987 mux { 833 mux {
988 !! 834 groups = "tdma_din1";
>> 835 function = "tdma";
>> 836 };
>> 837 };
>> 838
>> 839 tdmb_sclk_pins: tdmb_sclk {
>> 840 mux {
>> 841 groups = "tdmb_sclk";
989 842 function = "tdmb";
990 <<
991 }; 843 };
992 }; 844 };
993 845
994 tdmb_din3_pins !! 846 tdmb_sclk_slv_pins: tdmb_sclk_slv {
995 mux { 847 mux {
996 !! 848 groups = "tdmb_sclk_slv";
997 849 function = "tdmb";
998 <<
999 }; 850 };
1000 }; 851 };
1001 852
1002 tdmb_dout0_pi !! 853 tdmb_fs_pins: tdmb_fs {
1003 mux { 854 mux {
1004 !! 855 groups = "tdmb_fs";
1005 856 function = "tdmb";
1006 <<
1007 }; 857 };
1008 }; 858 };
1009 859
1010 tdmb_dout1_pi !! 860 tdmb_fs_slv_pins: tdmb_fs_slv {
1011 mux { 861 mux {
1012 !! 862 groups = "tdmb_fs_slv";
1013 863 function = "tdmb";
1014 <<
1015 }; 864 };
1016 }; 865 };
1017 866
1018 tdmb_dout2_pi !! 867 tdmb_din0_pins: tdmb_din0 {
1019 mux { 868 mux {
1020 !! 869 groups = "tdmb_din0";
1021 870 function = "tdmb";
1022 <<
1023 }; 871 };
1024 }; 872 };
1025 873
1026 tdmb_dout3_pi !! 874 tdmb_dout0_pins: tdmb_dout0 {
1027 mux { 875 mux {
1028 !! 876 groups = "tdmb_dout0";
1029 877 function = "tdmb";
1030 <<
1031 }; 878 };
1032 }; 879 };
1033 880
1034 tdmb_fs_pins: !! 881 tdmb_din1_pins: tdmb_din1 {
1035 mux { 882 mux {
1036 !! 883 groups = "tdmb_din1";
1037 884 function = "tdmb";
1038 <<
1039 }; 885 };
1040 }; 886 };
1041 887
1042 tdmb_fs_slv_p !! 888 tdmb_dout1_pins: tdmb_dout1 {
1043 mux { 889 mux {
1044 !! 890 groups = "tdmb_dout1";
1045 891 function = "tdmb";
1046 <<
1047 }; 892 };
1048 }; 893 };
1049 894
1050 tdmb_sclk_pin !! 895 tdmb_din2_pins: tdmb_din2 {
1051 mux { 896 mux {
1052 !! 897 groups = "tdmb_din2";
1053 898 function = "tdmb";
1054 <<
1055 }; 899 };
1056 }; 900 };
1057 901
1058 tdmb_sclk_slv !! 902 tdmb_dout2_pins: tdmb_dout2 {
1059 mux { 903 mux {
1060 !! 904 groups = "tdmb_dout2";
1061 905 function = "tdmb";
1062 <<
1063 }; 906 };
1064 }; 907 };
1065 908
1066 tdmc_fs_pins: !! 909 tdmb_din3_pins: tdmb_din3 {
1067 mux { 910 mux {
1068 !! 911 groups = "tdmb_din3";
1069 !! 912 function = "tdmb";
1070 <<
1071 }; 913 };
1072 }; 914 };
1073 915
1074 tdmc_fs_slv_p !! 916 tdmb_dout3_pins: tdmb_dout3 {
1075 mux { 917 mux {
1076 !! 918 groups = "tdmb_dout3";
1077 !! 919 function = "tdmb";
1078 <<
1079 }; 920 };
1080 }; 921 };
1081 922
1082 tdmc_sclk_pin 923 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 924 mux {
1084 925 groups = "tdmc_sclk";
1085 926 function = "tdmc";
1086 <<
1087 }; 927 };
1088 }; 928 };
1089 929
1090 tdmc_sclk_slv 930 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 931 mux {
1092 932 groups = "tdmc_sclk_slv";
1093 933 function = "tdmc";
1094 <<
1095 }; 934 };
1096 }; 935 };
1097 936
1098 tdmc_din0_pin !! 937 tdmc_fs_pins: tdmc_fs {
1099 mux { 938 mux {
1100 !! 939 groups = "tdmc_fs";
1101 940 function = "tdmc";
1102 <<
1103 }; 941 };
1104 }; 942 };
1105 943
1106 tdmc_din1_pin !! 944 tdmc_fs_slv_pins: tdmc_fs_slv {
1107 mux { 945 mux {
1108 !! 946 groups = "tdmc_fs_slv";
1109 947 function = "tdmc";
1110 <<
1111 }; 948 };
1112 }; 949 };
1113 950
1114 tdmc_din2_pin !! 951 tdmc_din0_pins: tdmc_din0 {
1115 mux { 952 mux {
1116 !! 953 groups = "tdmc_din0";
1117 954 function = "tdmc";
1118 <<
1119 }; 955 };
1120 }; 956 };
1121 957
1122 tdmc_din3_pin !! 958 tdmc_dout0_pins: tdmc_dout0 {
1123 mux { 959 mux {
1124 !! 960 groups = "tdmc_dout0";
1125 961 function = "tdmc";
1126 <<
1127 }; 962 };
1128 }; 963 };
1129 964
1130 tdmc_dout0_pi !! 965 tdmc_din1_pins: tdmc_din1 {
1131 mux { 966 mux {
1132 !! 967 groups = "tdmc_din1";
1133 968 function = "tdmc";
1134 <<
1135 }; 969 };
1136 }; 970 };
1137 971
1138 tdmc_dout1_pi 972 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 973 mux {
1140 974 groups = "tdmc_dout1";
1141 975 function = "tdmc";
1142 <<
1143 }; 976 };
1144 }; 977 };
1145 978
1146 tdmc_dout2_pi !! 979 tdmc_din2_pins: tdmc_din2 {
1147 mux { 980 mux {
1148 !! 981 groups = "tdmc_din2";
1149 982 function = "tdmc";
1150 <<
1151 }; 983 };
1152 }; 984 };
1153 985
1154 tdmc_dout3_pi !! 986 tdmc_dout2_pins: tdmc_dout2 {
1155 mux { 987 mux {
1156 !! 988 groups = "tdmc_dout2";
1157 989 function = "tdmc";
1158 <<
1159 }; <<
1160 }; <<
1161 <<
1162 uart_a_pins: <<
1163 mux { <<
1164 <<
1165 <<
1166 <<
1167 <<
1168 }; <<
1169 }; <<
1170 <<
1171 uart_a_cts_rt <<
1172 mux { <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 }; <<
1178 }; <<
1179 <<
1180 uart_b_x_pins <<
1181 mux { <<
1182 <<
1183 <<
1184 <<
1185 <<
1186 }; <<
1187 }; <<
1188 <<
1189 uart_b_x_cts_ <<
1190 mux { <<
1191 <<
1192 <<
1193 <<
1194 <<
1195 }; 990 };
1196 }; 991 };
1197 992
1198 uart_b_z_pins !! 993 tdmc_din3_pins: tdmc_din3 {
1199 mux { <<
1200 <<
1201 <<
1202 <<
1203 <<
1204 }; <<
1205 }; <<
1206 <<
1207 uart_b_z_cts_ <<
1208 mux { <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 }; <<
1214 }; <<
1215 <<
1216 uart_ao_b_z_p <<
1217 mux { 994 mux {
1218 !! 995 groups = "tdmc_din3";
1219 !! 996 function = "tdmc";
1220 <<
1221 <<
1222 }; 997 };
1223 }; 998 };
1224 999
1225 uart_ao_b_z_c !! 1000 tdmc_dout3_pins: tdmc_dout3 {
1226 mux { 1001 mux {
1227 !! 1002 groups = "tdmc_dout3";
1228 !! 1003 function = "tdmc";
1229 <<
1230 <<
1231 }; 1004 };
1232 }; 1005 };
1233 }; 1006 };
1234 }; 1007 };
1235 1008
1236 hiubus: bus@ff63c000 { !! 1009 sram: sram@fffc0000 {
1237 compatible = "simple- !! 1010 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1238 reg = <0x0 0xff63c000 !! 1011 reg = <0x0 0xfffc0000 0x0 0x20000>;
1239 #address-cells = <2>; !! 1012 #address-cells = <1>;
1240 #size-cells = <2>; !! 1013 #size-cells = <1>;
1241 ranges = <0x0 0x0 0x0 !! 1014 ranges = <0 0x0 0xfffc0000 0x20000>;
1242 <<
1243 sysctrl: system-contr <<
1244 compatible = <<
1245 <<
1246 reg = <0 0 0 <<
1247 <<
1248 clkc: clock-c <<
1249 compa <<
1250 #cloc <<
1251 clock <<
1252 clock <<
1253 }; <<
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; <<
1301 }; <<
1302 <<
1303 mailbox: mailbox@ff63c404 { <<
1304 compatible = "amlogic <<
1305 reg = <0 0xff63c404 0 <<
1306 interrupts = <GIC_SPI <<
1307 <GIC_SPI <<
1308 <GIC_SPI <<
1309 #mbox-cells = <1>; <<
1310 }; <<
1311 <<
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { <<
1326 compatible = "simple- <<
1327 reg = <0x0 0xff642000 <<
1328 #address-cells = <2>; <<
1329 #size-cells = <2>; <<
1330 ranges = <0x0 0x0 0x0 <<
1331 <<
1332 clkc_audio: clock-con <<
1333 compatible = <<
1334 reg = <0x0 0x <<
1335 #clock-cells <<
1336 <<
1337 clocks = <&cl <<
1338 <&cl <<
1339 <&cl <<
1340 <&cl <<
1341 <&cl <<
1342 <&cl <<
1343 <&cl <<
1344 <&cl <<
1345 <&cl <<
1346 clock-names = <<
1347 <<
1348 <<
1349 <<
1350 <<
1351 <<
1352 <<
1353 <<
1354 <<
1355 <<
1356 resets = <&re <<
1357 }; <<
1358 <<
1359 toddr_a: audio-contro <<
1360 compatible = <<
1361 reg = <0x0 0x <<
1362 #sound-dai-ce <<
1363 sound-name-pr <<
1364 interrupts = <<
1365 clocks = <&cl <<
1366 resets = <&ar <<
1367 amlogic,fifo- <<
1368 status = "dis <<
1369 }; <<
1370 <<
1371 toddr_b: audio-contro <<
1372 compatible = <<
1373 reg = <0x0 0x <<
1374 #sound-dai-ce <<
1375 sound-name-pr <<
1376 interrupts = <<
1377 clocks = <&cl <<
1378 resets = <&ar <<
1379 amlogic,fifo- <<
1380 status = "dis <<
1381 }; <<
1382 <<
1383 toddr_c: audio-contro <<
1384 compatible = <<
1385 reg = <0x0 0x <<
1386 #sound-dai-ce <<
1387 sound-name-pr <<
1388 interrupts = <<
1389 clocks = <&cl <<
1390 resets = <&ar <<
1391 amlogic,fifo- <<
1392 status = "dis <<
1393 }; <<
1394 <<
1395 frddr_a: audio-contro <<
1396 compatible = <<
1397 reg = <0x0 0x <<
1398 #sound-dai-ce <<
1399 sound-name-pr <<
1400 interrupts = <<
1401 clocks = <&cl <<
1402 resets = <&ar <<
1403 amlogic,fifo- <<
1404 status = "dis <<
1405 }; <<
1406 <<
1407 frddr_b: audio-contro <<
1408 compatible = <<
1409 reg = <0x0 0x <<
1410 #sound-dai-ce <<
1411 sound-name-pr <<
1412 interrupts = <<
1413 clocks = <&cl <<
1414 resets = <&ar <<
1415 amlogic,fifo- <<
1416 status = "dis <<
1417 }; <<
1418 <<
1419 frddr_c: audio-contro <<
1420 compatible = <<
1421 reg = <0x0 0x <<
1422 #sound-dai-ce <<
1423 sound-name-pr <<
1424 interrupts = <<
1425 clocks = <&cl <<
1426 resets = <&ar <<
1427 amlogic,fifo- <<
1428 status = "dis <<
1429 }; <<
1430 <<
1431 arb: reset-controller <<
1432 compatible = <<
1433 reg = <0x0 0x <<
1434 #reset-cells <<
1435 clocks = <&cl <<
1436 }; <<
1437 <<
1438 tdmin_a: audio-contro <<
1439 compatible = <<
1440 reg = <0x0 0x <<
1441 sound-name-pr <<
1442 clocks = <&cl <<
1443 <&cl <<
1444 <&cl <<
1445 <&cl <<
1446 <&cl <<
1447 clock-names = <<
1448 <<
1449 status = "dis <<
1450 }; <<
1451 <<
1452 tdmin_b: audio-contro <<
1453 compatible = <<
1454 reg = <0x0 0x <<
1455 sound-name-pr <<
1456 clocks = <&cl <<
1457 <&cl <<
1458 <&cl <<
1459 <&cl <<
1460 <&cl <<
1461 clock-names = <<
1462 <<
1463 status = "dis <<
1464 }; <<
1465 <<
1466 tdmin_c: audio-contro <<
1467 compatible = <<
1468 reg = <0x0 0x <<
1469 sound-name-pr <<
1470 clocks = <&cl <<
1471 <&cl <<
1472 <&cl <<
1473 <&cl <<
1474 <&cl <<
1475 clock-names = <<
1476 <<
1477 status = "dis <<
1478 }; <<
1479 <<
1480 tdmin_lb: audio-contr <<
1481 compatible = <<
1482 reg = <0x0 0x <<
1483 sound-name-pr <<
1484 clocks = <&cl <<
1485 <&cl <<
1486 <&cl <<
1487 <&cl <<
1488 <&cl <<
1489 clock-names = <<
1490 <<
1491 status = "dis <<
1492 }; <<
1493 <<
1494 spdifin: audio-contro <<
1495 compatible = <<
1496 reg = <0x0 0x <<
1497 #sound-dai-ce <<
1498 sound-name-pr <<
1499 interrupts = <<
1500 clocks = <&cl <<
1501 <&cl <<
1502 clock-names = <<
1503 status = "dis <<
1504 }; <<
1505 <<
1506 spdifout: audio-contr <<
1507 compatible = <<
1508 reg = <0x0 0x <<
1509 #sound-dai-ce <<
1510 sound-name-pr <<
1511 clocks = <&cl <<
1512 <&cl <<
1513 clock-names = <<
1514 status = "dis <<
1515 }; <<
1516 <<
1517 tdmout_a: audio-contr <<
1518 compatible = <<
1519 reg = <0x0 0x <<
1520 sound-name-pr <<
1521 clocks = <&cl <<
1522 <&cl <<
1523 <&cl <<
1524 <&cl <<
1525 <&cl <<
1526 clock-names = <<
1527 <<
1528 status = "dis <<
1529 }; <<
1530 1015
1531 tdmout_b: audio-contr !! 1016 cpu_scp_lpri: scp-shmem@0 {
1532 compatible = !! 1017 compatible = "amlogic,meson-axg-scp-shmem";
1533 reg = <0x0 0x !! 1018 reg = <0x13000 0x400>;
1534 sound-name-pr <<
1535 clocks = <&cl <<
1536 <&cl <<
1537 <&cl <<
1538 <&cl <<
1539 <&cl <<
1540 clock-names = <<
1541 <<
1542 status = "dis <<
1543 }; 1019 };
1544 1020
1545 tdmout_c: audio-contr !! 1021 cpu_scp_hpri: scp-shmem@200 {
1546 compatible = !! 1022 compatible = "amlogic,meson-axg-scp-shmem";
1547 reg = <0x0 0x !! 1023 reg = <0x13400 0x400>;
1548 sound-name-pr <<
1549 clocks = <&cl <<
1550 <&cl <<
1551 <&cl <<
1552 <&cl <<
1553 <&cl <<
1554 clock-names = <<
1555 <<
1556 status = "dis <<
1557 }; 1024 };
1558 }; 1025 };
1559 1026
1560 aobus: bus@ff800000 { 1027 aobus: bus@ff800000 {
1561 compatible = "simple- 1028 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1029 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1030 #address-cells = <2>;
1564 #size-cells = <2>; 1031 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1032 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1033
1567 sysctrl_AO: sys-ctrl@ 1034 sysctrl_AO: sys-ctrl@0 {
1568 compatible = !! 1035 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1569 reg = <0x0 0x !! 1036 reg = <0x0 0x0 0x0 0x100>;
1570 1037
1571 clkc_AO: cloc 1038 clkc_AO: clock-controller {
1572 compa 1039 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1040 #clock-cells = <1>;
1574 #rese 1041 #reset-cells = <1>;
1575 clock <<
1576 clock <<
1577 }; 1042 };
1578 }; 1043 };
1579 1044
1580 pinctrl_aobus: pinctr 1045 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1046 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1047 #address-cells = <2>;
1583 #size-cells = 1048 #size-cells = <2>;
1584 ranges; 1049 ranges;
1585 1050
1586 gpio_ao: bank 1051 gpio_ao: bank@14 {
1587 reg = 1052 reg = <0x0 0x00014 0x0 0x8>,
1588 !! 1053 <0x0 0x0002c 0x0 0x4>,
1589 !! 1054 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1055 reg-names = "mux", "pull", "gpio";
1591 gpio- 1056 gpio-controller;
1592 #gpio 1057 #gpio-cells = <2>;
1593 gpio- 1058 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1059 };
1595 1060
1596 i2c_ao_sck_4_ 1061 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1062 mux {
1598 1063 groups = "i2c_ao_sck_4";
1599 1064 function = "i2c_ao";
1600 <<
1601 }; 1065 };
1602 }; 1066 };
1603 1067
1604 i2c_ao_sck_8_ 1068 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1069 mux {
1606 1070 groups = "i2c_ao_sck_8";
1607 1071 function = "i2c_ao";
1608 <<
1609 }; 1072 };
1610 }; 1073 };
1611 1074
1612 i2c_ao_sck_10 1075 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1076 mux {
1614 1077 groups = "i2c_ao_sck_10";
1615 1078 function = "i2c_ao";
1616 <<
1617 }; 1079 };
1618 }; 1080 };
1619 1081
1620 i2c_ao_sda_5_ 1082 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1083 mux {
1622 1084 groups = "i2c_ao_sda_5";
1623 1085 function = "i2c_ao";
1624 <<
1625 }; 1086 };
1626 }; 1087 };
1627 1088
1628 i2c_ao_sda_9_ 1089 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1090 mux {
1630 1091 groups = "i2c_ao_sda_9";
1631 1092 function = "i2c_ao";
1632 <<
1633 }; 1093 };
1634 }; 1094 };
1635 1095
1636 i2c_ao_sda_11 1096 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1097 mux {
1638 1098 groups = "i2c_ao_sda_11";
1639 1099 function = "i2c_ao";
1640 <<
1641 }; 1100 };
1642 }; 1101 };
1643 1102
1644 remote_input_ 1103 remote_input_ao_pins: remote_input_ao {
1645 mux { 1104 mux {
1646 1105 groups = "remote_input_ao";
1647 1106 function = "remote_input_ao";
1648 <<
1649 }; 1107 };
1650 }; 1108 };
1651 1109
1652 uart_ao_a_pin 1110 uart_ao_a_pins: uart_ao_a {
1653 mux { 1111 mux {
1654 1112 groups = "uart_ao_tx_a",
1655 !! 1113 "uart_ao_rx_a";
1656 1114 function = "uart_ao_a";
1657 <<
1658 }; 1115 };
1659 }; 1116 };
1660 1117
1661 uart_ao_a_cts 1118 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1119 mux {
1663 1120 groups = "uart_ao_cts_a",
1664 !! 1121 "uart_ao_rts_a";
1665 1122 function = "uart_ao_a";
1666 <<
1667 }; 1123 };
1668 }; 1124 };
1669 1125
1670 uart_ao_b_pin 1126 uart_ao_b_pins: uart_ao_b {
1671 mux { 1127 mux {
1672 1128 groups = "uart_ao_tx_b",
1673 !! 1129 "uart_ao_rx_b";
1674 1130 function = "uart_ao_b";
1675 <<
1676 }; 1131 };
1677 }; 1132 };
1678 1133
1679 uart_ao_b_cts 1134 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1135 mux {
1681 1136 groups = "uart_ao_cts_b",
1682 !! 1137 "uart_ao_rts_b";
1683 1138 function = "uart_ao_b";
1684 <<
1685 }; 1139 };
1686 }; 1140 };
1687 }; 1141 };
1688 1142
1689 sec_AO: ao-secure@140 1143 sec_AO: ao-secure@140 {
1690 compatible = 1144 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1145 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1146 amlogic,has-chip-id;
1693 }; 1147 };
1694 1148
>> 1149 pwm_AO_ab: pwm@7000 {
>> 1150 compatible = "amlogic,meson-axg-ao-pwm";
>> 1151 reg = <0x0 0x07000 0x0 0x20>;
>> 1152 #pwm-cells = <3>;
>> 1153 status = "disabled";
>> 1154 };
>> 1155
1695 pwm_AO_cd: pwm@2000 { 1156 pwm_AO_cd: pwm@2000 {
1696 compatible = 1157 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1158 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1159 #pwm-cells = <3>;
1699 status = "dis 1160 status = "disabled";
1700 }; 1161 };
1701 1162
>> 1163 i2c_AO: i2c@5000 {
>> 1164 compatible = "amlogic,meson-axg-i2c";
>> 1165 reg = <0x0 0x05000 0x0 0x20>;
>> 1166 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
>> 1167 clocks = <&clkc CLKID_AO_I2C>;
>> 1168 #address-cells = <1>;
>> 1169 #size-cells = <0>;
>> 1170 status = "disabled";
>> 1171 };
>> 1172
1702 uart_AO: serial@3000 1173 uart_AO: serial@3000 {
1703 compatible = 1174 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1175 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1176 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1177 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1178 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1179 status = "disabled";
1709 }; 1180 };
1710 1181
1711 uart_AO_B: serial@400 1182 uart_AO_B: serial@4000 {
1712 compatible = 1183 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1184 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1185 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1186 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1187 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1188 status = "disabled";
1718 }; 1189 };
1719 1190
1720 i2c_AO: i2c@5000 { <<
1721 compatible = <<
1722 reg = <0x0 0x <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 #address-cell <<
1726 #size-cells = <<
1727 status = "dis <<
1728 }; <<
1729 <<
1730 pwm_AO_ab: pwm@7000 { <<
1731 compatible = <<
1732 reg = <0x0 0x <<
1733 #pwm-cells = <<
1734 status = "dis <<
1735 }; <<
1736 <<
1737 ir: ir@8000 { 1191 ir: ir@8000 {
1738 compatible = 1192 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1193 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1194 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1195 status = "disabled";
1742 }; 1196 };
1743 <<
1744 saradc: adc@9000 { <<
1745 compatible = <<
1746 "amlo <<
1747 reg = <0x0 0x <<
1748 #io-channel-c <<
1749 interrupts = <<
1750 clocks = <&xt <<
1751 <&cl <<
1752 <&cl <<
1753 <&cl <<
1754 clock-names = <<
1755 status = "dis <<
1756 }; <<
1757 }; <<
1758 <<
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; 1197 };
1766 <<
1767 gic: interrupt-controller@ffc <<
1768 compatible = "arm,gic <<
1769 reg = <0x0 0xffc01000 <<
1770 <0x0 0xffc02000 <<
1771 <0x0 0xffc04000 <<
1772 <0x0 0xffc06000 <<
1773 interrupt-controller; <<
1774 interrupts = <GIC_PPI <<
1775 (GIC_CPU_MASK <<
1776 #interrupt-cells = <3 <<
1777 #address-cells = <0>; <<
1778 }; <<
1779 <<
1780 cbus: bus@ffd00000 { <<
1781 compatible = "simple- <<
1782 reg = <0x0 0xffd00000 <<
1783 #address-cells = <2>; <<
1784 #size-cells = <2>; <<
1785 ranges = <0x0 0x0 0x0 <<
1786 <<
1787 reset: reset-controll <<
1788 compatible = <<
1789 reg = <0x0 0x <<
1790 #reset-cells <<
1791 }; <<
1792 <<
1793 gpio_intc: interrupt- <<
1794 compatible = <<
1795 <<
1796 reg = <0x0 0x <<
1797 interrupt-con <<
1798 #interrupt-ce <<
1799 amlogic,chann <<
1800 }; <<
1801 <<
1802 watchdog@f0d0 { <<
1803 compatible = <<
1804 reg = <0x0 0x <<
1805 clocks = <&xt <<
1806 }; <<
1807 <<
1808 pwm_ab: pwm@1b000 { <<
1809 compatible = <<
1810 reg = <0x0 0x <<
1811 #pwm-cells = <<
1812 status = "dis <<
1813 }; <<
1814 <<
1815 pwm_cd: pwm@1a000 { <<
1816 compatible = <<
1817 reg = <0x0 0x <<
1818 #pwm-cells = <<
1819 status = "dis <<
1820 }; <<
1821 <<
1822 spicc0: spi@13000 { <<
1823 compatible = <<
1824 reg = <0x0 0x <<
1825 interrupts = <<
1826 clocks = <&cl <<
1827 clock-names = <<
1828 #address-cell <<
1829 #size-cells = <<
1830 status = "dis <<
1831 }; <<
1832 <<
1833 spicc1: spi@15000 { <<
1834 compatible = <<
1835 reg = <0x0 0x <<
1836 interrupts = <<
1837 clocks = <&cl <<
1838 clock-names = <<
1839 #address-cell <<
1840 #size-cells = <<
1841 status = "dis <<
1842 }; <<
1843 <<
1844 clk_msr: clock-measur <<
1845 compatible = <<
1846 reg = <0x0 0x <<
1847 }; <<
1848 <<
1849 i2c3: i2c@1c000 { <<
1850 compatible = <<
1851 reg = <0x0 0x <<
1852 interrupts = <<
1853 clocks = <&cl <<
1854 #address-cell <<
1855 #size-cells = <<
1856 status = "dis <<
1857 }; <<
1858 <<
1859 i2c2: i2c@1d000 { <<
1860 compatible = <<
1861 reg = <0x0 0x <<
1862 interrupts = <<
1863 clocks = <&cl <<
1864 #address-cell <<
1865 #size-cells = <<
1866 status = "dis <<
1867 }; <<
1868 <<
1869 i2c1: i2c@1e000 { <<
1870 compatible = <<
1871 reg = <0x0 0x <<
1872 interrupts = <<
1873 clocks = <&cl <<
1874 #address-cell <<
1875 #size-cells = <<
1876 status = "dis <<
1877 }; <<
1878 <<
1879 i2c0: i2c@1f000 { <<
1880 compatible = <<
1881 reg = <0x0 0x <<
1882 interrupts = <<
1883 clocks = <&cl <<
1884 #address-cell <<
1885 #size-cells = <<
1886 status = "dis <<
1887 }; <<
1888 <<
1889 uart_B: serial@23000 <<
1890 compatible = <<
1891 reg = <0x0 0x <<
1892 interrupts = <<
1893 status = "dis <<
1894 clocks = <&xt <<
1895 clock-names = <<
1896 }; <<
1897 <<
1898 uart_A: serial@24000 <<
1899 compatible = <<
1900 reg = <0x0 0x <<
1901 interrupts = <<
1902 status = "dis <<
1903 clocks = <&xt <<
1904 clock-names = <<
1905 fifo-size = < <<
1906 }; <<
1907 }; <<
1908 <<
1909 apb: bus@ffe00000 { <<
1910 compatible = "simple- <<
1911 reg = <0x0 0xffe00000 <<
1912 #address-cells = <2>; <<
1913 #size-cells = <2>; <<
1914 ranges = <0x0 0x0 0x0 <<
1915 <<
1916 sd_emmc_b: mmc@5000 { <<
1917 compatible = <<
1918 reg = <0x0 0x <<
1919 interrupts = <<
1920 status = "dis <<
1921 clocks = <&cl <<
1922 <&clk <<
1923 <&clk <<
1924 clock-names = <<
1925 resets = <&re <<
1926 }; <<
1927 <<
1928 sd_emmc_c: mmc@7000 { <<
1929 compatible = <<
1930 reg = <0x0 0x <<
1931 interrupts = <<
1932 status = "dis <<
1933 clocks = <&cl <<
1934 <&clk <<
1935 <&clk <<
1936 clock-names = <<
1937 resets = <&re <<
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; <<
1965 <<
1966 sram: sram@fffc0000 { <<
1967 compatible = "mmio-sr <<
1968 reg = <0x0 0xfffc0000 <<
1969 #address-cells = <1>; <<
1970 #size-cells = <1>; <<
1971 ranges = <0 0x0 0xfff <<
1972 <<
1973 cpu_scp_lpri: scp-sra <<
1974 compatible = <<
1975 reg = <0x1300 <<
1976 }; <<
1977 <<
1978 cpu_scp_hpri: scp-sra <<
1979 compatible = <<
1980 reg = <0x1340 <<
1981 }; <<
1982 }; <<
1983 }; <<
1984 <<
1985 timer { <<
1986 compatible = "arm,armv8-timer <<
1987 interrupts = <GIC_PPI 13 <<
1988 (GIC_CPU_MASK_RAW(0xf <<
1989 <GIC_PPI 14 <<
1990 (GIC_CPU_MASK_RAW(0xf <<
1991 <GIC_PPI 11 <<
1992 (GIC_CPU_MASK_RAW(0xf <<
1993 <GIC_PPI 10 <<
1994 (GIC_CPU_MASK_RAW(0xf <<
1995 }; <<
1996 <<
1997 xtal: xtal-clk { <<
1998 compatible = "fixed-clock"; <<
1999 clock-frequency = <24000000>; <<
2000 clock-output-names = "xtal"; <<
2001 #clock-cells = <0>; <<
2002 }; 1198 };
2003 }; 1199 };
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