1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { !! 23 tdmif_a: audio-controller@0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { !! 34 tdmif_b: audio-controller@1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { !! 45 tdmif_c: audio-controller@2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
>> 56 ao_alt_xtal: ao_alt_xtal-clk {
>> 57 compatible = "fixed-clock";
>> 58 clock-frequency = <32000000>;
>> 59 clock-output-names = "ao_alt_xtal";
>> 60 #clock-cells = <0>;
>> 61 };
>> 62
57 arm-pmu { 63 arm-pmu {
58 compatible = "arm,cortex-a53-p 64 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 70 };
65 71
66 cpus { 72 cpus {
67 #address-cells = <0x2>; 73 #address-cells = <0x2>;
68 #size-cells = <0x0>; 74 #size-cells = <0x0>;
69 75
70 cpu0: cpu@0 { 76 cpu0: cpu@0 {
71 device_type = "cpu"; 77 device_type = "cpu";
72 compatible = "arm,cort !! 78 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <0x0 0x0>; 79 reg = <0x0 0x0>;
74 enable-method = "psci" 80 enable-method = "psci";
75 next-level-cache = <&l 81 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 <<
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 82 };
80 83
81 cpu1: cpu@1 { 84 cpu1: cpu@1 {
82 device_type = "cpu"; 85 device_type = "cpu";
83 compatible = "arm,cort !! 86 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>; 87 reg = <0x0 0x1>;
85 enable-method = "psci" 88 enable-method = "psci";
86 next-level-cache = <&l 89 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 <<
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 90 };
91 91
92 cpu2: cpu@2 { 92 cpu2: cpu@2 {
93 device_type = "cpu"; 93 device_type = "cpu";
94 compatible = "arm,cort !! 94 compatible = "arm,cortex-a53", "arm,armv8";
95 reg = <0x0 0x2>; 95 reg = <0x0 0x2>;
96 enable-method = "psci" 96 enable-method = "psci";
97 next-level-cache = <&l 97 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 <<
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 98 };
102 99
103 cpu3: cpu@3 { 100 cpu3: cpu@3 {
104 device_type = "cpu"; 101 device_type = "cpu";
105 compatible = "arm,cort !! 102 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x3>; 103 reg = <0x0 0x3>;
107 enable-method = "psci" 104 enable-method = "psci";
108 next-level-cache = <&l 105 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 <<
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 106 };
113 107
114 l2: l2-cache0 { 108 l2: l2-cache0 {
115 compatible = "cache"; 109 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 110 };
119 }; 111 };
120 112
121 sm: secure-monitor { <<
122 compatible = "amlogic,meson-gx <<
123 }; <<
124 <<
125 efuse: efuse { <<
126 compatible = "amlogic,meson-gx <<
127 clocks = <&clkc CLKID_EFUSE>; <<
128 #address-cells = <1>; <<
129 #size-cells = <1>; <<
130 read-only; <<
131 secure-monitor = <&sm>; <<
132 }; <<
133 <<
134 psci { 113 psci {
135 compatible = "arm,psci-1.0"; 114 compatible = "arm,psci-1.0";
136 method = "smc"; 115 method = "smc";
137 }; 116 };
138 117
139 reserved-memory { 118 reserved-memory {
140 #address-cells = <2>; 119 #address-cells = <2>;
141 #size-cells = <2>; 120 #size-cells = <2>;
142 ranges; 121 ranges;
143 122
144 /* 16 MiB reserved for Hardwar 123 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 124 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 125 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 126 no-map;
148 }; 127 };
149 128
150 /* Alternate 3 MiB reserved fo 129 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 130 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 131 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 132 no-map;
154 }; 133 };
155 }; 134 };
156 135
157 scpi { <<
158 compatible = "arm,scpi-pre-1.0 <<
159 mboxes = <&mailbox 1 &mailbox <<
160 shmem = <&cpu_scp_lpri &cpu_sc <<
161 <<
162 scpi_clocks: clocks { <<
163 compatible = "arm,scpi <<
164 <<
165 scpi_dvfs: clocks-0 { <<
166 compatible = " <<
167 #clock-cells = <<
168 clock-indices <<
169 clock-output-n <<
170 }; <<
171 }; <<
172 <<
173 scpi_sensors: sensors { <<
174 compatible = "amlogic, <<
175 #thermal-sensor-cells <<
176 }; <<
177 }; <<
178 <<
179 soc { 136 soc {
180 compatible = "simple-bus"; 137 compatible = "simple-bus";
181 #address-cells = <2>; 138 #address-cells = <2>;
182 #size-cells = <2>; 139 #size-cells = <2>;
183 ranges; 140 ranges;
184 141
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 142 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, !! 143 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
279 "snps,dwm !! 144 reg = <0x0 0xff3f0000 0x0 0x10000
280 "snps,dwm !! 145 0x0 0xff634540 0x0 0x8>;
281 reg = <0x0 0xff3f0000 <<
282 <0x0 0xff634540 <<
283 interrupts = <GIC_SPI 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 147 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 148 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 149 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 150 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 151 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 152 status = "disabled";
295 }; 153 };
296 154
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 155 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 156 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 157 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 158 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 159 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 160 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 161 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 162 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 163 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 164 status = "disabled";
316 }; 165 };
317 166
318 periphs: bus@ff634000 { 167 periphs: bus@ff634000 {
319 compatible = "simple-b 168 compatible = "simple-bus";
320 reg = <0x0 0xff634000 169 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 170 #address-cells = <2>;
322 #size-cells = <2>; 171 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 172 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 173
325 hwrng: rng@18 { 174 hwrng: rng@18 {
326 compatible = " 175 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 176 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 177 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 178 clock-names = "core";
330 }; 179 };
331 180
332 pinctrl_periphs: pinct 181 pinctrl_periphs: pinctrl@480 {
333 compatible = " 182 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 183 #address-cells = <2>;
335 #size-cells = 184 #size-cells = <2>;
336 ranges; 185 ranges;
337 186
338 gpio: bank@480 187 gpio: bank@480 {
339 reg = 188 reg = <0x0 0x00480 0x0 0x40>,
340 189 <0x0 0x004e8 0x0 0x14>,
341 190 <0x0 0x00520 0x0 0x14>,
342 191 <0x0 0x00430 0x0 0x3c>;
343 reg-na 192 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 193 gpio-controller;
345 #gpio- 194 #gpio-cells = <2>;
346 gpio-r 195 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 196 };
348 197
349 i2c0_pins: i2c 198 i2c0_pins: i2c0 {
350 mux { 199 mux {
351 200 groups = "i2c0_sck",
352 201 "i2c0_sda";
353 202 function = "i2c0";
354 <<
355 }; 203 };
356 }; 204 };
357 205
358 i2c1_x_pins: i 206 i2c1_x_pins: i2c1_x {
359 mux { 207 mux {
360 208 groups = "i2c1_sck_x",
361 209 "i2c1_sda_x";
362 210 function = "i2c1";
363 <<
364 }; 211 };
365 }; 212 };
366 213
367 i2c1_z_pins: i 214 i2c1_z_pins: i2c1_z {
368 mux { 215 mux {
369 216 groups = "i2c1_sck_z",
370 217 "i2c1_sda_z";
371 218 function = "i2c1";
372 <<
373 }; 219 };
374 }; 220 };
375 221
376 i2c2_a_pins: i 222 i2c2_a_pins: i2c2_a {
377 mux { 223 mux {
378 224 groups = "i2c2_sck_a",
379 225 "i2c2_sda_a";
380 226 function = "i2c2";
381 <<
382 }; 227 };
383 }; 228 };
384 229
385 i2c2_x_pins: i 230 i2c2_x_pins: i2c2_x {
386 mux { 231 mux {
387 232 groups = "i2c2_sck_x",
388 233 "i2c2_sda_x";
389 234 function = "i2c2";
390 <<
391 }; 235 };
392 }; 236 };
393 237
394 i2c3_a6_pins: 238 i2c3_a6_pins: i2c3_a6 {
395 mux { 239 mux {
396 240 groups = "i2c3_sda_a6",
397 241 "i2c3_sck_a7";
398 242 function = "i2c3";
399 <<
400 }; 243 };
401 }; 244 };
402 245
403 i2c3_a12_pins: 246 i2c3_a12_pins: i2c3_a12 {
404 mux { 247 mux {
405 248 groups = "i2c3_sda_a12",
406 249 "i2c3_sck_a13";
407 250 function = "i2c3";
408 <<
409 }; 251 };
410 }; 252 };
411 253
412 i2c3_a19_pins: 254 i2c3_a19_pins: i2c3_a19 {
413 mux { 255 mux {
414 256 groups = "i2c3_sda_a19",
415 257 "i2c3_sck_a20";
416 258 function = "i2c3";
417 <<
418 }; 259 };
419 }; 260 };
420 261
421 emmc_pins: emm 262 emmc_pins: emmc {
422 mux-0 <<
423 <<
424 <<
425 <<
426 <<
427 <<
428 <<
429 <<
430 <<
431 <<
432 <<
433 <<
434 }; <<
435 <<
436 mux-1 <<
437 <<
438 <<
439 <<
440 }; <<
441 }; <<
442 <<
443 nand_all_pins: <<
444 mux { 263 mux {
445 264 groups = "emmc_nand_d0",
446 265 "emmc_nand_d1",
447 266 "emmc_nand_d2",
448 267 "emmc_nand_d3",
449 268 "emmc_nand_d4",
450 269 "emmc_nand_d5",
451 270 "emmc_nand_d6",
452 271 "emmc_nand_d7",
453 !! 272 "emmc_clk",
454 !! 273 "emmc_cmd",
455 !! 274 "emmc_ds";
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: <<
465 mux { <<
466 <<
467 275 function = "emmc";
468 <<
469 }; 276 };
470 }; 277 };
471 278
472 emmc_clk_gate_ 279 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 280 mux {
474 281 groups = "BOOT_8";
475 282 function = "gpio_periphs";
>> 283 };
>> 284 cfg-pull-down {
>> 285 pins = "BOOT_8";
476 286 bias-pull-down;
477 }; 287 };
478 }; 288 };
479 289
480 eth_rgmii_x_pi 290 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 291 mux {
482 292 groups = "eth_mdio_x",
483 293 "eth_mdc_x",
484 294 "eth_rgmii_rx_clk_x",
485 295 "eth_rx_dv_x",
486 296 "eth_rxd0_x",
487 297 "eth_rxd1_x",
488 298 "eth_rxd2_rgmii",
489 299 "eth_rxd3_rgmii",
490 300 "eth_rgmii_tx_clk",
491 301 "eth_txen_x",
492 302 "eth_txd0_x",
493 303 "eth_txd1_x",
494 304 "eth_txd2_rgmii",
495 305 "eth_txd3_rgmii";
496 306 function = "eth";
497 <<
498 }; 307 };
499 }; 308 };
500 309
501 eth_rgmii_y_pi 310 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 311 mux {
503 312 groups = "eth_mdio_y",
504 313 "eth_mdc_y",
505 314 "eth_rgmii_rx_clk_y",
506 315 "eth_rx_dv_y",
507 316 "eth_rxd0_y",
508 317 "eth_rxd1_y",
509 318 "eth_rxd2_rgmii",
510 319 "eth_rxd3_rgmii",
511 320 "eth_rgmii_tx_clk",
512 321 "eth_txen_y",
513 322 "eth_txd0_y",
514 323 "eth_txd1_y",
515 324 "eth_txd2_rgmii",
516 325 "eth_txd3_rgmii";
517 326 function = "eth";
518 <<
519 }; 327 };
520 }; 328 };
521 329
522 eth_rmii_x_pin 330 eth_rmii_x_pins: eth-x-rmii {
523 mux { 331 mux {
524 332 groups = "eth_mdio_x",
525 333 "eth_mdc_x",
526 334 "eth_rgmii_rx_clk_x",
527 335 "eth_rx_dv_x",
528 336 "eth_rxd0_x",
529 337 "eth_rxd1_x",
530 338 "eth_txen_x",
531 339 "eth_txd0_x",
532 340 "eth_txd1_x";
533 341 function = "eth";
534 <<
535 }; 342 };
536 }; 343 };
537 344
538 eth_rmii_y_pin 345 eth_rmii_y_pins: eth-y-rmii {
539 mux { 346 mux {
540 347 groups = "eth_mdio_y",
541 348 "eth_mdc_y",
542 349 "eth_rgmii_rx_clk_y",
543 350 "eth_rx_dv_y",
544 351 "eth_rxd0_y",
545 352 "eth_rxd1_y",
546 353 "eth_txen_y",
547 354 "eth_txd0_y",
548 355 "eth_txd1_y";
549 356 function = "eth";
550 <<
551 }; 357 };
552 }; 358 };
553 359
554 mclk_b_pins: m 360 mclk_b_pins: mclk_b {
555 mux { 361 mux {
556 362 groups = "mclk_b";
557 363 function = "mclk_b";
558 <<
559 }; 364 };
560 }; 365 };
561 366
562 mclk_c_pins: m 367 mclk_c_pins: mclk_c {
563 mux { 368 mux {
564 369 groups = "mclk_c";
565 370 function = "mclk_c";
566 <<
567 }; 371 };
568 }; 372 };
569 373
570 pdm_dclk_a14_p 374 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 375 mux {
572 376 groups = "pdm_dclk_a14";
573 377 function = "pdm";
574 <<
575 }; 378 };
576 }; 379 };
577 380
578 pdm_dclk_a19_p 381 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 382 mux {
580 383 groups = "pdm_dclk_a19";
581 384 function = "pdm";
582 <<
583 }; 385 };
584 }; 386 };
585 387
586 pdm_din0_pins: 388 pdm_din0_pins: pdm_din0 {
587 mux { 389 mux {
588 390 groups = "pdm_din0";
589 391 function = "pdm";
590 <<
591 }; 392 };
592 }; 393 };
593 394
594 pdm_din1_pins: 395 pdm_din1_pins: pdm_din1 {
595 mux { 396 mux {
596 397 groups = "pdm_din1";
597 398 function = "pdm";
598 <<
599 }; 399 };
600 }; 400 };
601 401
602 pdm_din2_pins: 402 pdm_din2_pins: pdm_din2 {
603 mux { 403 mux {
604 404 groups = "pdm_din2";
605 405 function = "pdm";
606 <<
607 }; 406 };
608 }; 407 };
609 408
610 pdm_din3_pins: 409 pdm_din3_pins: pdm_din3 {
611 mux { 410 mux {
612 411 groups = "pdm_din3";
613 412 function = "pdm";
614 <<
615 }; 413 };
616 }; 414 };
617 415
618 pwm_a_a_pins: 416 pwm_a_a_pins: pwm_a_a {
619 mux { 417 mux {
620 418 groups = "pwm_a_a";
621 419 function = "pwm_a";
622 <<
623 }; 420 };
624 }; 421 };
625 422
626 pwm_a_x18_pins 423 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 424 mux {
628 425 groups = "pwm_a_x18";
629 426 function = "pwm_a";
630 <<
631 }; 427 };
632 }; 428 };
633 429
634 pwm_a_x20_pins 430 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 431 mux {
636 432 groups = "pwm_a_x20";
637 433 function = "pwm_a";
638 <<
639 }; 434 };
640 }; 435 };
641 436
642 pwm_a_z_pins: 437 pwm_a_z_pins: pwm_a_z {
643 mux { 438 mux {
644 439 groups = "pwm_a_z";
645 440 function = "pwm_a";
646 <<
647 }; 441 };
648 }; 442 };
649 443
650 pwm_b_a_pins: 444 pwm_b_a_pins: pwm_b_a {
651 mux { 445 mux {
652 446 groups = "pwm_b_a";
653 447 function = "pwm_b";
654 <<
655 }; 448 };
656 }; 449 };
657 450
658 pwm_b_x_pins: 451 pwm_b_x_pins: pwm_b_x {
659 mux { 452 mux {
660 453 groups = "pwm_b_x";
661 454 function = "pwm_b";
662 <<
663 }; 455 };
664 }; 456 };
665 457
666 pwm_b_z_pins: 458 pwm_b_z_pins: pwm_b_z {
667 mux { 459 mux {
668 460 groups = "pwm_b_z";
669 461 function = "pwm_b";
670 <<
671 }; 462 };
672 }; 463 };
673 464
674 pwm_c_a_pins: 465 pwm_c_a_pins: pwm_c_a {
675 mux { 466 mux {
676 467 groups = "pwm_c_a";
677 468 function = "pwm_c";
678 <<
679 }; 469 };
680 }; 470 };
681 471
682 pwm_c_x10_pins 472 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 473 mux {
684 474 groups = "pwm_c_x10";
685 475 function = "pwm_c";
686 <<
687 }; 476 };
688 }; 477 };
689 478
690 pwm_c_x17_pins 479 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 480 mux {
692 481 groups = "pwm_c_x17";
693 482 function = "pwm_c";
694 <<
695 }; 483 };
696 }; 484 };
697 485
698 pwm_d_x11_pins 486 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 487 mux {
700 488 groups = "pwm_d_x11";
701 489 function = "pwm_d";
702 <<
703 }; 490 };
704 }; 491 };
705 492
706 pwm_d_x16_pins 493 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 494 mux {
708 495 groups = "pwm_d_x16";
709 496 function = "pwm_d";
710 <<
711 }; 497 };
712 }; 498 };
713 499
714 sdio_pins: sdi 500 sdio_pins: sdio {
715 mux-0 !! 501 mux {
716 502 groups = "sdio_d0",
717 503 "sdio_d1",
718 504 "sdio_d2",
719 505 "sdio_d3",
720 !! 506 "sdio_cmd",
721 !! 507 "sdio_clk";
722 <<
723 }; <<
724 <<
725 mux-1 <<
726 <<
727 508 function = "sdio";
728 <<
729 }; 509 };
730 }; 510 };
731 511
732 sdio_clk_gate_ 512 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 513 mux {
734 514 groups = "GPIOX_4";
735 515 function = "gpio_periphs";
>> 516 };
>> 517 cfg-pull-down {
>> 518 pins = "GPIOX_4";
736 519 bias-pull-down;
737 }; 520 };
738 }; 521 };
739 522
740 spdif_in_z_pin 523 spdif_in_z_pins: spdif_in_z {
741 mux { 524 mux {
742 525 groups = "spdif_in_z";
743 526 function = "spdif_in";
744 <<
745 }; 527 };
746 }; 528 };
747 529
748 spdif_in_a1_pi 530 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 531 mux {
750 532 groups = "spdif_in_a1";
751 533 function = "spdif_in";
752 <<
753 }; 534 };
754 }; 535 };
755 536
756 spdif_in_a7_pi 537 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 538 mux {
758 539 groups = "spdif_in_a7";
759 540 function = "spdif_in";
760 <<
761 }; 541 };
762 }; 542 };
763 543
764 spdif_in_a19_p 544 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 545 mux {
766 546 groups = "spdif_in_a19";
767 547 function = "spdif_in";
768 <<
769 }; 548 };
770 }; 549 };
771 550
772 spdif_in_a20_p 551 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 552 mux {
774 553 groups = "spdif_in_a20";
775 554 function = "spdif_in";
776 <<
777 }; 555 };
778 }; 556 };
779 557
780 spdif_out_a1_p 558 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 559 mux {
782 560 groups = "spdif_out_a1";
783 561 function = "spdif_out";
784 <<
785 }; 562 };
786 }; 563 };
787 564
788 spdif_out_a11_ 565 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 566 mux {
790 567 groups = "spdif_out_a11";
791 568 function = "spdif_out";
792 <<
793 }; 569 };
794 }; 570 };
795 571
796 spdif_out_a19_ 572 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 573 mux {
798 574 groups = "spdif_out_a19";
799 575 function = "spdif_out";
800 <<
801 }; 576 };
802 }; 577 };
803 578
804 spdif_out_a20_ 579 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 580 mux {
806 581 groups = "spdif_out_a20";
807 582 function = "spdif_out";
808 <<
809 }; 583 };
810 }; 584 };
811 585
812 spdif_out_z_pi 586 spdif_out_z_pins: spdif_out_z {
813 mux { 587 mux {
814 588 groups = "spdif_out_z";
815 589 function = "spdif_out";
816 <<
817 }; 590 };
818 }; 591 };
819 592
820 spi0_pins: spi 593 spi0_pins: spi0 {
821 mux { 594 mux {
822 595 groups = "spi0_miso",
823 596 "spi0_mosi",
824 597 "spi0_clk";
825 598 function = "spi0";
826 <<
827 }; 599 };
828 }; 600 };
829 601
830 spi0_ss0_pins: 602 spi0_ss0_pins: spi0_ss0 {
831 mux { 603 mux {
832 604 groups = "spi0_ss0";
833 605 function = "spi0";
834 <<
835 }; 606 };
836 }; 607 };
837 608
838 spi0_ss1_pins: 609 spi0_ss1_pins: spi0_ss1 {
839 mux { 610 mux {
840 611 groups = "spi0_ss1";
841 612 function = "spi0";
842 <<
843 }; 613 };
844 }; 614 };
845 615
846 spi0_ss2_pins: 616 spi0_ss2_pins: spi0_ss2 {
847 mux { 617 mux {
848 618 groups = "spi0_ss2";
849 619 function = "spi0";
850 <<
851 }; 620 };
852 }; 621 };
853 622
854 spi1_a_pins: s 623 spi1_a_pins: spi1_a {
855 mux { 624 mux {
856 625 groups = "spi1_miso_a",
857 626 "spi1_mosi_a",
858 627 "spi1_clk_a";
859 628 function = "spi1";
860 <<
861 }; 629 };
862 }; 630 };
863 631
864 spi1_ss0_a_pin 632 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 633 mux {
866 634 groups = "spi1_ss0_a";
867 635 function = "spi1";
868 <<
869 }; 636 };
870 }; 637 };
871 638
872 spi1_ss1_pins: 639 spi1_ss1_pins: spi1_ss1 {
873 mux { 640 mux {
874 641 groups = "spi1_ss1";
875 642 function = "spi1";
876 <<
877 }; 643 };
878 }; 644 };
879 645
880 spi1_x_pins: s 646 spi1_x_pins: spi1_x {
881 mux { 647 mux {
882 648 groups = "spi1_miso_x",
883 649 "spi1_mosi_x",
884 650 "spi1_clk_x";
885 651 function = "spi1";
886 <<
887 }; 652 };
888 }; 653 };
889 654
890 spi1_ss0_x_pin 655 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 656 mux {
892 657 groups = "spi1_ss0_x";
893 658 function = "spi1";
894 <<
895 }; 659 };
896 }; 660 };
897 661
898 tdma_din0_pins 662 tdma_din0_pins: tdma_din0 {
899 mux { 663 mux {
900 664 groups = "tdma_din0";
901 665 function = "tdma";
902 <<
903 }; 666 };
904 }; 667 };
905 668
906 tdma_dout0_x14 669 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 670 mux {
908 671 groups = "tdma_dout0_x14";
909 672 function = "tdma";
910 <<
911 }; 673 };
912 }; 674 };
913 675
914 tdma_dout0_x15 676 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 677 mux {
916 678 groups = "tdma_dout0_x15";
917 679 function = "tdma";
918 <<
919 }; 680 };
920 }; 681 };
921 682
922 tdma_dout1_pin 683 tdma_dout1_pins: tdma_dout1 {
923 mux { 684 mux {
924 685 groups = "tdma_dout1";
925 686 function = "tdma";
926 <<
927 }; 687 };
928 }; 688 };
929 689
930 tdma_din1_pins 690 tdma_din1_pins: tdma_din1 {
931 mux { 691 mux {
932 692 groups = "tdma_din1";
933 693 function = "tdma";
934 <<
935 }; 694 };
936 }; 695 };
937 696
938 tdma_fs_pins: 697 tdma_fs_pins: tdma_fs {
939 mux { 698 mux {
940 699 groups = "tdma_fs";
941 700 function = "tdma";
942 <<
943 }; 701 };
944 }; 702 };
945 703
946 tdma_fs_slv_pi 704 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 705 mux {
948 706 groups = "tdma_fs_slv";
949 707 function = "tdma";
950 <<
951 }; 708 };
952 }; 709 };
953 710
954 tdma_sclk_pins 711 tdma_sclk_pins: tdma_sclk {
955 mux { 712 mux {
956 713 groups = "tdma_sclk";
957 714 function = "tdma";
958 <<
959 }; 715 };
960 }; 716 };
961 717
962 tdma_sclk_slv_ 718 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 719 mux {
964 720 groups = "tdma_sclk_slv";
965 721 function = "tdma";
966 <<
967 }; 722 };
968 }; 723 };
969 724
970 tdmb_din0_pins 725 tdmb_din0_pins: tdmb_din0 {
971 mux { 726 mux {
972 727 groups = "tdmb_din0";
973 728 function = "tdmb";
974 <<
975 }; 729 };
976 }; 730 };
977 731
978 tdmb_din1_pins 732 tdmb_din1_pins: tdmb_din1 {
979 mux { 733 mux {
980 734 groups = "tdmb_din1";
981 735 function = "tdmb";
982 <<
983 }; 736 };
984 }; 737 };
985 738
986 tdmb_din2_pins 739 tdmb_din2_pins: tdmb_din2 {
987 mux { 740 mux {
988 741 groups = "tdmb_din2";
989 742 function = "tdmb";
990 <<
991 }; 743 };
992 }; 744 };
993 745
994 tdmb_din3_pins 746 tdmb_din3_pins: tdmb_din3 {
995 mux { 747 mux {
996 748 groups = "tdmb_din3";
997 749 function = "tdmb";
998 <<
999 }; 750 };
1000 }; 751 };
1001 752
1002 tdmb_dout0_pi 753 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 754 mux {
1004 755 groups = "tdmb_dout0";
1005 756 function = "tdmb";
1006 <<
1007 }; 757 };
1008 }; 758 };
1009 759
1010 tdmb_dout1_pi 760 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 761 mux {
1012 762 groups = "tdmb_dout1";
1013 763 function = "tdmb";
1014 <<
1015 }; 764 };
1016 }; 765 };
1017 766
1018 tdmb_dout2_pi 767 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 768 mux {
1020 769 groups = "tdmb_dout2";
1021 770 function = "tdmb";
1022 <<
1023 }; 771 };
1024 }; 772 };
1025 773
1026 tdmb_dout3_pi 774 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 775 mux {
1028 776 groups = "tdmb_dout3";
1029 777 function = "tdmb";
1030 <<
1031 }; 778 };
1032 }; 779 };
1033 780
1034 tdmb_fs_pins: 781 tdmb_fs_pins: tdmb_fs {
1035 mux { 782 mux {
1036 783 groups = "tdmb_fs";
1037 784 function = "tdmb";
1038 <<
1039 }; 785 };
1040 }; 786 };
1041 787
1042 tdmb_fs_slv_p 788 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 789 mux {
1044 790 groups = "tdmb_fs_slv";
1045 791 function = "tdmb";
1046 <<
1047 }; 792 };
1048 }; 793 };
1049 794
1050 tdmb_sclk_pin 795 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 796 mux {
1052 797 groups = "tdmb_sclk";
1053 798 function = "tdmb";
1054 <<
1055 }; 799 };
1056 }; 800 };
1057 801
1058 tdmb_sclk_slv 802 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 803 mux {
1060 804 groups = "tdmb_sclk_slv";
1061 805 function = "tdmb";
1062 <<
1063 }; 806 };
1064 }; 807 };
1065 808
1066 tdmc_fs_pins: 809 tdmc_fs_pins: tdmc_fs {
1067 mux { 810 mux {
1068 811 groups = "tdmc_fs";
1069 812 function = "tdmc";
1070 <<
1071 }; 813 };
1072 }; 814 };
1073 815
1074 tdmc_fs_slv_p 816 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 817 mux {
1076 818 groups = "tdmc_fs_slv";
1077 819 function = "tdmc";
1078 <<
1079 }; 820 };
1080 }; 821 };
1081 822
1082 tdmc_sclk_pin 823 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 824 mux {
1084 825 groups = "tdmc_sclk";
1085 826 function = "tdmc";
1086 <<
1087 }; 827 };
1088 }; 828 };
1089 829
1090 tdmc_sclk_slv 830 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 831 mux {
1092 832 groups = "tdmc_sclk_slv";
1093 833 function = "tdmc";
1094 <<
1095 }; 834 };
1096 }; 835 };
1097 836
1098 tdmc_din0_pin 837 tdmc_din0_pins: tdmc_din0 {
1099 mux { 838 mux {
1100 839 groups = "tdmc_din0";
1101 840 function = "tdmc";
1102 <<
1103 }; 841 };
1104 }; 842 };
1105 843
1106 tdmc_din1_pin 844 tdmc_din1_pins: tdmc_din1 {
1107 mux { 845 mux {
1108 846 groups = "tdmc_din1";
1109 847 function = "tdmc";
1110 <<
1111 }; 848 };
1112 }; 849 };
1113 850
1114 tdmc_din2_pin 851 tdmc_din2_pins: tdmc_din2 {
1115 mux { 852 mux {
1116 853 groups = "tdmc_din2";
1117 854 function = "tdmc";
1118 <<
1119 }; 855 };
1120 }; 856 };
1121 857
1122 tdmc_din3_pin 858 tdmc_din3_pins: tdmc_din3 {
1123 mux { 859 mux {
1124 860 groups = "tdmc_din3";
1125 861 function = "tdmc";
1126 <<
1127 }; 862 };
1128 }; 863 };
1129 864
1130 tdmc_dout0_pi 865 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 866 mux {
1132 867 groups = "tdmc_dout0";
1133 868 function = "tdmc";
1134 <<
1135 }; 869 };
1136 }; 870 };
1137 871
1138 tdmc_dout1_pi 872 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 873 mux {
1140 874 groups = "tdmc_dout1";
1141 875 function = "tdmc";
1142 <<
1143 }; 876 };
1144 }; 877 };
1145 878
1146 tdmc_dout2_pi 879 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 880 mux {
1148 881 groups = "tdmc_dout2";
1149 882 function = "tdmc";
1150 <<
1151 }; 883 };
1152 }; 884 };
1153 885
1154 tdmc_dout3_pi 886 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 887 mux {
1156 888 groups = "tdmc_dout3";
1157 889 function = "tdmc";
1158 <<
1159 }; 890 };
1160 }; 891 };
1161 892
1162 uart_a_pins: 893 uart_a_pins: uart_a {
1163 mux { 894 mux {
1164 895 groups = "uart_tx_a",
1165 896 "uart_rx_a";
1166 897 function = "uart_a";
1167 <<
1168 }; 898 };
1169 }; 899 };
1170 900
1171 uart_a_cts_rt 901 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 902 mux {
1173 903 groups = "uart_cts_a",
1174 904 "uart_rts_a";
1175 905 function = "uart_a";
1176 <<
1177 }; 906 };
1178 }; 907 };
1179 908
1180 uart_b_x_pins 909 uart_b_x_pins: uart_b_x {
1181 mux { 910 mux {
1182 911 groups = "uart_tx_b_x",
1183 912 "uart_rx_b_x";
1184 913 function = "uart_b";
1185 <<
1186 }; 914 };
1187 }; 915 };
1188 916
1189 uart_b_x_cts_ 917 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 918 mux {
1191 919 groups = "uart_cts_b_x",
1192 920 "uart_rts_b_x";
1193 921 function = "uart_b";
1194 <<
1195 }; 922 };
1196 }; 923 };
1197 924
1198 uart_b_z_pins 925 uart_b_z_pins: uart_b_z {
1199 mux { 926 mux {
1200 927 groups = "uart_tx_b_z",
1201 928 "uart_rx_b_z";
1202 929 function = "uart_b";
1203 <<
1204 }; 930 };
1205 }; 931 };
1206 932
1207 uart_b_z_cts_ 933 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 934 mux {
1209 935 groups = "uart_cts_b_z",
1210 936 "uart_rts_b_z";
1211 937 function = "uart_b";
1212 <<
1213 }; 938 };
1214 }; 939 };
1215 940
1216 uart_ao_b_z_p 941 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 942 mux {
1218 943 groups = "uart_ao_tx_b_z",
1219 944 "uart_ao_rx_b_z";
1220 945 function = "uart_ao_b_z";
1221 <<
1222 }; 946 };
1223 }; 947 };
1224 948
1225 uart_ao_b_z_c 949 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 950 mux {
1227 951 groups = "uart_ao_cts_b_z",
1228 952 "uart_ao_rts_b_z";
1229 953 function = "uart_ao_b_z";
1230 <<
1231 }; 954 };
1232 }; 955 };
1233 }; 956 };
1234 }; 957 };
1235 958
1236 hiubus: bus@ff63c000 { 959 hiubus: bus@ff63c000 {
1237 compatible = "simple- 960 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 961 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 962 #address-cells = <2>;
1240 #size-cells = <2>; 963 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 964 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 965
1243 sysctrl: system-contr 966 sysctrl: system-controller@0 {
1244 compatible = 967 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 968 "simple-mfd", "syscon";
1246 reg = <0 0 0 969 reg = <0 0 0 0x400>;
1247 970
1248 clkc: clock-c 971 clkc: clock-controller {
1249 compa 972 compatible = "amlogic,axg-clkc";
1250 #cloc 973 #clock-cells = <1>;
1251 clock <<
1252 clock <<
1253 }; <<
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; 974 };
1300 }; 975 };
1301 }; 976 };
1302 977
1303 mailbox: mailbox@ff63c404 { !! 978 mailbox: mailbox@ff63dc00 {
1304 compatible = "amlogic !! 979 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 !! 980 reg = <0 0xff63dc00 0 0x400>;
1306 interrupts = <GIC_SPI 981 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 982 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 983 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 984 #mbox-cells = <1>;
1310 }; 985 };
1311 986
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 987 audio: bus@ff642000 {
1326 compatible = "simple- 988 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 989 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 990 #address-cells = <2>;
1329 #size-cells = <2>; 991 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 992 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 993
1332 clkc_audio: clock-con 994 clkc_audio: clock-controller@0 {
1333 compatible = 995 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 996 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 997 #clock-cells = <1>;
1336 998
1337 clocks = <&cl 999 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1000 <&clkc CLKID_MPLL0>,
1339 <&cl 1001 <&clkc CLKID_MPLL1>,
1340 <&cl 1002 <&clkc CLKID_MPLL2>,
1341 <&cl 1003 <&clkc CLKID_MPLL3>,
1342 <&cl 1004 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1005 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1006 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1007 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1008 clock-names = "pclk",
1347 1009 "mst_in0",
1348 1010 "mst_in1",
1349 1011 "mst_in2",
1350 1012 "mst_in3",
1351 1013 "mst_in4",
1352 1014 "mst_in5",
1353 1015 "mst_in6",
1354 1016 "mst_in7";
1355 1017
1356 resets = <&re 1018 resets = <&reset RESET_AUDIO>;
1357 }; 1019 };
1358 1020
1359 toddr_a: audio-contro 1021 toddr_a: audio-controller@100 {
1360 compatible = 1022 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x !! 1023 reg = <0x0 0x100 0x0 0x1c>;
1362 #sound-dai-ce 1024 #sound-dai-cells = <0>;
1363 sound-name-pr 1025 sound-name-prefix = "TODDR_A";
1364 interrupts = 1026 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1027 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1028 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- <<
1368 status = "dis 1029 status = "disabled";
1369 }; 1030 };
1370 1031
1371 toddr_b: audio-contro 1032 toddr_b: audio-controller@140 {
1372 compatible = 1033 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x !! 1034 reg = <0x0 0x140 0x0 0x1c>;
1374 #sound-dai-ce 1035 #sound-dai-cells = <0>;
1375 sound-name-pr 1036 sound-name-prefix = "TODDR_B";
1376 interrupts = 1037 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1038 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1039 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- <<
1380 status = "dis 1040 status = "disabled";
1381 }; 1041 };
1382 1042
1383 toddr_c: audio-contro 1043 toddr_c: audio-controller@180 {
1384 compatible = 1044 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x !! 1045 reg = <0x0 0x180 0x0 0x1c>;
1386 #sound-dai-ce 1046 #sound-dai-cells = <0>;
1387 sound-name-pr 1047 sound-name-prefix = "TODDR_C";
1388 interrupts = 1048 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1049 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1050 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- <<
1392 status = "dis 1051 status = "disabled";
1393 }; 1052 };
1394 1053
1395 frddr_a: audio-contro 1054 frddr_a: audio-controller@1c0 {
1396 compatible = 1055 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x !! 1056 reg = <0x0 0x1c0 0x0 0x1c>;
1398 #sound-dai-ce 1057 #sound-dai-cells = <0>;
1399 sound-name-pr 1058 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1059 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1060 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1061 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- <<
1404 status = "dis 1062 status = "disabled";
1405 }; 1063 };
1406 1064
1407 frddr_b: audio-contro 1065 frddr_b: audio-controller@200 {
1408 compatible = 1066 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x !! 1067 reg = <0x0 0x200 0x0 0x1c>;
1410 #sound-dai-ce 1068 #sound-dai-cells = <0>;
1411 sound-name-pr 1069 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1070 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1071 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1072 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- <<
1416 status = "dis 1073 status = "disabled";
1417 }; 1074 };
1418 1075
1419 frddr_c: audio-contro 1076 frddr_c: audio-controller@240 {
1420 compatible = 1077 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x !! 1078 reg = <0x0 0x240 0x0 0x1c>;
1422 #sound-dai-ce 1079 #sound-dai-cells = <0>;
1423 sound-name-pr 1080 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1081 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1082 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1083 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- <<
1428 status = "dis 1084 status = "disabled";
1429 }; 1085 };
1430 1086
1431 arb: reset-controller 1087 arb: reset-controller@280 {
1432 compatible = 1088 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1089 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1090 #reset-cells = <1>;
1435 clocks = <&cl 1091 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1092 };
1437 1093
1438 tdmin_a: audio-contro 1094 tdmin_a: audio-controller@300 {
1439 compatible = 1095 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1096 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1097 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1098 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1099 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1100 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1101 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1102 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1103 clock-names = "pclk", "sclk", "sclk_sel",
1448 1104 "lrclk", "lrclk_sel";
1449 status = "dis 1105 status = "disabled";
1450 }; 1106 };
1451 1107
1452 tdmin_b: audio-contro 1108 tdmin_b: audio-controller@340 {
1453 compatible = 1109 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1110 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1111 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1112 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1113 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1114 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1115 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1116 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1117 clock-names = "pclk", "sclk", "sclk_sel",
1462 1118 "lrclk", "lrclk_sel";
1463 status = "dis 1119 status = "disabled";
1464 }; 1120 };
1465 1121
1466 tdmin_c: audio-contro 1122 tdmin_c: audio-controller@380 {
1467 compatible = 1123 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1124 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1125 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1126 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1127 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1128 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1129 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1130 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1131 clock-names = "pclk", "sclk", "sclk_sel",
1476 1132 "lrclk", "lrclk_sel";
1477 status = "dis 1133 status = "disabled";
1478 }; 1134 };
1479 1135
1480 tdmin_lb: audio-contr 1136 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1137 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1138 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1139 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1140 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1141 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1142 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1143 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1144 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1145 clock-names = "pclk", "sclk", "sclk_sel",
1490 1146 "lrclk", "lrclk_sel";
1491 status = "dis 1147 status = "disabled";
1492 }; 1148 };
1493 1149
1494 spdifin: audio-contro <<
1495 compatible = <<
1496 reg = <0x0 0x <<
1497 #sound-dai-ce <<
1498 sound-name-pr <<
1499 interrupts = <<
1500 clocks = <&cl <<
1501 <&cl <<
1502 clock-names = <<
1503 status = "dis <<
1504 }; <<
1505 <<
1506 spdifout: audio-contr 1150 spdifout: audio-controller@480 {
1507 compatible = 1151 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1152 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1153 #sound-dai-cells = <0>;
1510 sound-name-pr 1154 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1155 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1156 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1157 clock-names = "pclk", "mclk";
1514 status = "dis 1158 status = "disabled";
1515 }; 1159 };
1516 1160
1517 tdmout_a: audio-contr 1161 tdmout_a: audio-controller@500 {
1518 compatible = 1162 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1163 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1164 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1165 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1166 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1167 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1168 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1169 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1170 clock-names = "pclk", "sclk", "sclk_sel",
1527 1171 "lrclk", "lrclk_sel";
1528 status = "dis 1172 status = "disabled";
1529 }; 1173 };
1530 1174
1531 tdmout_b: audio-contr 1175 tdmout_b: audio-controller@540 {
1532 compatible = 1176 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1177 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1178 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1179 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1180 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1181 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1182 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1183 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1184 clock-names = "pclk", "sclk", "sclk_sel",
1541 1185 "lrclk", "lrclk_sel";
1542 status = "dis 1186 status = "disabled";
1543 }; 1187 };
1544 1188
1545 tdmout_c: audio-contr 1189 tdmout_c: audio-controller@580 {
1546 compatible = 1190 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1191 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1192 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1193 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1194 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1195 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1196 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1197 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1198 clock-names = "pclk", "sclk", "sclk_sel",
1555 1199 "lrclk", "lrclk_sel";
1556 status = "dis 1200 status = "disabled";
1557 }; 1201 };
1558 }; 1202 };
1559 1203
1560 aobus: bus@ff800000 { 1204 aobus: bus@ff800000 {
1561 compatible = "simple- 1205 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1206 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1207 #address-cells = <2>;
1564 #size-cells = <2>; 1208 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1209 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1210
1567 sysctrl_AO: sys-ctrl@ 1211 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1212 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1213 reg = <0x0 0x0 0x0 0x100>;
1570 1214
1571 clkc_AO: cloc 1215 clkc_AO: clock-controller {
1572 compa 1216 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1217 #clock-cells = <1>;
1574 #rese 1218 #reset-cells = <1>;
1575 clock <<
1576 clock <<
1577 }; 1219 };
1578 }; 1220 };
1579 1221
1580 pinctrl_aobus: pinctr 1222 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1223 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1224 #address-cells = <2>;
1583 #size-cells = 1225 #size-cells = <2>;
1584 ranges; 1226 ranges;
1585 1227
1586 gpio_ao: bank 1228 gpio_ao: bank@14 {
1587 reg = 1229 reg = <0x0 0x00014 0x0 0x8>,
1588 1230 <0x0 0x0002c 0x0 0x4>,
1589 1231 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1232 reg-names = "mux", "pull", "gpio";
1591 gpio- 1233 gpio-controller;
1592 #gpio 1234 #gpio-cells = <2>;
1593 gpio- 1235 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1236 };
1595 1237
1596 i2c_ao_sck_4_ 1238 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1239 mux {
1598 1240 groups = "i2c_ao_sck_4";
1599 1241 function = "i2c_ao";
1600 <<
1601 }; 1242 };
1602 }; 1243 };
1603 1244
1604 i2c_ao_sck_8_ 1245 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1246 mux {
1606 1247 groups = "i2c_ao_sck_8";
1607 1248 function = "i2c_ao";
1608 <<
1609 }; 1249 };
1610 }; 1250 };
1611 1251
1612 i2c_ao_sck_10 1252 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1253 mux {
1614 1254 groups = "i2c_ao_sck_10";
1615 1255 function = "i2c_ao";
1616 <<
1617 }; 1256 };
1618 }; 1257 };
1619 1258
1620 i2c_ao_sda_5_ 1259 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1260 mux {
1622 1261 groups = "i2c_ao_sda_5";
1623 1262 function = "i2c_ao";
1624 <<
1625 }; 1263 };
1626 }; 1264 };
1627 1265
1628 i2c_ao_sda_9_ 1266 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1267 mux {
1630 1268 groups = "i2c_ao_sda_9";
1631 1269 function = "i2c_ao";
1632 <<
1633 }; 1270 };
1634 }; 1271 };
1635 1272
1636 i2c_ao_sda_11 1273 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1274 mux {
1638 1275 groups = "i2c_ao_sda_11";
1639 1276 function = "i2c_ao";
1640 <<
1641 }; 1277 };
1642 }; 1278 };
1643 1279
1644 remote_input_ 1280 remote_input_ao_pins: remote_input_ao {
1645 mux { 1281 mux {
1646 1282 groups = "remote_input_ao";
1647 1283 function = "remote_input_ao";
1648 <<
1649 }; 1284 };
1650 }; 1285 };
1651 1286
1652 uart_ao_a_pin 1287 uart_ao_a_pins: uart_ao_a {
1653 mux { 1288 mux {
1654 1289 groups = "uart_ao_tx_a",
1655 1290 "uart_ao_rx_a";
1656 1291 function = "uart_ao_a";
1657 <<
1658 }; 1292 };
1659 }; 1293 };
1660 1294
1661 uart_ao_a_cts 1295 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1296 mux {
1663 1297 groups = "uart_ao_cts_a",
1664 1298 "uart_ao_rts_a";
1665 1299 function = "uart_ao_a";
1666 <<
1667 }; 1300 };
1668 }; 1301 };
1669 1302
1670 uart_ao_b_pin 1303 uart_ao_b_pins: uart_ao_b {
1671 mux { 1304 mux {
1672 1305 groups = "uart_ao_tx_b",
1673 1306 "uart_ao_rx_b";
1674 1307 function = "uart_ao_b";
1675 <<
1676 }; 1308 };
1677 }; 1309 };
1678 1310
1679 uart_ao_b_cts 1311 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1312 mux {
1681 1313 groups = "uart_ao_cts_b",
1682 1314 "uart_ao_rts_b";
1683 1315 function = "uart_ao_b";
1684 <<
1685 }; 1316 };
1686 }; 1317 };
1687 }; 1318 };
1688 1319
1689 sec_AO: ao-secure@140 1320 sec_AO: ao-secure@140 {
1690 compatible = 1321 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1322 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1323 amlogic,has-chip-id;
1693 }; 1324 };
1694 1325
1695 pwm_AO_cd: pwm@2000 { 1326 pwm_AO_cd: pwm@2000 {
1696 compatible = 1327 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1328 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1329 #pwm-cells = <3>;
1699 status = "dis 1330 status = "disabled";
1700 }; 1331 };
1701 1332
1702 uart_AO: serial@3000 1333 uart_AO: serial@3000 {
1703 compatible = 1334 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1335 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1336 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1337 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1338 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1339 status = "disabled";
1709 }; 1340 };
1710 1341
1711 uart_AO_B: serial@400 1342 uart_AO_B: serial@4000 {
1712 compatible = 1343 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1344 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1345 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1346 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1347 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1348 status = "disabled";
1718 }; 1349 };
1719 1350
1720 i2c_AO: i2c@5000 { 1351 i2c_AO: i2c@5000 {
1721 compatible = 1352 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1353 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1354 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1355 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1356 #address-cells = <1>;
1726 #size-cells = 1357 #size-cells = <0>;
1727 status = "dis 1358 status = "disabled";
1728 }; 1359 };
1729 1360
1730 pwm_AO_ab: pwm@7000 { 1361 pwm_AO_ab: pwm@7000 {
1731 compatible = 1362 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1363 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1364 #pwm-cells = <3>;
1734 status = "dis 1365 status = "disabled";
1735 }; 1366 };
1736 1367
1737 ir: ir@8000 { 1368 ir: ir@8000 {
1738 compatible = 1369 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1370 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1371 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1372 status = "disabled";
1742 }; 1373 };
1743 1374
1744 saradc: adc@9000 { 1375 saradc: adc@9000 {
1745 compatible = 1376 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1377 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1378 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1379 #io-channel-cells = <1>;
1749 interrupts = 1380 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1381 clocks = <&xtal>,
1751 <&cl 1382 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1383 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1384 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1385 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1386 status = "disabled";
1756 }; 1387 };
1757 }; 1388 };
1758 1389
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1390 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1391 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1392 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1393 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1394 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1395 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1396 interrupt-controller;
1774 interrupts = <GIC_PPI 1397 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1398 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1399 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1400 #address-cells = <0>;
1778 }; 1401 };
1779 1402
1780 cbus: bus@ffd00000 { 1403 cbus: bus@ffd00000 {
1781 compatible = "simple- 1404 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1405 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1406 #address-cells = <2>;
1784 #size-cells = <2>; 1407 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1408 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1409
1787 reset: reset-controll 1410 reset: reset-controller@1004 {
1788 compatible = 1411 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1412 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1413 #reset-cells = <1>;
1791 }; 1414 };
1792 1415
1793 gpio_intc: interrupt- 1416 gpio_intc: interrupt-controller@f080 {
1794 compatible = !! 1417 compatible = "amlogic,meson-gpio-intc";
1795 <<
1796 reg = <0x0 0x 1418 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1419 interrupt-controller;
1798 #interrupt-ce 1420 #interrupt-cells = <2>;
1799 amlogic,chann 1421 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; !! 1422 status = "disabled";
1801 <<
1802 watchdog@f0d0 { <<
1803 compatible = <<
1804 reg = <0x0 0x <<
1805 clocks = <&xt <<
1806 }; 1423 };
1807 1424
1808 pwm_ab: pwm@1b000 { 1425 pwm_ab: pwm@1b000 {
1809 compatible = 1426 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1427 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1428 #pwm-cells = <3>;
1812 status = "dis 1429 status = "disabled";
1813 }; 1430 };
1814 1431
1815 pwm_cd: pwm@1a000 { 1432 pwm_cd: pwm@1a000 {
1816 compatible = 1433 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1434 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1435 #pwm-cells = <3>;
1819 status = "dis 1436 status = "disabled";
1820 }; 1437 };
1821 1438
1822 spicc0: spi@13000 { 1439 spicc0: spi@13000 {
1823 compatible = 1440 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1441 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1442 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1443 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1444 clock-names = "core";
1828 #address-cell 1445 #address-cells = <1>;
1829 #size-cells = 1446 #size-cells = <0>;
1830 status = "dis 1447 status = "disabled";
1831 }; 1448 };
1832 1449
1833 spicc1: spi@15000 { 1450 spicc1: spi@15000 {
1834 compatible = 1451 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1452 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1453 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1454 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1455 clock-names = "core";
1839 #address-cell 1456 #address-cells = <1>;
1840 #size-cells = 1457 #size-cells = <0>;
1841 status = "dis 1458 status = "disabled";
1842 }; 1459 };
1843 1460
1844 clk_msr: clock-measur <<
1845 compatible = <<
1846 reg = <0x0 0x <<
1847 }; <<
1848 <<
1849 i2c3: i2c@1c000 { 1461 i2c3: i2c@1c000 {
1850 compatible = 1462 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1463 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1464 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1465 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1466 #address-cells = <1>;
1855 #size-cells = 1467 #size-cells = <0>;
1856 status = "dis 1468 status = "disabled";
1857 }; 1469 };
1858 1470
1859 i2c2: i2c@1d000 { 1471 i2c2: i2c@1d000 {
1860 compatible = 1472 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1473 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1474 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1475 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1476 #address-cells = <1>;
1865 #size-cells = 1477 #size-cells = <0>;
1866 status = "dis 1478 status = "disabled";
1867 }; 1479 };
1868 1480
1869 i2c1: i2c@1e000 { 1481 i2c1: i2c@1e000 {
1870 compatible = 1482 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1483 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1484 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1485 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1486 #address-cells = <1>;
1875 #size-cells = 1487 #size-cells = <0>;
1876 status = "dis 1488 status = "disabled";
1877 }; 1489 };
1878 1490
1879 i2c0: i2c@1f000 { 1491 i2c0: i2c@1f000 {
1880 compatible = 1492 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1493 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1494 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1495 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1496 #address-cells = <1>;
1885 #size-cells = 1497 #size-cells = <0>;
1886 status = "dis 1498 status = "disabled";
1887 }; 1499 };
1888 1500
1889 uart_B: serial@23000 1501 uart_B: serial@23000 {
1890 compatible = 1502 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1503 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1504 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1505 status = "disabled";
1894 clocks = <&xt 1506 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1507 clock-names = "xtal", "pclk", "baud";
1896 }; 1508 };
1897 1509
1898 uart_A: serial@24000 1510 uart_A: serial@24000 {
1899 compatible = 1511 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1512 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1513 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1514 status = "disabled";
1903 clocks = <&xt 1515 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1516 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1517 };
1907 }; 1518 };
1908 1519
1909 apb: bus@ffe00000 { 1520 apb: bus@ffe00000 {
1910 compatible = "simple- 1521 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1522 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1523 #address-cells = <2>;
1913 #size-cells = <2>; 1524 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1525 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1526
1916 sd_emmc_b: mmc@5000 { !! 1527 sd_emmc_b: sd@5000 {
1917 compatible = 1528 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1529 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1530 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1531 status = "disabled";
1921 clocks = <&cl 1532 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1533 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1534 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1535 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1536 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1537 };
1927 1538
1928 sd_emmc_c: mmc@7000 { 1539 sd_emmc_c: mmc@7000 {
1929 compatible = 1540 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1541 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1542 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1543 status = "disabled";
1933 clocks = <&cl 1544 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1545 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1546 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1547 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1548 resets = <&reset RESET_SD_EMMC_C>;
1938 }; 1549 };
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; 1550 };
1965 1551
1966 sram: sram@fffc0000 { 1552 sram: sram@fffc0000 {
1967 compatible = "mmio-sr !! 1553 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1968 reg = <0x0 0xfffc0000 1554 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1555 #address-cells = <1>;
1970 #size-cells = <1>; 1556 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1557 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1558
1973 cpu_scp_lpri: scp-sra !! 1559 cpu_scp_lpri: scp-shmem@0 {
1974 compatible = 1560 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1561 reg = <0x13000 0x400>;
1976 }; 1562 };
1977 1563
1978 cpu_scp_hpri: scp-sra !! 1564 cpu_scp_hpri: scp-shmem@200 {
1979 compatible = 1565 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1566 reg = <0x13400 0x400>;
1981 }; 1567 };
1982 }; 1568 };
1983 }; 1569 };
1984 1570
1985 timer { 1571 timer {
1986 compatible = "arm,armv8-timer 1572 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1573 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1574 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1575 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1576 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1577 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1578 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1579 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1580 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1581 };
1996 1582
1997 xtal: xtal-clk { 1583 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1584 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1585 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1586 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1587 #clock-cells = <0>;
2002 }; 1588 };
2003 }; 1589 };
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