1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort !! 71 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort !! 80 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort !! 89 compatible = "arm,cortex-a53", "arm,armv8";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort !! 98 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { <<
126 compatible = "amlogic,meson-gx <<
127 clocks = <&clkc CLKID_EFUSE>; <<
128 #address-cells = <1>; <<
129 #size-cells = <1>; <<
130 read-only; <<
131 secure-monitor = <&sm>; <<
132 }; <<
133 <<
134 psci { 114 psci {
135 compatible = "arm,psci-1.0"; 115 compatible = "arm,psci-1.0";
136 method = "smc"; 116 method = "smc";
137 }; 117 };
138 118
139 reserved-memory { 119 reserved-memory {
140 #address-cells = <2>; 120 #address-cells = <2>;
141 #size-cells = <2>; 121 #size-cells = <2>;
142 ranges; 122 ranges;
143 123
144 /* 16 MiB reserved for Hardwar 124 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 125 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 126 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 127 no-map;
148 }; 128 };
149 129
150 /* Alternate 3 MiB reserved fo 130 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 131 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 132 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 133 no-map;
154 }; 134 };
155 }; 135 };
156 136
157 scpi { 137 scpi {
158 compatible = "arm,scpi-pre-1.0 138 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 139 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 140 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 141
162 scpi_clocks: clocks { 142 scpi_clocks: clocks {
163 compatible = "arm,scpi 143 compatible = "arm,scpi-clocks";
164 144
165 scpi_dvfs: clocks-0 { !! 145 scpi_dvfs: clock-controller {
166 compatible = " 146 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 147 #clock-cells = <1>;
168 clock-indices 148 clock-indices = <0>;
169 clock-output-n 149 clock-output-names = "vcpu";
170 }; 150 };
171 }; 151 };
172 152
173 scpi_sensors: sensors { 153 scpi_sensors: sensors {
174 compatible = "amlogic, !! 154 compatible = "amlogic,meson-gxbb-scpi-sensors";
175 #thermal-sensor-cells 155 #thermal-sensor-cells = <1>;
176 }; 156 };
177 }; 157 };
178 158
179 soc { 159 soc {
180 compatible = "simple-bus"; 160 compatible = "simple-bus";
181 #address-cells = <2>; 161 #address-cells = <2>;
182 #size-cells = <2>; 162 #size-cells = <2>;
183 ranges; 163 ranges;
184 164
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 165 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, !! 166 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
279 "snps,dwm !! 167 reg = <0x0 0xff3f0000 0x0 0x10000
280 "snps,dwm !! 168 0x0 0xff634540 0x0 0x8>;
281 reg = <0x0 0xff3f0000 <<
282 <0x0 0xff634540 <<
283 interrupts = <GIC_SPI 169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 170 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 171 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 172 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 173 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 174 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 175 status = "disabled";
295 }; 176 };
296 177
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 178 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 179 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 180 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 181 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 182 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 183 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 184 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 185 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 186 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 187 status = "disabled";
316 }; 188 };
317 189
318 periphs: bus@ff634000 { 190 periphs: bus@ff634000 {
319 compatible = "simple-b 191 compatible = "simple-bus";
320 reg = <0x0 0xff634000 192 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 193 #address-cells = <2>;
322 #size-cells = <2>; 194 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 195 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 196
325 hwrng: rng@18 { 197 hwrng: rng@18 {
326 compatible = " 198 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 199 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 200 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 201 clock-names = "core";
330 }; 202 };
331 203
332 pinctrl_periphs: pinct 204 pinctrl_periphs: pinctrl@480 {
333 compatible = " 205 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 206 #address-cells = <2>;
335 #size-cells = 207 #size-cells = <2>;
336 ranges; 208 ranges;
337 209
338 gpio: bank@480 210 gpio: bank@480 {
339 reg = 211 reg = <0x0 0x00480 0x0 0x40>,
340 212 <0x0 0x004e8 0x0 0x14>,
341 213 <0x0 0x00520 0x0 0x14>,
342 214 <0x0 0x00430 0x0 0x3c>;
343 reg-na 215 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 216 gpio-controller;
345 #gpio- 217 #gpio-cells = <2>;
346 gpio-r 218 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 219 };
348 220
349 i2c0_pins: i2c 221 i2c0_pins: i2c0 {
350 mux { 222 mux {
351 223 groups = "i2c0_sck",
352 224 "i2c0_sda";
353 225 function = "i2c0";
354 226 bias-disable;
355 }; 227 };
356 }; 228 };
357 229
358 i2c1_x_pins: i 230 i2c1_x_pins: i2c1_x {
359 mux { 231 mux {
360 232 groups = "i2c1_sck_x",
361 233 "i2c1_sda_x";
362 234 function = "i2c1";
363 235 bias-disable;
364 }; 236 };
365 }; 237 };
366 238
367 i2c1_z_pins: i 239 i2c1_z_pins: i2c1_z {
368 mux { 240 mux {
369 241 groups = "i2c1_sck_z",
370 242 "i2c1_sda_z";
371 243 function = "i2c1";
372 244 bias-disable;
373 }; 245 };
374 }; 246 };
375 247
376 i2c2_a_pins: i 248 i2c2_a_pins: i2c2_a {
377 mux { 249 mux {
378 250 groups = "i2c2_sck_a",
379 251 "i2c2_sda_a";
380 252 function = "i2c2";
381 253 bias-disable;
382 }; 254 };
383 }; 255 };
384 256
385 i2c2_x_pins: i 257 i2c2_x_pins: i2c2_x {
386 mux { 258 mux {
387 259 groups = "i2c2_sck_x",
388 260 "i2c2_sda_x";
389 261 function = "i2c2";
390 262 bias-disable;
391 }; 263 };
392 }; 264 };
393 265
394 i2c3_a6_pins: 266 i2c3_a6_pins: i2c3_a6 {
395 mux { 267 mux {
396 268 groups = "i2c3_sda_a6",
397 269 "i2c3_sck_a7";
398 270 function = "i2c3";
399 271 bias-disable;
400 }; 272 };
401 }; 273 };
402 274
403 i2c3_a12_pins: 275 i2c3_a12_pins: i2c3_a12 {
404 mux { 276 mux {
405 277 groups = "i2c3_sda_a12",
406 278 "i2c3_sck_a13";
407 279 function = "i2c3";
408 280 bias-disable;
409 }; 281 };
410 }; 282 };
411 283
412 i2c3_a19_pins: 284 i2c3_a19_pins: i2c3_a19 {
413 mux { 285 mux {
414 286 groups = "i2c3_sda_a19",
415 287 "i2c3_sck_a20";
416 288 function = "i2c3";
417 289 bias-disable;
418 }; 290 };
419 }; 291 };
420 292
421 emmc_pins: emm 293 emmc_pins: emmc {
422 mux-0 <<
423 <<
424 <<
425 <<
426 <<
427 <<
428 <<
429 <<
430 <<
431 <<
432 <<
433 <<
434 }; <<
435 <<
436 mux-1 <<
437 <<
438 <<
439 <<
440 }; <<
441 }; <<
442 <<
443 nand_all_pins: <<
444 mux { 294 mux {
445 295 groups = "emmc_nand_d0",
446 296 "emmc_nand_d1",
447 297 "emmc_nand_d2",
448 298 "emmc_nand_d3",
449 299 "emmc_nand_d4",
450 300 "emmc_nand_d5",
451 301 "emmc_nand_d6",
452 302 "emmc_nand_d7",
453 !! 303 "emmc_clk",
454 !! 304 "emmc_cmd",
455 !! 305 "emmc_ds";
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: <<
465 mux { <<
466 <<
467 306 function = "emmc";
468 !! 307 bias-disable;
469 }; 308 };
470 }; 309 };
471 310
472 emmc_clk_gate_ 311 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 312 mux {
474 313 groups = "BOOT_8";
475 314 function = "gpio_periphs";
476 315 bias-pull-down;
477 }; 316 };
478 }; 317 };
479 318
480 eth_rgmii_x_pi 319 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 320 mux {
482 321 groups = "eth_mdio_x",
483 322 "eth_mdc_x",
484 323 "eth_rgmii_rx_clk_x",
485 324 "eth_rx_dv_x",
486 325 "eth_rxd0_x",
487 326 "eth_rxd1_x",
488 327 "eth_rxd2_rgmii",
489 328 "eth_rxd3_rgmii",
490 329 "eth_rgmii_tx_clk",
491 330 "eth_txen_x",
492 331 "eth_txd0_x",
493 332 "eth_txd1_x",
494 333 "eth_txd2_rgmii",
495 334 "eth_txd3_rgmii";
496 335 function = "eth";
497 336 bias-disable;
498 }; 337 };
499 }; 338 };
500 339
501 eth_rgmii_y_pi 340 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 341 mux {
503 342 groups = "eth_mdio_y",
504 343 "eth_mdc_y",
505 344 "eth_rgmii_rx_clk_y",
506 345 "eth_rx_dv_y",
507 346 "eth_rxd0_y",
508 347 "eth_rxd1_y",
509 348 "eth_rxd2_rgmii",
510 349 "eth_rxd3_rgmii",
511 350 "eth_rgmii_tx_clk",
512 351 "eth_txen_y",
513 352 "eth_txd0_y",
514 353 "eth_txd1_y",
515 354 "eth_txd2_rgmii",
516 355 "eth_txd3_rgmii";
517 356 function = "eth";
518 357 bias-disable;
519 }; 358 };
520 }; 359 };
521 360
522 eth_rmii_x_pin 361 eth_rmii_x_pins: eth-x-rmii {
523 mux { 362 mux {
524 363 groups = "eth_mdio_x",
525 364 "eth_mdc_x",
526 365 "eth_rgmii_rx_clk_x",
527 366 "eth_rx_dv_x",
528 367 "eth_rxd0_x",
529 368 "eth_rxd1_x",
530 369 "eth_txen_x",
531 370 "eth_txd0_x",
532 371 "eth_txd1_x";
533 372 function = "eth";
534 373 bias-disable;
535 }; 374 };
536 }; 375 };
537 376
538 eth_rmii_y_pin 377 eth_rmii_y_pins: eth-y-rmii {
539 mux { 378 mux {
540 379 groups = "eth_mdio_y",
541 380 "eth_mdc_y",
542 381 "eth_rgmii_rx_clk_y",
543 382 "eth_rx_dv_y",
544 383 "eth_rxd0_y",
545 384 "eth_rxd1_y",
546 385 "eth_txen_y",
547 386 "eth_txd0_y",
548 387 "eth_txd1_y";
549 388 function = "eth";
550 389 bias-disable;
551 }; 390 };
552 }; 391 };
553 392
554 mclk_b_pins: m 393 mclk_b_pins: mclk_b {
555 mux { 394 mux {
556 395 groups = "mclk_b";
557 396 function = "mclk_b";
558 397 bias-disable;
559 }; 398 };
560 }; 399 };
561 400
562 mclk_c_pins: m 401 mclk_c_pins: mclk_c {
563 mux { 402 mux {
564 403 groups = "mclk_c";
565 404 function = "mclk_c";
566 405 bias-disable;
567 }; 406 };
568 }; 407 };
569 408
570 pdm_dclk_a14_p 409 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 410 mux {
572 411 groups = "pdm_dclk_a14";
573 412 function = "pdm";
574 413 bias-disable;
575 }; 414 };
576 }; 415 };
577 416
578 pdm_dclk_a19_p 417 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 418 mux {
580 419 groups = "pdm_dclk_a19";
581 420 function = "pdm";
582 421 bias-disable;
583 }; 422 };
584 }; 423 };
585 424
586 pdm_din0_pins: 425 pdm_din0_pins: pdm_din0 {
587 mux { 426 mux {
588 427 groups = "pdm_din0";
589 428 function = "pdm";
590 429 bias-disable;
591 }; 430 };
592 }; 431 };
593 432
594 pdm_din1_pins: 433 pdm_din1_pins: pdm_din1 {
595 mux { 434 mux {
596 435 groups = "pdm_din1";
597 436 function = "pdm";
598 437 bias-disable;
599 }; 438 };
600 }; 439 };
601 440
602 pdm_din2_pins: 441 pdm_din2_pins: pdm_din2 {
603 mux { 442 mux {
604 443 groups = "pdm_din2";
605 444 function = "pdm";
606 445 bias-disable;
607 }; 446 };
608 }; 447 };
609 448
610 pdm_din3_pins: 449 pdm_din3_pins: pdm_din3 {
611 mux { 450 mux {
612 451 groups = "pdm_din3";
613 452 function = "pdm";
614 453 bias-disable;
615 }; 454 };
616 }; 455 };
617 456
618 pwm_a_a_pins: 457 pwm_a_a_pins: pwm_a_a {
619 mux { 458 mux {
620 459 groups = "pwm_a_a";
621 460 function = "pwm_a";
622 461 bias-disable;
623 }; 462 };
624 }; 463 };
625 464
626 pwm_a_x18_pins 465 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 466 mux {
628 467 groups = "pwm_a_x18";
629 468 function = "pwm_a";
630 469 bias-disable;
631 }; 470 };
632 }; 471 };
633 472
634 pwm_a_x20_pins 473 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 474 mux {
636 475 groups = "pwm_a_x20";
637 476 function = "pwm_a";
638 477 bias-disable;
639 }; 478 };
640 }; 479 };
641 480
642 pwm_a_z_pins: 481 pwm_a_z_pins: pwm_a_z {
643 mux { 482 mux {
644 483 groups = "pwm_a_z";
645 484 function = "pwm_a";
646 485 bias-disable;
647 }; 486 };
648 }; 487 };
649 488
650 pwm_b_a_pins: 489 pwm_b_a_pins: pwm_b_a {
651 mux { 490 mux {
652 491 groups = "pwm_b_a";
653 492 function = "pwm_b";
654 493 bias-disable;
655 }; 494 };
656 }; 495 };
657 496
658 pwm_b_x_pins: 497 pwm_b_x_pins: pwm_b_x {
659 mux { 498 mux {
660 499 groups = "pwm_b_x";
661 500 function = "pwm_b";
662 501 bias-disable;
663 }; 502 };
664 }; 503 };
665 504
666 pwm_b_z_pins: 505 pwm_b_z_pins: pwm_b_z {
667 mux { 506 mux {
668 507 groups = "pwm_b_z";
669 508 function = "pwm_b";
670 509 bias-disable;
671 }; 510 };
672 }; 511 };
673 512
674 pwm_c_a_pins: 513 pwm_c_a_pins: pwm_c_a {
675 mux { 514 mux {
676 515 groups = "pwm_c_a";
677 516 function = "pwm_c";
678 517 bias-disable;
679 }; 518 };
680 }; 519 };
681 520
682 pwm_c_x10_pins 521 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 522 mux {
684 523 groups = "pwm_c_x10";
685 524 function = "pwm_c";
686 525 bias-disable;
687 }; 526 };
688 }; 527 };
689 528
690 pwm_c_x17_pins 529 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 530 mux {
692 531 groups = "pwm_c_x17";
693 532 function = "pwm_c";
694 533 bias-disable;
695 }; 534 };
696 }; 535 };
697 536
698 pwm_d_x11_pins 537 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 538 mux {
700 539 groups = "pwm_d_x11";
701 540 function = "pwm_d";
702 541 bias-disable;
703 }; 542 };
704 }; 543 };
705 544
706 pwm_d_x16_pins 545 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 546 mux {
708 547 groups = "pwm_d_x16";
709 548 function = "pwm_d";
710 549 bias-disable;
711 }; 550 };
712 }; 551 };
713 552
714 sdio_pins: sdi 553 sdio_pins: sdio {
715 mux-0 !! 554 mux {
716 555 groups = "sdio_d0",
717 556 "sdio_d1",
718 557 "sdio_d2",
719 558 "sdio_d3",
720 !! 559 "sdio_cmd",
721 !! 560 "sdio_clk";
722 <<
723 }; <<
724 <<
725 mux-1 <<
726 <<
727 561 function = "sdio";
728 562 bias-disable;
729 }; 563 };
730 }; 564 };
731 565
732 sdio_clk_gate_ 566 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 567 mux {
734 568 groups = "GPIOX_4";
735 569 function = "gpio_periphs";
736 570 bias-pull-down;
737 }; 571 };
738 }; 572 };
739 573
740 spdif_in_z_pin 574 spdif_in_z_pins: spdif_in_z {
741 mux { 575 mux {
742 576 groups = "spdif_in_z";
743 577 function = "spdif_in";
744 578 bias-disable;
745 }; 579 };
746 }; 580 };
747 581
748 spdif_in_a1_pi 582 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 583 mux {
750 584 groups = "spdif_in_a1";
751 585 function = "spdif_in";
752 586 bias-disable;
753 }; 587 };
754 }; 588 };
755 589
756 spdif_in_a7_pi 590 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 591 mux {
758 592 groups = "spdif_in_a7";
759 593 function = "spdif_in";
760 594 bias-disable;
761 }; 595 };
762 }; 596 };
763 597
764 spdif_in_a19_p 598 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 599 mux {
766 600 groups = "spdif_in_a19";
767 601 function = "spdif_in";
768 602 bias-disable;
769 }; 603 };
770 }; 604 };
771 605
772 spdif_in_a20_p 606 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 607 mux {
774 608 groups = "spdif_in_a20";
775 609 function = "spdif_in";
776 610 bias-disable;
777 }; 611 };
778 }; 612 };
779 613
780 spdif_out_a1_p 614 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 615 mux {
782 616 groups = "spdif_out_a1";
783 617 function = "spdif_out";
784 618 bias-disable;
785 }; 619 };
786 }; 620 };
787 621
788 spdif_out_a11_ 622 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 623 mux {
790 624 groups = "spdif_out_a11";
791 625 function = "spdif_out";
792 626 bias-disable;
793 }; 627 };
794 }; 628 };
795 629
796 spdif_out_a19_ 630 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 631 mux {
798 632 groups = "spdif_out_a19";
799 633 function = "spdif_out";
800 634 bias-disable;
801 }; 635 };
802 }; 636 };
803 637
804 spdif_out_a20_ 638 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 639 mux {
806 640 groups = "spdif_out_a20";
807 641 function = "spdif_out";
808 642 bias-disable;
809 }; 643 };
810 }; 644 };
811 645
812 spdif_out_z_pi 646 spdif_out_z_pins: spdif_out_z {
813 mux { 647 mux {
814 648 groups = "spdif_out_z";
815 649 function = "spdif_out";
816 650 bias-disable;
817 }; 651 };
818 }; 652 };
819 653
820 spi0_pins: spi 654 spi0_pins: spi0 {
821 mux { 655 mux {
822 656 groups = "spi0_miso",
823 657 "spi0_mosi",
824 658 "spi0_clk";
825 659 function = "spi0";
826 660 bias-disable;
827 }; 661 };
828 }; 662 };
829 663
830 spi0_ss0_pins: 664 spi0_ss0_pins: spi0_ss0 {
831 mux { 665 mux {
832 666 groups = "spi0_ss0";
833 667 function = "spi0";
834 668 bias-disable;
835 }; 669 };
836 }; 670 };
837 671
838 spi0_ss1_pins: 672 spi0_ss1_pins: spi0_ss1 {
839 mux { 673 mux {
840 674 groups = "spi0_ss1";
841 675 function = "spi0";
842 676 bias-disable;
843 }; 677 };
844 }; 678 };
845 679
846 spi0_ss2_pins: 680 spi0_ss2_pins: spi0_ss2 {
847 mux { 681 mux {
848 682 groups = "spi0_ss2";
849 683 function = "spi0";
850 684 bias-disable;
851 }; 685 };
852 }; 686 };
853 687
854 spi1_a_pins: s 688 spi1_a_pins: spi1_a {
855 mux { 689 mux {
856 690 groups = "spi1_miso_a",
857 691 "spi1_mosi_a",
858 692 "spi1_clk_a";
859 693 function = "spi1";
860 694 bias-disable;
861 }; 695 };
862 }; 696 };
863 697
864 spi1_ss0_a_pin 698 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 699 mux {
866 700 groups = "spi1_ss0_a";
867 701 function = "spi1";
868 702 bias-disable;
869 }; 703 };
870 }; 704 };
871 705
872 spi1_ss1_pins: 706 spi1_ss1_pins: spi1_ss1 {
873 mux { 707 mux {
874 708 groups = "spi1_ss1";
875 709 function = "spi1";
876 710 bias-disable;
877 }; 711 };
878 }; 712 };
879 713
880 spi1_x_pins: s 714 spi1_x_pins: spi1_x {
881 mux { 715 mux {
882 716 groups = "spi1_miso_x",
883 717 "spi1_mosi_x",
884 718 "spi1_clk_x";
885 719 function = "spi1";
886 720 bias-disable;
887 }; 721 };
888 }; 722 };
889 723
890 spi1_ss0_x_pin 724 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 725 mux {
892 726 groups = "spi1_ss0_x";
893 727 function = "spi1";
894 728 bias-disable;
895 }; 729 };
896 }; 730 };
897 731
898 tdma_din0_pins 732 tdma_din0_pins: tdma_din0 {
899 mux { 733 mux {
900 734 groups = "tdma_din0";
901 735 function = "tdma";
902 736 bias-disable;
903 }; 737 };
904 }; 738 };
905 739
906 tdma_dout0_x14 740 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 741 mux {
908 742 groups = "tdma_dout0_x14";
909 743 function = "tdma";
910 744 bias-disable;
911 }; 745 };
912 }; 746 };
913 747
914 tdma_dout0_x15 748 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 749 mux {
916 750 groups = "tdma_dout0_x15";
917 751 function = "tdma";
918 752 bias-disable;
919 }; 753 };
920 }; 754 };
921 755
922 tdma_dout1_pin 756 tdma_dout1_pins: tdma_dout1 {
923 mux { 757 mux {
924 758 groups = "tdma_dout1";
925 759 function = "tdma";
926 760 bias-disable;
927 }; 761 };
928 }; 762 };
929 763
930 tdma_din1_pins 764 tdma_din1_pins: tdma_din1 {
931 mux { 765 mux {
932 766 groups = "tdma_din1";
933 767 function = "tdma";
934 768 bias-disable;
935 }; 769 };
936 }; 770 };
937 771
938 tdma_fs_pins: 772 tdma_fs_pins: tdma_fs {
939 mux { 773 mux {
940 774 groups = "tdma_fs";
941 775 function = "tdma";
942 776 bias-disable;
943 }; 777 };
944 }; 778 };
945 779
946 tdma_fs_slv_pi 780 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 781 mux {
948 782 groups = "tdma_fs_slv";
949 783 function = "tdma";
950 784 bias-disable;
951 }; 785 };
952 }; 786 };
953 787
954 tdma_sclk_pins 788 tdma_sclk_pins: tdma_sclk {
955 mux { 789 mux {
956 790 groups = "tdma_sclk";
957 791 function = "tdma";
958 792 bias-disable;
959 }; 793 };
960 }; 794 };
961 795
962 tdma_sclk_slv_ 796 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 797 mux {
964 798 groups = "tdma_sclk_slv";
965 799 function = "tdma";
966 800 bias-disable;
967 }; 801 };
968 }; 802 };
969 803
970 tdmb_din0_pins 804 tdmb_din0_pins: tdmb_din0 {
971 mux { 805 mux {
972 806 groups = "tdmb_din0";
973 807 function = "tdmb";
974 808 bias-disable;
975 }; 809 };
976 }; 810 };
977 811
978 tdmb_din1_pins 812 tdmb_din1_pins: tdmb_din1 {
979 mux { 813 mux {
980 814 groups = "tdmb_din1";
981 815 function = "tdmb";
982 816 bias-disable;
983 }; 817 };
984 }; 818 };
985 819
986 tdmb_din2_pins 820 tdmb_din2_pins: tdmb_din2 {
987 mux { 821 mux {
988 822 groups = "tdmb_din2";
989 823 function = "tdmb";
990 824 bias-disable;
991 }; 825 };
992 }; 826 };
993 827
994 tdmb_din3_pins 828 tdmb_din3_pins: tdmb_din3 {
995 mux { 829 mux {
996 830 groups = "tdmb_din3";
997 831 function = "tdmb";
998 832 bias-disable;
999 }; 833 };
1000 }; 834 };
1001 835
1002 tdmb_dout0_pi 836 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 837 mux {
1004 838 groups = "tdmb_dout0";
1005 839 function = "tdmb";
1006 840 bias-disable;
1007 }; 841 };
1008 }; 842 };
1009 843
1010 tdmb_dout1_pi 844 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 845 mux {
1012 846 groups = "tdmb_dout1";
1013 847 function = "tdmb";
1014 848 bias-disable;
1015 }; 849 };
1016 }; 850 };
1017 851
1018 tdmb_dout2_pi 852 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 853 mux {
1020 854 groups = "tdmb_dout2";
1021 855 function = "tdmb";
1022 856 bias-disable;
1023 }; 857 };
1024 }; 858 };
1025 859
1026 tdmb_dout3_pi 860 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 861 mux {
1028 862 groups = "tdmb_dout3";
1029 863 function = "tdmb";
1030 864 bias-disable;
1031 }; 865 };
1032 }; 866 };
1033 867
1034 tdmb_fs_pins: 868 tdmb_fs_pins: tdmb_fs {
1035 mux { 869 mux {
1036 870 groups = "tdmb_fs";
1037 871 function = "tdmb";
1038 872 bias-disable;
1039 }; 873 };
1040 }; 874 };
1041 875
1042 tdmb_fs_slv_p 876 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 877 mux {
1044 878 groups = "tdmb_fs_slv";
1045 879 function = "tdmb";
1046 880 bias-disable;
1047 }; 881 };
1048 }; 882 };
1049 883
1050 tdmb_sclk_pin 884 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 885 mux {
1052 886 groups = "tdmb_sclk";
1053 887 function = "tdmb";
1054 888 bias-disable;
1055 }; 889 };
1056 }; 890 };
1057 891
1058 tdmb_sclk_slv 892 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 893 mux {
1060 894 groups = "tdmb_sclk_slv";
1061 895 function = "tdmb";
1062 896 bias-disable;
1063 }; 897 };
1064 }; 898 };
1065 899
1066 tdmc_fs_pins: 900 tdmc_fs_pins: tdmc_fs {
1067 mux { 901 mux {
1068 902 groups = "tdmc_fs";
1069 903 function = "tdmc";
1070 904 bias-disable;
1071 }; 905 };
1072 }; 906 };
1073 907
1074 tdmc_fs_slv_p 908 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 909 mux {
1076 910 groups = "tdmc_fs_slv";
1077 911 function = "tdmc";
1078 912 bias-disable;
1079 }; 913 };
1080 }; 914 };
1081 915
1082 tdmc_sclk_pin 916 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 917 mux {
1084 918 groups = "tdmc_sclk";
1085 919 function = "tdmc";
1086 920 bias-disable;
1087 }; 921 };
1088 }; 922 };
1089 923
1090 tdmc_sclk_slv 924 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 925 mux {
1092 926 groups = "tdmc_sclk_slv";
1093 927 function = "tdmc";
1094 928 bias-disable;
1095 }; 929 };
1096 }; 930 };
1097 931
1098 tdmc_din0_pin 932 tdmc_din0_pins: tdmc_din0 {
1099 mux { 933 mux {
1100 934 groups = "tdmc_din0";
1101 935 function = "tdmc";
1102 936 bias-disable;
1103 }; 937 };
1104 }; 938 };
1105 939
1106 tdmc_din1_pin 940 tdmc_din1_pins: tdmc_din1 {
1107 mux { 941 mux {
1108 942 groups = "tdmc_din1";
1109 943 function = "tdmc";
1110 944 bias-disable;
1111 }; 945 };
1112 }; 946 };
1113 947
1114 tdmc_din2_pin 948 tdmc_din2_pins: tdmc_din2 {
1115 mux { 949 mux {
1116 950 groups = "tdmc_din2";
1117 951 function = "tdmc";
1118 952 bias-disable;
1119 }; 953 };
1120 }; 954 };
1121 955
1122 tdmc_din3_pin 956 tdmc_din3_pins: tdmc_din3 {
1123 mux { 957 mux {
1124 958 groups = "tdmc_din3";
1125 959 function = "tdmc";
1126 960 bias-disable;
1127 }; 961 };
1128 }; 962 };
1129 963
1130 tdmc_dout0_pi 964 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 965 mux {
1132 966 groups = "tdmc_dout0";
1133 967 function = "tdmc";
1134 968 bias-disable;
1135 }; 969 };
1136 }; 970 };
1137 971
1138 tdmc_dout1_pi 972 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 973 mux {
1140 974 groups = "tdmc_dout1";
1141 975 function = "tdmc";
1142 976 bias-disable;
1143 }; 977 };
1144 }; 978 };
1145 979
1146 tdmc_dout2_pi 980 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 981 mux {
1148 982 groups = "tdmc_dout2";
1149 983 function = "tdmc";
1150 984 bias-disable;
1151 }; 985 };
1152 }; 986 };
1153 987
1154 tdmc_dout3_pi 988 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 989 mux {
1156 990 groups = "tdmc_dout3";
1157 991 function = "tdmc";
1158 992 bias-disable;
1159 }; 993 };
1160 }; 994 };
1161 995
1162 uart_a_pins: 996 uart_a_pins: uart_a {
1163 mux { 997 mux {
1164 998 groups = "uart_tx_a",
1165 999 "uart_rx_a";
1166 1000 function = "uart_a";
1167 1001 bias-disable;
1168 }; 1002 };
1169 }; 1003 };
1170 1004
1171 uart_a_cts_rt 1005 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1006 mux {
1173 1007 groups = "uart_cts_a",
1174 1008 "uart_rts_a";
1175 1009 function = "uart_a";
1176 1010 bias-disable;
1177 }; 1011 };
1178 }; 1012 };
1179 1013
1180 uart_b_x_pins 1014 uart_b_x_pins: uart_b_x {
1181 mux { 1015 mux {
1182 1016 groups = "uart_tx_b_x",
1183 1017 "uart_rx_b_x";
1184 1018 function = "uart_b";
1185 1019 bias-disable;
1186 }; 1020 };
1187 }; 1021 };
1188 1022
1189 uart_b_x_cts_ 1023 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1024 mux {
1191 1025 groups = "uart_cts_b_x",
1192 1026 "uart_rts_b_x";
1193 1027 function = "uart_b";
1194 1028 bias-disable;
1195 }; 1029 };
1196 }; 1030 };
1197 1031
1198 uart_b_z_pins 1032 uart_b_z_pins: uart_b_z {
1199 mux { 1033 mux {
1200 1034 groups = "uart_tx_b_z",
1201 1035 "uart_rx_b_z";
1202 1036 function = "uart_b";
1203 1037 bias-disable;
1204 }; 1038 };
1205 }; 1039 };
1206 1040
1207 uart_b_z_cts_ 1041 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1042 mux {
1209 1043 groups = "uart_cts_b_z",
1210 1044 "uart_rts_b_z";
1211 1045 function = "uart_b";
1212 1046 bias-disable;
1213 }; 1047 };
1214 }; 1048 };
1215 1049
1216 uart_ao_b_z_p 1050 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1051 mux {
1218 1052 groups = "uart_ao_tx_b_z",
1219 1053 "uart_ao_rx_b_z";
1220 1054 function = "uart_ao_b_z";
1221 1055 bias-disable;
1222 }; 1056 };
1223 }; 1057 };
1224 1058
1225 uart_ao_b_z_c 1059 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1060 mux {
1227 1061 groups = "uart_ao_cts_b_z",
1228 1062 "uart_ao_rts_b_z";
1229 1063 function = "uart_ao_b_z";
1230 1064 bias-disable;
1231 }; 1065 };
1232 }; 1066 };
1233 }; 1067 };
1234 }; 1068 };
1235 1069
1236 hiubus: bus@ff63c000 { 1070 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1071 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1072 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1073 #address-cells = <2>;
1240 #size-cells = <2>; 1074 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1075 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1076
1243 sysctrl: system-contr 1077 sysctrl: system-controller@0 {
1244 compatible = 1078 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1079 "simple-mfd", "syscon";
1246 reg = <0 0 0 1080 reg = <0 0 0 0x400>;
1247 1081
1248 clkc: clock-c 1082 clkc: clock-controller {
1249 compa 1083 compatible = "amlogic,axg-clkc";
1250 #cloc 1084 #clock-cells = <1>;
1251 clock 1085 clocks = <&xtal>;
1252 clock 1086 clock-names = "xtal";
1253 }; 1087 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1088 };
1301 }; 1089 };
1302 1090
1303 mailbox: mailbox@ff63c404 { 1091 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic !! 1092 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1093 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1094 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1095 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1096 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1097 #mbox-cells = <1>;
1310 }; 1098 };
1311 1099
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1100 audio: bus@ff642000 {
1326 compatible = "simple- 1101 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1102 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1103 #address-cells = <2>;
1329 #size-cells = <2>; 1104 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1105 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1106
1332 clkc_audio: clock-con 1107 clkc_audio: clock-controller@0 {
1333 compatible = 1108 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1109 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1110 #clock-cells = <1>;
1336 1111
1337 clocks = <&cl 1112 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1113 <&clkc CLKID_MPLL0>,
1339 <&cl 1114 <&clkc CLKID_MPLL1>,
1340 <&cl 1115 <&clkc CLKID_MPLL2>,
1341 <&cl 1116 <&clkc CLKID_MPLL3>,
1342 <&cl 1117 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1118 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1119 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1120 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1121 clock-names = "pclk",
1347 1122 "mst_in0",
1348 1123 "mst_in1",
1349 1124 "mst_in2",
1350 1125 "mst_in3",
1351 1126 "mst_in4",
1352 1127 "mst_in5",
1353 1128 "mst_in6",
1354 1129 "mst_in7";
1355 1130
1356 resets = <&re 1131 resets = <&reset RESET_AUDIO>;
1357 }; 1132 };
1358 1133
1359 toddr_a: audio-contro 1134 toddr_a: audio-controller@100 {
1360 compatible = 1135 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x !! 1136 reg = <0x0 0x100 0x0 0x1c>;
1362 #sound-dai-ce 1137 #sound-dai-cells = <0>;
1363 sound-name-pr 1138 sound-name-prefix = "TODDR_A";
1364 interrupts = 1139 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1140 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1141 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- <<
1368 status = "dis 1142 status = "disabled";
1369 }; 1143 };
1370 1144
1371 toddr_b: audio-contro 1145 toddr_b: audio-controller@140 {
1372 compatible = 1146 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x !! 1147 reg = <0x0 0x140 0x0 0x1c>;
1374 #sound-dai-ce 1148 #sound-dai-cells = <0>;
1375 sound-name-pr 1149 sound-name-prefix = "TODDR_B";
1376 interrupts = 1150 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1151 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1152 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- <<
1380 status = "dis 1153 status = "disabled";
1381 }; 1154 };
1382 1155
1383 toddr_c: audio-contro 1156 toddr_c: audio-controller@180 {
1384 compatible = 1157 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x !! 1158 reg = <0x0 0x180 0x0 0x1c>;
1386 #sound-dai-ce 1159 #sound-dai-cells = <0>;
1387 sound-name-pr 1160 sound-name-prefix = "TODDR_C";
1388 interrupts = 1161 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1162 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1163 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- <<
1392 status = "dis 1164 status = "disabled";
1393 }; 1165 };
1394 1166
1395 frddr_a: audio-contro 1167 frddr_a: audio-controller@1c0 {
1396 compatible = 1168 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x !! 1169 reg = <0x0 0x1c0 0x0 0x1c>;
1398 #sound-dai-ce 1170 #sound-dai-cells = <0>;
1399 sound-name-pr 1171 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1172 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1173 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1174 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- <<
1404 status = "dis 1175 status = "disabled";
1405 }; 1176 };
1406 1177
1407 frddr_b: audio-contro 1178 frddr_b: audio-controller@200 {
1408 compatible = 1179 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x !! 1180 reg = <0x0 0x200 0x0 0x1c>;
1410 #sound-dai-ce 1181 #sound-dai-cells = <0>;
1411 sound-name-pr 1182 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1183 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1184 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1185 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- <<
1416 status = "dis 1186 status = "disabled";
1417 }; 1187 };
1418 1188
1419 frddr_c: audio-contro 1189 frddr_c: audio-controller@240 {
1420 compatible = 1190 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x !! 1191 reg = <0x0 0x240 0x0 0x1c>;
1422 #sound-dai-ce 1192 #sound-dai-cells = <0>;
1423 sound-name-pr 1193 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1194 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1195 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1196 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- <<
1428 status = "dis 1197 status = "disabled";
1429 }; 1198 };
1430 1199
1431 arb: reset-controller 1200 arb: reset-controller@280 {
1432 compatible = 1201 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1202 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1203 #reset-cells = <1>;
1435 clocks = <&cl 1204 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1205 };
1437 1206
1438 tdmin_a: audio-contro 1207 tdmin_a: audio-controller@300 {
1439 compatible = 1208 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1209 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1210 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1211 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1212 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1213 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1214 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1215 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1216 clock-names = "pclk", "sclk", "sclk_sel",
1448 1217 "lrclk", "lrclk_sel";
1449 status = "dis 1218 status = "disabled";
1450 }; 1219 };
1451 1220
1452 tdmin_b: audio-contro 1221 tdmin_b: audio-controller@340 {
1453 compatible = 1222 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1223 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1224 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1225 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1226 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1227 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1228 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1229 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1230 clock-names = "pclk", "sclk", "sclk_sel",
1462 1231 "lrclk", "lrclk_sel";
1463 status = "dis 1232 status = "disabled";
1464 }; 1233 };
1465 1234
1466 tdmin_c: audio-contro 1235 tdmin_c: audio-controller@380 {
1467 compatible = 1236 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1237 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1238 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1239 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1240 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1241 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1242 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1243 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1244 clock-names = "pclk", "sclk", "sclk_sel",
1476 1245 "lrclk", "lrclk_sel";
1477 status = "dis 1246 status = "disabled";
1478 }; 1247 };
1479 1248
1480 tdmin_lb: audio-contr 1249 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1250 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1251 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1252 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1253 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1254 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1255 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1256 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1257 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1258 clock-names = "pclk", "sclk", "sclk_sel",
1490 1259 "lrclk", "lrclk_sel";
1491 status = "dis 1260 status = "disabled";
1492 }; 1261 };
1493 1262
1494 spdifin: audio-contro <<
1495 compatible = <<
1496 reg = <0x0 0x <<
1497 #sound-dai-ce <<
1498 sound-name-pr <<
1499 interrupts = <<
1500 clocks = <&cl <<
1501 <&cl <<
1502 clock-names = <<
1503 status = "dis <<
1504 }; <<
1505 <<
1506 spdifout: audio-contr 1263 spdifout: audio-controller@480 {
1507 compatible = 1264 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1265 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1266 #sound-dai-cells = <0>;
1510 sound-name-pr 1267 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1268 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1269 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1270 clock-names = "pclk", "mclk";
1514 status = "dis 1271 status = "disabled";
1515 }; 1272 };
1516 1273
1517 tdmout_a: audio-contr 1274 tdmout_a: audio-controller@500 {
1518 compatible = 1275 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1276 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1277 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1278 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1279 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1280 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1281 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1282 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1283 clock-names = "pclk", "sclk", "sclk_sel",
1527 1284 "lrclk", "lrclk_sel";
1528 status = "dis 1285 status = "disabled";
1529 }; 1286 };
1530 1287
1531 tdmout_b: audio-contr 1288 tdmout_b: audio-controller@540 {
1532 compatible = 1289 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1290 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1291 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1292 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1293 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1294 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1295 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1296 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1297 clock-names = "pclk", "sclk", "sclk_sel",
1541 1298 "lrclk", "lrclk_sel";
1542 status = "dis 1299 status = "disabled";
1543 }; 1300 };
1544 1301
1545 tdmout_c: audio-contr 1302 tdmout_c: audio-controller@580 {
1546 compatible = 1303 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1304 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1305 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1306 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1307 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1308 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1309 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1310 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1311 clock-names = "pclk", "sclk", "sclk_sel",
1555 1312 "lrclk", "lrclk_sel";
1556 status = "dis 1313 status = "disabled";
1557 }; 1314 };
1558 }; 1315 };
1559 1316
1560 aobus: bus@ff800000 { 1317 aobus: bus@ff800000 {
1561 compatible = "simple- 1318 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1319 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1320 #address-cells = <2>;
1564 #size-cells = <2>; 1321 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1322 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1323
1567 sysctrl_AO: sys-ctrl@ 1324 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1325 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1326 reg = <0x0 0x0 0x0 0x100>;
1570 1327
1571 clkc_AO: cloc 1328 clkc_AO: clock-controller {
1572 compa 1329 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1330 #clock-cells = <1>;
1574 #rese 1331 #reset-cells = <1>;
1575 clock 1332 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1333 clock-names = "xtal", "mpeg-clk";
1577 }; 1334 };
1578 }; 1335 };
1579 1336
1580 pinctrl_aobus: pinctr 1337 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1338 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1339 #address-cells = <2>;
1583 #size-cells = 1340 #size-cells = <2>;
1584 ranges; 1341 ranges;
1585 1342
1586 gpio_ao: bank 1343 gpio_ao: bank@14 {
1587 reg = 1344 reg = <0x0 0x00014 0x0 0x8>,
1588 1345 <0x0 0x0002c 0x0 0x4>,
1589 1346 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1347 reg-names = "mux", "pull", "gpio";
1591 gpio- 1348 gpio-controller;
1592 #gpio 1349 #gpio-cells = <2>;
1593 gpio- 1350 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1351 };
1595 1352
1596 i2c_ao_sck_4_ 1353 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1354 mux {
1598 1355 groups = "i2c_ao_sck_4";
1599 1356 function = "i2c_ao";
1600 1357 bias-disable;
1601 }; 1358 };
1602 }; 1359 };
1603 1360
1604 i2c_ao_sck_8_ 1361 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1362 mux {
1606 1363 groups = "i2c_ao_sck_8";
1607 1364 function = "i2c_ao";
1608 1365 bias-disable;
1609 }; 1366 };
1610 }; 1367 };
1611 1368
1612 i2c_ao_sck_10 1369 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1370 mux {
1614 1371 groups = "i2c_ao_sck_10";
1615 1372 function = "i2c_ao";
1616 1373 bias-disable;
1617 }; 1374 };
1618 }; 1375 };
1619 1376
1620 i2c_ao_sda_5_ 1377 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1378 mux {
1622 1379 groups = "i2c_ao_sda_5";
1623 1380 function = "i2c_ao";
1624 1381 bias-disable;
1625 }; 1382 };
1626 }; 1383 };
1627 1384
1628 i2c_ao_sda_9_ 1385 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1386 mux {
1630 1387 groups = "i2c_ao_sda_9";
1631 1388 function = "i2c_ao";
1632 1389 bias-disable;
1633 }; 1390 };
1634 }; 1391 };
1635 1392
1636 i2c_ao_sda_11 1393 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1394 mux {
1638 1395 groups = "i2c_ao_sda_11";
1639 1396 function = "i2c_ao";
1640 1397 bias-disable;
1641 }; 1398 };
1642 }; 1399 };
1643 1400
1644 remote_input_ 1401 remote_input_ao_pins: remote_input_ao {
1645 mux { 1402 mux {
1646 1403 groups = "remote_input_ao";
1647 1404 function = "remote_input_ao";
1648 1405 bias-disable;
1649 }; 1406 };
1650 }; 1407 };
1651 1408
1652 uart_ao_a_pin 1409 uart_ao_a_pins: uart_ao_a {
1653 mux { 1410 mux {
1654 1411 groups = "uart_ao_tx_a",
1655 1412 "uart_ao_rx_a";
1656 1413 function = "uart_ao_a";
1657 1414 bias-disable;
1658 }; 1415 };
1659 }; 1416 };
1660 1417
1661 uart_ao_a_cts 1418 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1419 mux {
1663 1420 groups = "uart_ao_cts_a",
1664 1421 "uart_ao_rts_a";
1665 1422 function = "uart_ao_a";
1666 1423 bias-disable;
1667 }; 1424 };
1668 }; 1425 };
1669 1426
1670 uart_ao_b_pin 1427 uart_ao_b_pins: uart_ao_b {
1671 mux { 1428 mux {
1672 1429 groups = "uart_ao_tx_b",
1673 1430 "uart_ao_rx_b";
1674 1431 function = "uart_ao_b";
1675 1432 bias-disable;
1676 }; 1433 };
1677 }; 1434 };
1678 1435
1679 uart_ao_b_cts 1436 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1437 mux {
1681 1438 groups = "uart_ao_cts_b",
1682 1439 "uart_ao_rts_b";
1683 1440 function = "uart_ao_b";
1684 1441 bias-disable;
1685 }; 1442 };
1686 }; 1443 };
1687 }; 1444 };
1688 1445
1689 sec_AO: ao-secure@140 1446 sec_AO: ao-secure@140 {
1690 compatible = 1447 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1448 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1449 amlogic,has-chip-id;
1693 }; 1450 };
1694 1451
1695 pwm_AO_cd: pwm@2000 { 1452 pwm_AO_cd: pwm@2000 {
1696 compatible = 1453 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1454 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1455 #pwm-cells = <3>;
1699 status = "dis 1456 status = "disabled";
1700 }; 1457 };
1701 1458
1702 uart_AO: serial@3000 1459 uart_AO: serial@3000 {
1703 compatible = 1460 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1461 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1462 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1463 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1464 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1465 status = "disabled";
1709 }; 1466 };
1710 1467
1711 uart_AO_B: serial@400 1468 uart_AO_B: serial@4000 {
1712 compatible = 1469 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1470 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1471 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1472 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1473 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1474 status = "disabled";
1718 }; 1475 };
1719 1476
1720 i2c_AO: i2c@5000 { 1477 i2c_AO: i2c@5000 {
1721 compatible = 1478 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1479 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1480 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1481 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1482 #address-cells = <1>;
1726 #size-cells = 1483 #size-cells = <0>;
1727 status = "dis 1484 status = "disabled";
1728 }; 1485 };
1729 1486
1730 pwm_AO_ab: pwm@7000 { 1487 pwm_AO_ab: pwm@7000 {
1731 compatible = 1488 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1489 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1490 #pwm-cells = <3>;
1734 status = "dis 1491 status = "disabled";
1735 }; 1492 };
1736 1493
1737 ir: ir@8000 { 1494 ir: ir@8000 {
1738 compatible = 1495 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1496 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1497 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1498 status = "disabled";
1742 }; 1499 };
1743 1500
1744 saradc: adc@9000 { 1501 saradc: adc@9000 {
1745 compatible = 1502 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1503 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1504 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1505 #io-channel-cells = <1>;
1749 interrupts = 1506 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1507 clocks = <&xtal>,
1751 <&cl 1508 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1509 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1510 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1511 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1512 status = "disabled";
1756 }; 1513 };
1757 }; 1514 };
1758 1515
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1516 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1517 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1518 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1519 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1520 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1521 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1522 interrupt-controller;
1774 interrupts = <GIC_PPI 1523 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1524 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1525 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1526 #address-cells = <0>;
1778 }; 1527 };
1779 1528
1780 cbus: bus@ffd00000 { 1529 cbus: bus@ffd00000 {
1781 compatible = "simple- 1530 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1531 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1532 #address-cells = <2>;
1784 #size-cells = <2>; 1533 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1534 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1535
1787 reset: reset-controll 1536 reset: reset-controller@1004 {
1788 compatible = 1537 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1538 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1539 #reset-cells = <1>;
1791 }; 1540 };
1792 1541
1793 gpio_intc: interrupt- 1542 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1543 compatible = "amlogic,meson-axg-gpio-intc",
1795 1544 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1545 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1546 interrupt-controller;
1798 #interrupt-ce 1547 #interrupt-cells = <2>;
1799 amlogic,chann 1548 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1549 };
1801 1550
1802 watchdog@f0d0 { 1551 watchdog@f0d0 {
1803 compatible = 1552 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1553 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1554 clocks = <&xtal>;
1806 }; 1555 };
1807 1556
1808 pwm_ab: pwm@1b000 { 1557 pwm_ab: pwm@1b000 {
1809 compatible = 1558 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1559 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1560 #pwm-cells = <3>;
1812 status = "dis 1561 status = "disabled";
1813 }; 1562 };
1814 1563
1815 pwm_cd: pwm@1a000 { 1564 pwm_cd: pwm@1a000 {
1816 compatible = 1565 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1566 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1567 #pwm-cells = <3>;
1819 status = "dis 1568 status = "disabled";
1820 }; 1569 };
1821 1570
1822 spicc0: spi@13000 { 1571 spicc0: spi@13000 {
1823 compatible = 1572 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1573 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1574 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1575 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1576 clock-names = "core";
1828 #address-cell 1577 #address-cells = <1>;
1829 #size-cells = 1578 #size-cells = <0>;
1830 status = "dis 1579 status = "disabled";
1831 }; 1580 };
1832 1581
1833 spicc1: spi@15000 { 1582 spicc1: spi@15000 {
1834 compatible = 1583 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1584 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1585 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1586 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1587 clock-names = "core";
1839 #address-cell 1588 #address-cells = <1>;
1840 #size-cells = 1589 #size-cells = <0>;
1841 status = "dis 1590 status = "disabled";
1842 }; 1591 };
1843 1592
1844 clk_msr: clock-measur <<
1845 compatible = <<
1846 reg = <0x0 0x <<
1847 }; <<
1848 <<
1849 i2c3: i2c@1c000 { 1593 i2c3: i2c@1c000 {
1850 compatible = 1594 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1595 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1596 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1597 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1598 #address-cells = <1>;
1855 #size-cells = 1599 #size-cells = <0>;
1856 status = "dis 1600 status = "disabled";
1857 }; 1601 };
1858 1602
1859 i2c2: i2c@1d000 { 1603 i2c2: i2c@1d000 {
1860 compatible = 1604 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1605 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1606 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1607 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1608 #address-cells = <1>;
1865 #size-cells = 1609 #size-cells = <0>;
1866 status = "dis 1610 status = "disabled";
1867 }; 1611 };
1868 1612
1869 i2c1: i2c@1e000 { 1613 i2c1: i2c@1e000 {
1870 compatible = 1614 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1615 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1616 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1617 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1618 #address-cells = <1>;
1875 #size-cells = 1619 #size-cells = <0>;
1876 status = "dis 1620 status = "disabled";
1877 }; 1621 };
1878 1622
1879 i2c0: i2c@1f000 { 1623 i2c0: i2c@1f000 {
1880 compatible = 1624 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1625 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1626 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1627 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1628 #address-cells = <1>;
1885 #size-cells = 1629 #size-cells = <0>;
1886 status = "dis 1630 status = "disabled";
1887 }; 1631 };
1888 1632
1889 uart_B: serial@23000 1633 uart_B: serial@23000 {
1890 compatible = 1634 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1635 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1636 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1637 status = "disabled";
1894 clocks = <&xt 1638 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1639 clock-names = "xtal", "pclk", "baud";
1896 }; 1640 };
1897 1641
1898 uart_A: serial@24000 1642 uart_A: serial@24000 {
1899 compatible = 1643 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1644 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1645 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1646 status = "disabled";
1903 clocks = <&xt 1647 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1648 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1649 };
1907 }; 1650 };
1908 1651
1909 apb: bus@ffe00000 { 1652 apb: bus@ffe00000 {
1910 compatible = "simple- 1653 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1654 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1655 #address-cells = <2>;
1913 #size-cells = <2>; 1656 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1657 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1658
1916 sd_emmc_b: mmc@5000 { !! 1659 sd_emmc_b: sd@5000 {
1917 compatible = 1660 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1661 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1662 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1663 status = "disabled";
1921 clocks = <&cl 1664 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1665 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1666 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1667 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1668 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1669 };
1927 1670
1928 sd_emmc_c: mmc@7000 { 1671 sd_emmc_c: mmc@7000 {
1929 compatible = 1672 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1673 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1674 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1675 status = "disabled";
1933 clocks = <&cl 1676 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1677 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1678 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1679 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1680 resets = <&reset RESET_SD_EMMC_C>;
1938 }; 1681 };
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; 1682 };
1965 1683
1966 sram: sram@fffc0000 { 1684 sram: sram@fffc0000 {
1967 compatible = "mmio-sr !! 1685 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1968 reg = <0x0 0xfffc0000 1686 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1687 #address-cells = <1>;
1970 #size-cells = <1>; 1688 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1689 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1690
1973 cpu_scp_lpri: scp-sra !! 1691 cpu_scp_lpri: scp-shmem@13000 {
1974 compatible = 1692 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1693 reg = <0x13000 0x400>;
1976 }; 1694 };
1977 1695
1978 cpu_scp_hpri: scp-sra !! 1696 cpu_scp_hpri: scp-shmem@13400 {
1979 compatible = 1697 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1698 reg = <0x13400 0x400>;
1981 }; 1699 };
1982 }; 1700 };
1983 }; 1701 };
1984 1702
1985 timer { 1703 timer {
1986 compatible = "arm,armv8-timer 1704 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1705 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1706 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1707 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1708 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1709 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1710 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1711 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1712 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1713 };
1996 1714
1997 xtal: xtal-clk { 1715 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1716 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1717 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1718 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1719 #clock-cells = <0>;
2002 }; 1720 };
2003 }; 1721 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.