1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; 120 secure-monitor = <&sm>;
132 }; 121 };
133 122
134 psci { 123 psci {
135 compatible = "arm,psci-1.0"; 124 compatible = "arm,psci-1.0";
136 method = "smc"; 125 method = "smc";
137 }; 126 };
138 127
139 reserved-memory { 128 reserved-memory {
140 #address-cells = <2>; 129 #address-cells = <2>;
141 #size-cells = <2>; 130 #size-cells = <2>;
142 ranges; 131 ranges;
143 132
144 /* 16 MiB reserved for Hardwar 133 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 134 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 135 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 136 no-map;
148 }; 137 };
149 138
150 /* Alternate 3 MiB reserved fo 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 140 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 141 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 142 no-map;
154 }; 143 };
155 }; 144 };
156 145
157 scpi { 146 scpi {
158 compatible = "arm,scpi-pre-1.0 147 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 148 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 150
162 scpi_clocks: clocks { 151 scpi_clocks: clocks {
163 compatible = "arm,scpi 152 compatible = "arm,scpi-clocks";
164 153
165 scpi_dvfs: clocks-0 { 154 scpi_dvfs: clocks-0 {
166 compatible = " 155 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 156 #clock-cells = <1>;
168 clock-indices 157 clock-indices = <0>;
169 clock-output-n 158 clock-output-names = "vcpu";
170 }; 159 };
171 }; 160 };
172 161
173 scpi_sensors: sensors { 162 scpi_sensors: sensors {
174 compatible = "amlogic, 163 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 164 #thermal-sensor-cells = <1>;
176 }; 165 };
177 }; 166 };
178 167
179 soc { 168 soc {
180 compatible = "simple-bus"; 169 compatible = "simple-bus";
181 #address-cells = <2>; 170 #address-cells = <2>;
182 #size-cells = <2>; 171 #size-cells = <2>;
183 ranges; 172 ranges;
184 173
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { 174 usb: usb@ffe09080 {
238 compatible = "amlogic, 175 compatible = "amlogic,meson-axg-usb-ctrl";
239 reg = <0x0 0xffe09080 176 reg = <0x0 0xffe09080 0x0 0x20>;
240 interrupts = <GIC_SPI 177 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; 178 #address-cells = <2>;
242 #size-cells = <2>; 179 #size-cells = <2>;
243 ranges; 180 ranges;
244 181
245 clocks = <&clkc CLKID_ 182 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
246 clock-names = "usb_ctr 183 clock-names = "usb_ctrl", "ddr";
247 resets = <&reset RESET 184 resets = <&reset RESET_USB_OTG>;
248 185
249 dr_mode = "otg"; 186 dr_mode = "otg";
250 187
251 phys = <&usb2_phy1>; 188 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1 189 phy-names = "usb2-phy1";
253 190
254 dwc2: usb@ff400000 { 191 dwc2: usb@ff400000 {
255 compatible = " 192 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
256 reg = <0x0 0xf 193 reg = <0x0 0xff400000 0x0 0x40000>;
257 interrupts = < 194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk 195 clocks = <&clkc CLKID_USB1>;
259 clock-names = 196 clock-names = "otg";
260 phys = <&usb2_ 197 phys = <&usb2_phy1>;
261 dr_mode = "per 198 dr_mode = "peripheral";
262 g-rx-fifo-size 199 g-rx-fifo-size = <192>;
263 g-np-tx-fifo-s 200 g-np-tx-fifo-size = <128>;
264 g-tx-fifo-size 201 g-tx-fifo-size = <128 128 16 16 16>;
265 }; 202 };
266 203
267 dwc3: usb@ff500000 { 204 dwc3: usb@ff500000 {
268 compatible = " 205 compatible = "snps,dwc3";
269 reg = <0x0 0xf 206 reg = <0x0 0xff500000 0x0 0x100000>;
270 interrupts = < 207 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
271 dr_mode = "hos 208 dr_mode = "host";
272 maximum-speed 209 maximum-speed = "high-speed";
273 snps,dis_u2_su 210 snps,dis_u2_susphy_quirk;
274 }; 211 };
275 }; 212 };
276 213
277 ethmac: ethernet@ff3f0000 { 214 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 215 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 216 "snps,dwmac-3.70a",
280 "snps,dwm 217 "snps,dwmac";
281 reg = <0x0 0xff3f0000 218 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 219 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 221 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 222 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 223 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 224 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 225 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 226 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 227 "timing-adjustment";
291 rx-fifo-depth = <4096> 228 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 229 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc <<
294 status = "disabled"; 230 status = "disabled";
295 }; 231 };
296 232
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 233 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 234 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 235 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 236 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 237 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 238 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 239 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 240 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 241 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 242 status = "disabled";
316 }; 243 };
317 244
318 periphs: bus@ff634000 { 245 periphs: bus@ff634000 {
319 compatible = "simple-b 246 compatible = "simple-bus";
320 reg = <0x0 0xff634000 247 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 248 #address-cells = <2>;
322 #size-cells = <2>; 249 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 250 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 251
325 hwrng: rng@18 { 252 hwrng: rng@18 {
326 compatible = " 253 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 254 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 255 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 256 clock-names = "core";
330 }; 257 };
331 258
332 pinctrl_periphs: pinct 259 pinctrl_periphs: pinctrl@480 {
333 compatible = " 260 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 261 #address-cells = <2>;
335 #size-cells = 262 #size-cells = <2>;
336 ranges; 263 ranges;
337 264
338 gpio: bank@480 265 gpio: bank@480 {
339 reg = 266 reg = <0x0 0x00480 0x0 0x40>,
340 267 <0x0 0x004e8 0x0 0x14>,
341 268 <0x0 0x00520 0x0 0x14>,
342 269 <0x0 0x00430 0x0 0x3c>;
343 reg-na 270 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 271 gpio-controller;
345 #gpio- 272 #gpio-cells = <2>;
346 gpio-r 273 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 274 };
348 275
349 i2c0_pins: i2c 276 i2c0_pins: i2c0 {
350 mux { 277 mux {
351 278 groups = "i2c0_sck",
352 279 "i2c0_sda";
353 280 function = "i2c0";
354 281 bias-disable;
355 }; 282 };
356 }; 283 };
357 284
358 i2c1_x_pins: i 285 i2c1_x_pins: i2c1_x {
359 mux { 286 mux {
360 287 groups = "i2c1_sck_x",
361 288 "i2c1_sda_x";
362 289 function = "i2c1";
363 290 bias-disable;
364 }; 291 };
365 }; 292 };
366 293
367 i2c1_z_pins: i 294 i2c1_z_pins: i2c1_z {
368 mux { 295 mux {
369 296 groups = "i2c1_sck_z",
370 297 "i2c1_sda_z";
371 298 function = "i2c1";
372 299 bias-disable;
373 }; 300 };
374 }; 301 };
375 302
376 i2c2_a_pins: i 303 i2c2_a_pins: i2c2_a {
377 mux { 304 mux {
378 305 groups = "i2c2_sck_a",
379 306 "i2c2_sda_a";
380 307 function = "i2c2";
381 308 bias-disable;
382 }; 309 };
383 }; 310 };
384 311
385 i2c2_x_pins: i 312 i2c2_x_pins: i2c2_x {
386 mux { 313 mux {
387 314 groups = "i2c2_sck_x",
388 315 "i2c2_sda_x";
389 316 function = "i2c2";
390 317 bias-disable;
391 }; 318 };
392 }; 319 };
393 320
394 i2c3_a6_pins: 321 i2c3_a6_pins: i2c3_a6 {
395 mux { 322 mux {
396 323 groups = "i2c3_sda_a6",
397 324 "i2c3_sck_a7";
398 325 function = "i2c3";
399 326 bias-disable;
400 }; 327 };
401 }; 328 };
402 329
403 i2c3_a12_pins: 330 i2c3_a12_pins: i2c3_a12 {
404 mux { 331 mux {
405 332 groups = "i2c3_sda_a12",
406 333 "i2c3_sck_a13";
407 334 function = "i2c3";
408 335 bias-disable;
409 }; 336 };
410 }; 337 };
411 338
412 i2c3_a19_pins: 339 i2c3_a19_pins: i2c3_a19 {
413 mux { 340 mux {
414 341 groups = "i2c3_sda_a19",
415 342 "i2c3_sck_a20";
416 343 function = "i2c3";
417 344 bias-disable;
418 }; 345 };
419 }; 346 };
420 347
421 emmc_pins: emm 348 emmc_pins: emmc {
422 mux-0 349 mux-0 {
423 350 groups = "emmc_nand_d0",
424 351 "emmc_nand_d1",
425 352 "emmc_nand_d2",
426 353 "emmc_nand_d3",
427 354 "emmc_nand_d4",
428 355 "emmc_nand_d5",
429 356 "emmc_nand_d6",
430 357 "emmc_nand_d7",
431 358 "emmc_cmd";
432 359 function = "emmc";
433 360 bias-pull-up;
434 }; 361 };
435 362
436 mux-1 363 mux-1 {
437 364 groups = "emmc_clk";
438 365 function = "emmc";
439 366 bias-disable;
440 }; 367 };
441 }; 368 };
442 369
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 370 emmc_ds_pins: emmc_ds {
465 mux { 371 mux {
466 372 groups = "emmc_ds";
467 373 function = "emmc";
468 374 bias-pull-down;
469 }; 375 };
470 }; 376 };
471 377
472 emmc_clk_gate_ 378 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 379 mux {
474 380 groups = "BOOT_8";
475 381 function = "gpio_periphs";
476 382 bias-pull-down;
477 }; 383 };
478 }; 384 };
479 385
480 eth_rgmii_x_pi 386 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 387 mux {
482 388 groups = "eth_mdio_x",
483 389 "eth_mdc_x",
484 390 "eth_rgmii_rx_clk_x",
485 391 "eth_rx_dv_x",
486 392 "eth_rxd0_x",
487 393 "eth_rxd1_x",
488 394 "eth_rxd2_rgmii",
489 395 "eth_rxd3_rgmii",
490 396 "eth_rgmii_tx_clk",
491 397 "eth_txen_x",
492 398 "eth_txd0_x",
493 399 "eth_txd1_x",
494 400 "eth_txd2_rgmii",
495 401 "eth_txd3_rgmii";
496 402 function = "eth";
497 403 bias-disable;
498 }; 404 };
499 }; 405 };
500 406
501 eth_rgmii_y_pi 407 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 408 mux {
503 409 groups = "eth_mdio_y",
504 410 "eth_mdc_y",
505 411 "eth_rgmii_rx_clk_y",
506 412 "eth_rx_dv_y",
507 413 "eth_rxd0_y",
508 414 "eth_rxd1_y",
509 415 "eth_rxd2_rgmii",
510 416 "eth_rxd3_rgmii",
511 417 "eth_rgmii_tx_clk",
512 418 "eth_txen_y",
513 419 "eth_txd0_y",
514 420 "eth_txd1_y",
515 421 "eth_txd2_rgmii",
516 422 "eth_txd3_rgmii";
517 423 function = "eth";
518 424 bias-disable;
519 }; 425 };
520 }; 426 };
521 427
522 eth_rmii_x_pin 428 eth_rmii_x_pins: eth-x-rmii {
523 mux { 429 mux {
524 430 groups = "eth_mdio_x",
525 431 "eth_mdc_x",
526 432 "eth_rgmii_rx_clk_x",
527 433 "eth_rx_dv_x",
528 434 "eth_rxd0_x",
529 435 "eth_rxd1_x",
530 436 "eth_txen_x",
531 437 "eth_txd0_x",
532 438 "eth_txd1_x";
533 439 function = "eth";
534 440 bias-disable;
535 }; 441 };
536 }; 442 };
537 443
538 eth_rmii_y_pin 444 eth_rmii_y_pins: eth-y-rmii {
539 mux { 445 mux {
540 446 groups = "eth_mdio_y",
541 447 "eth_mdc_y",
542 448 "eth_rgmii_rx_clk_y",
543 449 "eth_rx_dv_y",
544 450 "eth_rxd0_y",
545 451 "eth_rxd1_y",
546 452 "eth_txen_y",
547 453 "eth_txd0_y",
548 454 "eth_txd1_y";
549 455 function = "eth";
550 456 bias-disable;
551 }; 457 };
552 }; 458 };
553 459
554 mclk_b_pins: m 460 mclk_b_pins: mclk_b {
555 mux { 461 mux {
556 462 groups = "mclk_b";
557 463 function = "mclk_b";
558 464 bias-disable;
559 }; 465 };
560 }; 466 };
561 467
562 mclk_c_pins: m 468 mclk_c_pins: mclk_c {
563 mux { 469 mux {
564 470 groups = "mclk_c";
565 471 function = "mclk_c";
566 472 bias-disable;
567 }; 473 };
568 }; 474 };
569 475
570 pdm_dclk_a14_p 476 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 477 mux {
572 478 groups = "pdm_dclk_a14";
573 479 function = "pdm";
574 480 bias-disable;
575 }; 481 };
576 }; 482 };
577 483
578 pdm_dclk_a19_p 484 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 485 mux {
580 486 groups = "pdm_dclk_a19";
581 487 function = "pdm";
582 488 bias-disable;
583 }; 489 };
584 }; 490 };
585 491
586 pdm_din0_pins: 492 pdm_din0_pins: pdm_din0 {
587 mux { 493 mux {
588 494 groups = "pdm_din0";
589 495 function = "pdm";
590 496 bias-disable;
591 }; 497 };
592 }; 498 };
593 499
594 pdm_din1_pins: 500 pdm_din1_pins: pdm_din1 {
595 mux { 501 mux {
596 502 groups = "pdm_din1";
597 503 function = "pdm";
598 504 bias-disable;
599 }; 505 };
600 }; 506 };
601 507
602 pdm_din2_pins: 508 pdm_din2_pins: pdm_din2 {
603 mux { 509 mux {
604 510 groups = "pdm_din2";
605 511 function = "pdm";
606 512 bias-disable;
607 }; 513 };
608 }; 514 };
609 515
610 pdm_din3_pins: 516 pdm_din3_pins: pdm_din3 {
611 mux { 517 mux {
612 518 groups = "pdm_din3";
613 519 function = "pdm";
614 520 bias-disable;
615 }; 521 };
616 }; 522 };
617 523
618 pwm_a_a_pins: 524 pwm_a_a_pins: pwm_a_a {
619 mux { 525 mux {
620 526 groups = "pwm_a_a";
621 527 function = "pwm_a";
622 528 bias-disable;
623 }; 529 };
624 }; 530 };
625 531
626 pwm_a_x18_pins 532 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 533 mux {
628 534 groups = "pwm_a_x18";
629 535 function = "pwm_a";
630 536 bias-disable;
631 }; 537 };
632 }; 538 };
633 539
634 pwm_a_x20_pins 540 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 541 mux {
636 542 groups = "pwm_a_x20";
637 543 function = "pwm_a";
638 544 bias-disable;
639 }; 545 };
640 }; 546 };
641 547
642 pwm_a_z_pins: 548 pwm_a_z_pins: pwm_a_z {
643 mux { 549 mux {
644 550 groups = "pwm_a_z";
645 551 function = "pwm_a";
646 552 bias-disable;
647 }; 553 };
648 }; 554 };
649 555
650 pwm_b_a_pins: 556 pwm_b_a_pins: pwm_b_a {
651 mux { 557 mux {
652 558 groups = "pwm_b_a";
653 559 function = "pwm_b";
654 560 bias-disable;
655 }; 561 };
656 }; 562 };
657 563
658 pwm_b_x_pins: 564 pwm_b_x_pins: pwm_b_x {
659 mux { 565 mux {
660 566 groups = "pwm_b_x";
661 567 function = "pwm_b";
662 568 bias-disable;
663 }; 569 };
664 }; 570 };
665 571
666 pwm_b_z_pins: 572 pwm_b_z_pins: pwm_b_z {
667 mux { 573 mux {
668 574 groups = "pwm_b_z";
669 575 function = "pwm_b";
670 576 bias-disable;
671 }; 577 };
672 }; 578 };
673 579
674 pwm_c_a_pins: 580 pwm_c_a_pins: pwm_c_a {
675 mux { 581 mux {
676 582 groups = "pwm_c_a";
677 583 function = "pwm_c";
678 584 bias-disable;
679 }; 585 };
680 }; 586 };
681 587
682 pwm_c_x10_pins 588 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 589 mux {
684 590 groups = "pwm_c_x10";
685 591 function = "pwm_c";
686 592 bias-disable;
687 }; 593 };
688 }; 594 };
689 595
690 pwm_c_x17_pins 596 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 597 mux {
692 598 groups = "pwm_c_x17";
693 599 function = "pwm_c";
694 600 bias-disable;
695 }; 601 };
696 }; 602 };
697 603
698 pwm_d_x11_pins 604 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 605 mux {
700 606 groups = "pwm_d_x11";
701 607 function = "pwm_d";
702 608 bias-disable;
703 }; 609 };
704 }; 610 };
705 611
706 pwm_d_x16_pins 612 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 613 mux {
708 614 groups = "pwm_d_x16";
709 615 function = "pwm_d";
710 616 bias-disable;
711 }; 617 };
712 }; 618 };
713 619
714 sdio_pins: sdi 620 sdio_pins: sdio {
715 mux-0 621 mux-0 {
716 622 groups = "sdio_d0",
717 623 "sdio_d1",
718 624 "sdio_d2",
719 625 "sdio_d3",
720 626 "sdio_cmd";
721 627 function = "sdio";
722 628 bias-pull-up;
723 }; 629 };
724 630
725 mux-1 631 mux-1 {
726 632 groups = "sdio_clk";
727 633 function = "sdio";
728 634 bias-disable;
729 }; 635 };
730 }; 636 };
731 637
732 sdio_clk_gate_ 638 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 639 mux {
734 640 groups = "GPIOX_4";
735 641 function = "gpio_periphs";
736 642 bias-pull-down;
737 }; 643 };
738 }; 644 };
739 645
740 spdif_in_z_pin 646 spdif_in_z_pins: spdif_in_z {
741 mux { 647 mux {
742 648 groups = "spdif_in_z";
743 649 function = "spdif_in";
744 650 bias-disable;
745 }; 651 };
746 }; 652 };
747 653
748 spdif_in_a1_pi 654 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 655 mux {
750 656 groups = "spdif_in_a1";
751 657 function = "spdif_in";
752 658 bias-disable;
753 }; 659 };
754 }; 660 };
755 661
756 spdif_in_a7_pi 662 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 663 mux {
758 664 groups = "spdif_in_a7";
759 665 function = "spdif_in";
760 666 bias-disable;
761 }; 667 };
762 }; 668 };
763 669
764 spdif_in_a19_p 670 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 671 mux {
766 672 groups = "spdif_in_a19";
767 673 function = "spdif_in";
768 674 bias-disable;
769 }; 675 };
770 }; 676 };
771 677
772 spdif_in_a20_p 678 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 679 mux {
774 680 groups = "spdif_in_a20";
775 681 function = "spdif_in";
776 682 bias-disable;
777 }; 683 };
778 }; 684 };
779 685
780 spdif_out_a1_p 686 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 687 mux {
782 688 groups = "spdif_out_a1";
783 689 function = "spdif_out";
784 690 bias-disable;
785 }; 691 };
786 }; 692 };
787 693
788 spdif_out_a11_ 694 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 695 mux {
790 696 groups = "spdif_out_a11";
791 697 function = "spdif_out";
792 698 bias-disable;
793 }; 699 };
794 }; 700 };
795 701
796 spdif_out_a19_ 702 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 703 mux {
798 704 groups = "spdif_out_a19";
799 705 function = "spdif_out";
800 706 bias-disable;
801 }; 707 };
802 }; 708 };
803 709
804 spdif_out_a20_ 710 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 711 mux {
806 712 groups = "spdif_out_a20";
807 713 function = "spdif_out";
808 714 bias-disable;
809 }; 715 };
810 }; 716 };
811 717
812 spdif_out_z_pi 718 spdif_out_z_pins: spdif_out_z {
813 mux { 719 mux {
814 720 groups = "spdif_out_z";
815 721 function = "spdif_out";
816 722 bias-disable;
817 }; 723 };
818 }; 724 };
819 725
820 spi0_pins: spi 726 spi0_pins: spi0 {
821 mux { 727 mux {
822 728 groups = "spi0_miso",
823 729 "spi0_mosi",
824 730 "spi0_clk";
825 731 function = "spi0";
826 732 bias-disable;
827 }; 733 };
828 }; 734 };
829 735
830 spi0_ss0_pins: 736 spi0_ss0_pins: spi0_ss0 {
831 mux { 737 mux {
832 738 groups = "spi0_ss0";
833 739 function = "spi0";
834 740 bias-disable;
835 }; 741 };
836 }; 742 };
837 743
838 spi0_ss1_pins: 744 spi0_ss1_pins: spi0_ss1 {
839 mux { 745 mux {
840 746 groups = "spi0_ss1";
841 747 function = "spi0";
842 748 bias-disable;
843 }; 749 };
844 }; 750 };
845 751
846 spi0_ss2_pins: 752 spi0_ss2_pins: spi0_ss2 {
847 mux { 753 mux {
848 754 groups = "spi0_ss2";
849 755 function = "spi0";
850 756 bias-disable;
851 }; 757 };
852 }; 758 };
853 759
854 spi1_a_pins: s 760 spi1_a_pins: spi1_a {
855 mux { 761 mux {
856 762 groups = "spi1_miso_a",
857 763 "spi1_mosi_a",
858 764 "spi1_clk_a";
859 765 function = "spi1";
860 766 bias-disable;
861 }; 767 };
862 }; 768 };
863 769
864 spi1_ss0_a_pin 770 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 771 mux {
866 772 groups = "spi1_ss0_a";
867 773 function = "spi1";
868 774 bias-disable;
869 }; 775 };
870 }; 776 };
871 777
872 spi1_ss1_pins: 778 spi1_ss1_pins: spi1_ss1 {
873 mux { 779 mux {
874 780 groups = "spi1_ss1";
875 781 function = "spi1";
876 782 bias-disable;
877 }; 783 };
878 }; 784 };
879 785
880 spi1_x_pins: s 786 spi1_x_pins: spi1_x {
881 mux { 787 mux {
882 788 groups = "spi1_miso_x",
883 789 "spi1_mosi_x",
884 790 "spi1_clk_x";
885 791 function = "spi1";
886 792 bias-disable;
887 }; 793 };
888 }; 794 };
889 795
890 spi1_ss0_x_pin 796 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 797 mux {
892 798 groups = "spi1_ss0_x";
893 799 function = "spi1";
894 800 bias-disable;
895 }; 801 };
896 }; 802 };
897 803
898 tdma_din0_pins 804 tdma_din0_pins: tdma_din0 {
899 mux { 805 mux {
900 806 groups = "tdma_din0";
901 807 function = "tdma";
902 808 bias-disable;
903 }; 809 };
904 }; 810 };
905 811
906 tdma_dout0_x14 812 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 813 mux {
908 814 groups = "tdma_dout0_x14";
909 815 function = "tdma";
910 816 bias-disable;
911 }; 817 };
912 }; 818 };
913 819
914 tdma_dout0_x15 820 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 821 mux {
916 822 groups = "tdma_dout0_x15";
917 823 function = "tdma";
918 824 bias-disable;
919 }; 825 };
920 }; 826 };
921 827
922 tdma_dout1_pin 828 tdma_dout1_pins: tdma_dout1 {
923 mux { 829 mux {
924 830 groups = "tdma_dout1";
925 831 function = "tdma";
926 832 bias-disable;
927 }; 833 };
928 }; 834 };
929 835
930 tdma_din1_pins 836 tdma_din1_pins: tdma_din1 {
931 mux { 837 mux {
932 838 groups = "tdma_din1";
933 839 function = "tdma";
934 840 bias-disable;
935 }; 841 };
936 }; 842 };
937 843
938 tdma_fs_pins: 844 tdma_fs_pins: tdma_fs {
939 mux { 845 mux {
940 846 groups = "tdma_fs";
941 847 function = "tdma";
942 848 bias-disable;
943 }; 849 };
944 }; 850 };
945 851
946 tdma_fs_slv_pi 852 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 853 mux {
948 854 groups = "tdma_fs_slv";
949 855 function = "tdma";
950 856 bias-disable;
951 }; 857 };
952 }; 858 };
953 859
954 tdma_sclk_pins 860 tdma_sclk_pins: tdma_sclk {
955 mux { 861 mux {
956 862 groups = "tdma_sclk";
957 863 function = "tdma";
958 864 bias-disable;
959 }; 865 };
960 }; 866 };
961 867
962 tdma_sclk_slv_ 868 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 869 mux {
964 870 groups = "tdma_sclk_slv";
965 871 function = "tdma";
966 872 bias-disable;
967 }; 873 };
968 }; 874 };
969 875
970 tdmb_din0_pins 876 tdmb_din0_pins: tdmb_din0 {
971 mux { 877 mux {
972 878 groups = "tdmb_din0";
973 879 function = "tdmb";
974 880 bias-disable;
975 }; 881 };
976 }; 882 };
977 883
978 tdmb_din1_pins 884 tdmb_din1_pins: tdmb_din1 {
979 mux { 885 mux {
980 886 groups = "tdmb_din1";
981 887 function = "tdmb";
982 888 bias-disable;
983 }; 889 };
984 }; 890 };
985 891
986 tdmb_din2_pins 892 tdmb_din2_pins: tdmb_din2 {
987 mux { 893 mux {
988 894 groups = "tdmb_din2";
989 895 function = "tdmb";
990 896 bias-disable;
991 }; 897 };
992 }; 898 };
993 899
994 tdmb_din3_pins 900 tdmb_din3_pins: tdmb_din3 {
995 mux { 901 mux {
996 902 groups = "tdmb_din3";
997 903 function = "tdmb";
998 904 bias-disable;
999 }; 905 };
1000 }; 906 };
1001 907
1002 tdmb_dout0_pi 908 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 909 mux {
1004 910 groups = "tdmb_dout0";
1005 911 function = "tdmb";
1006 912 bias-disable;
1007 }; 913 };
1008 }; 914 };
1009 915
1010 tdmb_dout1_pi 916 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 917 mux {
1012 918 groups = "tdmb_dout1";
1013 919 function = "tdmb";
1014 920 bias-disable;
1015 }; 921 };
1016 }; 922 };
1017 923
1018 tdmb_dout2_pi 924 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 925 mux {
1020 926 groups = "tdmb_dout2";
1021 927 function = "tdmb";
1022 928 bias-disable;
1023 }; 929 };
1024 }; 930 };
1025 931
1026 tdmb_dout3_pi 932 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 933 mux {
1028 934 groups = "tdmb_dout3";
1029 935 function = "tdmb";
1030 936 bias-disable;
1031 }; 937 };
1032 }; 938 };
1033 939
1034 tdmb_fs_pins: 940 tdmb_fs_pins: tdmb_fs {
1035 mux { 941 mux {
1036 942 groups = "tdmb_fs";
1037 943 function = "tdmb";
1038 944 bias-disable;
1039 }; 945 };
1040 }; 946 };
1041 947
1042 tdmb_fs_slv_p 948 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 949 mux {
1044 950 groups = "tdmb_fs_slv";
1045 951 function = "tdmb";
1046 952 bias-disable;
1047 }; 953 };
1048 }; 954 };
1049 955
1050 tdmb_sclk_pin 956 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 957 mux {
1052 958 groups = "tdmb_sclk";
1053 959 function = "tdmb";
1054 960 bias-disable;
1055 }; 961 };
1056 }; 962 };
1057 963
1058 tdmb_sclk_slv 964 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 965 mux {
1060 966 groups = "tdmb_sclk_slv";
1061 967 function = "tdmb";
1062 968 bias-disable;
1063 }; 969 };
1064 }; 970 };
1065 971
1066 tdmc_fs_pins: 972 tdmc_fs_pins: tdmc_fs {
1067 mux { 973 mux {
1068 974 groups = "tdmc_fs";
1069 975 function = "tdmc";
1070 976 bias-disable;
1071 }; 977 };
1072 }; 978 };
1073 979
1074 tdmc_fs_slv_p 980 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 981 mux {
1076 982 groups = "tdmc_fs_slv";
1077 983 function = "tdmc";
1078 984 bias-disable;
1079 }; 985 };
1080 }; 986 };
1081 987
1082 tdmc_sclk_pin 988 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 989 mux {
1084 990 groups = "tdmc_sclk";
1085 991 function = "tdmc";
1086 992 bias-disable;
1087 }; 993 };
1088 }; 994 };
1089 995
1090 tdmc_sclk_slv 996 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 997 mux {
1092 998 groups = "tdmc_sclk_slv";
1093 999 function = "tdmc";
1094 1000 bias-disable;
1095 }; 1001 };
1096 }; 1002 };
1097 1003
1098 tdmc_din0_pin 1004 tdmc_din0_pins: tdmc_din0 {
1099 mux { 1005 mux {
1100 1006 groups = "tdmc_din0";
1101 1007 function = "tdmc";
1102 1008 bias-disable;
1103 }; 1009 };
1104 }; 1010 };
1105 1011
1106 tdmc_din1_pin 1012 tdmc_din1_pins: tdmc_din1 {
1107 mux { 1013 mux {
1108 1014 groups = "tdmc_din1";
1109 1015 function = "tdmc";
1110 1016 bias-disable;
1111 }; 1017 };
1112 }; 1018 };
1113 1019
1114 tdmc_din2_pin 1020 tdmc_din2_pins: tdmc_din2 {
1115 mux { 1021 mux {
1116 1022 groups = "tdmc_din2";
1117 1023 function = "tdmc";
1118 1024 bias-disable;
1119 }; 1025 };
1120 }; 1026 };
1121 1027
1122 tdmc_din3_pin 1028 tdmc_din3_pins: tdmc_din3 {
1123 mux { 1029 mux {
1124 1030 groups = "tdmc_din3";
1125 1031 function = "tdmc";
1126 1032 bias-disable;
1127 }; 1033 };
1128 }; 1034 };
1129 1035
1130 tdmc_dout0_pi 1036 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 1037 mux {
1132 1038 groups = "tdmc_dout0";
1133 1039 function = "tdmc";
1134 1040 bias-disable;
1135 }; 1041 };
1136 }; 1042 };
1137 1043
1138 tdmc_dout1_pi 1044 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1045 mux {
1140 1046 groups = "tdmc_dout1";
1141 1047 function = "tdmc";
1142 1048 bias-disable;
1143 }; 1049 };
1144 }; 1050 };
1145 1051
1146 tdmc_dout2_pi 1052 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1053 mux {
1148 1054 groups = "tdmc_dout2";
1149 1055 function = "tdmc";
1150 1056 bias-disable;
1151 }; 1057 };
1152 }; 1058 };
1153 1059
1154 tdmc_dout3_pi 1060 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1061 mux {
1156 1062 groups = "tdmc_dout3";
1157 1063 function = "tdmc";
1158 1064 bias-disable;
1159 }; 1065 };
1160 }; 1066 };
1161 1067
1162 uart_a_pins: 1068 uart_a_pins: uart_a {
1163 mux { 1069 mux {
1164 1070 groups = "uart_tx_a",
1165 1071 "uart_rx_a";
1166 1072 function = "uart_a";
1167 1073 bias-disable;
1168 }; 1074 };
1169 }; 1075 };
1170 1076
1171 uart_a_cts_rt 1077 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1078 mux {
1173 1079 groups = "uart_cts_a",
1174 1080 "uart_rts_a";
1175 1081 function = "uart_a";
1176 1082 bias-disable;
1177 }; 1083 };
1178 }; 1084 };
1179 1085
1180 uart_b_x_pins 1086 uart_b_x_pins: uart_b_x {
1181 mux { 1087 mux {
1182 1088 groups = "uart_tx_b_x",
1183 1089 "uart_rx_b_x";
1184 1090 function = "uart_b";
1185 1091 bias-disable;
1186 }; 1092 };
1187 }; 1093 };
1188 1094
1189 uart_b_x_cts_ 1095 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1096 mux {
1191 1097 groups = "uart_cts_b_x",
1192 1098 "uart_rts_b_x";
1193 1099 function = "uart_b";
1194 1100 bias-disable;
1195 }; 1101 };
1196 }; 1102 };
1197 1103
1198 uart_b_z_pins 1104 uart_b_z_pins: uart_b_z {
1199 mux { 1105 mux {
1200 1106 groups = "uart_tx_b_z",
1201 1107 "uart_rx_b_z";
1202 1108 function = "uart_b";
1203 1109 bias-disable;
1204 }; 1110 };
1205 }; 1111 };
1206 1112
1207 uart_b_z_cts_ 1113 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1114 mux {
1209 1115 groups = "uart_cts_b_z",
1210 1116 "uart_rts_b_z";
1211 1117 function = "uart_b";
1212 1118 bias-disable;
1213 }; 1119 };
1214 }; 1120 };
1215 1121
1216 uart_ao_b_z_p 1122 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1123 mux {
1218 1124 groups = "uart_ao_tx_b_z",
1219 1125 "uart_ao_rx_b_z";
1220 1126 function = "uart_ao_b_z";
1221 1127 bias-disable;
1222 }; 1128 };
1223 }; 1129 };
1224 1130
1225 uart_ao_b_z_c 1131 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1132 mux {
1227 1133 groups = "uart_ao_cts_b_z",
1228 1134 "uart_ao_rts_b_z";
1229 1135 function = "uart_ao_b_z";
1230 1136 bias-disable;
1231 }; 1137 };
1232 }; 1138 };
1233 }; 1139 };
1234 }; 1140 };
1235 1141
1236 hiubus: bus@ff63c000 { 1142 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1143 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1144 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1145 #address-cells = <2>;
1240 #size-cells = <2>; 1146 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1147 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1148
1243 sysctrl: system-contr 1149 sysctrl: system-controller@0 {
1244 compatible = 1150 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1151 "simple-mfd", "syscon";
1246 reg = <0 0 0 1152 reg = <0 0 0 0x400>;
1247 1153
1248 clkc: clock-c 1154 clkc: clock-controller {
1249 compa 1155 compatible = "amlogic,axg-clkc";
1250 #cloc 1156 #clock-cells = <1>;
1251 clock 1157 clocks = <&xtal>;
1252 clock 1158 clock-names = "xtal";
1253 }; 1159 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1160 };
1301 }; 1161 };
1302 1162
1303 mailbox: mailbox@ff63c404 { 1163 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1164 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1165 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1166 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1167 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1168 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1169 #mbox-cells = <1>;
1310 }; 1170 };
1311 1171
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1172 audio: bus@ff642000 {
1326 compatible = "simple- 1173 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1174 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1175 #address-cells = <2>;
1329 #size-cells = <2>; 1176 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1177 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1178
1332 clkc_audio: clock-con 1179 clkc_audio: clock-controller@0 {
1333 compatible = 1180 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1181 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1182 #clock-cells = <1>;
1336 1183
1337 clocks = <&cl 1184 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1185 <&clkc CLKID_MPLL0>,
1339 <&cl 1186 <&clkc CLKID_MPLL1>,
1340 <&cl 1187 <&clkc CLKID_MPLL2>,
1341 <&cl 1188 <&clkc CLKID_MPLL3>,
1342 <&cl 1189 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1190 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1191 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1192 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1193 clock-names = "pclk",
1347 1194 "mst_in0",
1348 1195 "mst_in1",
1349 1196 "mst_in2",
1350 1197 "mst_in3",
1351 1198 "mst_in4",
1352 1199 "mst_in5",
1353 1200 "mst_in6",
1354 1201 "mst_in7";
1355 1202
1356 resets = <&re 1203 resets = <&reset RESET_AUDIO>;
1357 }; 1204 };
1358 1205
1359 toddr_a: audio-contro 1206 toddr_a: audio-controller@100 {
1360 compatible = 1207 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1208 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1209 #sound-dai-cells = <0>;
1363 sound-name-pr 1210 sound-name-prefix = "TODDR_A";
1364 interrupts = 1211 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1212 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1213 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1214 amlogic,fifo-depth = <512>;
1368 status = "dis 1215 status = "disabled";
1369 }; 1216 };
1370 1217
1371 toddr_b: audio-contro 1218 toddr_b: audio-controller@140 {
1372 compatible = 1219 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1220 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1221 #sound-dai-cells = <0>;
1375 sound-name-pr 1222 sound-name-prefix = "TODDR_B";
1376 interrupts = 1223 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1224 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1225 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1226 amlogic,fifo-depth = <256>;
1380 status = "dis 1227 status = "disabled";
1381 }; 1228 };
1382 1229
1383 toddr_c: audio-contro 1230 toddr_c: audio-controller@180 {
1384 compatible = 1231 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1232 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1233 #sound-dai-cells = <0>;
1387 sound-name-pr 1234 sound-name-prefix = "TODDR_C";
1388 interrupts = 1235 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1236 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1237 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1238 amlogic,fifo-depth = <256>;
1392 status = "dis 1239 status = "disabled";
1393 }; 1240 };
1394 1241
1395 frddr_a: audio-contro 1242 frddr_a: audio-controller@1c0 {
1396 compatible = 1243 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1244 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1245 #sound-dai-cells = <0>;
1399 sound-name-pr 1246 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1247 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1248 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1249 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1250 amlogic,fifo-depth = <512>;
1404 status = "dis 1251 status = "disabled";
1405 }; 1252 };
1406 1253
1407 frddr_b: audio-contro 1254 frddr_b: audio-controller@200 {
1408 compatible = 1255 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1256 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1257 #sound-dai-cells = <0>;
1411 sound-name-pr 1258 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1259 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1260 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1261 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1262 amlogic,fifo-depth = <256>;
1416 status = "dis 1263 status = "disabled";
1417 }; 1264 };
1418 1265
1419 frddr_c: audio-contro 1266 frddr_c: audio-controller@240 {
1420 compatible = 1267 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1268 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1269 #sound-dai-cells = <0>;
1423 sound-name-pr 1270 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1271 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1272 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1273 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1274 amlogic,fifo-depth = <256>;
1428 status = "dis 1275 status = "disabled";
1429 }; 1276 };
1430 1277
1431 arb: reset-controller 1278 arb: reset-controller@280 {
1432 compatible = 1279 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1280 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1281 #reset-cells = <1>;
1435 clocks = <&cl 1282 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1283 };
1437 1284
1438 tdmin_a: audio-contro 1285 tdmin_a: audio-controller@300 {
1439 compatible = 1286 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1287 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1288 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1289 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1290 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1291 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1292 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1293 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1294 clock-names = "pclk", "sclk", "sclk_sel",
1448 1295 "lrclk", "lrclk_sel";
1449 status = "dis 1296 status = "disabled";
1450 }; 1297 };
1451 1298
1452 tdmin_b: audio-contro 1299 tdmin_b: audio-controller@340 {
1453 compatible = 1300 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1301 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1302 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1303 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1304 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1305 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1306 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1307 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1308 clock-names = "pclk", "sclk", "sclk_sel",
1462 1309 "lrclk", "lrclk_sel";
1463 status = "dis 1310 status = "disabled";
1464 }; 1311 };
1465 1312
1466 tdmin_c: audio-contro 1313 tdmin_c: audio-controller@380 {
1467 compatible = 1314 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1315 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1316 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1317 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1318 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1319 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1320 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1321 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1322 clock-names = "pclk", "sclk", "sclk_sel",
1476 1323 "lrclk", "lrclk_sel";
1477 status = "dis 1324 status = "disabled";
1478 }; 1325 };
1479 1326
1480 tdmin_lb: audio-contr 1327 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1328 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1329 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1330 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1331 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1332 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1333 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1334 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1335 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1336 clock-names = "pclk", "sclk", "sclk_sel",
1490 1337 "lrclk", "lrclk_sel";
1491 status = "dis 1338 status = "disabled";
1492 }; 1339 };
1493 1340
1494 spdifin: audio-contro 1341 spdifin: audio-controller@400 {
1495 compatible = 1342 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1343 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1344 #sound-dai-cells = <0>;
1498 sound-name-pr 1345 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1346 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1347 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1348 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1349 clock-names = "pclk", "refclk";
1503 status = "dis 1350 status = "disabled";
1504 }; 1351 };
1505 1352
1506 spdifout: audio-contr 1353 spdifout: audio-controller@480 {
1507 compatible = 1354 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1355 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1356 #sound-dai-cells = <0>;
1510 sound-name-pr 1357 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1358 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1359 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1360 clock-names = "pclk", "mclk";
1514 status = "dis 1361 status = "disabled";
1515 }; 1362 };
1516 1363
1517 tdmout_a: audio-contr 1364 tdmout_a: audio-controller@500 {
1518 compatible = 1365 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1366 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1367 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1368 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1369 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1370 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1371 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1372 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1373 clock-names = "pclk", "sclk", "sclk_sel",
1527 1374 "lrclk", "lrclk_sel";
1528 status = "dis 1375 status = "disabled";
1529 }; 1376 };
1530 1377
1531 tdmout_b: audio-contr 1378 tdmout_b: audio-controller@540 {
1532 compatible = 1379 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1380 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1381 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1382 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1383 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1384 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1385 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1386 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1387 clock-names = "pclk", "sclk", "sclk_sel",
1541 1388 "lrclk", "lrclk_sel";
1542 status = "dis 1389 status = "disabled";
1543 }; 1390 };
1544 1391
1545 tdmout_c: audio-contr 1392 tdmout_c: audio-controller@580 {
1546 compatible = 1393 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1394 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1395 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1396 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1397 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1398 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1399 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1400 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1401 clock-names = "pclk", "sclk", "sclk_sel",
1555 1402 "lrclk", "lrclk_sel";
1556 status = "dis 1403 status = "disabled";
1557 }; 1404 };
1558 }; 1405 };
1559 1406
1560 aobus: bus@ff800000 { 1407 aobus: bus@ff800000 {
1561 compatible = "simple- 1408 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1409 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1410 #address-cells = <2>;
1564 #size-cells = <2>; 1411 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1412 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1413
1567 sysctrl_AO: sys-ctrl@ 1414 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1415 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1416 reg = <0x0 0x0 0x0 0x100>;
1570 1417
1571 clkc_AO: cloc 1418 clkc_AO: clock-controller {
1572 compa 1419 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1420 #clock-cells = <1>;
1574 #rese 1421 #reset-cells = <1>;
1575 clock 1422 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1423 clock-names = "xtal", "mpeg-clk";
1577 }; 1424 };
1578 }; 1425 };
1579 1426
1580 pinctrl_aobus: pinctr 1427 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1428 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1429 #address-cells = <2>;
1583 #size-cells = 1430 #size-cells = <2>;
1584 ranges; 1431 ranges;
1585 1432
1586 gpio_ao: bank 1433 gpio_ao: bank@14 {
1587 reg = 1434 reg = <0x0 0x00014 0x0 0x8>,
1588 1435 <0x0 0x0002c 0x0 0x4>,
1589 1436 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1437 reg-names = "mux", "pull", "gpio";
1591 gpio- 1438 gpio-controller;
1592 #gpio 1439 #gpio-cells = <2>;
1593 gpio- 1440 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1441 };
1595 1442
1596 i2c_ao_sck_4_ 1443 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1444 mux {
1598 1445 groups = "i2c_ao_sck_4";
1599 1446 function = "i2c_ao";
1600 1447 bias-disable;
1601 }; 1448 };
1602 }; 1449 };
1603 1450
1604 i2c_ao_sck_8_ 1451 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1452 mux {
1606 1453 groups = "i2c_ao_sck_8";
1607 1454 function = "i2c_ao";
1608 1455 bias-disable;
1609 }; 1456 };
1610 }; 1457 };
1611 1458
1612 i2c_ao_sck_10 1459 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1460 mux {
1614 1461 groups = "i2c_ao_sck_10";
1615 1462 function = "i2c_ao";
1616 1463 bias-disable;
1617 }; 1464 };
1618 }; 1465 };
1619 1466
1620 i2c_ao_sda_5_ 1467 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1468 mux {
1622 1469 groups = "i2c_ao_sda_5";
1623 1470 function = "i2c_ao";
1624 1471 bias-disable;
1625 }; 1472 };
1626 }; 1473 };
1627 1474
1628 i2c_ao_sda_9_ 1475 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1476 mux {
1630 1477 groups = "i2c_ao_sda_9";
1631 1478 function = "i2c_ao";
1632 1479 bias-disable;
1633 }; 1480 };
1634 }; 1481 };
1635 1482
1636 i2c_ao_sda_11 1483 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1484 mux {
1638 1485 groups = "i2c_ao_sda_11";
1639 1486 function = "i2c_ao";
1640 1487 bias-disable;
1641 }; 1488 };
1642 }; 1489 };
1643 1490
1644 remote_input_ 1491 remote_input_ao_pins: remote_input_ao {
1645 mux { 1492 mux {
1646 1493 groups = "remote_input_ao";
1647 1494 function = "remote_input_ao";
1648 1495 bias-disable;
1649 }; 1496 };
1650 }; 1497 };
1651 1498
1652 uart_ao_a_pin 1499 uart_ao_a_pins: uart_ao_a {
1653 mux { 1500 mux {
1654 1501 groups = "uart_ao_tx_a",
1655 1502 "uart_ao_rx_a";
1656 1503 function = "uart_ao_a";
1657 1504 bias-disable;
1658 }; 1505 };
1659 }; 1506 };
1660 1507
1661 uart_ao_a_cts 1508 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1509 mux {
1663 1510 groups = "uart_ao_cts_a",
1664 1511 "uart_ao_rts_a";
1665 1512 function = "uart_ao_a";
1666 1513 bias-disable;
1667 }; 1514 };
1668 }; 1515 };
1669 1516
1670 uart_ao_b_pin 1517 uart_ao_b_pins: uart_ao_b {
1671 mux { 1518 mux {
1672 1519 groups = "uart_ao_tx_b",
1673 1520 "uart_ao_rx_b";
1674 1521 function = "uart_ao_b";
1675 1522 bias-disable;
1676 }; 1523 };
1677 }; 1524 };
1678 1525
1679 uart_ao_b_cts 1526 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1527 mux {
1681 1528 groups = "uart_ao_cts_b",
1682 1529 "uart_ao_rts_b";
1683 1530 function = "uart_ao_b";
1684 1531 bias-disable;
1685 }; 1532 };
1686 }; 1533 };
1687 }; 1534 };
1688 1535
1689 sec_AO: ao-secure@140 1536 sec_AO: ao-secure@140 {
1690 compatible = 1537 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1538 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1539 amlogic,has-chip-id;
1693 }; 1540 };
1694 1541
1695 pwm_AO_cd: pwm@2000 { 1542 pwm_AO_cd: pwm@2000 {
1696 compatible = 1543 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1544 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1545 #pwm-cells = <3>;
1699 status = "dis 1546 status = "disabled";
1700 }; 1547 };
1701 1548
1702 uart_AO: serial@3000 1549 uart_AO: serial@3000 {
1703 compatible = 1550 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1551 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1552 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1553 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1554 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1555 status = "disabled";
1709 }; 1556 };
1710 1557
1711 uart_AO_B: serial@400 1558 uart_AO_B: serial@4000 {
1712 compatible = 1559 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1560 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1561 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1562 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1563 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1564 status = "disabled";
1718 }; 1565 };
1719 1566
1720 i2c_AO: i2c@5000 { 1567 i2c_AO: i2c@5000 {
1721 compatible = 1568 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1569 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1570 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1571 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1572 #address-cells = <1>;
1726 #size-cells = 1573 #size-cells = <0>;
1727 status = "dis 1574 status = "disabled";
1728 }; 1575 };
1729 1576
1730 pwm_AO_ab: pwm@7000 { 1577 pwm_AO_ab: pwm@7000 {
1731 compatible = 1578 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1579 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1580 #pwm-cells = <3>;
1734 status = "dis 1581 status = "disabled";
1735 }; 1582 };
1736 1583
1737 ir: ir@8000 { 1584 ir: ir@8000 {
1738 compatible = 1585 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1586 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1587 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1588 status = "disabled";
1742 }; 1589 };
1743 1590
1744 saradc: adc@9000 { 1591 saradc: adc@9000 {
1745 compatible = 1592 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1593 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1594 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1595 #io-channel-cells = <1>;
1749 interrupts = 1596 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1597 clocks = <&xtal>,
1751 <&cl 1598 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1599 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1600 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1601 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1602 status = "disabled";
1756 }; 1603 };
1757 }; 1604 };
1758 1605
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1606 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1607 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1608 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1609 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1610 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1611 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1612 interrupt-controller;
1774 interrupts = <GIC_PPI 1613 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1614 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1615 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1616 #address-cells = <0>;
1778 }; 1617 };
1779 1618
1780 cbus: bus@ffd00000 { 1619 cbus: bus@ffd00000 {
1781 compatible = "simple- 1620 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1621 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1622 #address-cells = <2>;
1784 #size-cells = <2>; 1623 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1624 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1625
1787 reset: reset-controll 1626 reset: reset-controller@1004 {
1788 compatible = 1627 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1628 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1629 #reset-cells = <1>;
1791 }; 1630 };
1792 1631
1793 gpio_intc: interrupt- 1632 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1633 compatible = "amlogic,meson-axg-gpio-intc",
1795 1634 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1635 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1636 interrupt-controller;
1798 #interrupt-ce 1637 #interrupt-cells = <2>;
1799 amlogic,chann 1638 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1639 };
1801 1640
1802 watchdog@f0d0 { 1641 watchdog@f0d0 {
1803 compatible = 1642 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1643 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1644 clocks = <&xtal>;
1806 }; 1645 };
1807 1646
1808 pwm_ab: pwm@1b000 { 1647 pwm_ab: pwm@1b000 {
1809 compatible = 1648 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1649 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1650 #pwm-cells = <3>;
1812 status = "dis 1651 status = "disabled";
1813 }; 1652 };
1814 1653
1815 pwm_cd: pwm@1a000 { 1654 pwm_cd: pwm@1a000 {
1816 compatible = 1655 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1656 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1657 #pwm-cells = <3>;
1819 status = "dis 1658 status = "disabled";
1820 }; 1659 };
1821 1660
1822 spicc0: spi@13000 { 1661 spicc0: spi@13000 {
1823 compatible = 1662 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1663 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1664 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1665 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1666 clock-names = "core";
1828 #address-cell 1667 #address-cells = <1>;
1829 #size-cells = 1668 #size-cells = <0>;
1830 status = "dis 1669 status = "disabled";
1831 }; 1670 };
1832 1671
1833 spicc1: spi@15000 { 1672 spicc1: spi@15000 {
1834 compatible = 1673 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1674 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1675 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1676 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1677 clock-names = "core";
1839 #address-cell 1678 #address-cells = <1>;
1840 #size-cells = 1679 #size-cells = <0>;
1841 status = "dis 1680 status = "disabled";
1842 }; 1681 };
1843 1682
1844 clk_msr: clock-measur 1683 clk_msr: clock-measure@18000 {
1845 compatible = 1684 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1685 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1686 };
1848 1687
1849 i2c3: i2c@1c000 { 1688 i2c3: i2c@1c000 {
1850 compatible = 1689 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1690 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1691 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1692 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1693 #address-cells = <1>;
1855 #size-cells = 1694 #size-cells = <0>;
1856 status = "dis 1695 status = "disabled";
1857 }; 1696 };
1858 1697
1859 i2c2: i2c@1d000 { 1698 i2c2: i2c@1d000 {
1860 compatible = 1699 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1700 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1701 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1702 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1703 #address-cells = <1>;
1865 #size-cells = 1704 #size-cells = <0>;
1866 status = "dis 1705 status = "disabled";
1867 }; 1706 };
1868 1707
1869 i2c1: i2c@1e000 { 1708 i2c1: i2c@1e000 {
1870 compatible = 1709 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1710 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1711 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1712 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1713 #address-cells = <1>;
1875 #size-cells = 1714 #size-cells = <0>;
1876 status = "dis 1715 status = "disabled";
1877 }; 1716 };
1878 1717
1879 i2c0: i2c@1f000 { 1718 i2c0: i2c@1f000 {
1880 compatible = 1719 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1720 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1721 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1722 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1723 #address-cells = <1>;
1885 #size-cells = 1724 #size-cells = <0>;
1886 status = "dis 1725 status = "disabled";
1887 }; 1726 };
1888 1727
1889 uart_B: serial@23000 1728 uart_B: serial@23000 {
1890 compatible = 1729 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1730 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1731 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1732 status = "disabled";
1894 clocks = <&xt 1733 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1734 clock-names = "xtal", "pclk", "baud";
1896 }; 1735 };
1897 1736
1898 uart_A: serial@24000 1737 uart_A: serial@24000 {
1899 compatible = 1738 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1739 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1740 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1741 status = "disabled";
1903 clocks = <&xt 1742 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1743 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1744 };
1907 }; 1745 };
1908 1746
1909 apb: bus@ffe00000 { 1747 apb: bus@ffe00000 {
1910 compatible = "simple- 1748 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1749 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1750 #address-cells = <2>;
1913 #size-cells = <2>; 1751 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1752 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1753
1916 sd_emmc_b: mmc@5000 { !! 1754 sd_emmc_b: sd@5000 {
1917 compatible = 1755 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1756 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1757 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1758 status = "disabled";
1921 clocks = <&cl 1759 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1760 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1761 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1762 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1763 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1764 };
1927 1765
1928 sd_emmc_c: mmc@7000 { 1766 sd_emmc_c: mmc@7000 {
1929 compatible = 1767 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1768 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1769 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1770 status = "disabled";
1933 clocks = <&cl 1771 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1772 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1773 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1774 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1775 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; 1776 };
1954 1777
1955 usb2_phy1: phy@9020 { 1778 usb2_phy1: phy@9020 {
1956 compatible = 1779 compatible = "amlogic,meson-gxl-usb2-phy";
1957 #phy-cells = 1780 #phy-cells = <0>;
1958 reg = <0x0 0x 1781 reg = <0x0 0x9020 0x0 0x20>;
1959 clocks = <&cl 1782 clocks = <&clkc CLKID_USB>;
1960 clock-names = 1783 clock-names = "phy";
1961 resets = <&re 1784 resets = <&reset RESET_USB_OTG>;
1962 reset-names = 1785 reset-names = "phy";
1963 }; 1786 };
1964 }; 1787 };
1965 1788
1966 sram: sram@fffc0000 { 1789 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1790 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1791 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1792 #address-cells = <1>;
1970 #size-cells = <1>; 1793 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1794 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1795
1973 cpu_scp_lpri: scp-sra 1796 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1797 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1798 reg = <0x13000 0x400>;
1976 }; 1799 };
1977 1800
1978 cpu_scp_hpri: scp-sra 1801 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1802 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1803 reg = <0x13400 0x400>;
1981 }; 1804 };
1982 }; 1805 };
1983 }; 1806 };
1984 1807
1985 timer { 1808 timer {
1986 compatible = "arm,armv8-timer 1809 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1810 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1811 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1812 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1813 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1814 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1815 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1816 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1817 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1818 };
1996 1819
1997 xtal: xtal-clk { 1820 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1821 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1822 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1823 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1824 #clock-cells = <0>;
2002 }; 1825 };
2003 }; 1826 };
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