1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> 15 #include <dt-bindings/power/meson-axg-power.h>
16 16
17 / { 17 / {
18 compatible = "amlogic,meson-axg"; 18 compatible = "amlogic,meson-axg";
19 19
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 tdmif_a: audio-controller-0 { 24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 25 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 28 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 30 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 31 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 tdmif_b: audio-controller-1 { 35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 36 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 39 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 41 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 42 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 tdmif_c: audio-controller-2 { 46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 47 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 50 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 52 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 53 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 54 status = "disabled";
55 }; 55 };
56 56
57 arm-pmu { 57 arm-pmu {
58 compatible = "arm,cortex-a53-p 58 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 64 };
65 65
66 cpus { 66 cpus {
67 #address-cells = <0x2>; 67 #address-cells = <0x2>;
68 #size-cells = <0x0>; 68 #size-cells = <0x0>;
69 69
70 cpu0: cpu@0 { 70 cpu0: cpu@0 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 73 reg = <0x0 0x0>;
74 enable-method = "psci" 74 enable-method = "psci";
75 next-level-cache = <&l 75 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 76 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 77 };
80 78
81 cpu1: cpu@1 { 79 cpu1: cpu@1 {
82 device_type = "cpu"; 80 device_type = "cpu";
83 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 82 reg = <0x0 0x1>;
85 enable-method = "psci" 83 enable-method = "psci";
86 next-level-cache = <&l 84 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 85 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 86 };
91 87
92 cpu2: cpu@2 { 88 cpu2: cpu@2 {
93 device_type = "cpu"; 89 device_type = "cpu";
94 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 91 reg = <0x0 0x2>;
96 enable-method = "psci" 92 enable-method = "psci";
97 next-level-cache = <&l 93 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 94 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 95 };
102 96
103 cpu3: cpu@3 { 97 cpu3: cpu@3 {
104 device_type = "cpu"; 98 device_type = "cpu";
105 compatible = "arm,cort 99 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 100 reg = <0x0 0x3>;
107 enable-method = "psci" 101 enable-method = "psci";
108 next-level-cache = <&l 102 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 103 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 104 };
113 105
114 l2: l2-cache0 { 106 l2: l2-cache0 {
115 compatible = "cache"; 107 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 108 };
119 }; 109 };
120 110
121 sm: secure-monitor { 111 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 112 compatible = "amlogic,meson-gxbb-sm";
123 }; 113 };
124 114
125 efuse: efuse { 115 efuse: efuse {
126 compatible = "amlogic,meson-gx 116 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 117 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 118 #address-cells = <1>;
129 #size-cells = <1>; 119 #size-cells = <1>;
130 read-only; 120 read-only;
131 secure-monitor = <&sm>; 121 secure-monitor = <&sm>;
132 }; 122 };
133 123
134 psci { 124 psci {
135 compatible = "arm,psci-1.0"; 125 compatible = "arm,psci-1.0";
136 method = "smc"; 126 method = "smc";
137 }; 127 };
138 128
139 reserved-memory { 129 reserved-memory {
140 #address-cells = <2>; 130 #address-cells = <2>;
141 #size-cells = <2>; 131 #size-cells = <2>;
142 ranges; 132 ranges;
143 133
144 /* 16 MiB reserved for Hardwar 134 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 135 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 136 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 137 no-map;
148 }; 138 };
149 139
150 /* Alternate 3 MiB reserved fo 140 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 141 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 142 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 143 no-map;
154 }; 144 };
155 }; 145 };
156 146
157 scpi { 147 scpi {
158 compatible = "arm,scpi-pre-1.0 148 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 149 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 150 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 151
162 scpi_clocks: clocks { 152 scpi_clocks: clocks {
163 compatible = "arm,scpi 153 compatible = "arm,scpi-clocks";
164 154
165 scpi_dvfs: clocks-0 { 155 scpi_dvfs: clocks-0 {
166 compatible = " 156 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 157 #clock-cells = <1>;
168 clock-indices 158 clock-indices = <0>;
169 clock-output-n 159 clock-output-names = "vcpu";
170 }; 160 };
171 }; 161 };
172 162
173 scpi_sensors: sensors { 163 scpi_sensors: sensors {
174 compatible = "amlogic, 164 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 165 #thermal-sensor-cells = <1>;
176 }; 166 };
177 }; 167 };
178 168
179 soc { 169 soc {
180 compatible = "simple-bus"; 170 compatible = "simple-bus";
181 #address-cells = <2>; 171 #address-cells = <2>;
182 #size-cells = <2>; 172 #size-cells = <2>;
183 ranges; 173 ranges;
184 174
185 pcieA: pcie@f9800000 { 175 pcieA: pcie@f9800000 {
186 compatible = "amlogic, 176 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
187 reg = <0x0 0xf9800000 177 reg = <0x0 0xf9800000 0x0 0x400000>,
188 <0x0 0xff646000 178 <0x0 0xff646000 0x0 0x2000>,
189 <0x0 0xf9f00000 179 <0x0 0xf9f00000 0x0 0x100000>;
190 reg-names = "elbi", "c 180 reg-names = "elbi", "cfg", "config";
191 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
192 #interrupt-cells = <1> 182 #interrupt-cells = <1>;
193 interrupt-map-mask = < 183 interrupt-map-mask = <0 0 0 0>;
194 interrupt-map = <0 0 0 184 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
195 bus-range = <0x0 0xff> 185 bus-range = <0x0 0xff>;
196 #address-cells = <3>; 186 #address-cells = <3>;
197 #size-cells = <2>; 187 #size-cells = <2>;
198 device_type = "pci"; 188 device_type = "pci";
199 ranges = <0x82000000 0 189 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
200 190
201 clocks = <&clkc CLKID_ 191 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
202 clock-names = "general 192 clock-names = "general", "pclk", "port";
203 resets = <&reset RESET 193 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
204 reset-names = "port", 194 reset-names = "port", "apb";
205 num-lanes = <1>; 195 num-lanes = <1>;
206 phys = <&pcie_phy>; 196 phys = <&pcie_phy>;
207 phy-names = "pcie"; 197 phy-names = "pcie";
208 status = "disabled"; 198 status = "disabled";
209 }; 199 };
210 200
211 pcieB: pcie@fa000000 { 201 pcieB: pcie@fa000000 {
212 compatible = "amlogic, 202 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
213 reg = <0x0 0xfa000000 203 reg = <0x0 0xfa000000 0x0 0x400000>,
214 <0x0 0xff648000 204 <0x0 0xff648000 0x0 0x2000>,
215 <0x0 0xfa400000 205 <0x0 0xfa400000 0x0 0x100000>;
216 reg-names = "elbi", "c 206 reg-names = "elbi", "cfg", "config";
217 interrupts = <GIC_SPI 207 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
218 #interrupt-cells = <1> 208 #interrupt-cells = <1>;
219 interrupt-map-mask = < 209 interrupt-map-mask = <0 0 0 0>;
220 interrupt-map = <0 0 0 210 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
221 bus-range = <0x0 0xff> 211 bus-range = <0x0 0xff>;
222 #address-cells = <3>; 212 #address-cells = <3>;
223 #size-cells = <2>; 213 #size-cells = <2>;
224 device_type = "pci"; 214 device_type = "pci";
225 ranges = <0x82000000 0 215 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
226 216
227 clocks = <&clkc CLKID_ 217 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
228 clock-names = "general 218 clock-names = "general", "pclk", "port";
229 resets = <&reset RESET 219 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
230 reset-names = "port", 220 reset-names = "port", "apb";
231 num-lanes = <1>; 221 num-lanes = <1>;
232 phys = <&pcie_phy>; 222 phys = <&pcie_phy>;
233 phy-names = "pcie"; 223 phy-names = "pcie";
234 status = "disabled"; 224 status = "disabled";
235 }; 225 };
236 226
237 usb: usb@ffe09080 { 227 usb: usb@ffe09080 {
238 compatible = "amlogic, 228 compatible = "amlogic,meson-axg-usb-ctrl";
239 reg = <0x0 0xffe09080 229 reg = <0x0 0xffe09080 0x0 0x20>;
240 interrupts = <GIC_SPI 230 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; 231 #address-cells = <2>;
242 #size-cells = <2>; 232 #size-cells = <2>;
243 ranges; 233 ranges;
244 234
245 clocks = <&clkc CLKID_ 235 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
246 clock-names = "usb_ctr 236 clock-names = "usb_ctrl", "ddr";
247 resets = <&reset RESET 237 resets = <&reset RESET_USB_OTG>;
248 238
249 dr_mode = "otg"; 239 dr_mode = "otg";
250 240
251 phys = <&usb2_phy1>; 241 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1 242 phy-names = "usb2-phy1";
253 243
254 dwc2: usb@ff400000 { 244 dwc2: usb@ff400000 {
255 compatible = " 245 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
256 reg = <0x0 0xf 246 reg = <0x0 0xff400000 0x0 0x40000>;
257 interrupts = < 247 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk 248 clocks = <&clkc CLKID_USB1>;
259 clock-names = 249 clock-names = "otg";
260 phys = <&usb2_ 250 phys = <&usb2_phy1>;
261 dr_mode = "per 251 dr_mode = "peripheral";
262 g-rx-fifo-size 252 g-rx-fifo-size = <192>;
263 g-np-tx-fifo-s 253 g-np-tx-fifo-size = <128>;
264 g-tx-fifo-size 254 g-tx-fifo-size = <128 128 16 16 16>;
265 }; 255 };
266 256
267 dwc3: usb@ff500000 { 257 dwc3: usb@ff500000 {
268 compatible = " 258 compatible = "snps,dwc3";
269 reg = <0x0 0xf 259 reg = <0x0 0xff500000 0x0 0x100000>;
270 interrupts = < 260 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
271 dr_mode = "hos 261 dr_mode = "host";
272 maximum-speed 262 maximum-speed = "high-speed";
273 snps,dis_u2_su 263 snps,dis_u2_susphy_quirk;
274 }; 264 };
275 }; 265 };
276 266
277 ethmac: ethernet@ff3f0000 { 267 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 268 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 269 "snps,dwmac-3.70a",
280 "snps,dwm 270 "snps,dwmac";
281 reg = <0x0 0xff3f0000 271 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 272 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 273 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 274 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 275 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 276 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 277 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 278 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 279 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 280 "timing-adjustment";
291 rx-fifo-depth = <4096> 281 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 282 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc 283 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
294 status = "disabled"; 284 status = "disabled";
295 }; 285 };
296 286
297 pcie_phy: phy@ff644000 { 287 pcie_phy: phy@ff644000 {
298 compatible = "amlogic, 288 compatible = "amlogic,axg-pcie-phy";
299 reg = <0x0 0xff644000 289 reg = <0x0 0xff644000 0x0 0x1c>;
300 resets = <&reset RESET 290 resets = <&reset RESET_PCIE_PHY>;
301 phys = <&mipi_pcie_ana 291 phys = <&mipi_pcie_analog_dphy>;
302 phy-names = "analog"; 292 phy-names = "analog";
303 #phy-cells = <0>; 293 #phy-cells = <0>;
304 }; 294 };
305 295
306 pdm: audio-controller@ff632000 296 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 297 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 298 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 299 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 300 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 301 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 302 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 303 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 304 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 305 status = "disabled";
316 }; 306 };
317 307
318 periphs: bus@ff634000 { 308 periphs: bus@ff634000 {
319 compatible = "simple-b 309 compatible = "simple-bus";
320 reg = <0x0 0xff634000 310 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 311 #address-cells = <2>;
322 #size-cells = <2>; 312 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 313 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 314
325 hwrng: rng@18 { 315 hwrng: rng@18 {
326 compatible = " 316 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 317 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 318 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 319 clock-names = "core";
330 }; 320 };
331 321
332 pinctrl_periphs: pinct 322 pinctrl_periphs: pinctrl@480 {
333 compatible = " 323 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 324 #address-cells = <2>;
335 #size-cells = 325 #size-cells = <2>;
336 ranges; 326 ranges;
337 327
338 gpio: bank@480 328 gpio: bank@480 {
339 reg = 329 reg = <0x0 0x00480 0x0 0x40>,
340 330 <0x0 0x004e8 0x0 0x14>,
341 331 <0x0 0x00520 0x0 0x14>,
342 332 <0x0 0x00430 0x0 0x3c>;
343 reg-na 333 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 334 gpio-controller;
345 #gpio- 335 #gpio-cells = <2>;
346 gpio-r 336 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 337 };
348 338
349 i2c0_pins: i2c 339 i2c0_pins: i2c0 {
350 mux { 340 mux {
351 341 groups = "i2c0_sck",
352 342 "i2c0_sda";
353 343 function = "i2c0";
354 344 bias-disable;
355 }; 345 };
356 }; 346 };
357 347
358 i2c1_x_pins: i 348 i2c1_x_pins: i2c1_x {
359 mux { 349 mux {
360 350 groups = "i2c1_sck_x",
361 351 "i2c1_sda_x";
362 352 function = "i2c1";
363 353 bias-disable;
364 }; 354 };
365 }; 355 };
366 356
367 i2c1_z_pins: i 357 i2c1_z_pins: i2c1_z {
368 mux { 358 mux {
369 359 groups = "i2c1_sck_z",
370 360 "i2c1_sda_z";
371 361 function = "i2c1";
372 362 bias-disable;
373 }; 363 };
374 }; 364 };
375 365
376 i2c2_a_pins: i 366 i2c2_a_pins: i2c2_a {
377 mux { 367 mux {
378 368 groups = "i2c2_sck_a",
379 369 "i2c2_sda_a";
380 370 function = "i2c2";
381 371 bias-disable;
382 }; 372 };
383 }; 373 };
384 374
385 i2c2_x_pins: i 375 i2c2_x_pins: i2c2_x {
386 mux { 376 mux {
387 377 groups = "i2c2_sck_x",
388 378 "i2c2_sda_x";
389 379 function = "i2c2";
390 380 bias-disable;
391 }; 381 };
392 }; 382 };
393 383
394 i2c3_a6_pins: 384 i2c3_a6_pins: i2c3_a6 {
395 mux { 385 mux {
396 386 groups = "i2c3_sda_a6",
397 387 "i2c3_sck_a7";
398 388 function = "i2c3";
399 389 bias-disable;
400 }; 390 };
401 }; 391 };
402 392
403 i2c3_a12_pins: 393 i2c3_a12_pins: i2c3_a12 {
404 mux { 394 mux {
405 395 groups = "i2c3_sda_a12",
406 396 "i2c3_sck_a13";
407 397 function = "i2c3";
408 398 bias-disable;
409 }; 399 };
410 }; 400 };
411 401
412 i2c3_a19_pins: 402 i2c3_a19_pins: i2c3_a19 {
413 mux { 403 mux {
414 404 groups = "i2c3_sda_a19",
415 405 "i2c3_sck_a20";
416 406 function = "i2c3";
417 407 bias-disable;
418 }; 408 };
419 }; 409 };
420 410
421 emmc_pins: emm 411 emmc_pins: emmc {
422 mux-0 412 mux-0 {
423 413 groups = "emmc_nand_d0",
424 414 "emmc_nand_d1",
425 415 "emmc_nand_d2",
426 416 "emmc_nand_d3",
427 417 "emmc_nand_d4",
428 418 "emmc_nand_d5",
429 419 "emmc_nand_d6",
430 420 "emmc_nand_d7",
431 421 "emmc_cmd";
432 422 function = "emmc";
433 423 bias-pull-up;
434 }; 424 };
435 425
436 mux-1 426 mux-1 {
437 427 groups = "emmc_clk";
438 428 function = "emmc";
439 429 bias-disable;
440 }; 430 };
441 }; 431 };
442 432
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 433 emmc_ds_pins: emmc_ds {
465 mux { 434 mux {
466 435 groups = "emmc_ds";
467 436 function = "emmc";
468 437 bias-pull-down;
469 }; 438 };
470 }; 439 };
471 440
472 emmc_clk_gate_ 441 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 442 mux {
474 443 groups = "BOOT_8";
475 444 function = "gpio_periphs";
476 445 bias-pull-down;
477 }; 446 };
478 }; 447 };
479 448
480 eth_rgmii_x_pi 449 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 450 mux {
482 451 groups = "eth_mdio_x",
483 452 "eth_mdc_x",
484 453 "eth_rgmii_rx_clk_x",
485 454 "eth_rx_dv_x",
486 455 "eth_rxd0_x",
487 456 "eth_rxd1_x",
488 457 "eth_rxd2_rgmii",
489 458 "eth_rxd3_rgmii",
490 459 "eth_rgmii_tx_clk",
491 460 "eth_txen_x",
492 461 "eth_txd0_x",
493 462 "eth_txd1_x",
494 463 "eth_txd2_rgmii",
495 464 "eth_txd3_rgmii";
496 465 function = "eth";
497 466 bias-disable;
498 }; 467 };
499 }; 468 };
500 469
501 eth_rgmii_y_pi 470 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 471 mux {
503 472 groups = "eth_mdio_y",
504 473 "eth_mdc_y",
505 474 "eth_rgmii_rx_clk_y",
506 475 "eth_rx_dv_y",
507 476 "eth_rxd0_y",
508 477 "eth_rxd1_y",
509 478 "eth_rxd2_rgmii",
510 479 "eth_rxd3_rgmii",
511 480 "eth_rgmii_tx_clk",
512 481 "eth_txen_y",
513 482 "eth_txd0_y",
514 483 "eth_txd1_y",
515 484 "eth_txd2_rgmii",
516 485 "eth_txd3_rgmii";
517 486 function = "eth";
518 487 bias-disable;
519 }; 488 };
520 }; 489 };
521 490
522 eth_rmii_x_pin 491 eth_rmii_x_pins: eth-x-rmii {
523 mux { 492 mux {
524 493 groups = "eth_mdio_x",
525 494 "eth_mdc_x",
526 495 "eth_rgmii_rx_clk_x",
527 496 "eth_rx_dv_x",
528 497 "eth_rxd0_x",
529 498 "eth_rxd1_x",
530 499 "eth_txen_x",
531 500 "eth_txd0_x",
532 501 "eth_txd1_x";
533 502 function = "eth";
534 503 bias-disable;
535 }; 504 };
536 }; 505 };
537 506
538 eth_rmii_y_pin 507 eth_rmii_y_pins: eth-y-rmii {
539 mux { 508 mux {
540 509 groups = "eth_mdio_y",
541 510 "eth_mdc_y",
542 511 "eth_rgmii_rx_clk_y",
543 512 "eth_rx_dv_y",
544 513 "eth_rxd0_y",
545 514 "eth_rxd1_y",
546 515 "eth_txen_y",
547 516 "eth_txd0_y",
548 517 "eth_txd1_y";
549 518 function = "eth";
550 519 bias-disable;
551 }; 520 };
552 }; 521 };
553 522
554 mclk_b_pins: m 523 mclk_b_pins: mclk_b {
555 mux { 524 mux {
556 525 groups = "mclk_b";
557 526 function = "mclk_b";
558 527 bias-disable;
559 }; 528 };
560 }; 529 };
561 530
562 mclk_c_pins: m 531 mclk_c_pins: mclk_c {
563 mux { 532 mux {
564 533 groups = "mclk_c";
565 534 function = "mclk_c";
566 535 bias-disable;
567 }; 536 };
568 }; 537 };
569 538
570 pdm_dclk_a14_p 539 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 540 mux {
572 541 groups = "pdm_dclk_a14";
573 542 function = "pdm";
574 543 bias-disable;
575 }; 544 };
576 }; 545 };
577 546
578 pdm_dclk_a19_p 547 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 548 mux {
580 549 groups = "pdm_dclk_a19";
581 550 function = "pdm";
582 551 bias-disable;
583 }; 552 };
584 }; 553 };
585 554
586 pdm_din0_pins: 555 pdm_din0_pins: pdm_din0 {
587 mux { 556 mux {
588 557 groups = "pdm_din0";
589 558 function = "pdm";
590 559 bias-disable;
591 }; 560 };
592 }; 561 };
593 562
594 pdm_din1_pins: 563 pdm_din1_pins: pdm_din1 {
595 mux { 564 mux {
596 565 groups = "pdm_din1";
597 566 function = "pdm";
598 567 bias-disable;
599 }; 568 };
600 }; 569 };
601 570
602 pdm_din2_pins: 571 pdm_din2_pins: pdm_din2 {
603 mux { 572 mux {
604 573 groups = "pdm_din2";
605 574 function = "pdm";
606 575 bias-disable;
607 }; 576 };
608 }; 577 };
609 578
610 pdm_din3_pins: 579 pdm_din3_pins: pdm_din3 {
611 mux { 580 mux {
612 581 groups = "pdm_din3";
613 582 function = "pdm";
614 583 bias-disable;
615 }; 584 };
616 }; 585 };
617 586
618 pwm_a_a_pins: 587 pwm_a_a_pins: pwm_a_a {
619 mux { 588 mux {
620 589 groups = "pwm_a_a";
621 590 function = "pwm_a";
622 591 bias-disable;
623 }; 592 };
624 }; 593 };
625 594
626 pwm_a_x18_pins 595 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 596 mux {
628 597 groups = "pwm_a_x18";
629 598 function = "pwm_a";
630 599 bias-disable;
631 }; 600 };
632 }; 601 };
633 602
634 pwm_a_x20_pins 603 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 604 mux {
636 605 groups = "pwm_a_x20";
637 606 function = "pwm_a";
638 607 bias-disable;
639 }; 608 };
640 }; 609 };
641 610
642 pwm_a_z_pins: 611 pwm_a_z_pins: pwm_a_z {
643 mux { 612 mux {
644 613 groups = "pwm_a_z";
645 614 function = "pwm_a";
646 615 bias-disable;
647 }; 616 };
648 }; 617 };
649 618
650 pwm_b_a_pins: 619 pwm_b_a_pins: pwm_b_a {
651 mux { 620 mux {
652 621 groups = "pwm_b_a";
653 622 function = "pwm_b";
654 623 bias-disable;
655 }; 624 };
656 }; 625 };
657 626
658 pwm_b_x_pins: 627 pwm_b_x_pins: pwm_b_x {
659 mux { 628 mux {
660 629 groups = "pwm_b_x";
661 630 function = "pwm_b";
662 631 bias-disable;
663 }; 632 };
664 }; 633 };
665 634
666 pwm_b_z_pins: 635 pwm_b_z_pins: pwm_b_z {
667 mux { 636 mux {
668 637 groups = "pwm_b_z";
669 638 function = "pwm_b";
670 639 bias-disable;
671 }; 640 };
672 }; 641 };
673 642
674 pwm_c_a_pins: 643 pwm_c_a_pins: pwm_c_a {
675 mux { 644 mux {
676 645 groups = "pwm_c_a";
677 646 function = "pwm_c";
678 647 bias-disable;
679 }; 648 };
680 }; 649 };
681 650
682 pwm_c_x10_pins 651 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 652 mux {
684 653 groups = "pwm_c_x10";
685 654 function = "pwm_c";
686 655 bias-disable;
687 }; 656 };
688 }; 657 };
689 658
690 pwm_c_x17_pins 659 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 660 mux {
692 661 groups = "pwm_c_x17";
693 662 function = "pwm_c";
694 663 bias-disable;
695 }; 664 };
696 }; 665 };
697 666
698 pwm_d_x11_pins 667 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 668 mux {
700 669 groups = "pwm_d_x11";
701 670 function = "pwm_d";
702 671 bias-disable;
703 }; 672 };
704 }; 673 };
705 674
706 pwm_d_x16_pins 675 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 676 mux {
708 677 groups = "pwm_d_x16";
709 678 function = "pwm_d";
710 679 bias-disable;
711 }; 680 };
712 }; 681 };
713 682
714 sdio_pins: sdi 683 sdio_pins: sdio {
715 mux-0 684 mux-0 {
716 685 groups = "sdio_d0",
717 686 "sdio_d1",
718 687 "sdio_d2",
719 688 "sdio_d3",
720 689 "sdio_cmd";
721 690 function = "sdio";
722 691 bias-pull-up;
723 }; 692 };
724 693
725 mux-1 694 mux-1 {
726 695 groups = "sdio_clk";
727 696 function = "sdio";
728 697 bias-disable;
729 }; 698 };
730 }; 699 };
731 700
732 sdio_clk_gate_ 701 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 702 mux {
734 703 groups = "GPIOX_4";
735 704 function = "gpio_periphs";
736 705 bias-pull-down;
737 }; 706 };
738 }; 707 };
739 708
740 spdif_in_z_pin 709 spdif_in_z_pins: spdif_in_z {
741 mux { 710 mux {
742 711 groups = "spdif_in_z";
743 712 function = "spdif_in";
744 713 bias-disable;
745 }; 714 };
746 }; 715 };
747 716
748 spdif_in_a1_pi 717 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 718 mux {
750 719 groups = "spdif_in_a1";
751 720 function = "spdif_in";
752 721 bias-disable;
753 }; 722 };
754 }; 723 };
755 724
756 spdif_in_a7_pi 725 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 726 mux {
758 727 groups = "spdif_in_a7";
759 728 function = "spdif_in";
760 729 bias-disable;
761 }; 730 };
762 }; 731 };
763 732
764 spdif_in_a19_p 733 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 734 mux {
766 735 groups = "spdif_in_a19";
767 736 function = "spdif_in";
768 737 bias-disable;
769 }; 738 };
770 }; 739 };
771 740
772 spdif_in_a20_p 741 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 742 mux {
774 743 groups = "spdif_in_a20";
775 744 function = "spdif_in";
776 745 bias-disable;
777 }; 746 };
778 }; 747 };
779 748
780 spdif_out_a1_p 749 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 750 mux {
782 751 groups = "spdif_out_a1";
783 752 function = "spdif_out";
784 753 bias-disable;
785 }; 754 };
786 }; 755 };
787 756
788 spdif_out_a11_ 757 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 758 mux {
790 759 groups = "spdif_out_a11";
791 760 function = "spdif_out";
792 761 bias-disable;
793 }; 762 };
794 }; 763 };
795 764
796 spdif_out_a19_ 765 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 766 mux {
798 767 groups = "spdif_out_a19";
799 768 function = "spdif_out";
800 769 bias-disable;
801 }; 770 };
802 }; 771 };
803 772
804 spdif_out_a20_ 773 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 774 mux {
806 775 groups = "spdif_out_a20";
807 776 function = "spdif_out";
808 777 bias-disable;
809 }; 778 };
810 }; 779 };
811 780
812 spdif_out_z_pi 781 spdif_out_z_pins: spdif_out_z {
813 mux { 782 mux {
814 783 groups = "spdif_out_z";
815 784 function = "spdif_out";
816 785 bias-disable;
817 }; 786 };
818 }; 787 };
819 788
820 spi0_pins: spi 789 spi0_pins: spi0 {
821 mux { 790 mux {
822 791 groups = "spi0_miso",
823 792 "spi0_mosi",
824 793 "spi0_clk";
825 794 function = "spi0";
826 795 bias-disable;
827 }; 796 };
828 }; 797 };
829 798
830 spi0_ss0_pins: 799 spi0_ss0_pins: spi0_ss0 {
831 mux { 800 mux {
832 801 groups = "spi0_ss0";
833 802 function = "spi0";
834 803 bias-disable;
835 }; 804 };
836 }; 805 };
837 806
838 spi0_ss1_pins: 807 spi0_ss1_pins: spi0_ss1 {
839 mux { 808 mux {
840 809 groups = "spi0_ss1";
841 810 function = "spi0";
842 811 bias-disable;
843 }; 812 };
844 }; 813 };
845 814
846 spi0_ss2_pins: 815 spi0_ss2_pins: spi0_ss2 {
847 mux { 816 mux {
848 817 groups = "spi0_ss2";
849 818 function = "spi0";
850 819 bias-disable;
851 }; 820 };
852 }; 821 };
853 822
854 spi1_a_pins: s 823 spi1_a_pins: spi1_a {
855 mux { 824 mux {
856 825 groups = "spi1_miso_a",
857 826 "spi1_mosi_a",
858 827 "spi1_clk_a";
859 828 function = "spi1";
860 829 bias-disable;
861 }; 830 };
862 }; 831 };
863 832
864 spi1_ss0_a_pin 833 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 834 mux {
866 835 groups = "spi1_ss0_a";
867 836 function = "spi1";
868 837 bias-disable;
869 }; 838 };
870 }; 839 };
871 840
872 spi1_ss1_pins: 841 spi1_ss1_pins: spi1_ss1 {
873 mux { 842 mux {
874 843 groups = "spi1_ss1";
875 844 function = "spi1";
876 845 bias-disable;
877 }; 846 };
878 }; 847 };
879 848
880 spi1_x_pins: s 849 spi1_x_pins: spi1_x {
881 mux { 850 mux {
882 851 groups = "spi1_miso_x",
883 852 "spi1_mosi_x",
884 853 "spi1_clk_x";
885 854 function = "spi1";
886 855 bias-disable;
887 }; 856 };
888 }; 857 };
889 858
890 spi1_ss0_x_pin 859 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 860 mux {
892 861 groups = "spi1_ss0_x";
893 862 function = "spi1";
894 863 bias-disable;
895 }; 864 };
896 }; 865 };
897 866
898 tdma_din0_pins 867 tdma_din0_pins: tdma_din0 {
899 mux { 868 mux {
900 869 groups = "tdma_din0";
901 870 function = "tdma";
902 871 bias-disable;
903 }; 872 };
904 }; 873 };
905 874
906 tdma_dout0_x14 875 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 876 mux {
908 877 groups = "tdma_dout0_x14";
909 878 function = "tdma";
910 879 bias-disable;
911 }; 880 };
912 }; 881 };
913 882
914 tdma_dout0_x15 883 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 884 mux {
916 885 groups = "tdma_dout0_x15";
917 886 function = "tdma";
918 887 bias-disable;
919 }; 888 };
920 }; 889 };
921 890
922 tdma_dout1_pin 891 tdma_dout1_pins: tdma_dout1 {
923 mux { 892 mux {
924 893 groups = "tdma_dout1";
925 894 function = "tdma";
926 895 bias-disable;
927 }; 896 };
928 }; 897 };
929 898
930 tdma_din1_pins 899 tdma_din1_pins: tdma_din1 {
931 mux { 900 mux {
932 901 groups = "tdma_din1";
933 902 function = "tdma";
934 903 bias-disable;
935 }; 904 };
936 }; 905 };
937 906
938 tdma_fs_pins: 907 tdma_fs_pins: tdma_fs {
939 mux { 908 mux {
940 909 groups = "tdma_fs";
941 910 function = "tdma";
942 911 bias-disable;
943 }; 912 };
944 }; 913 };
945 914
946 tdma_fs_slv_pi 915 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 916 mux {
948 917 groups = "tdma_fs_slv";
949 918 function = "tdma";
950 919 bias-disable;
951 }; 920 };
952 }; 921 };
953 922
954 tdma_sclk_pins 923 tdma_sclk_pins: tdma_sclk {
955 mux { 924 mux {
956 925 groups = "tdma_sclk";
957 926 function = "tdma";
958 927 bias-disable;
959 }; 928 };
960 }; 929 };
961 930
962 tdma_sclk_slv_ 931 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 932 mux {
964 933 groups = "tdma_sclk_slv";
965 934 function = "tdma";
966 935 bias-disable;
967 }; 936 };
968 }; 937 };
969 938
970 tdmb_din0_pins 939 tdmb_din0_pins: tdmb_din0 {
971 mux { 940 mux {
972 941 groups = "tdmb_din0";
973 942 function = "tdmb";
974 943 bias-disable;
975 }; 944 };
976 }; 945 };
977 946
978 tdmb_din1_pins 947 tdmb_din1_pins: tdmb_din1 {
979 mux { 948 mux {
980 949 groups = "tdmb_din1";
981 950 function = "tdmb";
982 951 bias-disable;
983 }; 952 };
984 }; 953 };
985 954
986 tdmb_din2_pins 955 tdmb_din2_pins: tdmb_din2 {
987 mux { 956 mux {
988 957 groups = "tdmb_din2";
989 958 function = "tdmb";
990 959 bias-disable;
991 }; 960 };
992 }; 961 };
993 962
994 tdmb_din3_pins 963 tdmb_din3_pins: tdmb_din3 {
995 mux { 964 mux {
996 965 groups = "tdmb_din3";
997 966 function = "tdmb";
998 967 bias-disable;
999 }; 968 };
1000 }; 969 };
1001 970
1002 tdmb_dout0_pi 971 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 972 mux {
1004 973 groups = "tdmb_dout0";
1005 974 function = "tdmb";
1006 975 bias-disable;
1007 }; 976 };
1008 }; 977 };
1009 978
1010 tdmb_dout1_pi 979 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 980 mux {
1012 981 groups = "tdmb_dout1";
1013 982 function = "tdmb";
1014 983 bias-disable;
1015 }; 984 };
1016 }; 985 };
1017 986
1018 tdmb_dout2_pi 987 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 988 mux {
1020 989 groups = "tdmb_dout2";
1021 990 function = "tdmb";
1022 991 bias-disable;
1023 }; 992 };
1024 }; 993 };
1025 994
1026 tdmb_dout3_pi 995 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 996 mux {
1028 997 groups = "tdmb_dout3";
1029 998 function = "tdmb";
1030 999 bias-disable;
1031 }; 1000 };
1032 }; 1001 };
1033 1002
1034 tdmb_fs_pins: 1003 tdmb_fs_pins: tdmb_fs {
1035 mux { 1004 mux {
1036 1005 groups = "tdmb_fs";
1037 1006 function = "tdmb";
1038 1007 bias-disable;
1039 }; 1008 };
1040 }; 1009 };
1041 1010
1042 tdmb_fs_slv_p 1011 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 1012 mux {
1044 1013 groups = "tdmb_fs_slv";
1045 1014 function = "tdmb";
1046 1015 bias-disable;
1047 }; 1016 };
1048 }; 1017 };
1049 1018
1050 tdmb_sclk_pin 1019 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 1020 mux {
1052 1021 groups = "tdmb_sclk";
1053 1022 function = "tdmb";
1054 1023 bias-disable;
1055 }; 1024 };
1056 }; 1025 };
1057 1026
1058 tdmb_sclk_slv 1027 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 1028 mux {
1060 1029 groups = "tdmb_sclk_slv";
1061 1030 function = "tdmb";
1062 1031 bias-disable;
1063 }; 1032 };
1064 }; 1033 };
1065 1034
1066 tdmc_fs_pins: 1035 tdmc_fs_pins: tdmc_fs {
1067 mux { 1036 mux {
1068 1037 groups = "tdmc_fs";
1069 1038 function = "tdmc";
1070 1039 bias-disable;
1071 }; 1040 };
1072 }; 1041 };
1073 1042
1074 tdmc_fs_slv_p 1043 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 1044 mux {
1076 1045 groups = "tdmc_fs_slv";
1077 1046 function = "tdmc";
1078 1047 bias-disable;
1079 }; 1048 };
1080 }; 1049 };
1081 1050
1082 tdmc_sclk_pin 1051 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 1052 mux {
1084 1053 groups = "tdmc_sclk";
1085 1054 function = "tdmc";
1086 1055 bias-disable;
1087 }; 1056 };
1088 }; 1057 };
1089 1058
1090 tdmc_sclk_slv 1059 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 1060 mux {
1092 1061 groups = "tdmc_sclk_slv";
1093 1062 function = "tdmc";
1094 1063 bias-disable;
1095 }; 1064 };
1096 }; 1065 };
1097 1066
1098 tdmc_din0_pin 1067 tdmc_din0_pins: tdmc_din0 {
1099 mux { 1068 mux {
1100 1069 groups = "tdmc_din0";
1101 1070 function = "tdmc";
1102 1071 bias-disable;
1103 }; 1072 };
1104 }; 1073 };
1105 1074
1106 tdmc_din1_pin 1075 tdmc_din1_pins: tdmc_din1 {
1107 mux { 1076 mux {
1108 1077 groups = "tdmc_din1";
1109 1078 function = "tdmc";
1110 1079 bias-disable;
1111 }; 1080 };
1112 }; 1081 };
1113 1082
1114 tdmc_din2_pin 1083 tdmc_din2_pins: tdmc_din2 {
1115 mux { 1084 mux {
1116 1085 groups = "tdmc_din2";
1117 1086 function = "tdmc";
1118 1087 bias-disable;
1119 }; 1088 };
1120 }; 1089 };
1121 1090
1122 tdmc_din3_pin 1091 tdmc_din3_pins: tdmc_din3 {
1123 mux { 1092 mux {
1124 1093 groups = "tdmc_din3";
1125 1094 function = "tdmc";
1126 1095 bias-disable;
1127 }; 1096 };
1128 }; 1097 };
1129 1098
1130 tdmc_dout0_pi 1099 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 1100 mux {
1132 1101 groups = "tdmc_dout0";
1133 1102 function = "tdmc";
1134 1103 bias-disable;
1135 }; 1104 };
1136 }; 1105 };
1137 1106
1138 tdmc_dout1_pi 1107 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1108 mux {
1140 1109 groups = "tdmc_dout1";
1141 1110 function = "tdmc";
1142 1111 bias-disable;
1143 }; 1112 };
1144 }; 1113 };
1145 1114
1146 tdmc_dout2_pi 1115 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1116 mux {
1148 1117 groups = "tdmc_dout2";
1149 1118 function = "tdmc";
1150 1119 bias-disable;
1151 }; 1120 };
1152 }; 1121 };
1153 1122
1154 tdmc_dout3_pi 1123 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1124 mux {
1156 1125 groups = "tdmc_dout3";
1157 1126 function = "tdmc";
1158 1127 bias-disable;
1159 }; 1128 };
1160 }; 1129 };
1161 1130
1162 uart_a_pins: 1131 uart_a_pins: uart_a {
1163 mux { 1132 mux {
1164 1133 groups = "uart_tx_a",
1165 1134 "uart_rx_a";
1166 1135 function = "uart_a";
1167 1136 bias-disable;
1168 }; 1137 };
1169 }; 1138 };
1170 1139
1171 uart_a_cts_rt 1140 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1141 mux {
1173 1142 groups = "uart_cts_a",
1174 1143 "uart_rts_a";
1175 1144 function = "uart_a";
1176 1145 bias-disable;
1177 }; 1146 };
1178 }; 1147 };
1179 1148
1180 uart_b_x_pins 1149 uart_b_x_pins: uart_b_x {
1181 mux { 1150 mux {
1182 1151 groups = "uart_tx_b_x",
1183 1152 "uart_rx_b_x";
1184 1153 function = "uart_b";
1185 1154 bias-disable;
1186 }; 1155 };
1187 }; 1156 };
1188 1157
1189 uart_b_x_cts_ 1158 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1159 mux {
1191 1160 groups = "uart_cts_b_x",
1192 1161 "uart_rts_b_x";
1193 1162 function = "uart_b";
1194 1163 bias-disable;
1195 }; 1164 };
1196 }; 1165 };
1197 1166
1198 uart_b_z_pins 1167 uart_b_z_pins: uart_b_z {
1199 mux { 1168 mux {
1200 1169 groups = "uart_tx_b_z",
1201 1170 "uart_rx_b_z";
1202 1171 function = "uart_b";
1203 1172 bias-disable;
1204 }; 1173 };
1205 }; 1174 };
1206 1175
1207 uart_b_z_cts_ 1176 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1177 mux {
1209 1178 groups = "uart_cts_b_z",
1210 1179 "uart_rts_b_z";
1211 1180 function = "uart_b";
1212 1181 bias-disable;
1213 }; 1182 };
1214 }; 1183 };
1215 1184
1216 uart_ao_b_z_p 1185 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1186 mux {
1218 1187 groups = "uart_ao_tx_b_z",
1219 1188 "uart_ao_rx_b_z";
1220 1189 function = "uart_ao_b_z";
1221 1190 bias-disable;
1222 }; 1191 };
1223 }; 1192 };
1224 1193
1225 uart_ao_b_z_c 1194 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1195 mux {
1227 1196 groups = "uart_ao_cts_b_z",
1228 1197 "uart_ao_rts_b_z";
1229 1198 function = "uart_ao_b_z";
1230 1199 bias-disable;
1231 }; 1200 };
1232 }; 1201 };
1233 }; 1202 };
1234 }; 1203 };
1235 1204
1236 hiubus: bus@ff63c000 { 1205 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1206 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1207 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1208 #address-cells = <2>;
1240 #size-cells = <2>; 1209 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1210 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1211
1243 sysctrl: system-contr 1212 sysctrl: system-controller@0 {
1244 compatible = 1213 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1214 "simple-mfd", "syscon";
1246 reg = <0 0 0 1215 reg = <0 0 0 0x400>;
1247 1216
1248 clkc: clock-c 1217 clkc: clock-controller {
1249 compa 1218 compatible = "amlogic,axg-clkc";
1250 #cloc 1219 #clock-cells = <1>;
1251 clock 1220 clocks = <&xtal>;
1252 clock 1221 clock-names = "xtal";
1253 }; 1222 };
1254 1223
1255 pwrc: power-c 1224 pwrc: power-controller {
1256 compa 1225 compatible = "amlogic,meson-axg-pwrc";
1257 #powe 1226 #power-domain-cells = <1>;
1258 amlog 1227 amlogic,ao-sysctrl = <&sysctrl_AO>;
1259 reset 1228 resets = <&reset RESET_VIU>,
1260 1229 <&reset RESET_VENC>,
1261 1230 <&reset RESET_VCBUS>,
1262 1231 <&reset RESET_VENCL>,
1263 1232 <&reset RESET_VID_LOCK>;
1264 reset 1233 reset-names = "viu", "venc", "vcbus",
1265 1234 "vencl", "vid_lock";
1266 clock 1235 clocks = <&clkc CLKID_VPU>,
1267 1236 <&clkc CLKID_VAPB>;
1268 clock 1237 clock-names = "vpu", "vapb";
1269 /* 1238 /*
1270 * VP 1239 * VPU clocking is provided by two identical clock paths
1271 * VP 1240 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1272 * fr 1241 * free mux to safely change frequency while running.
1273 * Sa 1242 * Same for VAPB but with a final gate after the glitch free mux.
1274 */ 1243 */
1275 assig 1244 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1276 1245 <&clkc CLKID_VPU_0>,
1277 1246 <&clkc CLKID_VPU>, /* Glitch free mux */
1278 1247 <&clkc CLKID_VAPB_0_SEL>,
1279 1248 <&clkc CLKID_VAPB_0>,
1280 1249 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1281 assig 1250 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1282 1251 <0>, /* Do Nothing */
1283 1252 <&clkc CLKID_VPU_0>,
1284 1253 <&clkc CLKID_FCLK_DIV4>,
1285 1254 <0>, /* Do Nothing */
1286 1255 <&clkc CLKID_VAPB_0>;
1287 assig 1256 assigned-clock-rates = <0>, /* Do Nothing */
1288 1257 <250000000>,
1289 1258 <0>, /* Do Nothing */
1290 1259 <0>, /* Do Nothing */
1291 1260 <250000000>,
1292 1261 <0>; /* Do Nothing */
1293 }; 1262 };
1294 1263
1295 mipi_pcie_ana 1264 mipi_pcie_analog_dphy: phy {
1296 compa 1265 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1297 #phy- 1266 #phy-cells = <0>;
1298 statu 1267 status = "disabled";
1299 }; 1268 };
1300 }; 1269 };
1301 }; 1270 };
1302 1271
1303 mailbox: mailbox@ff63c404 { 1272 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1273 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1274 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1275 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1276 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1277 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1278 #mbox-cells = <1>;
1310 }; 1279 };
1311 1280
1312 mipi_dphy: phy@ff640000 { 1281 mipi_dphy: phy@ff640000 {
1313 compatible = "amlogic 1282 compatible = "amlogic,axg-mipi-dphy";
1314 reg = <0x0 0xff640000 1283 reg = <0x0 0xff640000 0x0 0x100>;
1315 clocks = <&clkc CLKID 1284 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1316 clock-names = "pclk"; 1285 clock-names = "pclk";
1317 resets = <&reset RESE 1286 resets = <&reset RESET_MIPI_PHY>;
1318 reset-names = "phy"; 1287 reset-names = "phy";
1319 phys = <&mipi_pcie_an 1288 phys = <&mipi_pcie_analog_dphy>;
1320 phy-names = "analog"; 1289 phy-names = "analog";
1321 #phy-cells = <0>; 1290 #phy-cells = <0>;
1322 status = "disabled"; 1291 status = "disabled";
1323 }; 1292 };
1324 1293
1325 audio: bus@ff642000 { 1294 audio: bus@ff642000 {
1326 compatible = "simple- 1295 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1296 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1297 #address-cells = <2>;
1329 #size-cells = <2>; 1298 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1299 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1300
1332 clkc_audio: clock-con 1301 clkc_audio: clock-controller@0 {
1333 compatible = 1302 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1303 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1304 #clock-cells = <1>;
1336 1305
1337 clocks = <&cl 1306 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1307 <&clkc CLKID_MPLL0>,
1339 <&cl 1308 <&clkc CLKID_MPLL1>,
1340 <&cl 1309 <&clkc CLKID_MPLL2>,
1341 <&cl 1310 <&clkc CLKID_MPLL3>,
1342 <&cl 1311 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1312 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1313 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1314 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1315 clock-names = "pclk",
1347 1316 "mst_in0",
1348 1317 "mst_in1",
1349 1318 "mst_in2",
1350 1319 "mst_in3",
1351 1320 "mst_in4",
1352 1321 "mst_in5",
1353 1322 "mst_in6",
1354 1323 "mst_in7";
1355 1324
1356 resets = <&re 1325 resets = <&reset RESET_AUDIO>;
1357 }; 1326 };
1358 1327
1359 toddr_a: audio-contro 1328 toddr_a: audio-controller@100 {
1360 compatible = 1329 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1330 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1331 #sound-dai-cells = <0>;
1363 sound-name-pr 1332 sound-name-prefix = "TODDR_A";
1364 interrupts = 1333 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1334 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1335 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1336 amlogic,fifo-depth = <512>;
1368 status = "dis 1337 status = "disabled";
1369 }; 1338 };
1370 1339
1371 toddr_b: audio-contro 1340 toddr_b: audio-controller@140 {
1372 compatible = 1341 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1342 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1343 #sound-dai-cells = <0>;
1375 sound-name-pr 1344 sound-name-prefix = "TODDR_B";
1376 interrupts = 1345 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1346 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1347 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1348 amlogic,fifo-depth = <256>;
1380 status = "dis 1349 status = "disabled";
1381 }; 1350 };
1382 1351
1383 toddr_c: audio-contro 1352 toddr_c: audio-controller@180 {
1384 compatible = 1353 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1354 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1355 #sound-dai-cells = <0>;
1387 sound-name-pr 1356 sound-name-prefix = "TODDR_C";
1388 interrupts = 1357 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1358 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1359 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1360 amlogic,fifo-depth = <256>;
1392 status = "dis 1361 status = "disabled";
1393 }; 1362 };
1394 1363
1395 frddr_a: audio-contro 1364 frddr_a: audio-controller@1c0 {
1396 compatible = 1365 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1366 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1367 #sound-dai-cells = <0>;
1399 sound-name-pr 1368 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1369 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1370 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1371 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1372 amlogic,fifo-depth = <512>;
1404 status = "dis 1373 status = "disabled";
1405 }; 1374 };
1406 1375
1407 frddr_b: audio-contro 1376 frddr_b: audio-controller@200 {
1408 compatible = 1377 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1378 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1379 #sound-dai-cells = <0>;
1411 sound-name-pr 1380 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1381 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1382 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1383 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1384 amlogic,fifo-depth = <256>;
1416 status = "dis 1385 status = "disabled";
1417 }; 1386 };
1418 1387
1419 frddr_c: audio-contro 1388 frddr_c: audio-controller@240 {
1420 compatible = 1389 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1390 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1391 #sound-dai-cells = <0>;
1423 sound-name-pr 1392 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1393 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1394 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1395 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1396 amlogic,fifo-depth = <256>;
1428 status = "dis 1397 status = "disabled";
1429 }; 1398 };
1430 1399
1431 arb: reset-controller 1400 arb: reset-controller@280 {
1432 compatible = 1401 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1402 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1403 #reset-cells = <1>;
1435 clocks = <&cl 1404 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1405 };
1437 1406
1438 tdmin_a: audio-contro 1407 tdmin_a: audio-controller@300 {
1439 compatible = 1408 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1409 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1410 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1411 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1412 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1413 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1414 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1415 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1416 clock-names = "pclk", "sclk", "sclk_sel",
1448 1417 "lrclk", "lrclk_sel";
1449 status = "dis 1418 status = "disabled";
1450 }; 1419 };
1451 1420
1452 tdmin_b: audio-contro 1421 tdmin_b: audio-controller@340 {
1453 compatible = 1422 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1423 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1424 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1425 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1426 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1427 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1428 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1429 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1430 clock-names = "pclk", "sclk", "sclk_sel",
1462 1431 "lrclk", "lrclk_sel";
1463 status = "dis 1432 status = "disabled";
1464 }; 1433 };
1465 1434
1466 tdmin_c: audio-contro 1435 tdmin_c: audio-controller@380 {
1467 compatible = 1436 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1437 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1438 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1439 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1440 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1441 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1442 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1443 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1444 clock-names = "pclk", "sclk", "sclk_sel",
1476 1445 "lrclk", "lrclk_sel";
1477 status = "dis 1446 status = "disabled";
1478 }; 1447 };
1479 1448
1480 tdmin_lb: audio-contr 1449 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1450 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1451 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1452 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1453 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1454 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1455 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1456 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1457 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1458 clock-names = "pclk", "sclk", "sclk_sel",
1490 1459 "lrclk", "lrclk_sel";
1491 status = "dis 1460 status = "disabled";
1492 }; 1461 };
1493 1462
1494 spdifin: audio-contro 1463 spdifin: audio-controller@400 {
1495 compatible = 1464 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1465 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1466 #sound-dai-cells = <0>;
1498 sound-name-pr 1467 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1468 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1469 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1470 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1471 clock-names = "pclk", "refclk";
1503 status = "dis 1472 status = "disabled";
1504 }; 1473 };
1505 1474
1506 spdifout: audio-contr 1475 spdifout: audio-controller@480 {
1507 compatible = 1476 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1477 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1478 #sound-dai-cells = <0>;
1510 sound-name-pr 1479 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1480 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1481 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1482 clock-names = "pclk", "mclk";
1514 status = "dis 1483 status = "disabled";
1515 }; 1484 };
1516 1485
1517 tdmout_a: audio-contr 1486 tdmout_a: audio-controller@500 {
1518 compatible = 1487 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1488 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1489 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1490 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1491 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1492 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1493 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1494 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1495 clock-names = "pclk", "sclk", "sclk_sel",
1527 1496 "lrclk", "lrclk_sel";
1528 status = "dis 1497 status = "disabled";
1529 }; 1498 };
1530 1499
1531 tdmout_b: audio-contr 1500 tdmout_b: audio-controller@540 {
1532 compatible = 1501 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1502 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1503 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1504 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1505 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1506 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1507 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1508 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1509 clock-names = "pclk", "sclk", "sclk_sel",
1541 1510 "lrclk", "lrclk_sel";
1542 status = "dis 1511 status = "disabled";
1543 }; 1512 };
1544 1513
1545 tdmout_c: audio-contr 1514 tdmout_c: audio-controller@580 {
1546 compatible = 1515 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1516 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1517 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1518 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1519 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1520 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1521 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1522 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1523 clock-names = "pclk", "sclk", "sclk_sel",
1555 1524 "lrclk", "lrclk_sel";
1556 status = "dis 1525 status = "disabled";
1557 }; 1526 };
1558 }; 1527 };
1559 1528
1560 aobus: bus@ff800000 { 1529 aobus: bus@ff800000 {
1561 compatible = "simple- 1530 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1531 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1532 #address-cells = <2>;
1564 #size-cells = <2>; 1533 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1534 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1535
1567 sysctrl_AO: sys-ctrl@ 1536 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1537 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1538 reg = <0x0 0x0 0x0 0x100>;
1570 1539
1571 clkc_AO: cloc 1540 clkc_AO: clock-controller {
1572 compa 1541 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1542 #clock-cells = <1>;
1574 #rese 1543 #reset-cells = <1>;
1575 clock 1544 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1545 clock-names = "xtal", "mpeg-clk";
1577 }; 1546 };
1578 }; 1547 };
1579 1548
1580 pinctrl_aobus: pinctr 1549 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1550 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1551 #address-cells = <2>;
1583 #size-cells = 1552 #size-cells = <2>;
1584 ranges; 1553 ranges;
1585 1554
1586 gpio_ao: bank 1555 gpio_ao: bank@14 {
1587 reg = 1556 reg = <0x0 0x00014 0x0 0x8>,
1588 1557 <0x0 0x0002c 0x0 0x4>,
1589 1558 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1559 reg-names = "mux", "pull", "gpio";
1591 gpio- 1560 gpio-controller;
1592 #gpio 1561 #gpio-cells = <2>;
1593 gpio- 1562 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1563 };
1595 1564
1596 i2c_ao_sck_4_ 1565 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1566 mux {
1598 1567 groups = "i2c_ao_sck_4";
1599 1568 function = "i2c_ao";
1600 1569 bias-disable;
1601 }; 1570 };
1602 }; 1571 };
1603 1572
1604 i2c_ao_sck_8_ 1573 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1574 mux {
1606 1575 groups = "i2c_ao_sck_8";
1607 1576 function = "i2c_ao";
1608 1577 bias-disable;
1609 }; 1578 };
1610 }; 1579 };
1611 1580
1612 i2c_ao_sck_10 1581 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1582 mux {
1614 1583 groups = "i2c_ao_sck_10";
1615 1584 function = "i2c_ao";
1616 1585 bias-disable;
1617 }; 1586 };
1618 }; 1587 };
1619 1588
1620 i2c_ao_sda_5_ 1589 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1590 mux {
1622 1591 groups = "i2c_ao_sda_5";
1623 1592 function = "i2c_ao";
1624 1593 bias-disable;
1625 }; 1594 };
1626 }; 1595 };
1627 1596
1628 i2c_ao_sda_9_ 1597 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1598 mux {
1630 1599 groups = "i2c_ao_sda_9";
1631 1600 function = "i2c_ao";
1632 1601 bias-disable;
1633 }; 1602 };
1634 }; 1603 };
1635 1604
1636 i2c_ao_sda_11 1605 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1606 mux {
1638 1607 groups = "i2c_ao_sda_11";
1639 1608 function = "i2c_ao";
1640 1609 bias-disable;
1641 }; 1610 };
1642 }; 1611 };
1643 1612
1644 remote_input_ 1613 remote_input_ao_pins: remote_input_ao {
1645 mux { 1614 mux {
1646 1615 groups = "remote_input_ao";
1647 1616 function = "remote_input_ao";
1648 1617 bias-disable;
1649 }; 1618 };
1650 }; 1619 };
1651 1620
1652 uart_ao_a_pin 1621 uart_ao_a_pins: uart_ao_a {
1653 mux { 1622 mux {
1654 1623 groups = "uart_ao_tx_a",
1655 1624 "uart_ao_rx_a";
1656 1625 function = "uart_ao_a";
1657 1626 bias-disable;
1658 }; 1627 };
1659 }; 1628 };
1660 1629
1661 uart_ao_a_cts 1630 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1631 mux {
1663 1632 groups = "uart_ao_cts_a",
1664 1633 "uart_ao_rts_a";
1665 1634 function = "uart_ao_a";
1666 1635 bias-disable;
1667 }; 1636 };
1668 }; 1637 };
1669 1638
1670 uart_ao_b_pin 1639 uart_ao_b_pins: uart_ao_b {
1671 mux { 1640 mux {
1672 1641 groups = "uart_ao_tx_b",
1673 1642 "uart_ao_rx_b";
1674 1643 function = "uart_ao_b";
1675 1644 bias-disable;
1676 }; 1645 };
1677 }; 1646 };
1678 1647
1679 uart_ao_b_cts 1648 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1649 mux {
1681 1650 groups = "uart_ao_cts_b",
1682 1651 "uart_ao_rts_b";
1683 1652 function = "uart_ao_b";
1684 1653 bias-disable;
1685 }; 1654 };
1686 }; 1655 };
1687 }; 1656 };
1688 1657
1689 sec_AO: ao-secure@140 1658 sec_AO: ao-secure@140 {
1690 compatible = 1659 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1660 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1661 amlogic,has-chip-id;
1693 }; 1662 };
1694 1663
1695 pwm_AO_cd: pwm@2000 { 1664 pwm_AO_cd: pwm@2000 {
1696 compatible = 1665 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1666 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1667 #pwm-cells = <3>;
1699 status = "dis 1668 status = "disabled";
1700 }; 1669 };
1701 1670
1702 uart_AO: serial@3000 1671 uart_AO: serial@3000 {
1703 compatible = 1672 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1673 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1674 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1675 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1676 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1677 status = "disabled";
1709 }; 1678 };
1710 1679
1711 uart_AO_B: serial@400 1680 uart_AO_B: serial@4000 {
1712 compatible = 1681 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1682 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1683 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1684 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1685 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1686 status = "disabled";
1718 }; 1687 };
1719 1688
1720 i2c_AO: i2c@5000 { 1689 i2c_AO: i2c@5000 {
1721 compatible = 1690 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1691 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1692 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1693 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1694 #address-cells = <1>;
1726 #size-cells = 1695 #size-cells = <0>;
1727 status = "dis 1696 status = "disabled";
1728 }; 1697 };
1729 1698
1730 pwm_AO_ab: pwm@7000 { 1699 pwm_AO_ab: pwm@7000 {
1731 compatible = 1700 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1701 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1702 #pwm-cells = <3>;
1734 status = "dis 1703 status = "disabled";
1735 }; 1704 };
1736 1705
1737 ir: ir@8000 { 1706 ir: ir@8000 {
1738 compatible = 1707 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1708 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1709 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1710 status = "disabled";
1742 }; 1711 };
1743 1712
1744 saradc: adc@9000 { 1713 saradc: adc@9000 {
1745 compatible = 1714 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1715 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1716 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1717 #io-channel-cells = <1>;
1749 interrupts = 1718 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1719 clocks = <&xtal>,
1751 <&cl 1720 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1721 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1722 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1723 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1724 status = "disabled";
1756 }; 1725 };
1757 }; 1726 };
1758 1727
1759 ge2d: ge2d@ff940000 { 1728 ge2d: ge2d@ff940000 {
1760 compatible = "amlogic 1729 compatible = "amlogic,axg-ge2d";
1761 reg = <0x0 0xff940000 1730 reg = <0x0 0xff940000 0x0 0x10000>;
1762 interrupts = <GIC_SPI 1731 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1763 clocks = <&clkc CLKID 1732 clocks = <&clkc CLKID_VAPB>;
1764 resets = <&reset RESE 1733 resets = <&reset RESET_GE2D>;
1765 }; 1734 };
1766 1735
1767 gic: interrupt-controller@ffc 1736 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1737 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1738 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1739 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1740 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1741 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1742 interrupt-controller;
1774 interrupts = <GIC_PPI 1743 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1744 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1745 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1746 #address-cells = <0>;
1778 }; 1747 };
1779 1748
1780 cbus: bus@ffd00000 { 1749 cbus: bus@ffd00000 {
1781 compatible = "simple- 1750 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1751 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1752 #address-cells = <2>;
1784 #size-cells = <2>; 1753 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1754 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1755
1787 reset: reset-controll 1756 reset: reset-controller@1004 {
1788 compatible = 1757 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1758 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1759 #reset-cells = <1>;
1791 }; 1760 };
1792 1761
1793 gpio_intc: interrupt- 1762 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1763 compatible = "amlogic,meson-axg-gpio-intc",
1795 1764 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1765 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1766 interrupt-controller;
1798 #interrupt-ce 1767 #interrupt-cells = <2>;
1799 amlogic,chann 1768 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1769 };
1801 1770
1802 watchdog@f0d0 { 1771 watchdog@f0d0 {
1803 compatible = 1772 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1773 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1774 clocks = <&xtal>;
1806 }; 1775 };
1807 1776
1808 pwm_ab: pwm@1b000 { 1777 pwm_ab: pwm@1b000 {
1809 compatible = 1778 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1779 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1780 #pwm-cells = <3>;
1812 status = "dis 1781 status = "disabled";
1813 }; 1782 };
1814 1783
1815 pwm_cd: pwm@1a000 { 1784 pwm_cd: pwm@1a000 {
1816 compatible = 1785 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1786 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1787 #pwm-cells = <3>;
1819 status = "dis 1788 status = "disabled";
1820 }; 1789 };
1821 1790
1822 spicc0: spi@13000 { 1791 spicc0: spi@13000 {
1823 compatible = 1792 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1793 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1794 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1795 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1796 clock-names = "core";
1828 #address-cell 1797 #address-cells = <1>;
1829 #size-cells = 1798 #size-cells = <0>;
1830 status = "dis 1799 status = "disabled";
1831 }; 1800 };
1832 1801
1833 spicc1: spi@15000 { 1802 spicc1: spi@15000 {
1834 compatible = 1803 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1804 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1805 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1806 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1807 clock-names = "core";
1839 #address-cell 1808 #address-cells = <1>;
1840 #size-cells = 1809 #size-cells = <0>;
1841 status = "dis 1810 status = "disabled";
1842 }; 1811 };
1843 1812
1844 clk_msr: clock-measur 1813 clk_msr: clock-measure@18000 {
1845 compatible = 1814 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1815 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1816 };
1848 1817
1849 i2c3: i2c@1c000 { 1818 i2c3: i2c@1c000 {
1850 compatible = 1819 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1820 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1821 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1822 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1823 #address-cells = <1>;
1855 #size-cells = 1824 #size-cells = <0>;
1856 status = "dis 1825 status = "disabled";
1857 }; 1826 };
1858 1827
1859 i2c2: i2c@1d000 { 1828 i2c2: i2c@1d000 {
1860 compatible = 1829 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1830 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1831 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1832 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1833 #address-cells = <1>;
1865 #size-cells = 1834 #size-cells = <0>;
1866 status = "dis 1835 status = "disabled";
1867 }; 1836 };
1868 1837
1869 i2c1: i2c@1e000 { 1838 i2c1: i2c@1e000 {
1870 compatible = 1839 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1840 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1841 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1842 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1843 #address-cells = <1>;
1875 #size-cells = 1844 #size-cells = <0>;
1876 status = "dis 1845 status = "disabled";
1877 }; 1846 };
1878 1847
1879 i2c0: i2c@1f000 { 1848 i2c0: i2c@1f000 {
1880 compatible = 1849 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1850 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1851 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1852 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1853 #address-cells = <1>;
1885 #size-cells = 1854 #size-cells = <0>;
1886 status = "dis 1855 status = "disabled";
1887 }; 1856 };
1888 1857
1889 uart_B: serial@23000 1858 uart_B: serial@23000 {
1890 compatible = 1859 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1860 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1861 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1862 status = "disabled";
1894 clocks = <&xt 1863 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1864 clock-names = "xtal", "pclk", "baud";
1896 }; 1865 };
1897 1866
1898 uart_A: serial@24000 1867 uart_A: serial@24000 {
1899 compatible = 1868 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1869 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1870 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1871 status = "disabled";
1903 clocks = <&xt 1872 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1873 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < 1874 fifo-size = <128>;
1906 }; 1875 };
1907 }; 1876 };
1908 1877
1909 apb: bus@ffe00000 { 1878 apb: bus@ffe00000 {
1910 compatible = "simple- 1879 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1880 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1881 #address-cells = <2>;
1913 #size-cells = <2>; 1882 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1883 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1884
1916 sd_emmc_b: mmc@5000 { !! 1885 sd_emmc_b: sd@5000 {
1917 compatible = 1886 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1887 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1888 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1889 status = "disabled";
1921 clocks = <&cl 1890 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1891 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1892 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1893 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1894 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1895 };
1927 1896
1928 sd_emmc_c: mmc@7000 { 1897 sd_emmc_c: mmc@7000 {
1929 compatible = 1898 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1899 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1900 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1901 status = "disabled";
1933 clocks = <&cl 1902 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1903 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1904 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1905 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1906 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; 1907 };
1954 1908
1955 usb2_phy1: phy@9020 { 1909 usb2_phy1: phy@9020 {
1956 compatible = 1910 compatible = "amlogic,meson-gxl-usb2-phy";
1957 #phy-cells = 1911 #phy-cells = <0>;
1958 reg = <0x0 0x 1912 reg = <0x0 0x9020 0x0 0x20>;
1959 clocks = <&cl 1913 clocks = <&clkc CLKID_USB>;
1960 clock-names = 1914 clock-names = "phy";
1961 resets = <&re 1915 resets = <&reset RESET_USB_OTG>;
1962 reset-names = 1916 reset-names = "phy";
1963 }; 1917 };
1964 }; 1918 };
1965 1919
1966 sram: sram@fffc0000 { 1920 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1921 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1922 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1923 #address-cells = <1>;
1970 #size-cells = <1>; 1924 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1925 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1926
1973 cpu_scp_lpri: scp-sra 1927 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1928 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1929 reg = <0x13000 0x400>;
1976 }; 1930 };
1977 1931
1978 cpu_scp_hpri: scp-sra 1932 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1933 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1934 reg = <0x13400 0x400>;
1981 }; 1935 };
1982 }; 1936 };
1983 }; 1937 };
1984 1938
1985 timer { 1939 timer {
1986 compatible = "arm,armv8-timer 1940 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1941 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1942 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1943 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1944 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1945 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1946 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1947 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1948 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1949 };
1996 1950
1997 xtal: xtal-clk { 1951 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1952 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1953 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1954 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1955 #clock-cells = <0>;
2002 }; 1956 };
2003 }; 1957 };
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