1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; <<
132 }; 120 };
133 121
134 psci { 122 psci {
135 compatible = "arm,psci-1.0"; 123 compatible = "arm,psci-1.0";
136 method = "smc"; 124 method = "smc";
137 }; 125 };
138 126
139 reserved-memory { 127 reserved-memory {
140 #address-cells = <2>; 128 #address-cells = <2>;
141 #size-cells = <2>; 129 #size-cells = <2>;
142 ranges; 130 ranges;
143 131
144 /* 16 MiB reserved for Hardwar 132 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 133 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 134 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 135 no-map;
148 }; 136 };
149 137
150 /* Alternate 3 MiB reserved fo 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 139 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 140 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 141 no-map;
154 }; 142 };
155 }; 143 };
156 144
157 scpi { 145 scpi {
158 compatible = "arm,scpi-pre-1.0 146 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 147 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 149
162 scpi_clocks: clocks { 150 scpi_clocks: clocks {
163 compatible = "arm,scpi 151 compatible = "arm,scpi-clocks";
164 152
165 scpi_dvfs: clocks-0 { !! 153 scpi_dvfs: clock-controller {
166 compatible = " 154 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 155 #clock-cells = <1>;
168 clock-indices 156 clock-indices = <0>;
169 clock-output-n 157 clock-output-names = "vcpu";
170 }; 158 };
171 }; 159 };
172 160
173 scpi_sensors: sensors { 161 scpi_sensors: sensors {
174 compatible = "amlogic, !! 162 compatible = "amlogic,meson-gxbb-scpi-sensors";
175 #thermal-sensor-cells 163 #thermal-sensor-cells = <1>;
176 }; 164 };
177 }; 165 };
178 166
179 soc { 167 soc {
180 compatible = "simple-bus"; 168 compatible = "simple-bus";
181 #address-cells = <2>; 169 #address-cells = <2>;
182 #size-cells = <2>; 170 #size-cells = <2>;
183 ranges; 171 ranges;
184 172
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 173 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, !! 174 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
279 "snps,dwm !! 175 reg = <0x0 0xff3f0000 0x0 0x10000
280 "snps,dwm !! 176 0x0 0xff634540 0x0 0x8>;
281 reg = <0x0 0xff3f0000 <<
282 <0x0 0xff634540 <<
283 interrupts = <GIC_SPI 177 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 178 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 179 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 180 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 181 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 182 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 183 status = "disabled";
295 }; 184 };
296 185
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 186 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 187 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 188 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 189 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 190 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 191 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 192 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 193 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 194 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 195 status = "disabled";
316 }; 196 };
317 197
318 periphs: bus@ff634000 { 198 periphs: bus@ff634000 {
319 compatible = "simple-b 199 compatible = "simple-bus";
320 reg = <0x0 0xff634000 200 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 201 #address-cells = <2>;
322 #size-cells = <2>; 202 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 203 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 204
325 hwrng: rng@18 { 205 hwrng: rng@18 {
326 compatible = " 206 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 207 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 208 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 209 clock-names = "core";
330 }; 210 };
331 211
332 pinctrl_periphs: pinct 212 pinctrl_periphs: pinctrl@480 {
333 compatible = " 213 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 214 #address-cells = <2>;
335 #size-cells = 215 #size-cells = <2>;
336 ranges; 216 ranges;
337 217
338 gpio: bank@480 218 gpio: bank@480 {
339 reg = 219 reg = <0x0 0x00480 0x0 0x40>,
340 220 <0x0 0x004e8 0x0 0x14>,
341 221 <0x0 0x00520 0x0 0x14>,
342 222 <0x0 0x00430 0x0 0x3c>;
343 reg-na 223 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 224 gpio-controller;
345 #gpio- 225 #gpio-cells = <2>;
346 gpio-r 226 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 227 };
348 228
349 i2c0_pins: i2c 229 i2c0_pins: i2c0 {
350 mux { 230 mux {
351 231 groups = "i2c0_sck",
352 232 "i2c0_sda";
353 233 function = "i2c0";
354 234 bias-disable;
355 }; 235 };
356 }; 236 };
357 237
358 i2c1_x_pins: i 238 i2c1_x_pins: i2c1_x {
359 mux { 239 mux {
360 240 groups = "i2c1_sck_x",
361 241 "i2c1_sda_x";
362 242 function = "i2c1";
363 243 bias-disable;
364 }; 244 };
365 }; 245 };
366 246
367 i2c1_z_pins: i 247 i2c1_z_pins: i2c1_z {
368 mux { 248 mux {
369 249 groups = "i2c1_sck_z",
370 250 "i2c1_sda_z";
371 251 function = "i2c1";
372 252 bias-disable;
373 }; 253 };
374 }; 254 };
375 255
376 i2c2_a_pins: i 256 i2c2_a_pins: i2c2_a {
377 mux { 257 mux {
378 258 groups = "i2c2_sck_a",
379 259 "i2c2_sda_a";
380 260 function = "i2c2";
381 261 bias-disable;
382 }; 262 };
383 }; 263 };
384 264
385 i2c2_x_pins: i 265 i2c2_x_pins: i2c2_x {
386 mux { 266 mux {
387 267 groups = "i2c2_sck_x",
388 268 "i2c2_sda_x";
389 269 function = "i2c2";
390 270 bias-disable;
391 }; 271 };
392 }; 272 };
393 273
394 i2c3_a6_pins: 274 i2c3_a6_pins: i2c3_a6 {
395 mux { 275 mux {
396 276 groups = "i2c3_sda_a6",
397 277 "i2c3_sck_a7";
398 278 function = "i2c3";
399 279 bias-disable;
400 }; 280 };
401 }; 281 };
402 282
403 i2c3_a12_pins: 283 i2c3_a12_pins: i2c3_a12 {
404 mux { 284 mux {
405 285 groups = "i2c3_sda_a12",
406 286 "i2c3_sck_a13";
407 287 function = "i2c3";
408 288 bias-disable;
409 }; 289 };
410 }; 290 };
411 291
412 i2c3_a19_pins: 292 i2c3_a19_pins: i2c3_a19 {
413 mux { 293 mux {
414 294 groups = "i2c3_sda_a19",
415 295 "i2c3_sck_a20";
416 296 function = "i2c3";
417 297 bias-disable;
418 }; 298 };
419 }; 299 };
420 300
421 emmc_pins: emm 301 emmc_pins: emmc {
422 mux-0 <<
423 <<
424 <<
425 <<
426 <<
427 <<
428 <<
429 <<
430 <<
431 <<
432 <<
433 <<
434 }; <<
435 <<
436 mux-1 <<
437 <<
438 <<
439 <<
440 }; <<
441 }; <<
442 <<
443 nand_all_pins: <<
444 mux { 302 mux {
445 303 groups = "emmc_nand_d0",
446 304 "emmc_nand_d1",
447 305 "emmc_nand_d2",
448 306 "emmc_nand_d3",
449 307 "emmc_nand_d4",
450 308 "emmc_nand_d5",
451 309 "emmc_nand_d6",
452 310 "emmc_nand_d7",
453 !! 311 "emmc_clk",
454 !! 312 "emmc_cmd",
455 !! 313 "emmc_ds";
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: <<
465 mux { <<
466 <<
467 314 function = "emmc";
468 !! 315 bias-disable;
469 }; 316 };
470 }; 317 };
471 318
472 emmc_clk_gate_ 319 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 320 mux {
474 321 groups = "BOOT_8";
475 322 function = "gpio_periphs";
476 323 bias-pull-down;
477 }; 324 };
478 }; 325 };
479 326
480 eth_rgmii_x_pi 327 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 328 mux {
482 329 groups = "eth_mdio_x",
483 330 "eth_mdc_x",
484 331 "eth_rgmii_rx_clk_x",
485 332 "eth_rx_dv_x",
486 333 "eth_rxd0_x",
487 334 "eth_rxd1_x",
488 335 "eth_rxd2_rgmii",
489 336 "eth_rxd3_rgmii",
490 337 "eth_rgmii_tx_clk",
491 338 "eth_txen_x",
492 339 "eth_txd0_x",
493 340 "eth_txd1_x",
494 341 "eth_txd2_rgmii",
495 342 "eth_txd3_rgmii";
496 343 function = "eth";
497 344 bias-disable;
498 }; 345 };
499 }; 346 };
500 347
501 eth_rgmii_y_pi 348 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 349 mux {
503 350 groups = "eth_mdio_y",
504 351 "eth_mdc_y",
505 352 "eth_rgmii_rx_clk_y",
506 353 "eth_rx_dv_y",
507 354 "eth_rxd0_y",
508 355 "eth_rxd1_y",
509 356 "eth_rxd2_rgmii",
510 357 "eth_rxd3_rgmii",
511 358 "eth_rgmii_tx_clk",
512 359 "eth_txen_y",
513 360 "eth_txd0_y",
514 361 "eth_txd1_y",
515 362 "eth_txd2_rgmii",
516 363 "eth_txd3_rgmii";
517 364 function = "eth";
518 365 bias-disable;
519 }; 366 };
520 }; 367 };
521 368
522 eth_rmii_x_pin 369 eth_rmii_x_pins: eth-x-rmii {
523 mux { 370 mux {
524 371 groups = "eth_mdio_x",
525 372 "eth_mdc_x",
526 373 "eth_rgmii_rx_clk_x",
527 374 "eth_rx_dv_x",
528 375 "eth_rxd0_x",
529 376 "eth_rxd1_x",
530 377 "eth_txen_x",
531 378 "eth_txd0_x",
532 379 "eth_txd1_x";
533 380 function = "eth";
534 381 bias-disable;
535 }; 382 };
536 }; 383 };
537 384
538 eth_rmii_y_pin 385 eth_rmii_y_pins: eth-y-rmii {
539 mux { 386 mux {
540 387 groups = "eth_mdio_y",
541 388 "eth_mdc_y",
542 389 "eth_rgmii_rx_clk_y",
543 390 "eth_rx_dv_y",
544 391 "eth_rxd0_y",
545 392 "eth_rxd1_y",
546 393 "eth_txen_y",
547 394 "eth_txd0_y",
548 395 "eth_txd1_y";
549 396 function = "eth";
550 397 bias-disable;
551 }; 398 };
552 }; 399 };
553 400
554 mclk_b_pins: m 401 mclk_b_pins: mclk_b {
555 mux { 402 mux {
556 403 groups = "mclk_b";
557 404 function = "mclk_b";
558 405 bias-disable;
559 }; 406 };
560 }; 407 };
561 408
562 mclk_c_pins: m 409 mclk_c_pins: mclk_c {
563 mux { 410 mux {
564 411 groups = "mclk_c";
565 412 function = "mclk_c";
566 413 bias-disable;
567 }; 414 };
568 }; 415 };
569 416
570 pdm_dclk_a14_p 417 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 418 mux {
572 419 groups = "pdm_dclk_a14";
573 420 function = "pdm";
574 421 bias-disable;
575 }; 422 };
576 }; 423 };
577 424
578 pdm_dclk_a19_p 425 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 426 mux {
580 427 groups = "pdm_dclk_a19";
581 428 function = "pdm";
582 429 bias-disable;
583 }; 430 };
584 }; 431 };
585 432
586 pdm_din0_pins: 433 pdm_din0_pins: pdm_din0 {
587 mux { 434 mux {
588 435 groups = "pdm_din0";
589 436 function = "pdm";
590 437 bias-disable;
591 }; 438 };
592 }; 439 };
593 440
594 pdm_din1_pins: 441 pdm_din1_pins: pdm_din1 {
595 mux { 442 mux {
596 443 groups = "pdm_din1";
597 444 function = "pdm";
598 445 bias-disable;
599 }; 446 };
600 }; 447 };
601 448
602 pdm_din2_pins: 449 pdm_din2_pins: pdm_din2 {
603 mux { 450 mux {
604 451 groups = "pdm_din2";
605 452 function = "pdm";
606 453 bias-disable;
607 }; 454 };
608 }; 455 };
609 456
610 pdm_din3_pins: 457 pdm_din3_pins: pdm_din3 {
611 mux { 458 mux {
612 459 groups = "pdm_din3";
613 460 function = "pdm";
614 461 bias-disable;
615 }; 462 };
616 }; 463 };
617 464
618 pwm_a_a_pins: 465 pwm_a_a_pins: pwm_a_a {
619 mux { 466 mux {
620 467 groups = "pwm_a_a";
621 468 function = "pwm_a";
622 469 bias-disable;
623 }; 470 };
624 }; 471 };
625 472
626 pwm_a_x18_pins 473 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 474 mux {
628 475 groups = "pwm_a_x18";
629 476 function = "pwm_a";
630 477 bias-disable;
631 }; 478 };
632 }; 479 };
633 480
634 pwm_a_x20_pins 481 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 482 mux {
636 483 groups = "pwm_a_x20";
637 484 function = "pwm_a";
638 485 bias-disable;
639 }; 486 };
640 }; 487 };
641 488
642 pwm_a_z_pins: 489 pwm_a_z_pins: pwm_a_z {
643 mux { 490 mux {
644 491 groups = "pwm_a_z";
645 492 function = "pwm_a";
646 493 bias-disable;
647 }; 494 };
648 }; 495 };
649 496
650 pwm_b_a_pins: 497 pwm_b_a_pins: pwm_b_a {
651 mux { 498 mux {
652 499 groups = "pwm_b_a";
653 500 function = "pwm_b";
654 501 bias-disable;
655 }; 502 };
656 }; 503 };
657 504
658 pwm_b_x_pins: 505 pwm_b_x_pins: pwm_b_x {
659 mux { 506 mux {
660 507 groups = "pwm_b_x";
661 508 function = "pwm_b";
662 509 bias-disable;
663 }; 510 };
664 }; 511 };
665 512
666 pwm_b_z_pins: 513 pwm_b_z_pins: pwm_b_z {
667 mux { 514 mux {
668 515 groups = "pwm_b_z";
669 516 function = "pwm_b";
670 517 bias-disable;
671 }; 518 };
672 }; 519 };
673 520
674 pwm_c_a_pins: 521 pwm_c_a_pins: pwm_c_a {
675 mux { 522 mux {
676 523 groups = "pwm_c_a";
677 524 function = "pwm_c";
678 525 bias-disable;
679 }; 526 };
680 }; 527 };
681 528
682 pwm_c_x10_pins 529 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 530 mux {
684 531 groups = "pwm_c_x10";
685 532 function = "pwm_c";
686 533 bias-disable;
687 }; 534 };
688 }; 535 };
689 536
690 pwm_c_x17_pins 537 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 538 mux {
692 539 groups = "pwm_c_x17";
693 540 function = "pwm_c";
694 541 bias-disable;
695 }; 542 };
696 }; 543 };
697 544
698 pwm_d_x11_pins 545 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 546 mux {
700 547 groups = "pwm_d_x11";
701 548 function = "pwm_d";
702 549 bias-disable;
703 }; 550 };
704 }; 551 };
705 552
706 pwm_d_x16_pins 553 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 554 mux {
708 555 groups = "pwm_d_x16";
709 556 function = "pwm_d";
710 557 bias-disable;
711 }; 558 };
712 }; 559 };
713 560
714 sdio_pins: sdi 561 sdio_pins: sdio {
715 mux-0 !! 562 mux {
716 563 groups = "sdio_d0",
717 564 "sdio_d1",
718 565 "sdio_d2",
719 566 "sdio_d3",
720 !! 567 "sdio_cmd",
721 !! 568 "sdio_clk";
722 <<
723 }; <<
724 <<
725 mux-1 <<
726 <<
727 569 function = "sdio";
728 570 bias-disable;
729 }; 571 };
730 }; 572 };
731 573
732 sdio_clk_gate_ 574 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 575 mux {
734 576 groups = "GPIOX_4";
735 577 function = "gpio_periphs";
736 578 bias-pull-down;
737 }; 579 };
738 }; 580 };
739 581
740 spdif_in_z_pin 582 spdif_in_z_pins: spdif_in_z {
741 mux { 583 mux {
742 584 groups = "spdif_in_z";
743 585 function = "spdif_in";
744 586 bias-disable;
745 }; 587 };
746 }; 588 };
747 589
748 spdif_in_a1_pi 590 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 591 mux {
750 592 groups = "spdif_in_a1";
751 593 function = "spdif_in";
752 594 bias-disable;
753 }; 595 };
754 }; 596 };
755 597
756 spdif_in_a7_pi 598 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 599 mux {
758 600 groups = "spdif_in_a7";
759 601 function = "spdif_in";
760 602 bias-disable;
761 }; 603 };
762 }; 604 };
763 605
764 spdif_in_a19_p 606 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 607 mux {
766 608 groups = "spdif_in_a19";
767 609 function = "spdif_in";
768 610 bias-disable;
769 }; 611 };
770 }; 612 };
771 613
772 spdif_in_a20_p 614 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 615 mux {
774 616 groups = "spdif_in_a20";
775 617 function = "spdif_in";
776 618 bias-disable;
777 }; 619 };
778 }; 620 };
779 621
780 spdif_out_a1_p 622 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 623 mux {
782 624 groups = "spdif_out_a1";
783 625 function = "spdif_out";
784 626 bias-disable;
785 }; 627 };
786 }; 628 };
787 629
788 spdif_out_a11_ 630 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 631 mux {
790 632 groups = "spdif_out_a11";
791 633 function = "spdif_out";
792 634 bias-disable;
793 }; 635 };
794 }; 636 };
795 637
796 spdif_out_a19_ 638 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 639 mux {
798 640 groups = "spdif_out_a19";
799 641 function = "spdif_out";
800 642 bias-disable;
801 }; 643 };
802 }; 644 };
803 645
804 spdif_out_a20_ 646 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 647 mux {
806 648 groups = "spdif_out_a20";
807 649 function = "spdif_out";
808 650 bias-disable;
809 }; 651 };
810 }; 652 };
811 653
812 spdif_out_z_pi 654 spdif_out_z_pins: spdif_out_z {
813 mux { 655 mux {
814 656 groups = "spdif_out_z";
815 657 function = "spdif_out";
816 658 bias-disable;
817 }; 659 };
818 }; 660 };
819 661
820 spi0_pins: spi 662 spi0_pins: spi0 {
821 mux { 663 mux {
822 664 groups = "spi0_miso",
823 665 "spi0_mosi",
824 666 "spi0_clk";
825 667 function = "spi0";
826 668 bias-disable;
827 }; 669 };
828 }; 670 };
829 671
830 spi0_ss0_pins: 672 spi0_ss0_pins: spi0_ss0 {
831 mux { 673 mux {
832 674 groups = "spi0_ss0";
833 675 function = "spi0";
834 676 bias-disable;
835 }; 677 };
836 }; 678 };
837 679
838 spi0_ss1_pins: 680 spi0_ss1_pins: spi0_ss1 {
839 mux { 681 mux {
840 682 groups = "spi0_ss1";
841 683 function = "spi0";
842 684 bias-disable;
843 }; 685 };
844 }; 686 };
845 687
846 spi0_ss2_pins: 688 spi0_ss2_pins: spi0_ss2 {
847 mux { 689 mux {
848 690 groups = "spi0_ss2";
849 691 function = "spi0";
850 692 bias-disable;
851 }; 693 };
852 }; 694 };
853 695
854 spi1_a_pins: s 696 spi1_a_pins: spi1_a {
855 mux { 697 mux {
856 698 groups = "spi1_miso_a",
857 699 "spi1_mosi_a",
858 700 "spi1_clk_a";
859 701 function = "spi1";
860 702 bias-disable;
861 }; 703 };
862 }; 704 };
863 705
864 spi1_ss0_a_pin 706 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 707 mux {
866 708 groups = "spi1_ss0_a";
867 709 function = "spi1";
868 710 bias-disable;
869 }; 711 };
870 }; 712 };
871 713
872 spi1_ss1_pins: 714 spi1_ss1_pins: spi1_ss1 {
873 mux { 715 mux {
874 716 groups = "spi1_ss1";
875 717 function = "spi1";
876 718 bias-disable;
877 }; 719 };
878 }; 720 };
879 721
880 spi1_x_pins: s 722 spi1_x_pins: spi1_x {
881 mux { 723 mux {
882 724 groups = "spi1_miso_x",
883 725 "spi1_mosi_x",
884 726 "spi1_clk_x";
885 727 function = "spi1";
886 728 bias-disable;
887 }; 729 };
888 }; 730 };
889 731
890 spi1_ss0_x_pin 732 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 733 mux {
892 734 groups = "spi1_ss0_x";
893 735 function = "spi1";
894 736 bias-disable;
895 }; 737 };
896 }; 738 };
897 739
898 tdma_din0_pins 740 tdma_din0_pins: tdma_din0 {
899 mux { 741 mux {
900 742 groups = "tdma_din0";
901 743 function = "tdma";
902 744 bias-disable;
903 }; 745 };
904 }; 746 };
905 747
906 tdma_dout0_x14 748 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 749 mux {
908 750 groups = "tdma_dout0_x14";
909 751 function = "tdma";
910 752 bias-disable;
911 }; 753 };
912 }; 754 };
913 755
914 tdma_dout0_x15 756 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 757 mux {
916 758 groups = "tdma_dout0_x15";
917 759 function = "tdma";
918 760 bias-disable;
919 }; 761 };
920 }; 762 };
921 763
922 tdma_dout1_pin 764 tdma_dout1_pins: tdma_dout1 {
923 mux { 765 mux {
924 766 groups = "tdma_dout1";
925 767 function = "tdma";
926 768 bias-disable;
927 }; 769 };
928 }; 770 };
929 771
930 tdma_din1_pins 772 tdma_din1_pins: tdma_din1 {
931 mux { 773 mux {
932 774 groups = "tdma_din1";
933 775 function = "tdma";
934 776 bias-disable;
935 }; 777 };
936 }; 778 };
937 779
938 tdma_fs_pins: 780 tdma_fs_pins: tdma_fs {
939 mux { 781 mux {
940 782 groups = "tdma_fs";
941 783 function = "tdma";
942 784 bias-disable;
943 }; 785 };
944 }; 786 };
945 787
946 tdma_fs_slv_pi 788 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 789 mux {
948 790 groups = "tdma_fs_slv";
949 791 function = "tdma";
950 792 bias-disable;
951 }; 793 };
952 }; 794 };
953 795
954 tdma_sclk_pins 796 tdma_sclk_pins: tdma_sclk {
955 mux { 797 mux {
956 798 groups = "tdma_sclk";
957 799 function = "tdma";
958 800 bias-disable;
959 }; 801 };
960 }; 802 };
961 803
962 tdma_sclk_slv_ 804 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 805 mux {
964 806 groups = "tdma_sclk_slv";
965 807 function = "tdma";
966 808 bias-disable;
967 }; 809 };
968 }; 810 };
969 811
970 tdmb_din0_pins 812 tdmb_din0_pins: tdmb_din0 {
971 mux { 813 mux {
972 814 groups = "tdmb_din0";
973 815 function = "tdmb";
974 816 bias-disable;
975 }; 817 };
976 }; 818 };
977 819
978 tdmb_din1_pins 820 tdmb_din1_pins: tdmb_din1 {
979 mux { 821 mux {
980 822 groups = "tdmb_din1";
981 823 function = "tdmb";
982 824 bias-disable;
983 }; 825 };
984 }; 826 };
985 827
986 tdmb_din2_pins 828 tdmb_din2_pins: tdmb_din2 {
987 mux { 829 mux {
988 830 groups = "tdmb_din2";
989 831 function = "tdmb";
990 832 bias-disable;
991 }; 833 };
992 }; 834 };
993 835
994 tdmb_din3_pins 836 tdmb_din3_pins: tdmb_din3 {
995 mux { 837 mux {
996 838 groups = "tdmb_din3";
997 839 function = "tdmb";
998 840 bias-disable;
999 }; 841 };
1000 }; 842 };
1001 843
1002 tdmb_dout0_pi 844 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 845 mux {
1004 846 groups = "tdmb_dout0";
1005 847 function = "tdmb";
1006 848 bias-disable;
1007 }; 849 };
1008 }; 850 };
1009 851
1010 tdmb_dout1_pi 852 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 853 mux {
1012 854 groups = "tdmb_dout1";
1013 855 function = "tdmb";
1014 856 bias-disable;
1015 }; 857 };
1016 }; 858 };
1017 859
1018 tdmb_dout2_pi 860 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 861 mux {
1020 862 groups = "tdmb_dout2";
1021 863 function = "tdmb";
1022 864 bias-disable;
1023 }; 865 };
1024 }; 866 };
1025 867
1026 tdmb_dout3_pi 868 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 869 mux {
1028 870 groups = "tdmb_dout3";
1029 871 function = "tdmb";
1030 872 bias-disable;
1031 }; 873 };
1032 }; 874 };
1033 875
1034 tdmb_fs_pins: 876 tdmb_fs_pins: tdmb_fs {
1035 mux { 877 mux {
1036 878 groups = "tdmb_fs";
1037 879 function = "tdmb";
1038 880 bias-disable;
1039 }; 881 };
1040 }; 882 };
1041 883
1042 tdmb_fs_slv_p 884 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 885 mux {
1044 886 groups = "tdmb_fs_slv";
1045 887 function = "tdmb";
1046 888 bias-disable;
1047 }; 889 };
1048 }; 890 };
1049 891
1050 tdmb_sclk_pin 892 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 893 mux {
1052 894 groups = "tdmb_sclk";
1053 895 function = "tdmb";
1054 896 bias-disable;
1055 }; 897 };
1056 }; 898 };
1057 899
1058 tdmb_sclk_slv 900 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 901 mux {
1060 902 groups = "tdmb_sclk_slv";
1061 903 function = "tdmb";
1062 904 bias-disable;
1063 }; 905 };
1064 }; 906 };
1065 907
1066 tdmc_fs_pins: 908 tdmc_fs_pins: tdmc_fs {
1067 mux { 909 mux {
1068 910 groups = "tdmc_fs";
1069 911 function = "tdmc";
1070 912 bias-disable;
1071 }; 913 };
1072 }; 914 };
1073 915
1074 tdmc_fs_slv_p 916 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 917 mux {
1076 918 groups = "tdmc_fs_slv";
1077 919 function = "tdmc";
1078 920 bias-disable;
1079 }; 921 };
1080 }; 922 };
1081 923
1082 tdmc_sclk_pin 924 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 925 mux {
1084 926 groups = "tdmc_sclk";
1085 927 function = "tdmc";
1086 928 bias-disable;
1087 }; 929 };
1088 }; 930 };
1089 931
1090 tdmc_sclk_slv 932 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 933 mux {
1092 934 groups = "tdmc_sclk_slv";
1093 935 function = "tdmc";
1094 936 bias-disable;
1095 }; 937 };
1096 }; 938 };
1097 939
1098 tdmc_din0_pin 940 tdmc_din0_pins: tdmc_din0 {
1099 mux { 941 mux {
1100 942 groups = "tdmc_din0";
1101 943 function = "tdmc";
1102 944 bias-disable;
1103 }; 945 };
1104 }; 946 };
1105 947
1106 tdmc_din1_pin 948 tdmc_din1_pins: tdmc_din1 {
1107 mux { 949 mux {
1108 950 groups = "tdmc_din1";
1109 951 function = "tdmc";
1110 952 bias-disable;
1111 }; 953 };
1112 }; 954 };
1113 955
1114 tdmc_din2_pin 956 tdmc_din2_pins: tdmc_din2 {
1115 mux { 957 mux {
1116 958 groups = "tdmc_din2";
1117 959 function = "tdmc";
1118 960 bias-disable;
1119 }; 961 };
1120 }; 962 };
1121 963
1122 tdmc_din3_pin 964 tdmc_din3_pins: tdmc_din3 {
1123 mux { 965 mux {
1124 966 groups = "tdmc_din3";
1125 967 function = "tdmc";
1126 968 bias-disable;
1127 }; 969 };
1128 }; 970 };
1129 971
1130 tdmc_dout0_pi 972 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 973 mux {
1132 974 groups = "tdmc_dout0";
1133 975 function = "tdmc";
1134 976 bias-disable;
1135 }; 977 };
1136 }; 978 };
1137 979
1138 tdmc_dout1_pi 980 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 981 mux {
1140 982 groups = "tdmc_dout1";
1141 983 function = "tdmc";
1142 984 bias-disable;
1143 }; 985 };
1144 }; 986 };
1145 987
1146 tdmc_dout2_pi 988 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 989 mux {
1148 990 groups = "tdmc_dout2";
1149 991 function = "tdmc";
1150 992 bias-disable;
1151 }; 993 };
1152 }; 994 };
1153 995
1154 tdmc_dout3_pi 996 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 997 mux {
1156 998 groups = "tdmc_dout3";
1157 999 function = "tdmc";
1158 1000 bias-disable;
1159 }; 1001 };
1160 }; 1002 };
1161 1003
1162 uart_a_pins: 1004 uart_a_pins: uart_a {
1163 mux { 1005 mux {
1164 1006 groups = "uart_tx_a",
1165 1007 "uart_rx_a";
1166 1008 function = "uart_a";
1167 1009 bias-disable;
1168 }; 1010 };
1169 }; 1011 };
1170 1012
1171 uart_a_cts_rt 1013 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1014 mux {
1173 1015 groups = "uart_cts_a",
1174 1016 "uart_rts_a";
1175 1017 function = "uart_a";
1176 1018 bias-disable;
1177 }; 1019 };
1178 }; 1020 };
1179 1021
1180 uart_b_x_pins 1022 uart_b_x_pins: uart_b_x {
1181 mux { 1023 mux {
1182 1024 groups = "uart_tx_b_x",
1183 1025 "uart_rx_b_x";
1184 1026 function = "uart_b";
1185 1027 bias-disable;
1186 }; 1028 };
1187 }; 1029 };
1188 1030
1189 uart_b_x_cts_ 1031 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1032 mux {
1191 1033 groups = "uart_cts_b_x",
1192 1034 "uart_rts_b_x";
1193 1035 function = "uart_b";
1194 1036 bias-disable;
1195 }; 1037 };
1196 }; 1038 };
1197 1039
1198 uart_b_z_pins 1040 uart_b_z_pins: uart_b_z {
1199 mux { 1041 mux {
1200 1042 groups = "uart_tx_b_z",
1201 1043 "uart_rx_b_z";
1202 1044 function = "uart_b";
1203 1045 bias-disable;
1204 }; 1046 };
1205 }; 1047 };
1206 1048
1207 uart_b_z_cts_ 1049 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1050 mux {
1209 1051 groups = "uart_cts_b_z",
1210 1052 "uart_rts_b_z";
1211 1053 function = "uart_b";
1212 1054 bias-disable;
1213 }; 1055 };
1214 }; 1056 };
1215 1057
1216 uart_ao_b_z_p 1058 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1059 mux {
1218 1060 groups = "uart_ao_tx_b_z",
1219 1061 "uart_ao_rx_b_z";
1220 1062 function = "uart_ao_b_z";
1221 1063 bias-disable;
1222 }; 1064 };
1223 }; 1065 };
1224 1066
1225 uart_ao_b_z_c 1067 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1068 mux {
1227 1069 groups = "uart_ao_cts_b_z",
1228 1070 "uart_ao_rts_b_z";
1229 1071 function = "uart_ao_b_z";
1230 1072 bias-disable;
1231 }; 1073 };
1232 }; 1074 };
1233 }; 1075 };
1234 }; 1076 };
1235 1077
1236 hiubus: bus@ff63c000 { 1078 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1079 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1080 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1081 #address-cells = <2>;
1240 #size-cells = <2>; 1082 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1083 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1084
1243 sysctrl: system-contr 1085 sysctrl: system-controller@0 {
1244 compatible = 1086 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1087 "simple-mfd", "syscon";
1246 reg = <0 0 0 1088 reg = <0 0 0 0x400>;
1247 1089
1248 clkc: clock-c 1090 clkc: clock-controller {
1249 compa 1091 compatible = "amlogic,axg-clkc";
1250 #cloc 1092 #clock-cells = <1>;
1251 clock 1093 clocks = <&xtal>;
1252 clock 1094 clock-names = "xtal";
1253 }; 1095 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1096 };
1301 }; 1097 };
1302 1098
1303 mailbox: mailbox@ff63c404 { 1099 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic !! 1100 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1101 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1102 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1103 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1104 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1105 #mbox-cells = <1>;
1310 }; 1106 };
1311 1107
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1108 audio: bus@ff642000 {
1326 compatible = "simple- 1109 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1110 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1111 #address-cells = <2>;
1329 #size-cells = <2>; 1112 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1113 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1114
1332 clkc_audio: clock-con 1115 clkc_audio: clock-controller@0 {
1333 compatible = 1116 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1117 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1118 #clock-cells = <1>;
1336 1119
1337 clocks = <&cl 1120 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1121 <&clkc CLKID_MPLL0>,
1339 <&cl 1122 <&clkc CLKID_MPLL1>,
1340 <&cl 1123 <&clkc CLKID_MPLL2>,
1341 <&cl 1124 <&clkc CLKID_MPLL3>,
1342 <&cl 1125 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1126 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1127 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1128 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1129 clock-names = "pclk",
1347 1130 "mst_in0",
1348 1131 "mst_in1",
1349 1132 "mst_in2",
1350 1133 "mst_in3",
1351 1134 "mst_in4",
1352 1135 "mst_in5",
1353 1136 "mst_in6",
1354 1137 "mst_in7";
1355 1138
1356 resets = <&re 1139 resets = <&reset RESET_AUDIO>;
1357 }; 1140 };
1358 1141
1359 toddr_a: audio-contro 1142 toddr_a: audio-controller@100 {
1360 compatible = 1143 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x !! 1144 reg = <0x0 0x100 0x0 0x1c>;
1362 #sound-dai-ce 1145 #sound-dai-cells = <0>;
1363 sound-name-pr 1146 sound-name-prefix = "TODDR_A";
1364 interrupts = 1147 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1148 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1149 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- <<
1368 status = "dis 1150 status = "disabled";
1369 }; 1151 };
1370 1152
1371 toddr_b: audio-contro 1153 toddr_b: audio-controller@140 {
1372 compatible = 1154 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x !! 1155 reg = <0x0 0x140 0x0 0x1c>;
1374 #sound-dai-ce 1156 #sound-dai-cells = <0>;
1375 sound-name-pr 1157 sound-name-prefix = "TODDR_B";
1376 interrupts = 1158 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1159 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1160 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- <<
1380 status = "dis 1161 status = "disabled";
1381 }; 1162 };
1382 1163
1383 toddr_c: audio-contro 1164 toddr_c: audio-controller@180 {
1384 compatible = 1165 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x !! 1166 reg = <0x0 0x180 0x0 0x1c>;
1386 #sound-dai-ce 1167 #sound-dai-cells = <0>;
1387 sound-name-pr 1168 sound-name-prefix = "TODDR_C";
1388 interrupts = 1169 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1170 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1171 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- <<
1392 status = "dis 1172 status = "disabled";
1393 }; 1173 };
1394 1174
1395 frddr_a: audio-contro 1175 frddr_a: audio-controller@1c0 {
1396 compatible = 1176 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x !! 1177 reg = <0x0 0x1c0 0x0 0x1c>;
1398 #sound-dai-ce 1178 #sound-dai-cells = <0>;
1399 sound-name-pr 1179 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1180 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1181 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1182 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- <<
1404 status = "dis 1183 status = "disabled";
1405 }; 1184 };
1406 1185
1407 frddr_b: audio-contro 1186 frddr_b: audio-controller@200 {
1408 compatible = 1187 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x !! 1188 reg = <0x0 0x200 0x0 0x1c>;
1410 #sound-dai-ce 1189 #sound-dai-cells = <0>;
1411 sound-name-pr 1190 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1191 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1192 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1193 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- <<
1416 status = "dis 1194 status = "disabled";
1417 }; 1195 };
1418 1196
1419 frddr_c: audio-contro 1197 frddr_c: audio-controller@240 {
1420 compatible = 1198 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x !! 1199 reg = <0x0 0x240 0x0 0x1c>;
1422 #sound-dai-ce 1200 #sound-dai-cells = <0>;
1423 sound-name-pr 1201 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1202 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1203 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1204 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- <<
1428 status = "dis 1205 status = "disabled";
1429 }; 1206 };
1430 1207
1431 arb: reset-controller 1208 arb: reset-controller@280 {
1432 compatible = 1209 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1210 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1211 #reset-cells = <1>;
1435 clocks = <&cl 1212 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1213 };
1437 1214
1438 tdmin_a: audio-contro 1215 tdmin_a: audio-controller@300 {
1439 compatible = 1216 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1217 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1218 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1219 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1220 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1221 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1222 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1223 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1224 clock-names = "pclk", "sclk", "sclk_sel",
1448 1225 "lrclk", "lrclk_sel";
1449 status = "dis 1226 status = "disabled";
1450 }; 1227 };
1451 1228
1452 tdmin_b: audio-contro 1229 tdmin_b: audio-controller@340 {
1453 compatible = 1230 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1231 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1232 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1233 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1234 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1235 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1236 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1237 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1238 clock-names = "pclk", "sclk", "sclk_sel",
1462 1239 "lrclk", "lrclk_sel";
1463 status = "dis 1240 status = "disabled";
1464 }; 1241 };
1465 1242
1466 tdmin_c: audio-contro 1243 tdmin_c: audio-controller@380 {
1467 compatible = 1244 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1245 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1246 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1247 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1248 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1249 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1250 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1251 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1252 clock-names = "pclk", "sclk", "sclk_sel",
1476 1253 "lrclk", "lrclk_sel";
1477 status = "dis 1254 status = "disabled";
1478 }; 1255 };
1479 1256
1480 tdmin_lb: audio-contr 1257 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1258 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1259 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1260 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1261 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1262 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1263 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1264 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1265 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1266 clock-names = "pclk", "sclk", "sclk_sel",
1490 1267 "lrclk", "lrclk_sel";
1491 status = "dis 1268 status = "disabled";
1492 }; 1269 };
1493 1270
1494 spdifin: audio-contro 1271 spdifin: audio-controller@400 {
1495 compatible = 1272 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1273 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1274 #sound-dai-cells = <0>;
1498 sound-name-pr 1275 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1276 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1277 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1278 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1279 clock-names = "pclk", "refclk";
1503 status = "dis 1280 status = "disabled";
1504 }; 1281 };
1505 1282
1506 spdifout: audio-contr 1283 spdifout: audio-controller@480 {
1507 compatible = 1284 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1285 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1286 #sound-dai-cells = <0>;
1510 sound-name-pr 1287 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1288 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1289 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1290 clock-names = "pclk", "mclk";
1514 status = "dis 1291 status = "disabled";
1515 }; 1292 };
1516 1293
1517 tdmout_a: audio-contr 1294 tdmout_a: audio-controller@500 {
1518 compatible = 1295 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1296 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1297 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1298 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1299 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1300 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1301 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1302 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1303 clock-names = "pclk", "sclk", "sclk_sel",
1527 1304 "lrclk", "lrclk_sel";
1528 status = "dis 1305 status = "disabled";
1529 }; 1306 };
1530 1307
1531 tdmout_b: audio-contr 1308 tdmout_b: audio-controller@540 {
1532 compatible = 1309 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1310 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1311 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1312 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1313 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1314 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1315 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1316 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1317 clock-names = "pclk", "sclk", "sclk_sel",
1541 1318 "lrclk", "lrclk_sel";
1542 status = "dis 1319 status = "disabled";
1543 }; 1320 };
1544 1321
1545 tdmout_c: audio-contr 1322 tdmout_c: audio-controller@580 {
1546 compatible = 1323 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1324 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1325 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1326 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1327 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1328 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1329 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1330 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1331 clock-names = "pclk", "sclk", "sclk_sel",
1555 1332 "lrclk", "lrclk_sel";
1556 status = "dis 1333 status = "disabled";
1557 }; 1334 };
1558 }; 1335 };
1559 1336
1560 aobus: bus@ff800000 { 1337 aobus: bus@ff800000 {
1561 compatible = "simple- 1338 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1339 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1340 #address-cells = <2>;
1564 #size-cells = <2>; 1341 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1342 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1343
1567 sysctrl_AO: sys-ctrl@ 1344 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1345 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1346 reg = <0x0 0x0 0x0 0x100>;
1570 1347
1571 clkc_AO: cloc 1348 clkc_AO: clock-controller {
1572 compa 1349 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1350 #clock-cells = <1>;
1574 #rese 1351 #reset-cells = <1>;
1575 clock 1352 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1353 clock-names = "xtal", "mpeg-clk";
1577 }; 1354 };
1578 }; 1355 };
1579 1356
1580 pinctrl_aobus: pinctr 1357 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1358 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1359 #address-cells = <2>;
1583 #size-cells = 1360 #size-cells = <2>;
1584 ranges; 1361 ranges;
1585 1362
1586 gpio_ao: bank 1363 gpio_ao: bank@14 {
1587 reg = 1364 reg = <0x0 0x00014 0x0 0x8>,
1588 1365 <0x0 0x0002c 0x0 0x4>,
1589 1366 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1367 reg-names = "mux", "pull", "gpio";
1591 gpio- 1368 gpio-controller;
1592 #gpio 1369 #gpio-cells = <2>;
1593 gpio- 1370 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1371 };
1595 1372
1596 i2c_ao_sck_4_ 1373 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1374 mux {
1598 1375 groups = "i2c_ao_sck_4";
1599 1376 function = "i2c_ao";
1600 1377 bias-disable;
1601 }; 1378 };
1602 }; 1379 };
1603 1380
1604 i2c_ao_sck_8_ 1381 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1382 mux {
1606 1383 groups = "i2c_ao_sck_8";
1607 1384 function = "i2c_ao";
1608 1385 bias-disable;
1609 }; 1386 };
1610 }; 1387 };
1611 1388
1612 i2c_ao_sck_10 1389 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1390 mux {
1614 1391 groups = "i2c_ao_sck_10";
1615 1392 function = "i2c_ao";
1616 1393 bias-disable;
1617 }; 1394 };
1618 }; 1395 };
1619 1396
1620 i2c_ao_sda_5_ 1397 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1398 mux {
1622 1399 groups = "i2c_ao_sda_5";
1623 1400 function = "i2c_ao";
1624 1401 bias-disable;
1625 }; 1402 };
1626 }; 1403 };
1627 1404
1628 i2c_ao_sda_9_ 1405 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1406 mux {
1630 1407 groups = "i2c_ao_sda_9";
1631 1408 function = "i2c_ao";
1632 1409 bias-disable;
1633 }; 1410 };
1634 }; 1411 };
1635 1412
1636 i2c_ao_sda_11 1413 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1414 mux {
1638 1415 groups = "i2c_ao_sda_11";
1639 1416 function = "i2c_ao";
1640 1417 bias-disable;
1641 }; 1418 };
1642 }; 1419 };
1643 1420
1644 remote_input_ 1421 remote_input_ao_pins: remote_input_ao {
1645 mux { 1422 mux {
1646 1423 groups = "remote_input_ao";
1647 1424 function = "remote_input_ao";
1648 1425 bias-disable;
1649 }; 1426 };
1650 }; 1427 };
1651 1428
1652 uart_ao_a_pin 1429 uart_ao_a_pins: uart_ao_a {
1653 mux { 1430 mux {
1654 1431 groups = "uart_ao_tx_a",
1655 1432 "uart_ao_rx_a";
1656 1433 function = "uart_ao_a";
1657 1434 bias-disable;
1658 }; 1435 };
1659 }; 1436 };
1660 1437
1661 uart_ao_a_cts 1438 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1439 mux {
1663 1440 groups = "uart_ao_cts_a",
1664 1441 "uart_ao_rts_a";
1665 1442 function = "uart_ao_a";
1666 1443 bias-disable;
1667 }; 1444 };
1668 }; 1445 };
1669 1446
1670 uart_ao_b_pin 1447 uart_ao_b_pins: uart_ao_b {
1671 mux { 1448 mux {
1672 1449 groups = "uart_ao_tx_b",
1673 1450 "uart_ao_rx_b";
1674 1451 function = "uart_ao_b";
1675 1452 bias-disable;
1676 }; 1453 };
1677 }; 1454 };
1678 1455
1679 uart_ao_b_cts 1456 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1457 mux {
1681 1458 groups = "uart_ao_cts_b",
1682 1459 "uart_ao_rts_b";
1683 1460 function = "uart_ao_b";
1684 1461 bias-disable;
1685 }; 1462 };
1686 }; 1463 };
1687 }; 1464 };
1688 1465
1689 sec_AO: ao-secure@140 1466 sec_AO: ao-secure@140 {
1690 compatible = 1467 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1468 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1469 amlogic,has-chip-id;
1693 }; 1470 };
1694 1471
1695 pwm_AO_cd: pwm@2000 { 1472 pwm_AO_cd: pwm@2000 {
1696 compatible = 1473 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1474 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1475 #pwm-cells = <3>;
1699 status = "dis 1476 status = "disabled";
1700 }; 1477 };
1701 1478
1702 uart_AO: serial@3000 1479 uart_AO: serial@3000 {
1703 compatible = 1480 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1481 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1482 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1483 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1484 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1485 status = "disabled";
1709 }; 1486 };
1710 1487
1711 uart_AO_B: serial@400 1488 uart_AO_B: serial@4000 {
1712 compatible = 1489 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1490 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1491 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1492 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1493 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1494 status = "disabled";
1718 }; 1495 };
1719 1496
1720 i2c_AO: i2c@5000 { 1497 i2c_AO: i2c@5000 {
1721 compatible = 1498 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1499 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1500 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1501 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1502 #address-cells = <1>;
1726 #size-cells = 1503 #size-cells = <0>;
1727 status = "dis 1504 status = "disabled";
1728 }; 1505 };
1729 1506
1730 pwm_AO_ab: pwm@7000 { 1507 pwm_AO_ab: pwm@7000 {
1731 compatible = 1508 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1509 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1510 #pwm-cells = <3>;
1734 status = "dis 1511 status = "disabled";
1735 }; 1512 };
1736 1513
1737 ir: ir@8000 { 1514 ir: ir@8000 {
1738 compatible = 1515 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1516 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1517 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1518 status = "disabled";
1742 }; 1519 };
1743 1520
1744 saradc: adc@9000 { 1521 saradc: adc@9000 {
1745 compatible = 1522 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1523 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1524 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1525 #io-channel-cells = <1>;
1749 interrupts = 1526 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1527 clocks = <&xtal>,
1751 <&cl 1528 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1529 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1530 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1531 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1532 status = "disabled";
1756 }; 1533 };
1757 }; 1534 };
1758 1535
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1536 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1537 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1538 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1539 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1540 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1541 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1542 interrupt-controller;
1774 interrupts = <GIC_PPI 1543 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1544 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1545 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1546 #address-cells = <0>;
1778 }; 1547 };
1779 1548
1780 cbus: bus@ffd00000 { 1549 cbus: bus@ffd00000 {
1781 compatible = "simple- 1550 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1551 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1552 #address-cells = <2>;
1784 #size-cells = <2>; 1553 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1554 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1555
1787 reset: reset-controll 1556 reset: reset-controller@1004 {
1788 compatible = 1557 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1558 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1559 #reset-cells = <1>;
1791 }; 1560 };
1792 1561
1793 gpio_intc: interrupt- 1562 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1563 compatible = "amlogic,meson-axg-gpio-intc",
1795 1564 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1565 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1566 interrupt-controller;
1798 #interrupt-ce 1567 #interrupt-cells = <2>;
1799 amlogic,chann 1568 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1569 };
1801 1570
1802 watchdog@f0d0 { 1571 watchdog@f0d0 {
1803 compatible = 1572 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1573 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1574 clocks = <&xtal>;
1806 }; 1575 };
1807 1576
1808 pwm_ab: pwm@1b000 { 1577 pwm_ab: pwm@1b000 {
1809 compatible = 1578 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1579 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1580 #pwm-cells = <3>;
1812 status = "dis 1581 status = "disabled";
1813 }; 1582 };
1814 1583
1815 pwm_cd: pwm@1a000 { 1584 pwm_cd: pwm@1a000 {
1816 compatible = 1585 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1586 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1587 #pwm-cells = <3>;
1819 status = "dis 1588 status = "disabled";
1820 }; 1589 };
1821 1590
1822 spicc0: spi@13000 { 1591 spicc0: spi@13000 {
1823 compatible = 1592 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1593 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1594 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1595 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1596 clock-names = "core";
1828 #address-cell 1597 #address-cells = <1>;
1829 #size-cells = 1598 #size-cells = <0>;
1830 status = "dis 1599 status = "disabled";
1831 }; 1600 };
1832 1601
1833 spicc1: spi@15000 { 1602 spicc1: spi@15000 {
1834 compatible = 1603 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1604 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1605 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1606 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1607 clock-names = "core";
1839 #address-cell 1608 #address-cells = <1>;
1840 #size-cells = 1609 #size-cells = <0>;
1841 status = "dis 1610 status = "disabled";
1842 }; 1611 };
1843 1612
1844 clk_msr: clock-measur 1613 clk_msr: clock-measure@18000 {
1845 compatible = 1614 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1615 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1616 };
1848 1617
1849 i2c3: i2c@1c000 { 1618 i2c3: i2c@1c000 {
1850 compatible = 1619 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1620 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1621 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1622 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1623 #address-cells = <1>;
1855 #size-cells = 1624 #size-cells = <0>;
1856 status = "dis 1625 status = "disabled";
1857 }; 1626 };
1858 1627
1859 i2c2: i2c@1d000 { 1628 i2c2: i2c@1d000 {
1860 compatible = 1629 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1630 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1631 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1632 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1633 #address-cells = <1>;
1865 #size-cells = 1634 #size-cells = <0>;
1866 status = "dis 1635 status = "disabled";
1867 }; 1636 };
1868 1637
1869 i2c1: i2c@1e000 { 1638 i2c1: i2c@1e000 {
1870 compatible = 1639 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1640 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1641 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1642 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1643 #address-cells = <1>;
1875 #size-cells = 1644 #size-cells = <0>;
1876 status = "dis 1645 status = "disabled";
1877 }; 1646 };
1878 1647
1879 i2c0: i2c@1f000 { 1648 i2c0: i2c@1f000 {
1880 compatible = 1649 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1650 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1651 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1652 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1653 #address-cells = <1>;
1885 #size-cells = 1654 #size-cells = <0>;
1886 status = "dis 1655 status = "disabled";
1887 }; 1656 };
1888 1657
1889 uart_B: serial@23000 1658 uart_B: serial@23000 {
1890 compatible = 1659 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1660 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1661 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1662 status = "disabled";
1894 clocks = <&xt 1663 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1664 clock-names = "xtal", "pclk", "baud";
1896 }; 1665 };
1897 1666
1898 uart_A: serial@24000 1667 uart_A: serial@24000 {
1899 compatible = 1668 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1669 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1670 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1671 status = "disabled";
1903 clocks = <&xt 1672 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1673 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1674 };
1907 }; 1675 };
1908 1676
1909 apb: bus@ffe00000 { 1677 apb: bus@ffe00000 {
1910 compatible = "simple- 1678 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1679 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1680 #address-cells = <2>;
1913 #size-cells = <2>; 1681 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1682 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1683
1916 sd_emmc_b: mmc@5000 { !! 1684 sd_emmc_b: sd@5000 {
1917 compatible = 1685 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1686 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1687 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1688 status = "disabled";
1921 clocks = <&cl 1689 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1690 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1691 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1692 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1693 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1694 };
1927 1695
1928 sd_emmc_c: mmc@7000 { 1696 sd_emmc_c: mmc@7000 {
1929 compatible = 1697 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1698 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1699 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1700 status = "disabled";
1933 clocks = <&cl 1701 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1702 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1703 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1704 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1705 resets = <&reset RESET_SD_EMMC_C>;
1938 }; 1706 };
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; 1707 };
1965 1708
1966 sram: sram@fffc0000 { 1709 sram: sram@fffc0000 {
1967 compatible = "mmio-sr !! 1710 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1968 reg = <0x0 0xfffc0000 1711 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1712 #address-cells = <1>;
1970 #size-cells = <1>; 1713 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1714 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1715
1973 cpu_scp_lpri: scp-sra !! 1716 cpu_scp_lpri: scp-shmem@13000 {
1974 compatible = 1717 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1718 reg = <0x13000 0x400>;
1976 }; 1719 };
1977 1720
1978 cpu_scp_hpri: scp-sra !! 1721 cpu_scp_hpri: scp-shmem@13400 {
1979 compatible = 1722 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1723 reg = <0x13400 0x400>;
1981 }; 1724 };
1982 }; 1725 };
1983 }; 1726 };
1984 1727
1985 timer { 1728 timer {
1986 compatible = "arm,armv8-timer 1729 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1730 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1731 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1732 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1733 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1734 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1735 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1736 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1737 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1738 };
1996 1739
1997 xtal: xtal-clk { 1740 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1741 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1742 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1743 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1744 #clock-cells = <0>;
2002 }; 1745 };
2003 }; 1746 };
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