1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; <<
132 }; 120 };
133 121
134 psci { 122 psci {
135 compatible = "arm,psci-1.0"; 123 compatible = "arm,psci-1.0";
136 method = "smc"; 124 method = "smc";
137 }; 125 };
138 126
139 reserved-memory { 127 reserved-memory {
140 #address-cells = <2>; 128 #address-cells = <2>;
141 #size-cells = <2>; 129 #size-cells = <2>;
142 ranges; 130 ranges;
143 131
144 /* 16 MiB reserved for Hardwar 132 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 133 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 134 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 135 no-map;
148 }; 136 };
149 137
150 /* Alternate 3 MiB reserved fo 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 139 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 140 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 141 no-map;
154 }; 142 };
155 }; 143 };
156 144
157 scpi { 145 scpi {
158 compatible = "arm,scpi-pre-1.0 146 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 147 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 149
162 scpi_clocks: clocks { 150 scpi_clocks: clocks {
163 compatible = "arm,scpi 151 compatible = "arm,scpi-clocks";
164 152
165 scpi_dvfs: clocks-0 { !! 153 scpi_dvfs: clock-controller {
166 compatible = " 154 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 155 #clock-cells = <1>;
168 clock-indices 156 clock-indices = <0>;
169 clock-output-n 157 clock-output-names = "vcpu";
170 }; 158 };
171 }; 159 };
172 160
173 scpi_sensors: sensors { 161 scpi_sensors: sensors {
174 compatible = "amlogic, !! 162 compatible = "amlogic,meson-gxbb-scpi-sensors";
175 #thermal-sensor-cells 163 #thermal-sensor-cells = <1>;
176 }; 164 };
177 }; 165 };
178 166
179 soc { 167 soc {
180 compatible = "simple-bus"; 168 compatible = "simple-bus";
181 #address-cells = <2>; 169 #address-cells = <2>;
182 #size-cells = <2>; 170 #size-cells = <2>;
183 ranges; 171 ranges;
184 172
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 173 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 174 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 175 "snps,dwmac-3.70a",
280 "snps,dwm 176 "snps,dwmac";
281 reg = <0x0 0xff3f0000 !! 177 reg = <0x0 0xff3f0000 0x0 0x10000
282 <0x0 0xff634540 !! 178 0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 179 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 180 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 181 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 182 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 183 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 184 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> <<
292 tx-fifo-depth = <2048> <<
293 power-domains = <&pwrc <<
294 status = "disabled"; 185 status = "disabled";
295 }; 186 };
296 187
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 188 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 189 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 190 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 191 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 192 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 193 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 194 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 195 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 196 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 197 status = "disabled";
316 }; 198 };
317 199
318 periphs: bus@ff634000 { 200 periphs: bus@ff634000 {
319 compatible = "simple-b 201 compatible = "simple-bus";
320 reg = <0x0 0xff634000 202 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 203 #address-cells = <2>;
322 #size-cells = <2>; 204 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 205 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 206
325 hwrng: rng@18 { 207 hwrng: rng@18 {
326 compatible = " 208 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 209 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 210 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 211 clock-names = "core";
330 }; 212 };
331 213
332 pinctrl_periphs: pinct 214 pinctrl_periphs: pinctrl@480 {
333 compatible = " 215 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 216 #address-cells = <2>;
335 #size-cells = 217 #size-cells = <2>;
336 ranges; 218 ranges;
337 219
338 gpio: bank@480 220 gpio: bank@480 {
339 reg = 221 reg = <0x0 0x00480 0x0 0x40>,
340 222 <0x0 0x004e8 0x0 0x14>,
341 223 <0x0 0x00520 0x0 0x14>,
342 224 <0x0 0x00430 0x0 0x3c>;
343 reg-na 225 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 226 gpio-controller;
345 #gpio- 227 #gpio-cells = <2>;
346 gpio-r 228 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 229 };
348 230
349 i2c0_pins: i2c 231 i2c0_pins: i2c0 {
350 mux { 232 mux {
351 233 groups = "i2c0_sck",
352 234 "i2c0_sda";
353 235 function = "i2c0";
354 236 bias-disable;
355 }; 237 };
356 }; 238 };
357 239
358 i2c1_x_pins: i 240 i2c1_x_pins: i2c1_x {
359 mux { 241 mux {
360 242 groups = "i2c1_sck_x",
361 243 "i2c1_sda_x";
362 244 function = "i2c1";
363 245 bias-disable;
364 }; 246 };
365 }; 247 };
366 248
367 i2c1_z_pins: i 249 i2c1_z_pins: i2c1_z {
368 mux { 250 mux {
369 251 groups = "i2c1_sck_z",
370 252 "i2c1_sda_z";
371 253 function = "i2c1";
372 254 bias-disable;
373 }; 255 };
374 }; 256 };
375 257
376 i2c2_a_pins: i 258 i2c2_a_pins: i2c2_a {
377 mux { 259 mux {
378 260 groups = "i2c2_sck_a",
379 261 "i2c2_sda_a";
380 262 function = "i2c2";
381 263 bias-disable;
382 }; 264 };
383 }; 265 };
384 266
385 i2c2_x_pins: i 267 i2c2_x_pins: i2c2_x {
386 mux { 268 mux {
387 269 groups = "i2c2_sck_x",
388 270 "i2c2_sda_x";
389 271 function = "i2c2";
390 272 bias-disable;
391 }; 273 };
392 }; 274 };
393 275
394 i2c3_a6_pins: 276 i2c3_a6_pins: i2c3_a6 {
395 mux { 277 mux {
396 278 groups = "i2c3_sda_a6",
397 279 "i2c3_sck_a7";
398 280 function = "i2c3";
399 281 bias-disable;
400 }; 282 };
401 }; 283 };
402 284
403 i2c3_a12_pins: 285 i2c3_a12_pins: i2c3_a12 {
404 mux { 286 mux {
405 287 groups = "i2c3_sda_a12",
406 288 "i2c3_sck_a13";
407 289 function = "i2c3";
408 290 bias-disable;
409 }; 291 };
410 }; 292 };
411 293
412 i2c3_a19_pins: 294 i2c3_a19_pins: i2c3_a19 {
413 mux { 295 mux {
414 296 groups = "i2c3_sda_a19",
415 297 "i2c3_sck_a20";
416 298 function = "i2c3";
417 299 bias-disable;
418 }; 300 };
419 }; 301 };
420 302
421 emmc_pins: emm 303 emmc_pins: emmc {
422 mux-0 304 mux-0 {
423 305 groups = "emmc_nand_d0",
424 306 "emmc_nand_d1",
425 307 "emmc_nand_d2",
426 308 "emmc_nand_d3",
427 309 "emmc_nand_d4",
428 310 "emmc_nand_d5",
429 311 "emmc_nand_d6",
430 312 "emmc_nand_d7",
431 313 "emmc_cmd";
432 314 function = "emmc";
433 315 bias-pull-up;
434 }; 316 };
435 317
436 mux-1 318 mux-1 {
437 319 groups = "emmc_clk";
438 320 function = "emmc";
439 321 bias-disable;
440 }; 322 };
441 }; 323 };
442 324
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 325 emmc_ds_pins: emmc_ds {
465 mux { 326 mux {
466 327 groups = "emmc_ds";
467 328 function = "emmc";
468 329 bias-pull-down;
469 }; 330 };
470 }; 331 };
471 332
472 emmc_clk_gate_ 333 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 334 mux {
474 335 groups = "BOOT_8";
475 336 function = "gpio_periphs";
476 337 bias-pull-down;
477 }; 338 };
478 }; 339 };
479 340
480 eth_rgmii_x_pi 341 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 342 mux {
482 343 groups = "eth_mdio_x",
483 344 "eth_mdc_x",
484 345 "eth_rgmii_rx_clk_x",
485 346 "eth_rx_dv_x",
486 347 "eth_rxd0_x",
487 348 "eth_rxd1_x",
488 349 "eth_rxd2_rgmii",
489 350 "eth_rxd3_rgmii",
490 351 "eth_rgmii_tx_clk",
491 352 "eth_txen_x",
492 353 "eth_txd0_x",
493 354 "eth_txd1_x",
494 355 "eth_txd2_rgmii",
495 356 "eth_txd3_rgmii";
496 357 function = "eth";
497 358 bias-disable;
498 }; 359 };
499 }; 360 };
500 361
501 eth_rgmii_y_pi 362 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 363 mux {
503 364 groups = "eth_mdio_y",
504 365 "eth_mdc_y",
505 366 "eth_rgmii_rx_clk_y",
506 367 "eth_rx_dv_y",
507 368 "eth_rxd0_y",
508 369 "eth_rxd1_y",
509 370 "eth_rxd2_rgmii",
510 371 "eth_rxd3_rgmii",
511 372 "eth_rgmii_tx_clk",
512 373 "eth_txen_y",
513 374 "eth_txd0_y",
514 375 "eth_txd1_y",
515 376 "eth_txd2_rgmii",
516 377 "eth_txd3_rgmii";
517 378 function = "eth";
518 379 bias-disable;
519 }; 380 };
520 }; 381 };
521 382
522 eth_rmii_x_pin 383 eth_rmii_x_pins: eth-x-rmii {
523 mux { 384 mux {
524 385 groups = "eth_mdio_x",
525 386 "eth_mdc_x",
526 387 "eth_rgmii_rx_clk_x",
527 388 "eth_rx_dv_x",
528 389 "eth_rxd0_x",
529 390 "eth_rxd1_x",
530 391 "eth_txen_x",
531 392 "eth_txd0_x",
532 393 "eth_txd1_x";
533 394 function = "eth";
534 395 bias-disable;
535 }; 396 };
536 }; 397 };
537 398
538 eth_rmii_y_pin 399 eth_rmii_y_pins: eth-y-rmii {
539 mux { 400 mux {
540 401 groups = "eth_mdio_y",
541 402 "eth_mdc_y",
542 403 "eth_rgmii_rx_clk_y",
543 404 "eth_rx_dv_y",
544 405 "eth_rxd0_y",
545 406 "eth_rxd1_y",
546 407 "eth_txen_y",
547 408 "eth_txd0_y",
548 409 "eth_txd1_y";
549 410 function = "eth";
550 411 bias-disable;
551 }; 412 };
552 }; 413 };
553 414
554 mclk_b_pins: m 415 mclk_b_pins: mclk_b {
555 mux { 416 mux {
556 417 groups = "mclk_b";
557 418 function = "mclk_b";
558 419 bias-disable;
559 }; 420 };
560 }; 421 };
561 422
562 mclk_c_pins: m 423 mclk_c_pins: mclk_c {
563 mux { 424 mux {
564 425 groups = "mclk_c";
565 426 function = "mclk_c";
566 427 bias-disable;
567 }; 428 };
568 }; 429 };
569 430
570 pdm_dclk_a14_p 431 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 432 mux {
572 433 groups = "pdm_dclk_a14";
573 434 function = "pdm";
574 435 bias-disable;
575 }; 436 };
576 }; 437 };
577 438
578 pdm_dclk_a19_p 439 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 440 mux {
580 441 groups = "pdm_dclk_a19";
581 442 function = "pdm";
582 443 bias-disable;
583 }; 444 };
584 }; 445 };
585 446
586 pdm_din0_pins: 447 pdm_din0_pins: pdm_din0 {
587 mux { 448 mux {
588 449 groups = "pdm_din0";
589 450 function = "pdm";
590 451 bias-disable;
591 }; 452 };
592 }; 453 };
593 454
594 pdm_din1_pins: 455 pdm_din1_pins: pdm_din1 {
595 mux { 456 mux {
596 457 groups = "pdm_din1";
597 458 function = "pdm";
598 459 bias-disable;
599 }; 460 };
600 }; 461 };
601 462
602 pdm_din2_pins: 463 pdm_din2_pins: pdm_din2 {
603 mux { 464 mux {
604 465 groups = "pdm_din2";
605 466 function = "pdm";
606 467 bias-disable;
607 }; 468 };
608 }; 469 };
609 470
610 pdm_din3_pins: 471 pdm_din3_pins: pdm_din3 {
611 mux { 472 mux {
612 473 groups = "pdm_din3";
613 474 function = "pdm";
614 475 bias-disable;
615 }; 476 };
616 }; 477 };
617 478
618 pwm_a_a_pins: 479 pwm_a_a_pins: pwm_a_a {
619 mux { 480 mux {
620 481 groups = "pwm_a_a";
621 482 function = "pwm_a";
622 483 bias-disable;
623 }; 484 };
624 }; 485 };
625 486
626 pwm_a_x18_pins 487 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 488 mux {
628 489 groups = "pwm_a_x18";
629 490 function = "pwm_a";
630 491 bias-disable;
631 }; 492 };
632 }; 493 };
633 494
634 pwm_a_x20_pins 495 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 496 mux {
636 497 groups = "pwm_a_x20";
637 498 function = "pwm_a";
638 499 bias-disable;
639 }; 500 };
640 }; 501 };
641 502
642 pwm_a_z_pins: 503 pwm_a_z_pins: pwm_a_z {
643 mux { 504 mux {
644 505 groups = "pwm_a_z";
645 506 function = "pwm_a";
646 507 bias-disable;
647 }; 508 };
648 }; 509 };
649 510
650 pwm_b_a_pins: 511 pwm_b_a_pins: pwm_b_a {
651 mux { 512 mux {
652 513 groups = "pwm_b_a";
653 514 function = "pwm_b";
654 515 bias-disable;
655 }; 516 };
656 }; 517 };
657 518
658 pwm_b_x_pins: 519 pwm_b_x_pins: pwm_b_x {
659 mux { 520 mux {
660 521 groups = "pwm_b_x";
661 522 function = "pwm_b";
662 523 bias-disable;
663 }; 524 };
664 }; 525 };
665 526
666 pwm_b_z_pins: 527 pwm_b_z_pins: pwm_b_z {
667 mux { 528 mux {
668 529 groups = "pwm_b_z";
669 530 function = "pwm_b";
670 531 bias-disable;
671 }; 532 };
672 }; 533 };
673 534
674 pwm_c_a_pins: 535 pwm_c_a_pins: pwm_c_a {
675 mux { 536 mux {
676 537 groups = "pwm_c_a";
677 538 function = "pwm_c";
678 539 bias-disable;
679 }; 540 };
680 }; 541 };
681 542
682 pwm_c_x10_pins 543 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 544 mux {
684 545 groups = "pwm_c_x10";
685 546 function = "pwm_c";
686 547 bias-disable;
687 }; 548 };
688 }; 549 };
689 550
690 pwm_c_x17_pins 551 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 552 mux {
692 553 groups = "pwm_c_x17";
693 554 function = "pwm_c";
694 555 bias-disable;
695 }; 556 };
696 }; 557 };
697 558
698 pwm_d_x11_pins 559 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 560 mux {
700 561 groups = "pwm_d_x11";
701 562 function = "pwm_d";
702 563 bias-disable;
703 }; 564 };
704 }; 565 };
705 566
706 pwm_d_x16_pins 567 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 568 mux {
708 569 groups = "pwm_d_x16";
709 570 function = "pwm_d";
710 571 bias-disable;
711 }; 572 };
712 }; 573 };
713 574
714 sdio_pins: sdi 575 sdio_pins: sdio {
715 mux-0 576 mux-0 {
716 577 groups = "sdio_d0",
717 578 "sdio_d1",
718 579 "sdio_d2",
719 580 "sdio_d3",
720 581 "sdio_cmd";
721 582 function = "sdio";
722 583 bias-pull-up;
723 }; 584 };
724 585
725 mux-1 586 mux-1 {
726 587 groups = "sdio_clk";
727 588 function = "sdio";
728 589 bias-disable;
729 }; 590 };
730 }; 591 };
731 592
732 sdio_clk_gate_ 593 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 594 mux {
734 595 groups = "GPIOX_4";
735 596 function = "gpio_periphs";
736 597 bias-pull-down;
737 }; 598 };
738 }; 599 };
739 600
740 spdif_in_z_pin 601 spdif_in_z_pins: spdif_in_z {
741 mux { 602 mux {
742 603 groups = "spdif_in_z";
743 604 function = "spdif_in";
744 605 bias-disable;
745 }; 606 };
746 }; 607 };
747 608
748 spdif_in_a1_pi 609 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 610 mux {
750 611 groups = "spdif_in_a1";
751 612 function = "spdif_in";
752 613 bias-disable;
753 }; 614 };
754 }; 615 };
755 616
756 spdif_in_a7_pi 617 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 618 mux {
758 619 groups = "spdif_in_a7";
759 620 function = "spdif_in";
760 621 bias-disable;
761 }; 622 };
762 }; 623 };
763 624
764 spdif_in_a19_p 625 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 626 mux {
766 627 groups = "spdif_in_a19";
767 628 function = "spdif_in";
768 629 bias-disable;
769 }; 630 };
770 }; 631 };
771 632
772 spdif_in_a20_p 633 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 634 mux {
774 635 groups = "spdif_in_a20";
775 636 function = "spdif_in";
776 637 bias-disable;
777 }; 638 };
778 }; 639 };
779 640
780 spdif_out_a1_p 641 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 642 mux {
782 643 groups = "spdif_out_a1";
783 644 function = "spdif_out";
784 645 bias-disable;
785 }; 646 };
786 }; 647 };
787 648
788 spdif_out_a11_ 649 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 650 mux {
790 651 groups = "spdif_out_a11";
791 652 function = "spdif_out";
792 653 bias-disable;
793 }; 654 };
794 }; 655 };
795 656
796 spdif_out_a19_ 657 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 658 mux {
798 659 groups = "spdif_out_a19";
799 660 function = "spdif_out";
800 661 bias-disable;
801 }; 662 };
802 }; 663 };
803 664
804 spdif_out_a20_ 665 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 666 mux {
806 667 groups = "spdif_out_a20";
807 668 function = "spdif_out";
808 669 bias-disable;
809 }; 670 };
810 }; 671 };
811 672
812 spdif_out_z_pi 673 spdif_out_z_pins: spdif_out_z {
813 mux { 674 mux {
814 675 groups = "spdif_out_z";
815 676 function = "spdif_out";
816 677 bias-disable;
817 }; 678 };
818 }; 679 };
819 680
820 spi0_pins: spi 681 spi0_pins: spi0 {
821 mux { 682 mux {
822 683 groups = "spi0_miso",
823 684 "spi0_mosi",
824 685 "spi0_clk";
825 686 function = "spi0";
826 687 bias-disable;
827 }; 688 };
828 }; 689 };
829 690
830 spi0_ss0_pins: 691 spi0_ss0_pins: spi0_ss0 {
831 mux { 692 mux {
832 693 groups = "spi0_ss0";
833 694 function = "spi0";
834 695 bias-disable;
835 }; 696 };
836 }; 697 };
837 698
838 spi0_ss1_pins: 699 spi0_ss1_pins: spi0_ss1 {
839 mux { 700 mux {
840 701 groups = "spi0_ss1";
841 702 function = "spi0";
842 703 bias-disable;
843 }; 704 };
844 }; 705 };
845 706
846 spi0_ss2_pins: 707 spi0_ss2_pins: spi0_ss2 {
847 mux { 708 mux {
848 709 groups = "spi0_ss2";
849 710 function = "spi0";
850 711 bias-disable;
851 }; 712 };
852 }; 713 };
853 714
854 spi1_a_pins: s 715 spi1_a_pins: spi1_a {
855 mux { 716 mux {
856 717 groups = "spi1_miso_a",
857 718 "spi1_mosi_a",
858 719 "spi1_clk_a";
859 720 function = "spi1";
860 721 bias-disable;
861 }; 722 };
862 }; 723 };
863 724
864 spi1_ss0_a_pin 725 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 726 mux {
866 727 groups = "spi1_ss0_a";
867 728 function = "spi1";
868 729 bias-disable;
869 }; 730 };
870 }; 731 };
871 732
872 spi1_ss1_pins: 733 spi1_ss1_pins: spi1_ss1 {
873 mux { 734 mux {
874 735 groups = "spi1_ss1";
875 736 function = "spi1";
876 737 bias-disable;
877 }; 738 };
878 }; 739 };
879 740
880 spi1_x_pins: s 741 spi1_x_pins: spi1_x {
881 mux { 742 mux {
882 743 groups = "spi1_miso_x",
883 744 "spi1_mosi_x",
884 745 "spi1_clk_x";
885 746 function = "spi1";
886 747 bias-disable;
887 }; 748 };
888 }; 749 };
889 750
890 spi1_ss0_x_pin 751 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 752 mux {
892 753 groups = "spi1_ss0_x";
893 754 function = "spi1";
894 755 bias-disable;
895 }; 756 };
896 }; 757 };
897 758
898 tdma_din0_pins 759 tdma_din0_pins: tdma_din0 {
899 mux { 760 mux {
900 761 groups = "tdma_din0";
901 762 function = "tdma";
902 763 bias-disable;
903 }; 764 };
904 }; 765 };
905 766
906 tdma_dout0_x14 767 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 768 mux {
908 769 groups = "tdma_dout0_x14";
909 770 function = "tdma";
910 771 bias-disable;
911 }; 772 };
912 }; 773 };
913 774
914 tdma_dout0_x15 775 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 776 mux {
916 777 groups = "tdma_dout0_x15";
917 778 function = "tdma";
918 779 bias-disable;
919 }; 780 };
920 }; 781 };
921 782
922 tdma_dout1_pin 783 tdma_dout1_pins: tdma_dout1 {
923 mux { 784 mux {
924 785 groups = "tdma_dout1";
925 786 function = "tdma";
926 787 bias-disable;
927 }; 788 };
928 }; 789 };
929 790
930 tdma_din1_pins 791 tdma_din1_pins: tdma_din1 {
931 mux { 792 mux {
932 793 groups = "tdma_din1";
933 794 function = "tdma";
934 795 bias-disable;
935 }; 796 };
936 }; 797 };
937 798
938 tdma_fs_pins: 799 tdma_fs_pins: tdma_fs {
939 mux { 800 mux {
940 801 groups = "tdma_fs";
941 802 function = "tdma";
942 803 bias-disable;
943 }; 804 };
944 }; 805 };
945 806
946 tdma_fs_slv_pi 807 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 808 mux {
948 809 groups = "tdma_fs_slv";
949 810 function = "tdma";
950 811 bias-disable;
951 }; 812 };
952 }; 813 };
953 814
954 tdma_sclk_pins 815 tdma_sclk_pins: tdma_sclk {
955 mux { 816 mux {
956 817 groups = "tdma_sclk";
957 818 function = "tdma";
958 819 bias-disable;
959 }; 820 };
960 }; 821 };
961 822
962 tdma_sclk_slv_ 823 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 824 mux {
964 825 groups = "tdma_sclk_slv";
965 826 function = "tdma";
966 827 bias-disable;
967 }; 828 };
968 }; 829 };
969 830
970 tdmb_din0_pins 831 tdmb_din0_pins: tdmb_din0 {
971 mux { 832 mux {
972 833 groups = "tdmb_din0";
973 834 function = "tdmb";
974 835 bias-disable;
975 }; 836 };
976 }; 837 };
977 838
978 tdmb_din1_pins 839 tdmb_din1_pins: tdmb_din1 {
979 mux { 840 mux {
980 841 groups = "tdmb_din1";
981 842 function = "tdmb";
982 843 bias-disable;
983 }; 844 };
984 }; 845 };
985 846
986 tdmb_din2_pins 847 tdmb_din2_pins: tdmb_din2 {
987 mux { 848 mux {
988 849 groups = "tdmb_din2";
989 850 function = "tdmb";
990 851 bias-disable;
991 }; 852 };
992 }; 853 };
993 854
994 tdmb_din3_pins 855 tdmb_din3_pins: tdmb_din3 {
995 mux { 856 mux {
996 857 groups = "tdmb_din3";
997 858 function = "tdmb";
998 859 bias-disable;
999 }; 860 };
1000 }; 861 };
1001 862
1002 tdmb_dout0_pi 863 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 864 mux {
1004 865 groups = "tdmb_dout0";
1005 866 function = "tdmb";
1006 867 bias-disable;
1007 }; 868 };
1008 }; 869 };
1009 870
1010 tdmb_dout1_pi 871 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 872 mux {
1012 873 groups = "tdmb_dout1";
1013 874 function = "tdmb";
1014 875 bias-disable;
1015 }; 876 };
1016 }; 877 };
1017 878
1018 tdmb_dout2_pi 879 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 880 mux {
1020 881 groups = "tdmb_dout2";
1021 882 function = "tdmb";
1022 883 bias-disable;
1023 }; 884 };
1024 }; 885 };
1025 886
1026 tdmb_dout3_pi 887 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 888 mux {
1028 889 groups = "tdmb_dout3";
1029 890 function = "tdmb";
1030 891 bias-disable;
1031 }; 892 };
1032 }; 893 };
1033 894
1034 tdmb_fs_pins: 895 tdmb_fs_pins: tdmb_fs {
1035 mux { 896 mux {
1036 897 groups = "tdmb_fs";
1037 898 function = "tdmb";
1038 899 bias-disable;
1039 }; 900 };
1040 }; 901 };
1041 902
1042 tdmb_fs_slv_p 903 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 904 mux {
1044 905 groups = "tdmb_fs_slv";
1045 906 function = "tdmb";
1046 907 bias-disable;
1047 }; 908 };
1048 }; 909 };
1049 910
1050 tdmb_sclk_pin 911 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 912 mux {
1052 913 groups = "tdmb_sclk";
1053 914 function = "tdmb";
1054 915 bias-disable;
1055 }; 916 };
1056 }; 917 };
1057 918
1058 tdmb_sclk_slv 919 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 920 mux {
1060 921 groups = "tdmb_sclk_slv";
1061 922 function = "tdmb";
1062 923 bias-disable;
1063 }; 924 };
1064 }; 925 };
1065 926
1066 tdmc_fs_pins: 927 tdmc_fs_pins: tdmc_fs {
1067 mux { 928 mux {
1068 929 groups = "tdmc_fs";
1069 930 function = "tdmc";
1070 931 bias-disable;
1071 }; 932 };
1072 }; 933 };
1073 934
1074 tdmc_fs_slv_p 935 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 936 mux {
1076 937 groups = "tdmc_fs_slv";
1077 938 function = "tdmc";
1078 939 bias-disable;
1079 }; 940 };
1080 }; 941 };
1081 942
1082 tdmc_sclk_pin 943 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 944 mux {
1084 945 groups = "tdmc_sclk";
1085 946 function = "tdmc";
1086 947 bias-disable;
1087 }; 948 };
1088 }; 949 };
1089 950
1090 tdmc_sclk_slv 951 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 952 mux {
1092 953 groups = "tdmc_sclk_slv";
1093 954 function = "tdmc";
1094 955 bias-disable;
1095 }; 956 };
1096 }; 957 };
1097 958
1098 tdmc_din0_pin 959 tdmc_din0_pins: tdmc_din0 {
1099 mux { 960 mux {
1100 961 groups = "tdmc_din0";
1101 962 function = "tdmc";
1102 963 bias-disable;
1103 }; 964 };
1104 }; 965 };
1105 966
1106 tdmc_din1_pin 967 tdmc_din1_pins: tdmc_din1 {
1107 mux { 968 mux {
1108 969 groups = "tdmc_din1";
1109 970 function = "tdmc";
1110 971 bias-disable;
1111 }; 972 };
1112 }; 973 };
1113 974
1114 tdmc_din2_pin 975 tdmc_din2_pins: tdmc_din2 {
1115 mux { 976 mux {
1116 977 groups = "tdmc_din2";
1117 978 function = "tdmc";
1118 979 bias-disable;
1119 }; 980 };
1120 }; 981 };
1121 982
1122 tdmc_din3_pin 983 tdmc_din3_pins: tdmc_din3 {
1123 mux { 984 mux {
1124 985 groups = "tdmc_din3";
1125 986 function = "tdmc";
1126 987 bias-disable;
1127 }; 988 };
1128 }; 989 };
1129 990
1130 tdmc_dout0_pi 991 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 992 mux {
1132 993 groups = "tdmc_dout0";
1133 994 function = "tdmc";
1134 995 bias-disable;
1135 }; 996 };
1136 }; 997 };
1137 998
1138 tdmc_dout1_pi 999 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1000 mux {
1140 1001 groups = "tdmc_dout1";
1141 1002 function = "tdmc";
1142 1003 bias-disable;
1143 }; 1004 };
1144 }; 1005 };
1145 1006
1146 tdmc_dout2_pi 1007 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1008 mux {
1148 1009 groups = "tdmc_dout2";
1149 1010 function = "tdmc";
1150 1011 bias-disable;
1151 }; 1012 };
1152 }; 1013 };
1153 1014
1154 tdmc_dout3_pi 1015 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1016 mux {
1156 1017 groups = "tdmc_dout3";
1157 1018 function = "tdmc";
1158 1019 bias-disable;
1159 }; 1020 };
1160 }; 1021 };
1161 1022
1162 uart_a_pins: 1023 uart_a_pins: uart_a {
1163 mux { 1024 mux {
1164 1025 groups = "uart_tx_a",
1165 1026 "uart_rx_a";
1166 1027 function = "uart_a";
1167 1028 bias-disable;
1168 }; 1029 };
1169 }; 1030 };
1170 1031
1171 uart_a_cts_rt 1032 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1033 mux {
1173 1034 groups = "uart_cts_a",
1174 1035 "uart_rts_a";
1175 1036 function = "uart_a";
1176 1037 bias-disable;
1177 }; 1038 };
1178 }; 1039 };
1179 1040
1180 uart_b_x_pins 1041 uart_b_x_pins: uart_b_x {
1181 mux { 1042 mux {
1182 1043 groups = "uart_tx_b_x",
1183 1044 "uart_rx_b_x";
1184 1045 function = "uart_b";
1185 1046 bias-disable;
1186 }; 1047 };
1187 }; 1048 };
1188 1049
1189 uart_b_x_cts_ 1050 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1051 mux {
1191 1052 groups = "uart_cts_b_x",
1192 1053 "uart_rts_b_x";
1193 1054 function = "uart_b";
1194 1055 bias-disable;
1195 }; 1056 };
1196 }; 1057 };
1197 1058
1198 uart_b_z_pins 1059 uart_b_z_pins: uart_b_z {
1199 mux { 1060 mux {
1200 1061 groups = "uart_tx_b_z",
1201 1062 "uart_rx_b_z";
1202 1063 function = "uart_b";
1203 1064 bias-disable;
1204 }; 1065 };
1205 }; 1066 };
1206 1067
1207 uart_b_z_cts_ 1068 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1069 mux {
1209 1070 groups = "uart_cts_b_z",
1210 1071 "uart_rts_b_z";
1211 1072 function = "uart_b";
1212 1073 bias-disable;
1213 }; 1074 };
1214 }; 1075 };
1215 1076
1216 uart_ao_b_z_p 1077 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1078 mux {
1218 1079 groups = "uart_ao_tx_b_z",
1219 1080 "uart_ao_rx_b_z";
1220 1081 function = "uart_ao_b_z";
1221 1082 bias-disable;
1222 }; 1083 };
1223 }; 1084 };
1224 1085
1225 uart_ao_b_z_c 1086 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1087 mux {
1227 1088 groups = "uart_ao_cts_b_z",
1228 1089 "uart_ao_rts_b_z";
1229 1090 function = "uart_ao_b_z";
1230 1091 bias-disable;
1231 }; 1092 };
1232 }; 1093 };
1233 }; 1094 };
1234 }; 1095 };
1235 1096
1236 hiubus: bus@ff63c000 { 1097 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1098 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1099 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1100 #address-cells = <2>;
1240 #size-cells = <2>; 1101 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1102 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1103
1243 sysctrl: system-contr 1104 sysctrl: system-controller@0 {
1244 compatible = 1105 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1106 "simple-mfd", "syscon";
1246 reg = <0 0 0 1107 reg = <0 0 0 0x400>;
1247 1108
1248 clkc: clock-c 1109 clkc: clock-controller {
1249 compa 1110 compatible = "amlogic,axg-clkc";
1250 #cloc 1111 #clock-cells = <1>;
1251 clock 1112 clocks = <&xtal>;
1252 clock 1113 clock-names = "xtal";
1253 }; 1114 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1115 };
1301 }; 1116 };
1302 1117
1303 mailbox: mailbox@ff63c404 { 1118 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic !! 1119 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1120 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1121 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1122 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1123 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1124 #mbox-cells = <1>;
1310 }; 1125 };
1311 1126
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1127 audio: bus@ff642000 {
1326 compatible = "simple- 1128 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1129 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1130 #address-cells = <2>;
1329 #size-cells = <2>; 1131 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1132 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1133
1332 clkc_audio: clock-con 1134 clkc_audio: clock-controller@0 {
1333 compatible = 1135 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1136 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1137 #clock-cells = <1>;
1336 1138
1337 clocks = <&cl 1139 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1140 <&clkc CLKID_MPLL0>,
1339 <&cl 1141 <&clkc CLKID_MPLL1>,
1340 <&cl 1142 <&clkc CLKID_MPLL2>,
1341 <&cl 1143 <&clkc CLKID_MPLL3>,
1342 <&cl 1144 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1145 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1146 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1147 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1148 clock-names = "pclk",
1347 1149 "mst_in0",
1348 1150 "mst_in1",
1349 1151 "mst_in2",
1350 1152 "mst_in3",
1351 1153 "mst_in4",
1352 1154 "mst_in5",
1353 1155 "mst_in6",
1354 1156 "mst_in7";
1355 1157
1356 resets = <&re 1158 resets = <&reset RESET_AUDIO>;
1357 }; 1159 };
1358 1160
1359 toddr_a: audio-contro 1161 toddr_a: audio-controller@100 {
1360 compatible = 1162 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x !! 1163 reg = <0x0 0x100 0x0 0x1c>;
1362 #sound-dai-ce 1164 #sound-dai-cells = <0>;
1363 sound-name-pr 1165 sound-name-prefix = "TODDR_A";
1364 interrupts = 1166 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1167 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1168 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- <<
1368 status = "dis 1169 status = "disabled";
1369 }; 1170 };
1370 1171
1371 toddr_b: audio-contro 1172 toddr_b: audio-controller@140 {
1372 compatible = 1173 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x !! 1174 reg = <0x0 0x140 0x0 0x1c>;
1374 #sound-dai-ce 1175 #sound-dai-cells = <0>;
1375 sound-name-pr 1176 sound-name-prefix = "TODDR_B";
1376 interrupts = 1177 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1178 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1179 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- <<
1380 status = "dis 1180 status = "disabled";
1381 }; 1181 };
1382 1182
1383 toddr_c: audio-contro 1183 toddr_c: audio-controller@180 {
1384 compatible = 1184 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x !! 1185 reg = <0x0 0x180 0x0 0x1c>;
1386 #sound-dai-ce 1186 #sound-dai-cells = <0>;
1387 sound-name-pr 1187 sound-name-prefix = "TODDR_C";
1388 interrupts = 1188 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1189 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1190 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- <<
1392 status = "dis 1191 status = "disabled";
1393 }; 1192 };
1394 1193
1395 frddr_a: audio-contro 1194 frddr_a: audio-controller@1c0 {
1396 compatible = 1195 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x !! 1196 reg = <0x0 0x1c0 0x0 0x1c>;
1398 #sound-dai-ce 1197 #sound-dai-cells = <0>;
1399 sound-name-pr 1198 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1199 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1200 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1201 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- <<
1404 status = "dis 1202 status = "disabled";
1405 }; 1203 };
1406 1204
1407 frddr_b: audio-contro 1205 frddr_b: audio-controller@200 {
1408 compatible = 1206 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x !! 1207 reg = <0x0 0x200 0x0 0x1c>;
1410 #sound-dai-ce 1208 #sound-dai-cells = <0>;
1411 sound-name-pr 1209 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1210 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1211 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1212 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- <<
1416 status = "dis 1213 status = "disabled";
1417 }; 1214 };
1418 1215
1419 frddr_c: audio-contro 1216 frddr_c: audio-controller@240 {
1420 compatible = 1217 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x !! 1218 reg = <0x0 0x240 0x0 0x1c>;
1422 #sound-dai-ce 1219 #sound-dai-cells = <0>;
1423 sound-name-pr 1220 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1221 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1222 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1223 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- <<
1428 status = "dis 1224 status = "disabled";
1429 }; 1225 };
1430 1226
1431 arb: reset-controller 1227 arb: reset-controller@280 {
1432 compatible = 1228 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1229 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1230 #reset-cells = <1>;
1435 clocks = <&cl 1231 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1232 };
1437 1233
1438 tdmin_a: audio-contro 1234 tdmin_a: audio-controller@300 {
1439 compatible = 1235 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1236 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1237 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1238 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1239 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1240 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1241 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1242 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1243 clock-names = "pclk", "sclk", "sclk_sel",
1448 1244 "lrclk", "lrclk_sel";
1449 status = "dis 1245 status = "disabled";
1450 }; 1246 };
1451 1247
1452 tdmin_b: audio-contro 1248 tdmin_b: audio-controller@340 {
1453 compatible = 1249 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1250 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1251 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1252 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1253 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1254 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1255 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1256 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1257 clock-names = "pclk", "sclk", "sclk_sel",
1462 1258 "lrclk", "lrclk_sel";
1463 status = "dis 1259 status = "disabled";
1464 }; 1260 };
1465 1261
1466 tdmin_c: audio-contro 1262 tdmin_c: audio-controller@380 {
1467 compatible = 1263 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1264 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1265 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1266 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1267 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1268 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1269 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1270 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1271 clock-names = "pclk", "sclk", "sclk_sel",
1476 1272 "lrclk", "lrclk_sel";
1477 status = "dis 1273 status = "disabled";
1478 }; 1274 };
1479 1275
1480 tdmin_lb: audio-contr 1276 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1277 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1278 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1279 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1280 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1281 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1282 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1283 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1284 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1285 clock-names = "pclk", "sclk", "sclk_sel",
1490 1286 "lrclk", "lrclk_sel";
1491 status = "dis 1287 status = "disabled";
1492 }; 1288 };
1493 1289
1494 spdifin: audio-contro 1290 spdifin: audio-controller@400 {
1495 compatible = 1291 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1292 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1293 #sound-dai-cells = <0>;
1498 sound-name-pr 1294 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1295 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1296 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1297 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1298 clock-names = "pclk", "refclk";
1503 status = "dis 1299 status = "disabled";
1504 }; 1300 };
1505 1301
1506 spdifout: audio-contr 1302 spdifout: audio-controller@480 {
1507 compatible = 1303 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1304 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1305 #sound-dai-cells = <0>;
1510 sound-name-pr 1306 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1307 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1308 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1309 clock-names = "pclk", "mclk";
1514 status = "dis 1310 status = "disabled";
1515 }; 1311 };
1516 1312
1517 tdmout_a: audio-contr 1313 tdmout_a: audio-controller@500 {
1518 compatible = 1314 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1315 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1316 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1317 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1318 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1319 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1320 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1321 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1322 clock-names = "pclk", "sclk", "sclk_sel",
1527 1323 "lrclk", "lrclk_sel";
1528 status = "dis 1324 status = "disabled";
1529 }; 1325 };
1530 1326
1531 tdmout_b: audio-contr 1327 tdmout_b: audio-controller@540 {
1532 compatible = 1328 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1329 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1330 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1331 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1332 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1333 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1334 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1335 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1336 clock-names = "pclk", "sclk", "sclk_sel",
1541 1337 "lrclk", "lrclk_sel";
1542 status = "dis 1338 status = "disabled";
1543 }; 1339 };
1544 1340
1545 tdmout_c: audio-contr 1341 tdmout_c: audio-controller@580 {
1546 compatible = 1342 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1343 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1344 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1345 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1346 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1347 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1348 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1349 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1350 clock-names = "pclk", "sclk", "sclk_sel",
1555 1351 "lrclk", "lrclk_sel";
1556 status = "dis 1352 status = "disabled";
1557 }; 1353 };
1558 }; 1354 };
1559 1355
1560 aobus: bus@ff800000 { 1356 aobus: bus@ff800000 {
1561 compatible = "simple- 1357 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1358 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1359 #address-cells = <2>;
1564 #size-cells = <2>; 1360 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1361 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1362
1567 sysctrl_AO: sys-ctrl@ 1363 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1364 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1365 reg = <0x0 0x0 0x0 0x100>;
1570 1366
1571 clkc_AO: cloc 1367 clkc_AO: clock-controller {
1572 compa 1368 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1369 #clock-cells = <1>;
1574 #rese 1370 #reset-cells = <1>;
1575 clock 1371 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1372 clock-names = "xtal", "mpeg-clk";
1577 }; 1373 };
1578 }; 1374 };
1579 1375
1580 pinctrl_aobus: pinctr 1376 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1377 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1378 #address-cells = <2>;
1583 #size-cells = 1379 #size-cells = <2>;
1584 ranges; 1380 ranges;
1585 1381
1586 gpio_ao: bank 1382 gpio_ao: bank@14 {
1587 reg = 1383 reg = <0x0 0x00014 0x0 0x8>,
1588 1384 <0x0 0x0002c 0x0 0x4>,
1589 1385 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1386 reg-names = "mux", "pull", "gpio";
1591 gpio- 1387 gpio-controller;
1592 #gpio 1388 #gpio-cells = <2>;
1593 gpio- 1389 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1390 };
1595 1391
1596 i2c_ao_sck_4_ 1392 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1393 mux {
1598 1394 groups = "i2c_ao_sck_4";
1599 1395 function = "i2c_ao";
1600 1396 bias-disable;
1601 }; 1397 };
1602 }; 1398 };
1603 1399
1604 i2c_ao_sck_8_ 1400 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1401 mux {
1606 1402 groups = "i2c_ao_sck_8";
1607 1403 function = "i2c_ao";
1608 1404 bias-disable;
1609 }; 1405 };
1610 }; 1406 };
1611 1407
1612 i2c_ao_sck_10 1408 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1409 mux {
1614 1410 groups = "i2c_ao_sck_10";
1615 1411 function = "i2c_ao";
1616 1412 bias-disable;
1617 }; 1413 };
1618 }; 1414 };
1619 1415
1620 i2c_ao_sda_5_ 1416 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1417 mux {
1622 1418 groups = "i2c_ao_sda_5";
1623 1419 function = "i2c_ao";
1624 1420 bias-disable;
1625 }; 1421 };
1626 }; 1422 };
1627 1423
1628 i2c_ao_sda_9_ 1424 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1425 mux {
1630 1426 groups = "i2c_ao_sda_9";
1631 1427 function = "i2c_ao";
1632 1428 bias-disable;
1633 }; 1429 };
1634 }; 1430 };
1635 1431
1636 i2c_ao_sda_11 1432 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1433 mux {
1638 1434 groups = "i2c_ao_sda_11";
1639 1435 function = "i2c_ao";
1640 1436 bias-disable;
1641 }; 1437 };
1642 }; 1438 };
1643 1439
1644 remote_input_ 1440 remote_input_ao_pins: remote_input_ao {
1645 mux { 1441 mux {
1646 1442 groups = "remote_input_ao";
1647 1443 function = "remote_input_ao";
1648 1444 bias-disable;
1649 }; 1445 };
1650 }; 1446 };
1651 1447
1652 uart_ao_a_pin 1448 uart_ao_a_pins: uart_ao_a {
1653 mux { 1449 mux {
1654 1450 groups = "uart_ao_tx_a",
1655 1451 "uart_ao_rx_a";
1656 1452 function = "uart_ao_a";
1657 1453 bias-disable;
1658 }; 1454 };
1659 }; 1455 };
1660 1456
1661 uart_ao_a_cts 1457 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1458 mux {
1663 1459 groups = "uart_ao_cts_a",
1664 1460 "uart_ao_rts_a";
1665 1461 function = "uart_ao_a";
1666 1462 bias-disable;
1667 }; 1463 };
1668 }; 1464 };
1669 1465
1670 uart_ao_b_pin 1466 uart_ao_b_pins: uart_ao_b {
1671 mux { 1467 mux {
1672 1468 groups = "uart_ao_tx_b",
1673 1469 "uart_ao_rx_b";
1674 1470 function = "uart_ao_b";
1675 1471 bias-disable;
1676 }; 1472 };
1677 }; 1473 };
1678 1474
1679 uart_ao_b_cts 1475 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1476 mux {
1681 1477 groups = "uart_ao_cts_b",
1682 1478 "uart_ao_rts_b";
1683 1479 function = "uart_ao_b";
1684 1480 bias-disable;
1685 }; 1481 };
1686 }; 1482 };
1687 }; 1483 };
1688 1484
1689 sec_AO: ao-secure@140 1485 sec_AO: ao-secure@140 {
1690 compatible = 1486 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1487 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1488 amlogic,has-chip-id;
1693 }; 1489 };
1694 1490
1695 pwm_AO_cd: pwm@2000 { 1491 pwm_AO_cd: pwm@2000 {
1696 compatible = 1492 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1493 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1494 #pwm-cells = <3>;
1699 status = "dis 1495 status = "disabled";
1700 }; 1496 };
1701 1497
1702 uart_AO: serial@3000 1498 uart_AO: serial@3000 {
1703 compatible = 1499 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1500 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1501 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1502 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1503 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1504 status = "disabled";
1709 }; 1505 };
1710 1506
1711 uart_AO_B: serial@400 1507 uart_AO_B: serial@4000 {
1712 compatible = 1508 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1509 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1510 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1511 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1512 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1513 status = "disabled";
1718 }; 1514 };
1719 1515
1720 i2c_AO: i2c@5000 { 1516 i2c_AO: i2c@5000 {
1721 compatible = 1517 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1518 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1519 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1520 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1521 #address-cells = <1>;
1726 #size-cells = 1522 #size-cells = <0>;
1727 status = "dis 1523 status = "disabled";
1728 }; 1524 };
1729 1525
1730 pwm_AO_ab: pwm@7000 { 1526 pwm_AO_ab: pwm@7000 {
1731 compatible = 1527 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1528 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1529 #pwm-cells = <3>;
1734 status = "dis 1530 status = "disabled";
1735 }; 1531 };
1736 1532
1737 ir: ir@8000 { 1533 ir: ir@8000 {
1738 compatible = 1534 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1535 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1536 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1537 status = "disabled";
1742 }; 1538 };
1743 1539
1744 saradc: adc@9000 { 1540 saradc: adc@9000 {
1745 compatible = 1541 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1542 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1543 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1544 #io-channel-cells = <1>;
1749 interrupts = 1545 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1546 clocks = <&xtal>,
1751 <&cl 1547 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1548 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1549 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1550 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1551 status = "disabled";
1756 }; 1552 };
1757 }; 1553 };
1758 1554
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1555 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1556 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1557 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1558 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1559 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1560 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1561 interrupt-controller;
1774 interrupts = <GIC_PPI 1562 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1563 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1564 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1565 #address-cells = <0>;
1778 }; 1566 };
1779 1567
1780 cbus: bus@ffd00000 { 1568 cbus: bus@ffd00000 {
1781 compatible = "simple- 1569 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1570 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1571 #address-cells = <2>;
1784 #size-cells = <2>; 1572 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1573 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1574
1787 reset: reset-controll 1575 reset: reset-controller@1004 {
1788 compatible = 1576 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1577 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1578 #reset-cells = <1>;
1791 }; 1579 };
1792 1580
1793 gpio_intc: interrupt- 1581 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1582 compatible = "amlogic,meson-axg-gpio-intc",
1795 1583 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1584 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1585 interrupt-controller;
1798 #interrupt-ce 1586 #interrupt-cells = <2>;
1799 amlogic,chann 1587 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1588 };
1801 1589
1802 watchdog@f0d0 { 1590 watchdog@f0d0 {
1803 compatible = 1591 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1592 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1593 clocks = <&xtal>;
1806 }; 1594 };
1807 1595
1808 pwm_ab: pwm@1b000 { 1596 pwm_ab: pwm@1b000 {
1809 compatible = 1597 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1598 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1599 #pwm-cells = <3>;
1812 status = "dis 1600 status = "disabled";
1813 }; 1601 };
1814 1602
1815 pwm_cd: pwm@1a000 { 1603 pwm_cd: pwm@1a000 {
1816 compatible = 1604 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1605 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1606 #pwm-cells = <3>;
1819 status = "dis 1607 status = "disabled";
1820 }; 1608 };
1821 1609
1822 spicc0: spi@13000 { 1610 spicc0: spi@13000 {
1823 compatible = 1611 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1612 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1613 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1614 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1615 clock-names = "core";
1828 #address-cell 1616 #address-cells = <1>;
1829 #size-cells = 1617 #size-cells = <0>;
1830 status = "dis 1618 status = "disabled";
1831 }; 1619 };
1832 1620
1833 spicc1: spi@15000 { 1621 spicc1: spi@15000 {
1834 compatible = 1622 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1623 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1625 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1626 clock-names = "core";
1839 #address-cell 1627 #address-cells = <1>;
1840 #size-cells = 1628 #size-cells = <0>;
1841 status = "dis 1629 status = "disabled";
1842 }; 1630 };
1843 1631
1844 clk_msr: clock-measur 1632 clk_msr: clock-measure@18000 {
1845 compatible = 1633 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1634 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1635 };
1848 1636
1849 i2c3: i2c@1c000 { 1637 i2c3: i2c@1c000 {
1850 compatible = 1638 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1639 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1640 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1641 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1642 #address-cells = <1>;
1855 #size-cells = 1643 #size-cells = <0>;
1856 status = "dis 1644 status = "disabled";
1857 }; 1645 };
1858 1646
1859 i2c2: i2c@1d000 { 1647 i2c2: i2c@1d000 {
1860 compatible = 1648 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1649 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1650 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1651 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1652 #address-cells = <1>;
1865 #size-cells = 1653 #size-cells = <0>;
1866 status = "dis 1654 status = "disabled";
1867 }; 1655 };
1868 1656
1869 i2c1: i2c@1e000 { 1657 i2c1: i2c@1e000 {
1870 compatible = 1658 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1659 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1660 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1661 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1662 #address-cells = <1>;
1875 #size-cells = 1663 #size-cells = <0>;
1876 status = "dis 1664 status = "disabled";
1877 }; 1665 };
1878 1666
1879 i2c0: i2c@1f000 { 1667 i2c0: i2c@1f000 {
1880 compatible = 1668 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1669 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1670 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1671 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1672 #address-cells = <1>;
1885 #size-cells = 1673 #size-cells = <0>;
1886 status = "dis 1674 status = "disabled";
1887 }; 1675 };
1888 1676
1889 uart_B: serial@23000 1677 uart_B: serial@23000 {
1890 compatible = 1678 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1679 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1680 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1681 status = "disabled";
1894 clocks = <&xt 1682 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1683 clock-names = "xtal", "pclk", "baud";
1896 }; 1684 };
1897 1685
1898 uart_A: serial@24000 1686 uart_A: serial@24000 {
1899 compatible = 1687 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1688 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1689 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1690 status = "disabled";
1903 clocks = <&xt 1691 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1692 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1693 };
1907 }; 1694 };
1908 1695
1909 apb: bus@ffe00000 { 1696 apb: bus@ffe00000 {
1910 compatible = "simple- 1697 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1698 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1699 #address-cells = <2>;
1913 #size-cells = <2>; 1700 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1701 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1702
1916 sd_emmc_b: mmc@5000 { !! 1703 sd_emmc_b: sd@5000 {
1917 compatible = 1704 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1705 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1706 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1707 status = "disabled";
1921 clocks = <&cl 1708 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1709 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1710 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1711 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1712 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1713 };
1927 1714
1928 sd_emmc_c: mmc@7000 { 1715 sd_emmc_c: mmc@7000 {
1929 compatible = 1716 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1717 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1718 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1719 status = "disabled";
1933 clocks = <&cl 1720 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1721 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1722 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1723 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1724 resets = <&reset RESET_SD_EMMC_C>;
1938 }; 1725 };
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; <<
1964 }; 1726 };
1965 1727
1966 sram: sram@fffc0000 { 1728 sram: sram@fffc0000 {
1967 compatible = "mmio-sr !! 1729 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1968 reg = <0x0 0xfffc0000 1730 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1731 #address-cells = <1>;
1970 #size-cells = <1>; 1732 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1733 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1734
1973 cpu_scp_lpri: scp-sra !! 1735 cpu_scp_lpri: scp-shmem@13000 {
1974 compatible = 1736 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1737 reg = <0x13000 0x400>;
1976 }; 1738 };
1977 1739
1978 cpu_scp_hpri: scp-sra !! 1740 cpu_scp_hpri: scp-shmem@13400 {
1979 compatible = 1741 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1742 reg = <0x13400 0x400>;
1981 }; 1743 };
1982 }; 1744 };
1983 }; 1745 };
1984 1746
1985 timer { 1747 timer {
1986 compatible = "arm,armv8-timer 1748 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1749 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1750 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1751 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1752 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1753 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1754 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1755 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1756 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1757 };
1996 1758
1997 xtal: xtal-clk { 1759 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1760 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1761 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1762 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1763 #clock-cells = <0>;
2002 }; 1764 };
2003 }; 1765 };
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