1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; <<
132 }; 120 };
133 121
134 psci { 122 psci {
135 compatible = "arm,psci-1.0"; 123 compatible = "arm,psci-1.0";
136 method = "smc"; 124 method = "smc";
137 }; 125 };
138 126
139 reserved-memory { 127 reserved-memory {
140 #address-cells = <2>; 128 #address-cells = <2>;
141 #size-cells = <2>; 129 #size-cells = <2>;
142 ranges; 130 ranges;
143 131
144 /* 16 MiB reserved for Hardwar 132 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 133 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 134 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 135 no-map;
148 }; 136 };
149 137
150 /* Alternate 3 MiB reserved fo 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 139 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 140 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 141 no-map;
154 }; 142 };
155 }; 143 };
156 144
157 scpi { 145 scpi {
158 compatible = "arm,scpi-pre-1.0 146 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 147 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 149
162 scpi_clocks: clocks { 150 scpi_clocks: clocks {
163 compatible = "arm,scpi 151 compatible = "arm,scpi-clocks";
164 152
165 scpi_dvfs: clocks-0 { 153 scpi_dvfs: clocks-0 {
166 compatible = " 154 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 155 #clock-cells = <1>;
168 clock-indices 156 clock-indices = <0>;
169 clock-output-n 157 clock-output-names = "vcpu";
170 }; 158 };
171 }; 159 };
172 160
173 scpi_sensors: sensors { 161 scpi_sensors: sensors {
174 compatible = "amlogic, 162 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 163 #thermal-sensor-cells = <1>;
176 }; 164 };
177 }; 165 };
178 166
179 soc { 167 soc {
180 compatible = "simple-bus"; 168 compatible = "simple-bus";
181 #address-cells = <2>; 169 #address-cells = <2>;
182 #size-cells = <2>; 170 #size-cells = <2>;
183 ranges; 171 ranges;
184 172
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 173 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 174 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 175 "snps,dwmac-3.70a",
280 "snps,dwm 176 "snps,dwmac";
281 reg = <0x0 0xff3f0000 177 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 178 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 179 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 180 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 181 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 182 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 183 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 184 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> 185 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 186 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc <<
294 status = "disabled"; 187 status = "disabled";
295 }; 188 };
296 189
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 190 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 191 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 192 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 193 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 194 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 195 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 196 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 197 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 198 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 199 status = "disabled";
316 }; 200 };
317 201
318 periphs: bus@ff634000 { 202 periphs: bus@ff634000 {
319 compatible = "simple-b 203 compatible = "simple-bus";
320 reg = <0x0 0xff634000 204 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 205 #address-cells = <2>;
322 #size-cells = <2>; 206 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 207 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 208
325 hwrng: rng@18 { 209 hwrng: rng@18 {
326 compatible = " 210 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 211 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 212 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 213 clock-names = "core";
330 }; 214 };
331 215
332 pinctrl_periphs: pinct 216 pinctrl_periphs: pinctrl@480 {
333 compatible = " 217 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 218 #address-cells = <2>;
335 #size-cells = 219 #size-cells = <2>;
336 ranges; 220 ranges;
337 221
338 gpio: bank@480 222 gpio: bank@480 {
339 reg = 223 reg = <0x0 0x00480 0x0 0x40>,
340 224 <0x0 0x004e8 0x0 0x14>,
341 225 <0x0 0x00520 0x0 0x14>,
342 226 <0x0 0x00430 0x0 0x3c>;
343 reg-na 227 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 228 gpio-controller;
345 #gpio- 229 #gpio-cells = <2>;
346 gpio-r 230 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 231 };
348 232
349 i2c0_pins: i2c 233 i2c0_pins: i2c0 {
350 mux { 234 mux {
351 235 groups = "i2c0_sck",
352 236 "i2c0_sda";
353 237 function = "i2c0";
354 238 bias-disable;
355 }; 239 };
356 }; 240 };
357 241
358 i2c1_x_pins: i 242 i2c1_x_pins: i2c1_x {
359 mux { 243 mux {
360 244 groups = "i2c1_sck_x",
361 245 "i2c1_sda_x";
362 246 function = "i2c1";
363 247 bias-disable;
364 }; 248 };
365 }; 249 };
366 250
367 i2c1_z_pins: i 251 i2c1_z_pins: i2c1_z {
368 mux { 252 mux {
369 253 groups = "i2c1_sck_z",
370 254 "i2c1_sda_z";
371 255 function = "i2c1";
372 256 bias-disable;
373 }; 257 };
374 }; 258 };
375 259
376 i2c2_a_pins: i 260 i2c2_a_pins: i2c2_a {
377 mux { 261 mux {
378 262 groups = "i2c2_sck_a",
379 263 "i2c2_sda_a";
380 264 function = "i2c2";
381 265 bias-disable;
382 }; 266 };
383 }; 267 };
384 268
385 i2c2_x_pins: i 269 i2c2_x_pins: i2c2_x {
386 mux { 270 mux {
387 271 groups = "i2c2_sck_x",
388 272 "i2c2_sda_x";
389 273 function = "i2c2";
390 274 bias-disable;
391 }; 275 };
392 }; 276 };
393 277
394 i2c3_a6_pins: 278 i2c3_a6_pins: i2c3_a6 {
395 mux { 279 mux {
396 280 groups = "i2c3_sda_a6",
397 281 "i2c3_sck_a7";
398 282 function = "i2c3";
399 283 bias-disable;
400 }; 284 };
401 }; 285 };
402 286
403 i2c3_a12_pins: 287 i2c3_a12_pins: i2c3_a12 {
404 mux { 288 mux {
405 289 groups = "i2c3_sda_a12",
406 290 "i2c3_sck_a13";
407 291 function = "i2c3";
408 292 bias-disable;
409 }; 293 };
410 }; 294 };
411 295
412 i2c3_a19_pins: 296 i2c3_a19_pins: i2c3_a19 {
413 mux { 297 mux {
414 298 groups = "i2c3_sda_a19",
415 299 "i2c3_sck_a20";
416 300 function = "i2c3";
417 301 bias-disable;
418 }; 302 };
419 }; 303 };
420 304
421 emmc_pins: emm 305 emmc_pins: emmc {
422 mux-0 306 mux-0 {
423 307 groups = "emmc_nand_d0",
424 308 "emmc_nand_d1",
425 309 "emmc_nand_d2",
426 310 "emmc_nand_d3",
427 311 "emmc_nand_d4",
428 312 "emmc_nand_d5",
429 313 "emmc_nand_d6",
430 314 "emmc_nand_d7",
431 315 "emmc_cmd";
432 316 function = "emmc";
433 317 bias-pull-up;
434 }; 318 };
435 319
436 mux-1 320 mux-1 {
437 321 groups = "emmc_clk";
438 322 function = "emmc";
439 323 bias-disable;
440 }; 324 };
441 }; 325 };
442 326
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 327 emmc_ds_pins: emmc_ds {
465 mux { 328 mux {
466 329 groups = "emmc_ds";
467 330 function = "emmc";
468 331 bias-pull-down;
469 }; 332 };
470 }; 333 };
471 334
472 emmc_clk_gate_ 335 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 336 mux {
474 337 groups = "BOOT_8";
475 338 function = "gpio_periphs";
476 339 bias-pull-down;
477 }; 340 };
478 }; 341 };
479 342
480 eth_rgmii_x_pi 343 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 344 mux {
482 345 groups = "eth_mdio_x",
483 346 "eth_mdc_x",
484 347 "eth_rgmii_rx_clk_x",
485 348 "eth_rx_dv_x",
486 349 "eth_rxd0_x",
487 350 "eth_rxd1_x",
488 351 "eth_rxd2_rgmii",
489 352 "eth_rxd3_rgmii",
490 353 "eth_rgmii_tx_clk",
491 354 "eth_txen_x",
492 355 "eth_txd0_x",
493 356 "eth_txd1_x",
494 357 "eth_txd2_rgmii",
495 358 "eth_txd3_rgmii";
496 359 function = "eth";
497 360 bias-disable;
498 }; 361 };
499 }; 362 };
500 363
501 eth_rgmii_y_pi 364 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 365 mux {
503 366 groups = "eth_mdio_y",
504 367 "eth_mdc_y",
505 368 "eth_rgmii_rx_clk_y",
506 369 "eth_rx_dv_y",
507 370 "eth_rxd0_y",
508 371 "eth_rxd1_y",
509 372 "eth_rxd2_rgmii",
510 373 "eth_rxd3_rgmii",
511 374 "eth_rgmii_tx_clk",
512 375 "eth_txen_y",
513 376 "eth_txd0_y",
514 377 "eth_txd1_y",
515 378 "eth_txd2_rgmii",
516 379 "eth_txd3_rgmii";
517 380 function = "eth";
518 381 bias-disable;
519 }; 382 };
520 }; 383 };
521 384
522 eth_rmii_x_pin 385 eth_rmii_x_pins: eth-x-rmii {
523 mux { 386 mux {
524 387 groups = "eth_mdio_x",
525 388 "eth_mdc_x",
526 389 "eth_rgmii_rx_clk_x",
527 390 "eth_rx_dv_x",
528 391 "eth_rxd0_x",
529 392 "eth_rxd1_x",
530 393 "eth_txen_x",
531 394 "eth_txd0_x",
532 395 "eth_txd1_x";
533 396 function = "eth";
534 397 bias-disable;
535 }; 398 };
536 }; 399 };
537 400
538 eth_rmii_y_pin 401 eth_rmii_y_pins: eth-y-rmii {
539 mux { 402 mux {
540 403 groups = "eth_mdio_y",
541 404 "eth_mdc_y",
542 405 "eth_rgmii_rx_clk_y",
543 406 "eth_rx_dv_y",
544 407 "eth_rxd0_y",
545 408 "eth_rxd1_y",
546 409 "eth_txen_y",
547 410 "eth_txd0_y",
548 411 "eth_txd1_y";
549 412 function = "eth";
550 413 bias-disable;
551 }; 414 };
552 }; 415 };
553 416
554 mclk_b_pins: m 417 mclk_b_pins: mclk_b {
555 mux { 418 mux {
556 419 groups = "mclk_b";
557 420 function = "mclk_b";
558 421 bias-disable;
559 }; 422 };
560 }; 423 };
561 424
562 mclk_c_pins: m 425 mclk_c_pins: mclk_c {
563 mux { 426 mux {
564 427 groups = "mclk_c";
565 428 function = "mclk_c";
566 429 bias-disable;
567 }; 430 };
568 }; 431 };
569 432
570 pdm_dclk_a14_p 433 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 434 mux {
572 435 groups = "pdm_dclk_a14";
573 436 function = "pdm";
574 437 bias-disable;
575 }; 438 };
576 }; 439 };
577 440
578 pdm_dclk_a19_p 441 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 442 mux {
580 443 groups = "pdm_dclk_a19";
581 444 function = "pdm";
582 445 bias-disable;
583 }; 446 };
584 }; 447 };
585 448
586 pdm_din0_pins: 449 pdm_din0_pins: pdm_din0 {
587 mux { 450 mux {
588 451 groups = "pdm_din0";
589 452 function = "pdm";
590 453 bias-disable;
591 }; 454 };
592 }; 455 };
593 456
594 pdm_din1_pins: 457 pdm_din1_pins: pdm_din1 {
595 mux { 458 mux {
596 459 groups = "pdm_din1";
597 460 function = "pdm";
598 461 bias-disable;
599 }; 462 };
600 }; 463 };
601 464
602 pdm_din2_pins: 465 pdm_din2_pins: pdm_din2 {
603 mux { 466 mux {
604 467 groups = "pdm_din2";
605 468 function = "pdm";
606 469 bias-disable;
607 }; 470 };
608 }; 471 };
609 472
610 pdm_din3_pins: 473 pdm_din3_pins: pdm_din3 {
611 mux { 474 mux {
612 475 groups = "pdm_din3";
613 476 function = "pdm";
614 477 bias-disable;
615 }; 478 };
616 }; 479 };
617 480
618 pwm_a_a_pins: 481 pwm_a_a_pins: pwm_a_a {
619 mux { 482 mux {
620 483 groups = "pwm_a_a";
621 484 function = "pwm_a";
622 485 bias-disable;
623 }; 486 };
624 }; 487 };
625 488
626 pwm_a_x18_pins 489 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 490 mux {
628 491 groups = "pwm_a_x18";
629 492 function = "pwm_a";
630 493 bias-disable;
631 }; 494 };
632 }; 495 };
633 496
634 pwm_a_x20_pins 497 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 498 mux {
636 499 groups = "pwm_a_x20";
637 500 function = "pwm_a";
638 501 bias-disable;
639 }; 502 };
640 }; 503 };
641 504
642 pwm_a_z_pins: 505 pwm_a_z_pins: pwm_a_z {
643 mux { 506 mux {
644 507 groups = "pwm_a_z";
645 508 function = "pwm_a";
646 509 bias-disable;
647 }; 510 };
648 }; 511 };
649 512
650 pwm_b_a_pins: 513 pwm_b_a_pins: pwm_b_a {
651 mux { 514 mux {
652 515 groups = "pwm_b_a";
653 516 function = "pwm_b";
654 517 bias-disable;
655 }; 518 };
656 }; 519 };
657 520
658 pwm_b_x_pins: 521 pwm_b_x_pins: pwm_b_x {
659 mux { 522 mux {
660 523 groups = "pwm_b_x";
661 524 function = "pwm_b";
662 525 bias-disable;
663 }; 526 };
664 }; 527 };
665 528
666 pwm_b_z_pins: 529 pwm_b_z_pins: pwm_b_z {
667 mux { 530 mux {
668 531 groups = "pwm_b_z";
669 532 function = "pwm_b";
670 533 bias-disable;
671 }; 534 };
672 }; 535 };
673 536
674 pwm_c_a_pins: 537 pwm_c_a_pins: pwm_c_a {
675 mux { 538 mux {
676 539 groups = "pwm_c_a";
677 540 function = "pwm_c";
678 541 bias-disable;
679 }; 542 };
680 }; 543 };
681 544
682 pwm_c_x10_pins 545 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 546 mux {
684 547 groups = "pwm_c_x10";
685 548 function = "pwm_c";
686 549 bias-disable;
687 }; 550 };
688 }; 551 };
689 552
690 pwm_c_x17_pins 553 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 554 mux {
692 555 groups = "pwm_c_x17";
693 556 function = "pwm_c";
694 557 bias-disable;
695 }; 558 };
696 }; 559 };
697 560
698 pwm_d_x11_pins 561 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 562 mux {
700 563 groups = "pwm_d_x11";
701 564 function = "pwm_d";
702 565 bias-disable;
703 }; 566 };
704 }; 567 };
705 568
706 pwm_d_x16_pins 569 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 570 mux {
708 571 groups = "pwm_d_x16";
709 572 function = "pwm_d";
710 573 bias-disable;
711 }; 574 };
712 }; 575 };
713 576
714 sdio_pins: sdi 577 sdio_pins: sdio {
715 mux-0 578 mux-0 {
716 579 groups = "sdio_d0",
717 580 "sdio_d1",
718 581 "sdio_d2",
719 582 "sdio_d3",
720 583 "sdio_cmd";
721 584 function = "sdio";
722 585 bias-pull-up;
723 }; 586 };
724 587
725 mux-1 588 mux-1 {
726 589 groups = "sdio_clk";
727 590 function = "sdio";
728 591 bias-disable;
729 }; 592 };
730 }; 593 };
731 594
732 sdio_clk_gate_ 595 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 596 mux {
734 597 groups = "GPIOX_4";
735 598 function = "gpio_periphs";
736 599 bias-pull-down;
737 }; 600 };
738 }; 601 };
739 602
740 spdif_in_z_pin 603 spdif_in_z_pins: spdif_in_z {
741 mux { 604 mux {
742 605 groups = "spdif_in_z";
743 606 function = "spdif_in";
744 607 bias-disable;
745 }; 608 };
746 }; 609 };
747 610
748 spdif_in_a1_pi 611 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 612 mux {
750 613 groups = "spdif_in_a1";
751 614 function = "spdif_in";
752 615 bias-disable;
753 }; 616 };
754 }; 617 };
755 618
756 spdif_in_a7_pi 619 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 620 mux {
758 621 groups = "spdif_in_a7";
759 622 function = "spdif_in";
760 623 bias-disable;
761 }; 624 };
762 }; 625 };
763 626
764 spdif_in_a19_p 627 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 628 mux {
766 629 groups = "spdif_in_a19";
767 630 function = "spdif_in";
768 631 bias-disable;
769 }; 632 };
770 }; 633 };
771 634
772 spdif_in_a20_p 635 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 636 mux {
774 637 groups = "spdif_in_a20";
775 638 function = "spdif_in";
776 639 bias-disable;
777 }; 640 };
778 }; 641 };
779 642
780 spdif_out_a1_p 643 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 644 mux {
782 645 groups = "spdif_out_a1";
783 646 function = "spdif_out";
784 647 bias-disable;
785 }; 648 };
786 }; 649 };
787 650
788 spdif_out_a11_ 651 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 652 mux {
790 653 groups = "spdif_out_a11";
791 654 function = "spdif_out";
792 655 bias-disable;
793 }; 656 };
794 }; 657 };
795 658
796 spdif_out_a19_ 659 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 660 mux {
798 661 groups = "spdif_out_a19";
799 662 function = "spdif_out";
800 663 bias-disable;
801 }; 664 };
802 }; 665 };
803 666
804 spdif_out_a20_ 667 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 668 mux {
806 669 groups = "spdif_out_a20";
807 670 function = "spdif_out";
808 671 bias-disable;
809 }; 672 };
810 }; 673 };
811 674
812 spdif_out_z_pi 675 spdif_out_z_pins: spdif_out_z {
813 mux { 676 mux {
814 677 groups = "spdif_out_z";
815 678 function = "spdif_out";
816 679 bias-disable;
817 }; 680 };
818 }; 681 };
819 682
820 spi0_pins: spi 683 spi0_pins: spi0 {
821 mux { 684 mux {
822 685 groups = "spi0_miso",
823 686 "spi0_mosi",
824 687 "spi0_clk";
825 688 function = "spi0";
826 689 bias-disable;
827 }; 690 };
828 }; 691 };
829 692
830 spi0_ss0_pins: 693 spi0_ss0_pins: spi0_ss0 {
831 mux { 694 mux {
832 695 groups = "spi0_ss0";
833 696 function = "spi0";
834 697 bias-disable;
835 }; 698 };
836 }; 699 };
837 700
838 spi0_ss1_pins: 701 spi0_ss1_pins: spi0_ss1 {
839 mux { 702 mux {
840 703 groups = "spi0_ss1";
841 704 function = "spi0";
842 705 bias-disable;
843 }; 706 };
844 }; 707 };
845 708
846 spi0_ss2_pins: 709 spi0_ss2_pins: spi0_ss2 {
847 mux { 710 mux {
848 711 groups = "spi0_ss2";
849 712 function = "spi0";
850 713 bias-disable;
851 }; 714 };
852 }; 715 };
853 716
854 spi1_a_pins: s 717 spi1_a_pins: spi1_a {
855 mux { 718 mux {
856 719 groups = "spi1_miso_a",
857 720 "spi1_mosi_a",
858 721 "spi1_clk_a";
859 722 function = "spi1";
860 723 bias-disable;
861 }; 724 };
862 }; 725 };
863 726
864 spi1_ss0_a_pin 727 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 728 mux {
866 729 groups = "spi1_ss0_a";
867 730 function = "spi1";
868 731 bias-disable;
869 }; 732 };
870 }; 733 };
871 734
872 spi1_ss1_pins: 735 spi1_ss1_pins: spi1_ss1 {
873 mux { 736 mux {
874 737 groups = "spi1_ss1";
875 738 function = "spi1";
876 739 bias-disable;
877 }; 740 };
878 }; 741 };
879 742
880 spi1_x_pins: s 743 spi1_x_pins: spi1_x {
881 mux { 744 mux {
882 745 groups = "spi1_miso_x",
883 746 "spi1_mosi_x",
884 747 "spi1_clk_x";
885 748 function = "spi1";
886 749 bias-disable;
887 }; 750 };
888 }; 751 };
889 752
890 spi1_ss0_x_pin 753 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 754 mux {
892 755 groups = "spi1_ss0_x";
893 756 function = "spi1";
894 757 bias-disable;
895 }; 758 };
896 }; 759 };
897 760
898 tdma_din0_pins 761 tdma_din0_pins: tdma_din0 {
899 mux { 762 mux {
900 763 groups = "tdma_din0";
901 764 function = "tdma";
902 765 bias-disable;
903 }; 766 };
904 }; 767 };
905 768
906 tdma_dout0_x14 769 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 770 mux {
908 771 groups = "tdma_dout0_x14";
909 772 function = "tdma";
910 773 bias-disable;
911 }; 774 };
912 }; 775 };
913 776
914 tdma_dout0_x15 777 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 778 mux {
916 779 groups = "tdma_dout0_x15";
917 780 function = "tdma";
918 781 bias-disable;
919 }; 782 };
920 }; 783 };
921 784
922 tdma_dout1_pin 785 tdma_dout1_pins: tdma_dout1 {
923 mux { 786 mux {
924 787 groups = "tdma_dout1";
925 788 function = "tdma";
926 789 bias-disable;
927 }; 790 };
928 }; 791 };
929 792
930 tdma_din1_pins 793 tdma_din1_pins: tdma_din1 {
931 mux { 794 mux {
932 795 groups = "tdma_din1";
933 796 function = "tdma";
934 797 bias-disable;
935 }; 798 };
936 }; 799 };
937 800
938 tdma_fs_pins: 801 tdma_fs_pins: tdma_fs {
939 mux { 802 mux {
940 803 groups = "tdma_fs";
941 804 function = "tdma";
942 805 bias-disable;
943 }; 806 };
944 }; 807 };
945 808
946 tdma_fs_slv_pi 809 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 810 mux {
948 811 groups = "tdma_fs_slv";
949 812 function = "tdma";
950 813 bias-disable;
951 }; 814 };
952 }; 815 };
953 816
954 tdma_sclk_pins 817 tdma_sclk_pins: tdma_sclk {
955 mux { 818 mux {
956 819 groups = "tdma_sclk";
957 820 function = "tdma";
958 821 bias-disable;
959 }; 822 };
960 }; 823 };
961 824
962 tdma_sclk_slv_ 825 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 826 mux {
964 827 groups = "tdma_sclk_slv";
965 828 function = "tdma";
966 829 bias-disable;
967 }; 830 };
968 }; 831 };
969 832
970 tdmb_din0_pins 833 tdmb_din0_pins: tdmb_din0 {
971 mux { 834 mux {
972 835 groups = "tdmb_din0";
973 836 function = "tdmb";
974 837 bias-disable;
975 }; 838 };
976 }; 839 };
977 840
978 tdmb_din1_pins 841 tdmb_din1_pins: tdmb_din1 {
979 mux { 842 mux {
980 843 groups = "tdmb_din1";
981 844 function = "tdmb";
982 845 bias-disable;
983 }; 846 };
984 }; 847 };
985 848
986 tdmb_din2_pins 849 tdmb_din2_pins: tdmb_din2 {
987 mux { 850 mux {
988 851 groups = "tdmb_din2";
989 852 function = "tdmb";
990 853 bias-disable;
991 }; 854 };
992 }; 855 };
993 856
994 tdmb_din3_pins 857 tdmb_din3_pins: tdmb_din3 {
995 mux { 858 mux {
996 859 groups = "tdmb_din3";
997 860 function = "tdmb";
998 861 bias-disable;
999 }; 862 };
1000 }; 863 };
1001 864
1002 tdmb_dout0_pi 865 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 866 mux {
1004 867 groups = "tdmb_dout0";
1005 868 function = "tdmb";
1006 869 bias-disable;
1007 }; 870 };
1008 }; 871 };
1009 872
1010 tdmb_dout1_pi 873 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 874 mux {
1012 875 groups = "tdmb_dout1";
1013 876 function = "tdmb";
1014 877 bias-disable;
1015 }; 878 };
1016 }; 879 };
1017 880
1018 tdmb_dout2_pi 881 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 882 mux {
1020 883 groups = "tdmb_dout2";
1021 884 function = "tdmb";
1022 885 bias-disable;
1023 }; 886 };
1024 }; 887 };
1025 888
1026 tdmb_dout3_pi 889 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 890 mux {
1028 891 groups = "tdmb_dout3";
1029 892 function = "tdmb";
1030 893 bias-disable;
1031 }; 894 };
1032 }; 895 };
1033 896
1034 tdmb_fs_pins: 897 tdmb_fs_pins: tdmb_fs {
1035 mux { 898 mux {
1036 899 groups = "tdmb_fs";
1037 900 function = "tdmb";
1038 901 bias-disable;
1039 }; 902 };
1040 }; 903 };
1041 904
1042 tdmb_fs_slv_p 905 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 906 mux {
1044 907 groups = "tdmb_fs_slv";
1045 908 function = "tdmb";
1046 909 bias-disable;
1047 }; 910 };
1048 }; 911 };
1049 912
1050 tdmb_sclk_pin 913 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 914 mux {
1052 915 groups = "tdmb_sclk";
1053 916 function = "tdmb";
1054 917 bias-disable;
1055 }; 918 };
1056 }; 919 };
1057 920
1058 tdmb_sclk_slv 921 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 922 mux {
1060 923 groups = "tdmb_sclk_slv";
1061 924 function = "tdmb";
1062 925 bias-disable;
1063 }; 926 };
1064 }; 927 };
1065 928
1066 tdmc_fs_pins: 929 tdmc_fs_pins: tdmc_fs {
1067 mux { 930 mux {
1068 931 groups = "tdmc_fs";
1069 932 function = "tdmc";
1070 933 bias-disable;
1071 }; 934 };
1072 }; 935 };
1073 936
1074 tdmc_fs_slv_p 937 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 938 mux {
1076 939 groups = "tdmc_fs_slv";
1077 940 function = "tdmc";
1078 941 bias-disable;
1079 }; 942 };
1080 }; 943 };
1081 944
1082 tdmc_sclk_pin 945 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 946 mux {
1084 947 groups = "tdmc_sclk";
1085 948 function = "tdmc";
1086 949 bias-disable;
1087 }; 950 };
1088 }; 951 };
1089 952
1090 tdmc_sclk_slv 953 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 954 mux {
1092 955 groups = "tdmc_sclk_slv";
1093 956 function = "tdmc";
1094 957 bias-disable;
1095 }; 958 };
1096 }; 959 };
1097 960
1098 tdmc_din0_pin 961 tdmc_din0_pins: tdmc_din0 {
1099 mux { 962 mux {
1100 963 groups = "tdmc_din0";
1101 964 function = "tdmc";
1102 965 bias-disable;
1103 }; 966 };
1104 }; 967 };
1105 968
1106 tdmc_din1_pin 969 tdmc_din1_pins: tdmc_din1 {
1107 mux { 970 mux {
1108 971 groups = "tdmc_din1";
1109 972 function = "tdmc";
1110 973 bias-disable;
1111 }; 974 };
1112 }; 975 };
1113 976
1114 tdmc_din2_pin 977 tdmc_din2_pins: tdmc_din2 {
1115 mux { 978 mux {
1116 979 groups = "tdmc_din2";
1117 980 function = "tdmc";
1118 981 bias-disable;
1119 }; 982 };
1120 }; 983 };
1121 984
1122 tdmc_din3_pin 985 tdmc_din3_pins: tdmc_din3 {
1123 mux { 986 mux {
1124 987 groups = "tdmc_din3";
1125 988 function = "tdmc";
1126 989 bias-disable;
1127 }; 990 };
1128 }; 991 };
1129 992
1130 tdmc_dout0_pi 993 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 994 mux {
1132 995 groups = "tdmc_dout0";
1133 996 function = "tdmc";
1134 997 bias-disable;
1135 }; 998 };
1136 }; 999 };
1137 1000
1138 tdmc_dout1_pi 1001 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1002 mux {
1140 1003 groups = "tdmc_dout1";
1141 1004 function = "tdmc";
1142 1005 bias-disable;
1143 }; 1006 };
1144 }; 1007 };
1145 1008
1146 tdmc_dout2_pi 1009 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1010 mux {
1148 1011 groups = "tdmc_dout2";
1149 1012 function = "tdmc";
1150 1013 bias-disable;
1151 }; 1014 };
1152 }; 1015 };
1153 1016
1154 tdmc_dout3_pi 1017 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1018 mux {
1156 1019 groups = "tdmc_dout3";
1157 1020 function = "tdmc";
1158 1021 bias-disable;
1159 }; 1022 };
1160 }; 1023 };
1161 1024
1162 uart_a_pins: 1025 uart_a_pins: uart_a {
1163 mux { 1026 mux {
1164 1027 groups = "uart_tx_a",
1165 1028 "uart_rx_a";
1166 1029 function = "uart_a";
1167 1030 bias-disable;
1168 }; 1031 };
1169 }; 1032 };
1170 1033
1171 uart_a_cts_rt 1034 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1035 mux {
1173 1036 groups = "uart_cts_a",
1174 1037 "uart_rts_a";
1175 1038 function = "uart_a";
1176 1039 bias-disable;
1177 }; 1040 };
1178 }; 1041 };
1179 1042
1180 uart_b_x_pins 1043 uart_b_x_pins: uart_b_x {
1181 mux { 1044 mux {
1182 1045 groups = "uart_tx_b_x",
1183 1046 "uart_rx_b_x";
1184 1047 function = "uart_b";
1185 1048 bias-disable;
1186 }; 1049 };
1187 }; 1050 };
1188 1051
1189 uart_b_x_cts_ 1052 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1053 mux {
1191 1054 groups = "uart_cts_b_x",
1192 1055 "uart_rts_b_x";
1193 1056 function = "uart_b";
1194 1057 bias-disable;
1195 }; 1058 };
1196 }; 1059 };
1197 1060
1198 uart_b_z_pins 1061 uart_b_z_pins: uart_b_z {
1199 mux { 1062 mux {
1200 1063 groups = "uart_tx_b_z",
1201 1064 "uart_rx_b_z";
1202 1065 function = "uart_b";
1203 1066 bias-disable;
1204 }; 1067 };
1205 }; 1068 };
1206 1069
1207 uart_b_z_cts_ 1070 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1071 mux {
1209 1072 groups = "uart_cts_b_z",
1210 1073 "uart_rts_b_z";
1211 1074 function = "uart_b";
1212 1075 bias-disable;
1213 }; 1076 };
1214 }; 1077 };
1215 1078
1216 uart_ao_b_z_p 1079 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1080 mux {
1218 1081 groups = "uart_ao_tx_b_z",
1219 1082 "uart_ao_rx_b_z";
1220 1083 function = "uart_ao_b_z";
1221 1084 bias-disable;
1222 }; 1085 };
1223 }; 1086 };
1224 1087
1225 uart_ao_b_z_c 1088 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1089 mux {
1227 1090 groups = "uart_ao_cts_b_z",
1228 1091 "uart_ao_rts_b_z";
1229 1092 function = "uart_ao_b_z";
1230 1093 bias-disable;
1231 }; 1094 };
1232 }; 1095 };
1233 }; 1096 };
1234 }; 1097 };
1235 1098
1236 hiubus: bus@ff63c000 { 1099 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1100 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1101 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1102 #address-cells = <2>;
1240 #size-cells = <2>; 1103 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1104 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1105
1243 sysctrl: system-contr 1106 sysctrl: system-controller@0 {
1244 compatible = 1107 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1108 "simple-mfd", "syscon";
1246 reg = <0 0 0 1109 reg = <0 0 0 0x400>;
1247 1110
1248 clkc: clock-c 1111 clkc: clock-controller {
1249 compa 1112 compatible = "amlogic,axg-clkc";
1250 #cloc 1113 #clock-cells = <1>;
1251 clock 1114 clocks = <&xtal>;
1252 clock 1115 clock-names = "xtal";
1253 }; 1116 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1117 };
1301 }; 1118 };
1302 1119
1303 mailbox: mailbox@ff63c404 { 1120 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1121 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1122 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1123 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1124 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1125 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1126 #mbox-cells = <1>;
1310 }; 1127 };
1311 1128
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1129 audio: bus@ff642000 {
1326 compatible = "simple- 1130 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1131 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1132 #address-cells = <2>;
1329 #size-cells = <2>; 1133 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1134 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1135
1332 clkc_audio: clock-con 1136 clkc_audio: clock-controller@0 {
1333 compatible = 1137 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1138 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1139 #clock-cells = <1>;
1336 1140
1337 clocks = <&cl 1141 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1142 <&clkc CLKID_MPLL0>,
1339 <&cl 1143 <&clkc CLKID_MPLL1>,
1340 <&cl 1144 <&clkc CLKID_MPLL2>,
1341 <&cl 1145 <&clkc CLKID_MPLL3>,
1342 <&cl 1146 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1147 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1148 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1149 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1150 clock-names = "pclk",
1347 1151 "mst_in0",
1348 1152 "mst_in1",
1349 1153 "mst_in2",
1350 1154 "mst_in3",
1351 1155 "mst_in4",
1352 1156 "mst_in5",
1353 1157 "mst_in6",
1354 1158 "mst_in7";
1355 1159
1356 resets = <&re 1160 resets = <&reset RESET_AUDIO>;
1357 }; 1161 };
1358 1162
1359 toddr_a: audio-contro 1163 toddr_a: audio-controller@100 {
1360 compatible = 1164 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1165 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1166 #sound-dai-cells = <0>;
1363 sound-name-pr 1167 sound-name-prefix = "TODDR_A";
1364 interrupts = 1168 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1169 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1170 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- <<
1368 status = "dis 1171 status = "disabled";
1369 }; 1172 };
1370 1173
1371 toddr_b: audio-contro 1174 toddr_b: audio-controller@140 {
1372 compatible = 1175 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1176 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1177 #sound-dai-cells = <0>;
1375 sound-name-pr 1178 sound-name-prefix = "TODDR_B";
1376 interrupts = 1179 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1180 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1181 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- <<
1380 status = "dis 1182 status = "disabled";
1381 }; 1183 };
1382 1184
1383 toddr_c: audio-contro 1185 toddr_c: audio-controller@180 {
1384 compatible = 1186 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1187 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1188 #sound-dai-cells = <0>;
1387 sound-name-pr 1189 sound-name-prefix = "TODDR_C";
1388 interrupts = 1190 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1191 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1192 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- <<
1392 status = "dis 1193 status = "disabled";
1393 }; 1194 };
1394 1195
1395 frddr_a: audio-contro 1196 frddr_a: audio-controller@1c0 {
1396 compatible = 1197 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1198 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1199 #sound-dai-cells = <0>;
1399 sound-name-pr 1200 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1201 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1202 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1203 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- <<
1404 status = "dis 1204 status = "disabled";
1405 }; 1205 };
1406 1206
1407 frddr_b: audio-contro 1207 frddr_b: audio-controller@200 {
1408 compatible = 1208 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1209 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1210 #sound-dai-cells = <0>;
1411 sound-name-pr 1211 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1212 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1213 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1214 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- <<
1416 status = "dis 1215 status = "disabled";
1417 }; 1216 };
1418 1217
1419 frddr_c: audio-contro 1218 frddr_c: audio-controller@240 {
1420 compatible = 1219 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1220 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1221 #sound-dai-cells = <0>;
1423 sound-name-pr 1222 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1223 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1224 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1225 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- <<
1428 status = "dis 1226 status = "disabled";
1429 }; 1227 };
1430 1228
1431 arb: reset-controller 1229 arb: reset-controller@280 {
1432 compatible = 1230 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1231 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1232 #reset-cells = <1>;
1435 clocks = <&cl 1233 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1234 };
1437 1235
1438 tdmin_a: audio-contro 1236 tdmin_a: audio-controller@300 {
1439 compatible = 1237 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1238 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1239 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1240 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1241 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1242 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1243 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1244 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1245 clock-names = "pclk", "sclk", "sclk_sel",
1448 1246 "lrclk", "lrclk_sel";
1449 status = "dis 1247 status = "disabled";
1450 }; 1248 };
1451 1249
1452 tdmin_b: audio-contro 1250 tdmin_b: audio-controller@340 {
1453 compatible = 1251 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1252 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1253 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1254 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1255 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1256 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1257 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1258 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1259 clock-names = "pclk", "sclk", "sclk_sel",
1462 1260 "lrclk", "lrclk_sel";
1463 status = "dis 1261 status = "disabled";
1464 }; 1262 };
1465 1263
1466 tdmin_c: audio-contro 1264 tdmin_c: audio-controller@380 {
1467 compatible = 1265 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1266 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1267 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1268 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1269 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1270 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1271 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1272 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1273 clock-names = "pclk", "sclk", "sclk_sel",
1476 1274 "lrclk", "lrclk_sel";
1477 status = "dis 1275 status = "disabled";
1478 }; 1276 };
1479 1277
1480 tdmin_lb: audio-contr 1278 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1279 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1280 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1281 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1282 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1283 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1284 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1285 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1286 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1287 clock-names = "pclk", "sclk", "sclk_sel",
1490 1288 "lrclk", "lrclk_sel";
1491 status = "dis 1289 status = "disabled";
1492 }; 1290 };
1493 1291
1494 spdifin: audio-contro 1292 spdifin: audio-controller@400 {
1495 compatible = 1293 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1294 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1295 #sound-dai-cells = <0>;
1498 sound-name-pr 1296 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1297 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1298 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1299 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1300 clock-names = "pclk", "refclk";
1503 status = "dis 1301 status = "disabled";
1504 }; 1302 };
1505 1303
1506 spdifout: audio-contr 1304 spdifout: audio-controller@480 {
1507 compatible = 1305 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1306 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1307 #sound-dai-cells = <0>;
1510 sound-name-pr 1308 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1309 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1310 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1311 clock-names = "pclk", "mclk";
1514 status = "dis 1312 status = "disabled";
1515 }; 1313 };
1516 1314
1517 tdmout_a: audio-contr 1315 tdmout_a: audio-controller@500 {
1518 compatible = 1316 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1317 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1318 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1319 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1320 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1321 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1322 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1323 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1324 clock-names = "pclk", "sclk", "sclk_sel",
1527 1325 "lrclk", "lrclk_sel";
1528 status = "dis 1326 status = "disabled";
1529 }; 1327 };
1530 1328
1531 tdmout_b: audio-contr 1329 tdmout_b: audio-controller@540 {
1532 compatible = 1330 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1331 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1332 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1333 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1334 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1335 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1336 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1337 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1338 clock-names = "pclk", "sclk", "sclk_sel",
1541 1339 "lrclk", "lrclk_sel";
1542 status = "dis 1340 status = "disabled";
1543 }; 1341 };
1544 1342
1545 tdmout_c: audio-contr 1343 tdmout_c: audio-controller@580 {
1546 compatible = 1344 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1345 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1346 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1347 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1348 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1349 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1350 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1351 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1352 clock-names = "pclk", "sclk", "sclk_sel",
1555 1353 "lrclk", "lrclk_sel";
1556 status = "dis 1354 status = "disabled";
1557 }; 1355 };
1558 }; 1356 };
1559 1357
1560 aobus: bus@ff800000 { 1358 aobus: bus@ff800000 {
1561 compatible = "simple- 1359 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1360 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1361 #address-cells = <2>;
1564 #size-cells = <2>; 1362 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1363 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1364
1567 sysctrl_AO: sys-ctrl@ 1365 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1366 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1367 reg = <0x0 0x0 0x0 0x100>;
1570 1368
1571 clkc_AO: cloc 1369 clkc_AO: clock-controller {
1572 compa 1370 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1371 #clock-cells = <1>;
1574 #rese 1372 #reset-cells = <1>;
1575 clock 1373 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1374 clock-names = "xtal", "mpeg-clk";
1577 }; 1375 };
1578 }; 1376 };
1579 1377
1580 pinctrl_aobus: pinctr 1378 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1379 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1380 #address-cells = <2>;
1583 #size-cells = 1381 #size-cells = <2>;
1584 ranges; 1382 ranges;
1585 1383
1586 gpio_ao: bank 1384 gpio_ao: bank@14 {
1587 reg = 1385 reg = <0x0 0x00014 0x0 0x8>,
1588 1386 <0x0 0x0002c 0x0 0x4>,
1589 1387 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1388 reg-names = "mux", "pull", "gpio";
1591 gpio- 1389 gpio-controller;
1592 #gpio 1390 #gpio-cells = <2>;
1593 gpio- 1391 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1392 };
1595 1393
1596 i2c_ao_sck_4_ 1394 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1395 mux {
1598 1396 groups = "i2c_ao_sck_4";
1599 1397 function = "i2c_ao";
1600 1398 bias-disable;
1601 }; 1399 };
1602 }; 1400 };
1603 1401
1604 i2c_ao_sck_8_ 1402 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1403 mux {
1606 1404 groups = "i2c_ao_sck_8";
1607 1405 function = "i2c_ao";
1608 1406 bias-disable;
1609 }; 1407 };
1610 }; 1408 };
1611 1409
1612 i2c_ao_sck_10 1410 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1411 mux {
1614 1412 groups = "i2c_ao_sck_10";
1615 1413 function = "i2c_ao";
1616 1414 bias-disable;
1617 }; 1415 };
1618 }; 1416 };
1619 1417
1620 i2c_ao_sda_5_ 1418 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1419 mux {
1622 1420 groups = "i2c_ao_sda_5";
1623 1421 function = "i2c_ao";
1624 1422 bias-disable;
1625 }; 1423 };
1626 }; 1424 };
1627 1425
1628 i2c_ao_sda_9_ 1426 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1427 mux {
1630 1428 groups = "i2c_ao_sda_9";
1631 1429 function = "i2c_ao";
1632 1430 bias-disable;
1633 }; 1431 };
1634 }; 1432 };
1635 1433
1636 i2c_ao_sda_11 1434 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1435 mux {
1638 1436 groups = "i2c_ao_sda_11";
1639 1437 function = "i2c_ao";
1640 1438 bias-disable;
1641 }; 1439 };
1642 }; 1440 };
1643 1441
1644 remote_input_ 1442 remote_input_ao_pins: remote_input_ao {
1645 mux { 1443 mux {
1646 1444 groups = "remote_input_ao";
1647 1445 function = "remote_input_ao";
1648 1446 bias-disable;
1649 }; 1447 };
1650 }; 1448 };
1651 1449
1652 uart_ao_a_pin 1450 uart_ao_a_pins: uart_ao_a {
1653 mux { 1451 mux {
1654 1452 groups = "uart_ao_tx_a",
1655 1453 "uart_ao_rx_a";
1656 1454 function = "uart_ao_a";
1657 1455 bias-disable;
1658 }; 1456 };
1659 }; 1457 };
1660 1458
1661 uart_ao_a_cts 1459 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1460 mux {
1663 1461 groups = "uart_ao_cts_a",
1664 1462 "uart_ao_rts_a";
1665 1463 function = "uart_ao_a";
1666 1464 bias-disable;
1667 }; 1465 };
1668 }; 1466 };
1669 1467
1670 uart_ao_b_pin 1468 uart_ao_b_pins: uart_ao_b {
1671 mux { 1469 mux {
1672 1470 groups = "uart_ao_tx_b",
1673 1471 "uart_ao_rx_b";
1674 1472 function = "uart_ao_b";
1675 1473 bias-disable;
1676 }; 1474 };
1677 }; 1475 };
1678 1476
1679 uart_ao_b_cts 1477 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1478 mux {
1681 1479 groups = "uart_ao_cts_b",
1682 1480 "uart_ao_rts_b";
1683 1481 function = "uart_ao_b";
1684 1482 bias-disable;
1685 }; 1483 };
1686 }; 1484 };
1687 }; 1485 };
1688 1486
1689 sec_AO: ao-secure@140 1487 sec_AO: ao-secure@140 {
1690 compatible = 1488 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1489 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1490 amlogic,has-chip-id;
1693 }; 1491 };
1694 1492
1695 pwm_AO_cd: pwm@2000 { 1493 pwm_AO_cd: pwm@2000 {
1696 compatible = 1494 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1495 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1496 #pwm-cells = <3>;
1699 status = "dis 1497 status = "disabled";
1700 }; 1498 };
1701 1499
1702 uart_AO: serial@3000 1500 uart_AO: serial@3000 {
1703 compatible = 1501 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1502 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1503 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1504 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1505 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1506 status = "disabled";
1709 }; 1507 };
1710 1508
1711 uart_AO_B: serial@400 1509 uart_AO_B: serial@4000 {
1712 compatible = 1510 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1511 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1512 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1513 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1514 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1515 status = "disabled";
1718 }; 1516 };
1719 1517
1720 i2c_AO: i2c@5000 { 1518 i2c_AO: i2c@5000 {
1721 compatible = 1519 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1520 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1521 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1522 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1523 #address-cells = <1>;
1726 #size-cells = 1524 #size-cells = <0>;
1727 status = "dis 1525 status = "disabled";
1728 }; 1526 };
1729 1527
1730 pwm_AO_ab: pwm@7000 { 1528 pwm_AO_ab: pwm@7000 {
1731 compatible = 1529 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1530 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1531 #pwm-cells = <3>;
1734 status = "dis 1532 status = "disabled";
1735 }; 1533 };
1736 1534
1737 ir: ir@8000 { 1535 ir: ir@8000 {
1738 compatible = 1536 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1537 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1538 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1539 status = "disabled";
1742 }; 1540 };
1743 1541
1744 saradc: adc@9000 { 1542 saradc: adc@9000 {
1745 compatible = 1543 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1544 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1545 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1546 #io-channel-cells = <1>;
1749 interrupts = 1547 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1548 clocks = <&xtal>,
1751 <&cl 1549 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1550 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1551 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1552 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1553 status = "disabled";
1756 }; 1554 };
1757 }; 1555 };
1758 1556
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1557 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1558 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1559 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1560 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1561 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1562 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1563 interrupt-controller;
1774 interrupts = <GIC_PPI 1564 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1565 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1566 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1567 #address-cells = <0>;
1778 }; 1568 };
1779 1569
1780 cbus: bus@ffd00000 { 1570 cbus: bus@ffd00000 {
1781 compatible = "simple- 1571 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1572 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1573 #address-cells = <2>;
1784 #size-cells = <2>; 1574 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1575 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1576
1787 reset: reset-controll 1577 reset: reset-controller@1004 {
1788 compatible = 1578 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1579 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1580 #reset-cells = <1>;
1791 }; 1581 };
1792 1582
1793 gpio_intc: interrupt- 1583 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1584 compatible = "amlogic,meson-axg-gpio-intc",
1795 1585 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1586 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1587 interrupt-controller;
1798 #interrupt-ce 1588 #interrupt-cells = <2>;
1799 amlogic,chann 1589 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1590 };
1801 1591
1802 watchdog@f0d0 { 1592 watchdog@f0d0 {
1803 compatible = 1593 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1594 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1595 clocks = <&xtal>;
1806 }; 1596 };
1807 1597
1808 pwm_ab: pwm@1b000 { 1598 pwm_ab: pwm@1b000 {
1809 compatible = 1599 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1600 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1601 #pwm-cells = <3>;
1812 status = "dis 1602 status = "disabled";
1813 }; 1603 };
1814 1604
1815 pwm_cd: pwm@1a000 { 1605 pwm_cd: pwm@1a000 {
1816 compatible = 1606 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1607 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1608 #pwm-cells = <3>;
1819 status = "dis 1609 status = "disabled";
1820 }; 1610 };
1821 1611
1822 spicc0: spi@13000 { 1612 spicc0: spi@13000 {
1823 compatible = 1613 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1614 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1615 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1616 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1617 clock-names = "core";
1828 #address-cell 1618 #address-cells = <1>;
1829 #size-cells = 1619 #size-cells = <0>;
1830 status = "dis 1620 status = "disabled";
1831 }; 1621 };
1832 1622
1833 spicc1: spi@15000 { 1623 spicc1: spi@15000 {
1834 compatible = 1624 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1625 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1626 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1627 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1628 clock-names = "core";
1839 #address-cell 1629 #address-cells = <1>;
1840 #size-cells = 1630 #size-cells = <0>;
1841 status = "dis 1631 status = "disabled";
1842 }; 1632 };
1843 1633
1844 clk_msr: clock-measur 1634 clk_msr: clock-measure@18000 {
1845 compatible = 1635 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1636 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1637 };
1848 1638
1849 i2c3: i2c@1c000 { 1639 i2c3: i2c@1c000 {
1850 compatible = 1640 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1641 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1642 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1643 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1644 #address-cells = <1>;
1855 #size-cells = 1645 #size-cells = <0>;
1856 status = "dis 1646 status = "disabled";
1857 }; 1647 };
1858 1648
1859 i2c2: i2c@1d000 { 1649 i2c2: i2c@1d000 {
1860 compatible = 1650 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1651 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1652 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1653 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1654 #address-cells = <1>;
1865 #size-cells = 1655 #size-cells = <0>;
1866 status = "dis 1656 status = "disabled";
1867 }; 1657 };
1868 1658
1869 i2c1: i2c@1e000 { 1659 i2c1: i2c@1e000 {
1870 compatible = 1660 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1661 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1662 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1663 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1664 #address-cells = <1>;
1875 #size-cells = 1665 #size-cells = <0>;
1876 status = "dis 1666 status = "disabled";
1877 }; 1667 };
1878 1668
1879 i2c0: i2c@1f000 { 1669 i2c0: i2c@1f000 {
1880 compatible = 1670 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1671 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1672 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1673 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1674 #address-cells = <1>;
1885 #size-cells = 1675 #size-cells = <0>;
1886 status = "dis 1676 status = "disabled";
1887 }; 1677 };
1888 1678
1889 uart_B: serial@23000 1679 uart_B: serial@23000 {
1890 compatible = 1680 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1681 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1682 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1683 status = "disabled";
1894 clocks = <&xt 1684 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1685 clock-names = "xtal", "pclk", "baud";
1896 }; 1686 };
1897 1687
1898 uart_A: serial@24000 1688 uart_A: serial@24000 {
1899 compatible = 1689 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1690 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1691 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1692 status = "disabled";
1903 clocks = <&xt 1693 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1694 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1695 };
1907 }; 1696 };
1908 1697
1909 apb: bus@ffe00000 { 1698 apb: bus@ffe00000 {
1910 compatible = "simple- 1699 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1700 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1701 #address-cells = <2>;
1913 #size-cells = <2>; 1702 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1703 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1704
1916 sd_emmc_b: mmc@5000 { !! 1705 sd_emmc_b: sd@5000 {
1917 compatible = 1706 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1707 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1708 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1709 status = "disabled";
1921 clocks = <&cl 1710 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1711 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1712 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1713 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1714 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1715 };
1927 1716
1928 sd_emmc_c: mmc@7000 { 1717 sd_emmc_c: mmc@7000 {
1929 compatible = 1718 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1719 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1720 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1721 status = "disabled";
1933 clocks = <&cl 1722 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1723 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1724 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1725 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1726 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; 1727 };
1964 }; 1728 };
1965 1729
1966 sram: sram@fffc0000 { 1730 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1731 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1732 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1733 #address-cells = <1>;
1970 #size-cells = <1>; 1734 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1735 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1736
1973 cpu_scp_lpri: scp-sra 1737 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1738 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1739 reg = <0x13000 0x400>;
1976 }; 1740 };
1977 1741
1978 cpu_scp_hpri: scp-sra 1742 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1743 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1744 reg = <0x13400 0x400>;
1981 }; 1745 };
1982 }; 1746 };
1983 }; 1747 };
1984 1748
1985 timer { 1749 timer {
1986 compatible = "arm,armv8-timer 1750 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1751 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1752 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1753 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1754 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1755 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1756 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1757 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1758 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1759 };
1996 1760
1997 xtal: xtal-clk { 1761 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1762 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1763 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1764 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1765 #clock-cells = <0>;
2002 }; 1766 };
2003 }; 1767 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.