1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; 120 secure-monitor = <&sm>;
132 }; 121 };
133 122
134 psci { 123 psci {
135 compatible = "arm,psci-1.0"; 124 compatible = "arm,psci-1.0";
136 method = "smc"; 125 method = "smc";
137 }; 126 };
138 127
139 reserved-memory { 128 reserved-memory {
140 #address-cells = <2>; 129 #address-cells = <2>;
141 #size-cells = <2>; 130 #size-cells = <2>;
142 ranges; 131 ranges;
143 132
144 /* 16 MiB reserved for Hardwar 133 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 134 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 135 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 136 no-map;
148 }; 137 };
149 138
150 /* Alternate 3 MiB reserved fo 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 140 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 141 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 142 no-map;
154 }; 143 };
155 }; 144 };
156 145
157 scpi { 146 scpi {
158 compatible = "arm,scpi-pre-1.0 147 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 148 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 150
162 scpi_clocks: clocks { 151 scpi_clocks: clocks {
163 compatible = "arm,scpi 152 compatible = "arm,scpi-clocks";
164 153
165 scpi_dvfs: clocks-0 { !! 154 scpi_dvfs: clock-controller {
166 compatible = " 155 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 156 #clock-cells = <1>;
168 clock-indices 157 clock-indices = <0>;
169 clock-output-n 158 clock-output-names = "vcpu";
170 }; 159 };
171 }; 160 };
172 161
173 scpi_sensors: sensors { 162 scpi_sensors: sensors {
174 compatible = "amlogic, !! 163 compatible = "amlogic,meson-gxbb-scpi-sensors";
175 #thermal-sensor-cells 164 #thermal-sensor-cells = <1>;
176 }; 165 };
177 }; 166 };
178 167
179 soc { 168 soc {
180 compatible = "simple-bus"; 169 compatible = "simple-bus";
181 #address-cells = <2>; 170 #address-cells = <2>;
182 #size-cells = <2>; 171 #size-cells = <2>;
183 ranges; 172 ranges;
184 173
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 174 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 175 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 176 "snps,dwmac-3.70a",
280 "snps,dwm 177 "snps,dwmac";
281 reg = <0x0 0xff3f0000 178 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 179 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 180 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 181 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 182 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 183 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ !! 184 <&clkc CLKID_MPLL2>;
288 <&clkc CLKID_ !! 185 clock-names = "stmmaceth", "clkin0", "clkin1";
289 clock-names = "stmmace <<
290 "timing- <<
291 rx-fifo-depth = <4096> 186 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 187 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc <<
294 status = "disabled"; 188 status = "disabled";
295 }; 189 };
296 190
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 191 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 192 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 193 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 194 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 195 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 196 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 197 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 198 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 199 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 200 status = "disabled";
316 }; 201 };
317 202
318 periphs: bus@ff634000 { 203 periphs: bus@ff634000 {
319 compatible = "simple-b 204 compatible = "simple-bus";
320 reg = <0x0 0xff634000 205 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 206 #address-cells = <2>;
322 #size-cells = <2>; 207 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 208 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 209
325 hwrng: rng@18 { 210 hwrng: rng@18 {
326 compatible = " 211 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 212 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 213 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 214 clock-names = "core";
330 }; 215 };
331 216
332 pinctrl_periphs: pinct 217 pinctrl_periphs: pinctrl@480 {
333 compatible = " 218 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 219 #address-cells = <2>;
335 #size-cells = 220 #size-cells = <2>;
336 ranges; 221 ranges;
337 222
338 gpio: bank@480 223 gpio: bank@480 {
339 reg = 224 reg = <0x0 0x00480 0x0 0x40>,
340 225 <0x0 0x004e8 0x0 0x14>,
341 226 <0x0 0x00520 0x0 0x14>,
342 227 <0x0 0x00430 0x0 0x3c>;
343 reg-na 228 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 229 gpio-controller;
345 #gpio- 230 #gpio-cells = <2>;
346 gpio-r 231 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 232 };
348 233
349 i2c0_pins: i2c 234 i2c0_pins: i2c0 {
350 mux { 235 mux {
351 236 groups = "i2c0_sck",
352 237 "i2c0_sda";
353 238 function = "i2c0";
354 239 bias-disable;
355 }; 240 };
356 }; 241 };
357 242
358 i2c1_x_pins: i 243 i2c1_x_pins: i2c1_x {
359 mux { 244 mux {
360 245 groups = "i2c1_sck_x",
361 246 "i2c1_sda_x";
362 247 function = "i2c1";
363 248 bias-disable;
364 }; 249 };
365 }; 250 };
366 251
367 i2c1_z_pins: i 252 i2c1_z_pins: i2c1_z {
368 mux { 253 mux {
369 254 groups = "i2c1_sck_z",
370 255 "i2c1_sda_z";
371 256 function = "i2c1";
372 257 bias-disable;
373 }; 258 };
374 }; 259 };
375 260
376 i2c2_a_pins: i 261 i2c2_a_pins: i2c2_a {
377 mux { 262 mux {
378 263 groups = "i2c2_sck_a",
379 264 "i2c2_sda_a";
380 265 function = "i2c2";
381 266 bias-disable;
382 }; 267 };
383 }; 268 };
384 269
385 i2c2_x_pins: i 270 i2c2_x_pins: i2c2_x {
386 mux { 271 mux {
387 272 groups = "i2c2_sck_x",
388 273 "i2c2_sda_x";
389 274 function = "i2c2";
390 275 bias-disable;
391 }; 276 };
392 }; 277 };
393 278
394 i2c3_a6_pins: 279 i2c3_a6_pins: i2c3_a6 {
395 mux { 280 mux {
396 281 groups = "i2c3_sda_a6",
397 282 "i2c3_sck_a7";
398 283 function = "i2c3";
399 284 bias-disable;
400 }; 285 };
401 }; 286 };
402 287
403 i2c3_a12_pins: 288 i2c3_a12_pins: i2c3_a12 {
404 mux { 289 mux {
405 290 groups = "i2c3_sda_a12",
406 291 "i2c3_sck_a13";
407 292 function = "i2c3";
408 293 bias-disable;
409 }; 294 };
410 }; 295 };
411 296
412 i2c3_a19_pins: 297 i2c3_a19_pins: i2c3_a19 {
413 mux { 298 mux {
414 299 groups = "i2c3_sda_a19",
415 300 "i2c3_sck_a20";
416 301 function = "i2c3";
417 302 bias-disable;
418 }; 303 };
419 }; 304 };
420 305
421 emmc_pins: emm 306 emmc_pins: emmc {
422 mux-0 307 mux-0 {
423 308 groups = "emmc_nand_d0",
424 309 "emmc_nand_d1",
425 310 "emmc_nand_d2",
426 311 "emmc_nand_d3",
427 312 "emmc_nand_d4",
428 313 "emmc_nand_d5",
429 314 "emmc_nand_d6",
430 315 "emmc_nand_d7",
431 316 "emmc_cmd";
432 317 function = "emmc";
433 318 bias-pull-up;
434 }; 319 };
435 320
436 mux-1 321 mux-1 {
437 322 groups = "emmc_clk";
438 323 function = "emmc";
439 324 bias-disable;
440 }; 325 };
441 }; 326 };
442 327
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 328 emmc_ds_pins: emmc_ds {
465 mux { 329 mux {
466 330 groups = "emmc_ds";
467 331 function = "emmc";
468 332 bias-pull-down;
469 }; 333 };
470 }; 334 };
471 335
472 emmc_clk_gate_ 336 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 337 mux {
474 338 groups = "BOOT_8";
475 339 function = "gpio_periphs";
476 340 bias-pull-down;
477 }; 341 };
478 }; 342 };
479 343
480 eth_rgmii_x_pi 344 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 345 mux {
482 346 groups = "eth_mdio_x",
483 347 "eth_mdc_x",
484 348 "eth_rgmii_rx_clk_x",
485 349 "eth_rx_dv_x",
486 350 "eth_rxd0_x",
487 351 "eth_rxd1_x",
488 352 "eth_rxd2_rgmii",
489 353 "eth_rxd3_rgmii",
490 354 "eth_rgmii_tx_clk",
491 355 "eth_txen_x",
492 356 "eth_txd0_x",
493 357 "eth_txd1_x",
494 358 "eth_txd2_rgmii",
495 359 "eth_txd3_rgmii";
496 360 function = "eth";
497 361 bias-disable;
498 }; 362 };
499 }; 363 };
500 364
501 eth_rgmii_y_pi 365 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 366 mux {
503 367 groups = "eth_mdio_y",
504 368 "eth_mdc_y",
505 369 "eth_rgmii_rx_clk_y",
506 370 "eth_rx_dv_y",
507 371 "eth_rxd0_y",
508 372 "eth_rxd1_y",
509 373 "eth_rxd2_rgmii",
510 374 "eth_rxd3_rgmii",
511 375 "eth_rgmii_tx_clk",
512 376 "eth_txen_y",
513 377 "eth_txd0_y",
514 378 "eth_txd1_y",
515 379 "eth_txd2_rgmii",
516 380 "eth_txd3_rgmii";
517 381 function = "eth";
518 382 bias-disable;
519 }; 383 };
520 }; 384 };
521 385
522 eth_rmii_x_pin 386 eth_rmii_x_pins: eth-x-rmii {
523 mux { 387 mux {
524 388 groups = "eth_mdio_x",
525 389 "eth_mdc_x",
526 390 "eth_rgmii_rx_clk_x",
527 391 "eth_rx_dv_x",
528 392 "eth_rxd0_x",
529 393 "eth_rxd1_x",
530 394 "eth_txen_x",
531 395 "eth_txd0_x",
532 396 "eth_txd1_x";
533 397 function = "eth";
534 398 bias-disable;
535 }; 399 };
536 }; 400 };
537 401
538 eth_rmii_y_pin 402 eth_rmii_y_pins: eth-y-rmii {
539 mux { 403 mux {
540 404 groups = "eth_mdio_y",
541 405 "eth_mdc_y",
542 406 "eth_rgmii_rx_clk_y",
543 407 "eth_rx_dv_y",
544 408 "eth_rxd0_y",
545 409 "eth_rxd1_y",
546 410 "eth_txen_y",
547 411 "eth_txd0_y",
548 412 "eth_txd1_y";
549 413 function = "eth";
550 414 bias-disable;
551 }; 415 };
552 }; 416 };
553 417
554 mclk_b_pins: m 418 mclk_b_pins: mclk_b {
555 mux { 419 mux {
556 420 groups = "mclk_b";
557 421 function = "mclk_b";
558 422 bias-disable;
559 }; 423 };
560 }; 424 };
561 425
562 mclk_c_pins: m 426 mclk_c_pins: mclk_c {
563 mux { 427 mux {
564 428 groups = "mclk_c";
565 429 function = "mclk_c";
566 430 bias-disable;
567 }; 431 };
568 }; 432 };
569 433
570 pdm_dclk_a14_p 434 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 435 mux {
572 436 groups = "pdm_dclk_a14";
573 437 function = "pdm";
574 438 bias-disable;
575 }; 439 };
576 }; 440 };
577 441
578 pdm_dclk_a19_p 442 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 443 mux {
580 444 groups = "pdm_dclk_a19";
581 445 function = "pdm";
582 446 bias-disable;
583 }; 447 };
584 }; 448 };
585 449
586 pdm_din0_pins: 450 pdm_din0_pins: pdm_din0 {
587 mux { 451 mux {
588 452 groups = "pdm_din0";
589 453 function = "pdm";
590 454 bias-disable;
591 }; 455 };
592 }; 456 };
593 457
594 pdm_din1_pins: 458 pdm_din1_pins: pdm_din1 {
595 mux { 459 mux {
596 460 groups = "pdm_din1";
597 461 function = "pdm";
598 462 bias-disable;
599 }; 463 };
600 }; 464 };
601 465
602 pdm_din2_pins: 466 pdm_din2_pins: pdm_din2 {
603 mux { 467 mux {
604 468 groups = "pdm_din2";
605 469 function = "pdm";
606 470 bias-disable;
607 }; 471 };
608 }; 472 };
609 473
610 pdm_din3_pins: 474 pdm_din3_pins: pdm_din3 {
611 mux { 475 mux {
612 476 groups = "pdm_din3";
613 477 function = "pdm";
614 478 bias-disable;
615 }; 479 };
616 }; 480 };
617 481
618 pwm_a_a_pins: 482 pwm_a_a_pins: pwm_a_a {
619 mux { 483 mux {
620 484 groups = "pwm_a_a";
621 485 function = "pwm_a";
622 486 bias-disable;
623 }; 487 };
624 }; 488 };
625 489
626 pwm_a_x18_pins 490 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 491 mux {
628 492 groups = "pwm_a_x18";
629 493 function = "pwm_a";
630 494 bias-disable;
631 }; 495 };
632 }; 496 };
633 497
634 pwm_a_x20_pins 498 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 499 mux {
636 500 groups = "pwm_a_x20";
637 501 function = "pwm_a";
638 502 bias-disable;
639 }; 503 };
640 }; 504 };
641 505
642 pwm_a_z_pins: 506 pwm_a_z_pins: pwm_a_z {
643 mux { 507 mux {
644 508 groups = "pwm_a_z";
645 509 function = "pwm_a";
646 510 bias-disable;
647 }; 511 };
648 }; 512 };
649 513
650 pwm_b_a_pins: 514 pwm_b_a_pins: pwm_b_a {
651 mux { 515 mux {
652 516 groups = "pwm_b_a";
653 517 function = "pwm_b";
654 518 bias-disable;
655 }; 519 };
656 }; 520 };
657 521
658 pwm_b_x_pins: 522 pwm_b_x_pins: pwm_b_x {
659 mux { 523 mux {
660 524 groups = "pwm_b_x";
661 525 function = "pwm_b";
662 526 bias-disable;
663 }; 527 };
664 }; 528 };
665 529
666 pwm_b_z_pins: 530 pwm_b_z_pins: pwm_b_z {
667 mux { 531 mux {
668 532 groups = "pwm_b_z";
669 533 function = "pwm_b";
670 534 bias-disable;
671 }; 535 };
672 }; 536 };
673 537
674 pwm_c_a_pins: 538 pwm_c_a_pins: pwm_c_a {
675 mux { 539 mux {
676 540 groups = "pwm_c_a";
677 541 function = "pwm_c";
678 542 bias-disable;
679 }; 543 };
680 }; 544 };
681 545
682 pwm_c_x10_pins 546 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 547 mux {
684 548 groups = "pwm_c_x10";
685 549 function = "pwm_c";
686 550 bias-disable;
687 }; 551 };
688 }; 552 };
689 553
690 pwm_c_x17_pins 554 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 555 mux {
692 556 groups = "pwm_c_x17";
693 557 function = "pwm_c";
694 558 bias-disable;
695 }; 559 };
696 }; 560 };
697 561
698 pwm_d_x11_pins 562 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 563 mux {
700 564 groups = "pwm_d_x11";
701 565 function = "pwm_d";
702 566 bias-disable;
703 }; 567 };
704 }; 568 };
705 569
706 pwm_d_x16_pins 570 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 571 mux {
708 572 groups = "pwm_d_x16";
709 573 function = "pwm_d";
710 574 bias-disable;
711 }; 575 };
712 }; 576 };
713 577
714 sdio_pins: sdi 578 sdio_pins: sdio {
715 mux-0 579 mux-0 {
716 580 groups = "sdio_d0",
717 581 "sdio_d1",
718 582 "sdio_d2",
719 583 "sdio_d3",
720 584 "sdio_cmd";
721 585 function = "sdio";
722 586 bias-pull-up;
723 }; 587 };
724 588
725 mux-1 589 mux-1 {
726 590 groups = "sdio_clk";
727 591 function = "sdio";
728 592 bias-disable;
729 }; 593 };
730 }; 594 };
731 595
732 sdio_clk_gate_ 596 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 597 mux {
734 598 groups = "GPIOX_4";
735 599 function = "gpio_periphs";
736 600 bias-pull-down;
737 }; 601 };
738 }; 602 };
739 603
740 spdif_in_z_pin 604 spdif_in_z_pins: spdif_in_z {
741 mux { 605 mux {
742 606 groups = "spdif_in_z";
743 607 function = "spdif_in";
744 608 bias-disable;
745 }; 609 };
746 }; 610 };
747 611
748 spdif_in_a1_pi 612 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 613 mux {
750 614 groups = "spdif_in_a1";
751 615 function = "spdif_in";
752 616 bias-disable;
753 }; 617 };
754 }; 618 };
755 619
756 spdif_in_a7_pi 620 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 621 mux {
758 622 groups = "spdif_in_a7";
759 623 function = "spdif_in";
760 624 bias-disable;
761 }; 625 };
762 }; 626 };
763 627
764 spdif_in_a19_p 628 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 629 mux {
766 630 groups = "spdif_in_a19";
767 631 function = "spdif_in";
768 632 bias-disable;
769 }; 633 };
770 }; 634 };
771 635
772 spdif_in_a20_p 636 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 637 mux {
774 638 groups = "spdif_in_a20";
775 639 function = "spdif_in";
776 640 bias-disable;
777 }; 641 };
778 }; 642 };
779 643
780 spdif_out_a1_p 644 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 645 mux {
782 646 groups = "spdif_out_a1";
783 647 function = "spdif_out";
784 648 bias-disable;
785 }; 649 };
786 }; 650 };
787 651
788 spdif_out_a11_ 652 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 653 mux {
790 654 groups = "spdif_out_a11";
791 655 function = "spdif_out";
792 656 bias-disable;
793 }; 657 };
794 }; 658 };
795 659
796 spdif_out_a19_ 660 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 661 mux {
798 662 groups = "spdif_out_a19";
799 663 function = "spdif_out";
800 664 bias-disable;
801 }; 665 };
802 }; 666 };
803 667
804 spdif_out_a20_ 668 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 669 mux {
806 670 groups = "spdif_out_a20";
807 671 function = "spdif_out";
808 672 bias-disable;
809 }; 673 };
810 }; 674 };
811 675
812 spdif_out_z_pi 676 spdif_out_z_pins: spdif_out_z {
813 mux { 677 mux {
814 678 groups = "spdif_out_z";
815 679 function = "spdif_out";
816 680 bias-disable;
817 }; 681 };
818 }; 682 };
819 683
820 spi0_pins: spi 684 spi0_pins: spi0 {
821 mux { 685 mux {
822 686 groups = "spi0_miso",
823 687 "spi0_mosi",
824 688 "spi0_clk";
825 689 function = "spi0";
826 690 bias-disable;
827 }; 691 };
828 }; 692 };
829 693
830 spi0_ss0_pins: 694 spi0_ss0_pins: spi0_ss0 {
831 mux { 695 mux {
832 696 groups = "spi0_ss0";
833 697 function = "spi0";
834 698 bias-disable;
835 }; 699 };
836 }; 700 };
837 701
838 spi0_ss1_pins: 702 spi0_ss1_pins: spi0_ss1 {
839 mux { 703 mux {
840 704 groups = "spi0_ss1";
841 705 function = "spi0";
842 706 bias-disable;
843 }; 707 };
844 }; 708 };
845 709
846 spi0_ss2_pins: 710 spi0_ss2_pins: spi0_ss2 {
847 mux { 711 mux {
848 712 groups = "spi0_ss2";
849 713 function = "spi0";
850 714 bias-disable;
851 }; 715 };
852 }; 716 };
853 717
854 spi1_a_pins: s 718 spi1_a_pins: spi1_a {
855 mux { 719 mux {
856 720 groups = "spi1_miso_a",
857 721 "spi1_mosi_a",
858 722 "spi1_clk_a";
859 723 function = "spi1";
860 724 bias-disable;
861 }; 725 };
862 }; 726 };
863 727
864 spi1_ss0_a_pin 728 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 729 mux {
866 730 groups = "spi1_ss0_a";
867 731 function = "spi1";
868 732 bias-disable;
869 }; 733 };
870 }; 734 };
871 735
872 spi1_ss1_pins: 736 spi1_ss1_pins: spi1_ss1 {
873 mux { 737 mux {
874 738 groups = "spi1_ss1";
875 739 function = "spi1";
876 740 bias-disable;
877 }; 741 };
878 }; 742 };
879 743
880 spi1_x_pins: s 744 spi1_x_pins: spi1_x {
881 mux { 745 mux {
882 746 groups = "spi1_miso_x",
883 747 "spi1_mosi_x",
884 748 "spi1_clk_x";
885 749 function = "spi1";
886 750 bias-disable;
887 }; 751 };
888 }; 752 };
889 753
890 spi1_ss0_x_pin 754 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 755 mux {
892 756 groups = "spi1_ss0_x";
893 757 function = "spi1";
894 758 bias-disable;
895 }; 759 };
896 }; 760 };
897 761
898 tdma_din0_pins 762 tdma_din0_pins: tdma_din0 {
899 mux { 763 mux {
900 764 groups = "tdma_din0";
901 765 function = "tdma";
902 766 bias-disable;
903 }; 767 };
904 }; 768 };
905 769
906 tdma_dout0_x14 770 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 771 mux {
908 772 groups = "tdma_dout0_x14";
909 773 function = "tdma";
910 774 bias-disable;
911 }; 775 };
912 }; 776 };
913 777
914 tdma_dout0_x15 778 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 779 mux {
916 780 groups = "tdma_dout0_x15";
917 781 function = "tdma";
918 782 bias-disable;
919 }; 783 };
920 }; 784 };
921 785
922 tdma_dout1_pin 786 tdma_dout1_pins: tdma_dout1 {
923 mux { 787 mux {
924 788 groups = "tdma_dout1";
925 789 function = "tdma";
926 790 bias-disable;
927 }; 791 };
928 }; 792 };
929 793
930 tdma_din1_pins 794 tdma_din1_pins: tdma_din1 {
931 mux { 795 mux {
932 796 groups = "tdma_din1";
933 797 function = "tdma";
934 798 bias-disable;
935 }; 799 };
936 }; 800 };
937 801
938 tdma_fs_pins: 802 tdma_fs_pins: tdma_fs {
939 mux { 803 mux {
940 804 groups = "tdma_fs";
941 805 function = "tdma";
942 806 bias-disable;
943 }; 807 };
944 }; 808 };
945 809
946 tdma_fs_slv_pi 810 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 811 mux {
948 812 groups = "tdma_fs_slv";
949 813 function = "tdma";
950 814 bias-disable;
951 }; 815 };
952 }; 816 };
953 817
954 tdma_sclk_pins 818 tdma_sclk_pins: tdma_sclk {
955 mux { 819 mux {
956 820 groups = "tdma_sclk";
957 821 function = "tdma";
958 822 bias-disable;
959 }; 823 };
960 }; 824 };
961 825
962 tdma_sclk_slv_ 826 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 827 mux {
964 828 groups = "tdma_sclk_slv";
965 829 function = "tdma";
966 830 bias-disable;
967 }; 831 };
968 }; 832 };
969 833
970 tdmb_din0_pins 834 tdmb_din0_pins: tdmb_din0 {
971 mux { 835 mux {
972 836 groups = "tdmb_din0";
973 837 function = "tdmb";
974 838 bias-disable;
975 }; 839 };
976 }; 840 };
977 841
978 tdmb_din1_pins 842 tdmb_din1_pins: tdmb_din1 {
979 mux { 843 mux {
980 844 groups = "tdmb_din1";
981 845 function = "tdmb";
982 846 bias-disable;
983 }; 847 };
984 }; 848 };
985 849
986 tdmb_din2_pins 850 tdmb_din2_pins: tdmb_din2 {
987 mux { 851 mux {
988 852 groups = "tdmb_din2";
989 853 function = "tdmb";
990 854 bias-disable;
991 }; 855 };
992 }; 856 };
993 857
994 tdmb_din3_pins 858 tdmb_din3_pins: tdmb_din3 {
995 mux { 859 mux {
996 860 groups = "tdmb_din3";
997 861 function = "tdmb";
998 862 bias-disable;
999 }; 863 };
1000 }; 864 };
1001 865
1002 tdmb_dout0_pi 866 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 867 mux {
1004 868 groups = "tdmb_dout0";
1005 869 function = "tdmb";
1006 870 bias-disable;
1007 }; 871 };
1008 }; 872 };
1009 873
1010 tdmb_dout1_pi 874 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 875 mux {
1012 876 groups = "tdmb_dout1";
1013 877 function = "tdmb";
1014 878 bias-disable;
1015 }; 879 };
1016 }; 880 };
1017 881
1018 tdmb_dout2_pi 882 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 883 mux {
1020 884 groups = "tdmb_dout2";
1021 885 function = "tdmb";
1022 886 bias-disable;
1023 }; 887 };
1024 }; 888 };
1025 889
1026 tdmb_dout3_pi 890 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 891 mux {
1028 892 groups = "tdmb_dout3";
1029 893 function = "tdmb";
1030 894 bias-disable;
1031 }; 895 };
1032 }; 896 };
1033 897
1034 tdmb_fs_pins: 898 tdmb_fs_pins: tdmb_fs {
1035 mux { 899 mux {
1036 900 groups = "tdmb_fs";
1037 901 function = "tdmb";
1038 902 bias-disable;
1039 }; 903 };
1040 }; 904 };
1041 905
1042 tdmb_fs_slv_p 906 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 907 mux {
1044 908 groups = "tdmb_fs_slv";
1045 909 function = "tdmb";
1046 910 bias-disable;
1047 }; 911 };
1048 }; 912 };
1049 913
1050 tdmb_sclk_pin 914 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 915 mux {
1052 916 groups = "tdmb_sclk";
1053 917 function = "tdmb";
1054 918 bias-disable;
1055 }; 919 };
1056 }; 920 };
1057 921
1058 tdmb_sclk_slv 922 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 923 mux {
1060 924 groups = "tdmb_sclk_slv";
1061 925 function = "tdmb";
1062 926 bias-disable;
1063 }; 927 };
1064 }; 928 };
1065 929
1066 tdmc_fs_pins: 930 tdmc_fs_pins: tdmc_fs {
1067 mux { 931 mux {
1068 932 groups = "tdmc_fs";
1069 933 function = "tdmc";
1070 934 bias-disable;
1071 }; 935 };
1072 }; 936 };
1073 937
1074 tdmc_fs_slv_p 938 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 939 mux {
1076 940 groups = "tdmc_fs_slv";
1077 941 function = "tdmc";
1078 942 bias-disable;
1079 }; 943 };
1080 }; 944 };
1081 945
1082 tdmc_sclk_pin 946 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 947 mux {
1084 948 groups = "tdmc_sclk";
1085 949 function = "tdmc";
1086 950 bias-disable;
1087 }; 951 };
1088 }; 952 };
1089 953
1090 tdmc_sclk_slv 954 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 955 mux {
1092 956 groups = "tdmc_sclk_slv";
1093 957 function = "tdmc";
1094 958 bias-disable;
1095 }; 959 };
1096 }; 960 };
1097 961
1098 tdmc_din0_pin 962 tdmc_din0_pins: tdmc_din0 {
1099 mux { 963 mux {
1100 964 groups = "tdmc_din0";
1101 965 function = "tdmc";
1102 966 bias-disable;
1103 }; 967 };
1104 }; 968 };
1105 969
1106 tdmc_din1_pin 970 tdmc_din1_pins: tdmc_din1 {
1107 mux { 971 mux {
1108 972 groups = "tdmc_din1";
1109 973 function = "tdmc";
1110 974 bias-disable;
1111 }; 975 };
1112 }; 976 };
1113 977
1114 tdmc_din2_pin 978 tdmc_din2_pins: tdmc_din2 {
1115 mux { 979 mux {
1116 980 groups = "tdmc_din2";
1117 981 function = "tdmc";
1118 982 bias-disable;
1119 }; 983 };
1120 }; 984 };
1121 985
1122 tdmc_din3_pin 986 tdmc_din3_pins: tdmc_din3 {
1123 mux { 987 mux {
1124 988 groups = "tdmc_din3";
1125 989 function = "tdmc";
1126 990 bias-disable;
1127 }; 991 };
1128 }; 992 };
1129 993
1130 tdmc_dout0_pi 994 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 995 mux {
1132 996 groups = "tdmc_dout0";
1133 997 function = "tdmc";
1134 998 bias-disable;
1135 }; 999 };
1136 }; 1000 };
1137 1001
1138 tdmc_dout1_pi 1002 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1003 mux {
1140 1004 groups = "tdmc_dout1";
1141 1005 function = "tdmc";
1142 1006 bias-disable;
1143 }; 1007 };
1144 }; 1008 };
1145 1009
1146 tdmc_dout2_pi 1010 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1011 mux {
1148 1012 groups = "tdmc_dout2";
1149 1013 function = "tdmc";
1150 1014 bias-disable;
1151 }; 1015 };
1152 }; 1016 };
1153 1017
1154 tdmc_dout3_pi 1018 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1019 mux {
1156 1020 groups = "tdmc_dout3";
1157 1021 function = "tdmc";
1158 1022 bias-disable;
1159 }; 1023 };
1160 }; 1024 };
1161 1025
1162 uart_a_pins: 1026 uart_a_pins: uart_a {
1163 mux { 1027 mux {
1164 1028 groups = "uart_tx_a",
1165 1029 "uart_rx_a";
1166 1030 function = "uart_a";
1167 1031 bias-disable;
1168 }; 1032 };
1169 }; 1033 };
1170 1034
1171 uart_a_cts_rt 1035 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1036 mux {
1173 1037 groups = "uart_cts_a",
1174 1038 "uart_rts_a";
1175 1039 function = "uart_a";
1176 1040 bias-disable;
1177 }; 1041 };
1178 }; 1042 };
1179 1043
1180 uart_b_x_pins 1044 uart_b_x_pins: uart_b_x {
1181 mux { 1045 mux {
1182 1046 groups = "uart_tx_b_x",
1183 1047 "uart_rx_b_x";
1184 1048 function = "uart_b";
1185 1049 bias-disable;
1186 }; 1050 };
1187 }; 1051 };
1188 1052
1189 uart_b_x_cts_ 1053 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1054 mux {
1191 1055 groups = "uart_cts_b_x",
1192 1056 "uart_rts_b_x";
1193 1057 function = "uart_b";
1194 1058 bias-disable;
1195 }; 1059 };
1196 }; 1060 };
1197 1061
1198 uart_b_z_pins 1062 uart_b_z_pins: uart_b_z {
1199 mux { 1063 mux {
1200 1064 groups = "uart_tx_b_z",
1201 1065 "uart_rx_b_z";
1202 1066 function = "uart_b";
1203 1067 bias-disable;
1204 }; 1068 };
1205 }; 1069 };
1206 1070
1207 uart_b_z_cts_ 1071 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1072 mux {
1209 1073 groups = "uart_cts_b_z",
1210 1074 "uart_rts_b_z";
1211 1075 function = "uart_b";
1212 1076 bias-disable;
1213 }; 1077 };
1214 }; 1078 };
1215 1079
1216 uart_ao_b_z_p 1080 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1081 mux {
1218 1082 groups = "uart_ao_tx_b_z",
1219 1083 "uart_ao_rx_b_z";
1220 1084 function = "uart_ao_b_z";
1221 1085 bias-disable;
1222 }; 1086 };
1223 }; 1087 };
1224 1088
1225 uart_ao_b_z_c 1089 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1090 mux {
1227 1091 groups = "uart_ao_cts_b_z",
1228 1092 "uart_ao_rts_b_z";
1229 1093 function = "uart_ao_b_z";
1230 1094 bias-disable;
1231 }; 1095 };
1232 }; 1096 };
1233 }; 1097 };
1234 }; 1098 };
1235 1099
1236 hiubus: bus@ff63c000 { 1100 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1101 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1102 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1103 #address-cells = <2>;
1240 #size-cells = <2>; 1104 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1105 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1106
1243 sysctrl: system-contr 1107 sysctrl: system-controller@0 {
1244 compatible = 1108 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1109 "simple-mfd", "syscon";
1246 reg = <0 0 0 1110 reg = <0 0 0 0x400>;
1247 1111
1248 clkc: clock-c 1112 clkc: clock-controller {
1249 compa 1113 compatible = "amlogic,axg-clkc";
1250 #cloc 1114 #clock-cells = <1>;
1251 clock 1115 clocks = <&xtal>;
1252 clock 1116 clock-names = "xtal";
1253 }; 1117 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1118 };
1301 }; 1119 };
1302 1120
1303 mailbox: mailbox@ff63c404 { 1121 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1122 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1123 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1124 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1125 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1126 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1127 #mbox-cells = <1>;
1310 }; 1128 };
1311 1129
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1130 audio: bus@ff642000 {
1326 compatible = "simple- 1131 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1132 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1133 #address-cells = <2>;
1329 #size-cells = <2>; 1134 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1135 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1136
1332 clkc_audio: clock-con 1137 clkc_audio: clock-controller@0 {
1333 compatible = 1138 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1139 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1140 #clock-cells = <1>;
1336 1141
1337 clocks = <&cl 1142 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1143 <&clkc CLKID_MPLL0>,
1339 <&cl 1144 <&clkc CLKID_MPLL1>,
1340 <&cl 1145 <&clkc CLKID_MPLL2>,
1341 <&cl 1146 <&clkc CLKID_MPLL3>,
1342 <&cl 1147 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1148 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1149 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1150 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1151 clock-names = "pclk",
1347 1152 "mst_in0",
1348 1153 "mst_in1",
1349 1154 "mst_in2",
1350 1155 "mst_in3",
1351 1156 "mst_in4",
1352 1157 "mst_in5",
1353 1158 "mst_in6",
1354 1159 "mst_in7";
1355 1160
1356 resets = <&re 1161 resets = <&reset RESET_AUDIO>;
1357 }; 1162 };
1358 1163
1359 toddr_a: audio-contro 1164 toddr_a: audio-controller@100 {
1360 compatible = 1165 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1166 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1167 #sound-dai-cells = <0>;
1363 sound-name-pr 1168 sound-name-prefix = "TODDR_A";
1364 interrupts = 1169 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1170 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1171 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1172 amlogic,fifo-depth = <512>;
1368 status = "dis 1173 status = "disabled";
1369 }; 1174 };
1370 1175
1371 toddr_b: audio-contro 1176 toddr_b: audio-controller@140 {
1372 compatible = 1177 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1178 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1179 #sound-dai-cells = <0>;
1375 sound-name-pr 1180 sound-name-prefix = "TODDR_B";
1376 interrupts = 1181 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1182 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1183 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1184 amlogic,fifo-depth = <256>;
1380 status = "dis 1185 status = "disabled";
1381 }; 1186 };
1382 1187
1383 toddr_c: audio-contro 1188 toddr_c: audio-controller@180 {
1384 compatible = 1189 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1190 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1191 #sound-dai-cells = <0>;
1387 sound-name-pr 1192 sound-name-prefix = "TODDR_C";
1388 interrupts = 1193 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1194 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1195 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1196 amlogic,fifo-depth = <256>;
1392 status = "dis 1197 status = "disabled";
1393 }; 1198 };
1394 1199
1395 frddr_a: audio-contro 1200 frddr_a: audio-controller@1c0 {
1396 compatible = 1201 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1202 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1203 #sound-dai-cells = <0>;
1399 sound-name-pr 1204 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1205 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1206 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1207 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1208 amlogic,fifo-depth = <512>;
1404 status = "dis 1209 status = "disabled";
1405 }; 1210 };
1406 1211
1407 frddr_b: audio-contro 1212 frddr_b: audio-controller@200 {
1408 compatible = 1213 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1214 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1215 #sound-dai-cells = <0>;
1411 sound-name-pr 1216 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1217 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1218 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1219 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1220 amlogic,fifo-depth = <256>;
1416 status = "dis 1221 status = "disabled";
1417 }; 1222 };
1418 1223
1419 frddr_c: audio-contro 1224 frddr_c: audio-controller@240 {
1420 compatible = 1225 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1226 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1227 #sound-dai-cells = <0>;
1423 sound-name-pr 1228 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1229 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1230 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1231 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1232 amlogic,fifo-depth = <256>;
1428 status = "dis 1233 status = "disabled";
1429 }; 1234 };
1430 1235
1431 arb: reset-controller 1236 arb: reset-controller@280 {
1432 compatible = 1237 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1238 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1239 #reset-cells = <1>;
1435 clocks = <&cl 1240 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1241 };
1437 1242
1438 tdmin_a: audio-contro 1243 tdmin_a: audio-controller@300 {
1439 compatible = 1244 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1245 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1246 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1247 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1248 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1249 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1250 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1251 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1252 clock-names = "pclk", "sclk", "sclk_sel",
1448 1253 "lrclk", "lrclk_sel";
1449 status = "dis 1254 status = "disabled";
1450 }; 1255 };
1451 1256
1452 tdmin_b: audio-contro 1257 tdmin_b: audio-controller@340 {
1453 compatible = 1258 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1259 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1260 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1261 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1262 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1263 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1264 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1265 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1266 clock-names = "pclk", "sclk", "sclk_sel",
1462 1267 "lrclk", "lrclk_sel";
1463 status = "dis 1268 status = "disabled";
1464 }; 1269 };
1465 1270
1466 tdmin_c: audio-contro 1271 tdmin_c: audio-controller@380 {
1467 compatible = 1272 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1273 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1274 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1275 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1276 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1277 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1278 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1279 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1280 clock-names = "pclk", "sclk", "sclk_sel",
1476 1281 "lrclk", "lrclk_sel";
1477 status = "dis 1282 status = "disabled";
1478 }; 1283 };
1479 1284
1480 tdmin_lb: audio-contr 1285 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1286 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1287 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1288 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1289 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1290 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1291 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1292 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1293 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1294 clock-names = "pclk", "sclk", "sclk_sel",
1490 1295 "lrclk", "lrclk_sel";
1491 status = "dis 1296 status = "disabled";
1492 }; 1297 };
1493 1298
1494 spdifin: audio-contro 1299 spdifin: audio-controller@400 {
1495 compatible = 1300 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1301 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1302 #sound-dai-cells = <0>;
1498 sound-name-pr 1303 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1304 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1305 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1306 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1307 clock-names = "pclk", "refclk";
1503 status = "dis 1308 status = "disabled";
1504 }; 1309 };
1505 1310
1506 spdifout: audio-contr 1311 spdifout: audio-controller@480 {
1507 compatible = 1312 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1313 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1314 #sound-dai-cells = <0>;
1510 sound-name-pr 1315 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1316 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1317 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1318 clock-names = "pclk", "mclk";
1514 status = "dis 1319 status = "disabled";
1515 }; 1320 };
1516 1321
1517 tdmout_a: audio-contr 1322 tdmout_a: audio-controller@500 {
1518 compatible = 1323 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1324 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1325 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1326 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1327 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1328 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1329 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1330 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1331 clock-names = "pclk", "sclk", "sclk_sel",
1527 1332 "lrclk", "lrclk_sel";
1528 status = "dis 1333 status = "disabled";
1529 }; 1334 };
1530 1335
1531 tdmout_b: audio-contr 1336 tdmout_b: audio-controller@540 {
1532 compatible = 1337 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1338 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1339 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1340 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1341 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1342 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1343 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1344 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1345 clock-names = "pclk", "sclk", "sclk_sel",
1541 1346 "lrclk", "lrclk_sel";
1542 status = "dis 1347 status = "disabled";
1543 }; 1348 };
1544 1349
1545 tdmout_c: audio-contr 1350 tdmout_c: audio-controller@580 {
1546 compatible = 1351 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1352 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1353 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1354 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1355 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1356 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1357 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1358 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1359 clock-names = "pclk", "sclk", "sclk_sel",
1555 1360 "lrclk", "lrclk_sel";
1556 status = "dis 1361 status = "disabled";
1557 }; 1362 };
1558 }; 1363 };
1559 1364
1560 aobus: bus@ff800000 { 1365 aobus: bus@ff800000 {
1561 compatible = "simple- 1366 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1367 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1368 #address-cells = <2>;
1564 #size-cells = <2>; 1369 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1370 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1371
1567 sysctrl_AO: sys-ctrl@ 1372 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1373 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1374 reg = <0x0 0x0 0x0 0x100>;
1570 1375
1571 clkc_AO: cloc 1376 clkc_AO: clock-controller {
1572 compa 1377 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1378 #clock-cells = <1>;
1574 #rese 1379 #reset-cells = <1>;
1575 clock 1380 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1381 clock-names = "xtal", "mpeg-clk";
1577 }; 1382 };
1578 }; 1383 };
1579 1384
1580 pinctrl_aobus: pinctr 1385 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1386 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1387 #address-cells = <2>;
1583 #size-cells = 1388 #size-cells = <2>;
1584 ranges; 1389 ranges;
1585 1390
1586 gpio_ao: bank 1391 gpio_ao: bank@14 {
1587 reg = 1392 reg = <0x0 0x00014 0x0 0x8>,
1588 1393 <0x0 0x0002c 0x0 0x4>,
1589 1394 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1395 reg-names = "mux", "pull", "gpio";
1591 gpio- 1396 gpio-controller;
1592 #gpio 1397 #gpio-cells = <2>;
1593 gpio- 1398 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1399 };
1595 1400
1596 i2c_ao_sck_4_ 1401 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1402 mux {
1598 1403 groups = "i2c_ao_sck_4";
1599 1404 function = "i2c_ao";
1600 1405 bias-disable;
1601 }; 1406 };
1602 }; 1407 };
1603 1408
1604 i2c_ao_sck_8_ 1409 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1410 mux {
1606 1411 groups = "i2c_ao_sck_8";
1607 1412 function = "i2c_ao";
1608 1413 bias-disable;
1609 }; 1414 };
1610 }; 1415 };
1611 1416
1612 i2c_ao_sck_10 1417 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1418 mux {
1614 1419 groups = "i2c_ao_sck_10";
1615 1420 function = "i2c_ao";
1616 1421 bias-disable;
1617 }; 1422 };
1618 }; 1423 };
1619 1424
1620 i2c_ao_sda_5_ 1425 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1426 mux {
1622 1427 groups = "i2c_ao_sda_5";
1623 1428 function = "i2c_ao";
1624 1429 bias-disable;
1625 }; 1430 };
1626 }; 1431 };
1627 1432
1628 i2c_ao_sda_9_ 1433 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1434 mux {
1630 1435 groups = "i2c_ao_sda_9";
1631 1436 function = "i2c_ao";
1632 1437 bias-disable;
1633 }; 1438 };
1634 }; 1439 };
1635 1440
1636 i2c_ao_sda_11 1441 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1442 mux {
1638 1443 groups = "i2c_ao_sda_11";
1639 1444 function = "i2c_ao";
1640 1445 bias-disable;
1641 }; 1446 };
1642 }; 1447 };
1643 1448
1644 remote_input_ 1449 remote_input_ao_pins: remote_input_ao {
1645 mux { 1450 mux {
1646 1451 groups = "remote_input_ao";
1647 1452 function = "remote_input_ao";
1648 1453 bias-disable;
1649 }; 1454 };
1650 }; 1455 };
1651 1456
1652 uart_ao_a_pin 1457 uart_ao_a_pins: uart_ao_a {
1653 mux { 1458 mux {
1654 1459 groups = "uart_ao_tx_a",
1655 1460 "uart_ao_rx_a";
1656 1461 function = "uart_ao_a";
1657 1462 bias-disable;
1658 }; 1463 };
1659 }; 1464 };
1660 1465
1661 uart_ao_a_cts 1466 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1467 mux {
1663 1468 groups = "uart_ao_cts_a",
1664 1469 "uart_ao_rts_a";
1665 1470 function = "uart_ao_a";
1666 1471 bias-disable;
1667 }; 1472 };
1668 }; 1473 };
1669 1474
1670 uart_ao_b_pin 1475 uart_ao_b_pins: uart_ao_b {
1671 mux { 1476 mux {
1672 1477 groups = "uart_ao_tx_b",
1673 1478 "uart_ao_rx_b";
1674 1479 function = "uart_ao_b";
1675 1480 bias-disable;
1676 }; 1481 };
1677 }; 1482 };
1678 1483
1679 uart_ao_b_cts 1484 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1485 mux {
1681 1486 groups = "uart_ao_cts_b",
1682 1487 "uart_ao_rts_b";
1683 1488 function = "uart_ao_b";
1684 1489 bias-disable;
1685 }; 1490 };
1686 }; 1491 };
1687 }; 1492 };
1688 1493
1689 sec_AO: ao-secure@140 1494 sec_AO: ao-secure@140 {
1690 compatible = 1495 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1496 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1497 amlogic,has-chip-id;
1693 }; 1498 };
1694 1499
1695 pwm_AO_cd: pwm@2000 { 1500 pwm_AO_cd: pwm@2000 {
1696 compatible = 1501 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1502 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1503 #pwm-cells = <3>;
1699 status = "dis 1504 status = "disabled";
1700 }; 1505 };
1701 1506
1702 uart_AO: serial@3000 1507 uart_AO: serial@3000 {
1703 compatible = 1508 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1509 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1510 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1511 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1512 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1513 status = "disabled";
1709 }; 1514 };
1710 1515
1711 uart_AO_B: serial@400 1516 uart_AO_B: serial@4000 {
1712 compatible = 1517 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1518 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1519 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1520 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1521 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1522 status = "disabled";
1718 }; 1523 };
1719 1524
1720 i2c_AO: i2c@5000 { 1525 i2c_AO: i2c@5000 {
1721 compatible = 1526 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1527 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1528 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1529 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1530 #address-cells = <1>;
1726 #size-cells = 1531 #size-cells = <0>;
1727 status = "dis 1532 status = "disabled";
1728 }; 1533 };
1729 1534
1730 pwm_AO_ab: pwm@7000 { 1535 pwm_AO_ab: pwm@7000 {
1731 compatible = 1536 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1537 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1538 #pwm-cells = <3>;
1734 status = "dis 1539 status = "disabled";
1735 }; 1540 };
1736 1541
1737 ir: ir@8000 { 1542 ir: ir@8000 {
1738 compatible = 1543 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1544 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1545 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1546 status = "disabled";
1742 }; 1547 };
1743 1548
1744 saradc: adc@9000 { 1549 saradc: adc@9000 {
1745 compatible = 1550 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1551 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1552 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1553 #io-channel-cells = <1>;
1749 interrupts = 1554 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1555 clocks = <&xtal>,
1751 <&cl 1556 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1557 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1558 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1559 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1560 status = "disabled";
1756 }; 1561 };
1757 }; 1562 };
1758 1563
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1564 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1565 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1566 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1567 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1568 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1569 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1570 interrupt-controller;
1774 interrupts = <GIC_PPI 1571 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1572 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1573 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1574 #address-cells = <0>;
1778 }; 1575 };
1779 1576
1780 cbus: bus@ffd00000 { 1577 cbus: bus@ffd00000 {
1781 compatible = "simple- 1578 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1579 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1580 #address-cells = <2>;
1784 #size-cells = <2>; 1581 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1582 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1583
1787 reset: reset-controll 1584 reset: reset-controller@1004 {
1788 compatible = 1585 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1586 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1587 #reset-cells = <1>;
1791 }; 1588 };
1792 1589
1793 gpio_intc: interrupt- 1590 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1591 compatible = "amlogic,meson-axg-gpio-intc",
1795 1592 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1593 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1594 interrupt-controller;
1798 #interrupt-ce 1595 #interrupt-cells = <2>;
1799 amlogic,chann 1596 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1597 };
1801 1598
1802 watchdog@f0d0 { 1599 watchdog@f0d0 {
1803 compatible = 1600 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1601 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1602 clocks = <&xtal>;
1806 }; 1603 };
1807 1604
1808 pwm_ab: pwm@1b000 { 1605 pwm_ab: pwm@1b000 {
1809 compatible = 1606 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1607 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1608 #pwm-cells = <3>;
1812 status = "dis 1609 status = "disabled";
1813 }; 1610 };
1814 1611
1815 pwm_cd: pwm@1a000 { 1612 pwm_cd: pwm@1a000 {
1816 compatible = 1613 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1614 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1615 #pwm-cells = <3>;
1819 status = "dis 1616 status = "disabled";
1820 }; 1617 };
1821 1618
1822 spicc0: spi@13000 { 1619 spicc0: spi@13000 {
1823 compatible = 1620 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1621 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1622 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1623 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1624 clock-names = "core";
1828 #address-cell 1625 #address-cells = <1>;
1829 #size-cells = 1626 #size-cells = <0>;
1830 status = "dis 1627 status = "disabled";
1831 }; 1628 };
1832 1629
1833 spicc1: spi@15000 { 1630 spicc1: spi@15000 {
1834 compatible = 1631 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1632 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1633 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1634 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1635 clock-names = "core";
1839 #address-cell 1636 #address-cells = <1>;
1840 #size-cells = 1637 #size-cells = <0>;
1841 status = "dis 1638 status = "disabled";
1842 }; 1639 };
1843 1640
1844 clk_msr: clock-measur 1641 clk_msr: clock-measure@18000 {
1845 compatible = 1642 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1643 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1644 };
1848 1645
1849 i2c3: i2c@1c000 { 1646 i2c3: i2c@1c000 {
1850 compatible = 1647 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1648 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1649 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1650 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1651 #address-cells = <1>;
1855 #size-cells = 1652 #size-cells = <0>;
1856 status = "dis 1653 status = "disabled";
1857 }; 1654 };
1858 1655
1859 i2c2: i2c@1d000 { 1656 i2c2: i2c@1d000 {
1860 compatible = 1657 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1658 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1659 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1660 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1661 #address-cells = <1>;
1865 #size-cells = 1662 #size-cells = <0>;
1866 status = "dis 1663 status = "disabled";
1867 }; 1664 };
1868 1665
1869 i2c1: i2c@1e000 { 1666 i2c1: i2c@1e000 {
1870 compatible = 1667 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1668 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1669 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1670 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1671 #address-cells = <1>;
1875 #size-cells = 1672 #size-cells = <0>;
1876 status = "dis 1673 status = "disabled";
1877 }; 1674 };
1878 1675
1879 i2c0: i2c@1f000 { 1676 i2c0: i2c@1f000 {
1880 compatible = 1677 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1678 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1679 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1680 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1681 #address-cells = <1>;
1885 #size-cells = 1682 #size-cells = <0>;
1886 status = "dis 1683 status = "disabled";
1887 }; 1684 };
1888 1685
1889 uart_B: serial@23000 1686 uart_B: serial@23000 {
1890 compatible = 1687 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1688 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1689 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1690 status = "disabled";
1894 clocks = <&xt 1691 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1692 clock-names = "xtal", "pclk", "baud";
1896 }; 1693 };
1897 1694
1898 uart_A: serial@24000 1695 uart_A: serial@24000 {
1899 compatible = 1696 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1697 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1698 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1699 status = "disabled";
1903 clocks = <&xt 1700 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1701 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1702 };
1907 }; 1703 };
1908 1704
1909 apb: bus@ffe00000 { 1705 apb: bus@ffe00000 {
1910 compatible = "simple- 1706 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1707 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1708 #address-cells = <2>;
1913 #size-cells = <2>; 1709 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1710 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1711
1916 sd_emmc_b: mmc@5000 { !! 1712 sd_emmc_b: sd@5000 {
1917 compatible = 1713 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1714 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1715 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1716 status = "disabled";
1921 clocks = <&cl 1717 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1718 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1719 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1720 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1721 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1722 };
1927 1723
1928 sd_emmc_c: mmc@7000 { 1724 sd_emmc_c: mmc@7000 {
1929 compatible = 1725 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1726 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1727 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1728 status = "disabled";
1933 clocks = <&cl 1729 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1730 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1731 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1732 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1733 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; 1734 };
1964 }; 1735 };
1965 1736
1966 sram: sram@fffc0000 { 1737 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1738 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1739 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1740 #address-cells = <1>;
1970 #size-cells = <1>; 1741 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1742 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1743
1973 cpu_scp_lpri: scp-sra 1744 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1745 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1746 reg = <0x13000 0x400>;
1976 }; 1747 };
1977 1748
1978 cpu_scp_hpri: scp-sra 1749 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1750 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1751 reg = <0x13400 0x400>;
1981 }; 1752 };
1982 }; 1753 };
1983 }; 1754 };
1984 1755
1985 timer { 1756 timer {
1986 compatible = "arm,armv8-timer 1757 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1758 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1759 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1760 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1761 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1762 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1763 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1764 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1765 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1766 };
1996 1767
1997 xtal: xtal-clk { 1768 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1769 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1770 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1771 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1772 #clock-cells = <0>;
2002 }; 1773 };
2003 }; 1774 };
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