1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> <<
16 15
17 / { 16 / {
18 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
19 18
20 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 22
24 tdmif_a: audio-controller-0 { 23 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 24 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 25 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 26 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 30 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 tdmif_b: audio-controller-1 { 34 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 35 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 36 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 37 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 41 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 42 status = "disabled";
44 }; 43 };
45 44
46 tdmif_c: audio-controller-2 { 45 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 46 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 47 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 48 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 52 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 53 status = "disabled";
55 }; 54 };
56 55
57 arm-pmu { 56 arm-pmu {
58 compatible = "arm,cortex-a53-p 57 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 63 };
65 64
66 cpus { 65 cpus {
67 #address-cells = <0x2>; 66 #address-cells = <0x2>;
68 #size-cells = <0x0>; 67 #size-cells = <0x0>;
69 68
70 cpu0: cpu@0 { 69 cpu0: cpu@0 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 72 reg = <0x0 0x0>;
74 enable-method = "psci" 73 enable-method = "psci";
75 next-level-cache = <&l 74 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 75 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 76 };
80 77
81 cpu1: cpu@1 { 78 cpu1: cpu@1 {
82 device_type = "cpu"; 79 device_type = "cpu";
83 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 81 reg = <0x0 0x1>;
85 enable-method = "psci" 82 enable-method = "psci";
86 next-level-cache = <&l 83 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 84 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 85 };
91 86
92 cpu2: cpu@2 { 87 cpu2: cpu@2 {
93 device_type = "cpu"; 88 device_type = "cpu";
94 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 90 reg = <0x0 0x2>;
96 enable-method = "psci" 91 enable-method = "psci";
97 next-level-cache = <&l 92 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 93 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 94 };
102 95
103 cpu3: cpu@3 { 96 cpu3: cpu@3 {
104 device_type = "cpu"; 97 device_type = "cpu";
105 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 99 reg = <0x0 0x3>;
107 enable-method = "psci" 100 enable-method = "psci";
108 next-level-cache = <&l 101 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 102 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 103 };
113 104
114 l2: l2-cache0 { 105 l2: l2-cache0 {
115 compatible = "cache"; 106 compatible = "cache";
116 cache-level = <2>; <<
117 cache-unified; <<
118 }; 107 };
119 }; 108 };
120 109
121 sm: secure-monitor { 110 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 111 compatible = "amlogic,meson-gxbb-sm";
123 }; 112 };
124 113
125 efuse: efuse { 114 efuse: efuse {
126 compatible = "amlogic,meson-gx 115 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 116 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 117 #address-cells = <1>;
129 #size-cells = <1>; 118 #size-cells = <1>;
130 read-only; 119 read-only;
131 secure-monitor = <&sm>; 120 secure-monitor = <&sm>;
132 }; 121 };
133 122
134 psci { 123 psci {
135 compatible = "arm,psci-1.0"; 124 compatible = "arm,psci-1.0";
136 method = "smc"; 125 method = "smc";
137 }; 126 };
138 127
139 reserved-memory { 128 reserved-memory {
140 #address-cells = <2>; 129 #address-cells = <2>;
141 #size-cells = <2>; 130 #size-cells = <2>;
142 ranges; 131 ranges;
143 132
144 /* 16 MiB reserved for Hardwar 133 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 134 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 135 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 136 no-map;
148 }; 137 };
149 138
150 /* Alternate 3 MiB reserved fo 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 140 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 141 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 142 no-map;
154 }; 143 };
155 }; 144 };
156 145
157 scpi { 146 scpi {
158 compatible = "arm,scpi-pre-1.0 147 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 148 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 150
162 scpi_clocks: clocks { 151 scpi_clocks: clocks {
163 compatible = "arm,scpi 152 compatible = "arm,scpi-clocks";
164 153
165 scpi_dvfs: clocks-0 { !! 154 scpi_dvfs: clock-controller {
166 compatible = " 155 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 156 #clock-cells = <1>;
168 clock-indices 157 clock-indices = <0>;
169 clock-output-n 158 clock-output-names = "vcpu";
170 }; 159 };
171 }; 160 };
172 161
173 scpi_sensors: sensors { 162 scpi_sensors: sensors {
174 compatible = "amlogic, !! 163 compatible = "amlogic,meson-gxbb-scpi-sensors";
175 #thermal-sensor-cells 164 #thermal-sensor-cells = <1>;
176 }; 165 };
177 }; 166 };
178 167
179 soc { 168 soc {
180 compatible = "simple-bus"; 169 compatible = "simple-bus";
181 #address-cells = <2>; 170 #address-cells = <2>;
182 #size-cells = <2>; 171 #size-cells = <2>;
183 ranges; 172 ranges;
184 173
185 pcieA: pcie@f9800000 { <<
186 compatible = "amlogic, <<
187 reg = <0x0 0xf9800000 <<
188 <0x0 0xff646000 <<
189 <0x0 0xf9f00000 <<
190 reg-names = "elbi", "c <<
191 interrupts = <GIC_SPI <<
192 #interrupt-cells = <1> <<
193 interrupt-map-mask = < <<
194 interrupt-map = <0 0 0 <<
195 bus-range = <0x0 0xff> <<
196 #address-cells = <3>; <<
197 #size-cells = <2>; <<
198 device_type = "pci"; <<
199 ranges = <0x82000000 0 <<
200 <<
201 clocks = <&clkc CLKID_ <<
202 clock-names = "general <<
203 resets = <&reset RESET <<
204 reset-names = "port", <<
205 num-lanes = <1>; <<
206 phys = <&pcie_phy>; <<
207 phy-names = "pcie"; <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 pcieB: pcie@fa000000 { <<
212 compatible = "amlogic, <<
213 reg = <0x0 0xfa000000 <<
214 <0x0 0xff648000 <<
215 <0x0 0xfa400000 <<
216 reg-names = "elbi", "c <<
217 interrupts = <GIC_SPI <<
218 #interrupt-cells = <1> <<
219 interrupt-map-mask = < <<
220 interrupt-map = <0 0 0 <<
221 bus-range = <0x0 0xff> <<
222 #address-cells = <3>; <<
223 #size-cells = <2>; <<
224 device_type = "pci"; <<
225 ranges = <0x82000000 0 <<
226 <<
227 clocks = <&clkc CLKID_ <<
228 clock-names = "general <<
229 resets = <&reset RESET <<
230 reset-names = "port", <<
231 num-lanes = <1>; <<
232 phys = <&pcie_phy>; <<
233 phy-names = "pcie"; <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 usb: usb@ffe09080 { <<
238 compatible = "amlogic, <<
239 reg = <0x0 0xffe09080 <<
240 interrupts = <GIC_SPI <<
241 #address-cells = <2>; <<
242 #size-cells = <2>; <<
243 ranges; <<
244 <<
245 clocks = <&clkc CLKID_ <<
246 clock-names = "usb_ctr <<
247 resets = <&reset RESET <<
248 <<
249 dr_mode = "otg"; <<
250 <<
251 phys = <&usb2_phy1>; <<
252 phy-names = "usb2-phy1 <<
253 <<
254 dwc2: usb@ff400000 { <<
255 compatible = " <<
256 reg = <0x0 0xf <<
257 interrupts = < <<
258 clocks = <&clk <<
259 clock-names = <<
260 phys = <&usb2_ <<
261 dr_mode = "per <<
262 g-rx-fifo-size <<
263 g-np-tx-fifo-s <<
264 g-tx-fifo-size <<
265 }; <<
266 <<
267 dwc3: usb@ff500000 { <<
268 compatible = " <<
269 reg = <0x0 0xf <<
270 interrupts = < <<
271 dr_mode = "hos <<
272 maximum-speed <<
273 snps,dis_u2_su <<
274 }; <<
275 }; <<
276 <<
277 ethmac: ethernet@ff3f0000 { 174 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 175 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 176 "snps,dwmac-3.70a",
280 "snps,dwm 177 "snps,dwmac";
281 reg = <0x0 0xff3f0000 178 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 179 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 180 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 181 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 182 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 183 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 184 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 185 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 186 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 187 "timing-adjustment";
291 rx-fifo-depth = <4096> 188 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 189 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc !! 190 resets = <&reset RESET_ETHERNET>;
>> 191 reset-names = "stmmaceth";
294 status = "disabled"; 192 status = "disabled";
295 }; 193 };
296 194
297 pcie_phy: phy@ff644000 { <<
298 compatible = "amlogic, <<
299 reg = <0x0 0xff644000 <<
300 resets = <&reset RESET <<
301 phys = <&mipi_pcie_ana <<
302 phy-names = "analog"; <<
303 #phy-cells = <0>; <<
304 }; <<
305 <<
306 pdm: audio-controller@ff632000 195 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 196 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 197 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 198 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 199 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 200 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 201 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 202 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 203 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 204 status = "disabled";
316 }; 205 };
317 206
318 periphs: bus@ff634000 { 207 periphs: bus@ff634000 {
319 compatible = "simple-b 208 compatible = "simple-bus";
320 reg = <0x0 0xff634000 209 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 210 #address-cells = <2>;
322 #size-cells = <2>; 211 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 212 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 213
325 hwrng: rng@18 { 214 hwrng: rng@18 {
326 compatible = " 215 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 216 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 217 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 218 clock-names = "core";
330 }; 219 };
331 220
332 pinctrl_periphs: pinct 221 pinctrl_periphs: pinctrl@480 {
333 compatible = " 222 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 223 #address-cells = <2>;
335 #size-cells = 224 #size-cells = <2>;
336 ranges; 225 ranges;
337 226
338 gpio: bank@480 227 gpio: bank@480 {
339 reg = 228 reg = <0x0 0x00480 0x0 0x40>,
340 229 <0x0 0x004e8 0x0 0x14>,
341 230 <0x0 0x00520 0x0 0x14>,
342 231 <0x0 0x00430 0x0 0x3c>;
343 reg-na 232 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 233 gpio-controller;
345 #gpio- 234 #gpio-cells = <2>;
346 gpio-r 235 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 236 };
348 237
349 i2c0_pins: i2c 238 i2c0_pins: i2c0 {
350 mux { 239 mux {
351 240 groups = "i2c0_sck",
352 241 "i2c0_sda";
353 242 function = "i2c0";
354 243 bias-disable;
355 }; 244 };
356 }; 245 };
357 246
358 i2c1_x_pins: i 247 i2c1_x_pins: i2c1_x {
359 mux { 248 mux {
360 249 groups = "i2c1_sck_x",
361 250 "i2c1_sda_x";
362 251 function = "i2c1";
363 252 bias-disable;
364 }; 253 };
365 }; 254 };
366 255
367 i2c1_z_pins: i 256 i2c1_z_pins: i2c1_z {
368 mux { 257 mux {
369 258 groups = "i2c1_sck_z",
370 259 "i2c1_sda_z";
371 260 function = "i2c1";
372 261 bias-disable;
373 }; 262 };
374 }; 263 };
375 264
376 i2c2_a_pins: i 265 i2c2_a_pins: i2c2_a {
377 mux { 266 mux {
378 267 groups = "i2c2_sck_a",
379 268 "i2c2_sda_a";
380 269 function = "i2c2";
381 270 bias-disable;
382 }; 271 };
383 }; 272 };
384 273
385 i2c2_x_pins: i 274 i2c2_x_pins: i2c2_x {
386 mux { 275 mux {
387 276 groups = "i2c2_sck_x",
388 277 "i2c2_sda_x";
389 278 function = "i2c2";
390 279 bias-disable;
391 }; 280 };
392 }; 281 };
393 282
394 i2c3_a6_pins: 283 i2c3_a6_pins: i2c3_a6 {
395 mux { 284 mux {
396 285 groups = "i2c3_sda_a6",
397 286 "i2c3_sck_a7";
398 287 function = "i2c3";
399 288 bias-disable;
400 }; 289 };
401 }; 290 };
402 291
403 i2c3_a12_pins: 292 i2c3_a12_pins: i2c3_a12 {
404 mux { 293 mux {
405 294 groups = "i2c3_sda_a12",
406 295 "i2c3_sck_a13";
407 296 function = "i2c3";
408 297 bias-disable;
409 }; 298 };
410 }; 299 };
411 300
412 i2c3_a19_pins: 301 i2c3_a19_pins: i2c3_a19 {
413 mux { 302 mux {
414 303 groups = "i2c3_sda_a19",
415 304 "i2c3_sck_a20";
416 305 function = "i2c3";
417 306 bias-disable;
418 }; 307 };
419 }; 308 };
420 309
421 emmc_pins: emm 310 emmc_pins: emmc {
422 mux-0 311 mux-0 {
423 312 groups = "emmc_nand_d0",
424 313 "emmc_nand_d1",
425 314 "emmc_nand_d2",
426 315 "emmc_nand_d3",
427 316 "emmc_nand_d4",
428 317 "emmc_nand_d5",
429 318 "emmc_nand_d6",
430 319 "emmc_nand_d7",
431 320 "emmc_cmd";
432 321 function = "emmc";
433 322 bias-pull-up;
434 }; 323 };
435 324
436 mux-1 325 mux-1 {
437 326 groups = "emmc_clk";
438 327 function = "emmc";
439 328 bias-disable;
440 }; 329 };
441 }; 330 };
442 331
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 332 emmc_ds_pins: emmc_ds {
465 mux { 333 mux {
466 334 groups = "emmc_ds";
467 335 function = "emmc";
468 336 bias-pull-down;
469 }; 337 };
470 }; 338 };
471 339
472 emmc_clk_gate_ 340 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 341 mux {
474 342 groups = "BOOT_8";
475 343 function = "gpio_periphs";
476 344 bias-pull-down;
477 }; 345 };
478 }; 346 };
479 347
480 eth_rgmii_x_pi 348 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 349 mux {
482 350 groups = "eth_mdio_x",
483 351 "eth_mdc_x",
484 352 "eth_rgmii_rx_clk_x",
485 353 "eth_rx_dv_x",
486 354 "eth_rxd0_x",
487 355 "eth_rxd1_x",
488 356 "eth_rxd2_rgmii",
489 357 "eth_rxd3_rgmii",
490 358 "eth_rgmii_tx_clk",
491 359 "eth_txen_x",
492 360 "eth_txd0_x",
493 361 "eth_txd1_x",
494 362 "eth_txd2_rgmii",
495 363 "eth_txd3_rgmii";
496 364 function = "eth";
497 365 bias-disable;
498 }; 366 };
499 }; 367 };
500 368
501 eth_rgmii_y_pi 369 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 370 mux {
503 371 groups = "eth_mdio_y",
504 372 "eth_mdc_y",
505 373 "eth_rgmii_rx_clk_y",
506 374 "eth_rx_dv_y",
507 375 "eth_rxd0_y",
508 376 "eth_rxd1_y",
509 377 "eth_rxd2_rgmii",
510 378 "eth_rxd3_rgmii",
511 379 "eth_rgmii_tx_clk",
512 380 "eth_txen_y",
513 381 "eth_txd0_y",
514 382 "eth_txd1_y",
515 383 "eth_txd2_rgmii",
516 384 "eth_txd3_rgmii";
517 385 function = "eth";
518 386 bias-disable;
519 }; 387 };
520 }; 388 };
521 389
522 eth_rmii_x_pin 390 eth_rmii_x_pins: eth-x-rmii {
523 mux { 391 mux {
524 392 groups = "eth_mdio_x",
525 393 "eth_mdc_x",
526 394 "eth_rgmii_rx_clk_x",
527 395 "eth_rx_dv_x",
528 396 "eth_rxd0_x",
529 397 "eth_rxd1_x",
530 398 "eth_txen_x",
531 399 "eth_txd0_x",
532 400 "eth_txd1_x";
533 401 function = "eth";
534 402 bias-disable;
535 }; 403 };
536 }; 404 };
537 405
538 eth_rmii_y_pin 406 eth_rmii_y_pins: eth-y-rmii {
539 mux { 407 mux {
540 408 groups = "eth_mdio_y",
541 409 "eth_mdc_y",
542 410 "eth_rgmii_rx_clk_y",
543 411 "eth_rx_dv_y",
544 412 "eth_rxd0_y",
545 413 "eth_rxd1_y",
546 414 "eth_txen_y",
547 415 "eth_txd0_y",
548 416 "eth_txd1_y";
549 417 function = "eth";
550 418 bias-disable;
551 }; 419 };
552 }; 420 };
553 421
554 mclk_b_pins: m 422 mclk_b_pins: mclk_b {
555 mux { 423 mux {
556 424 groups = "mclk_b";
557 425 function = "mclk_b";
558 426 bias-disable;
559 }; 427 };
560 }; 428 };
561 429
562 mclk_c_pins: m 430 mclk_c_pins: mclk_c {
563 mux { 431 mux {
564 432 groups = "mclk_c";
565 433 function = "mclk_c";
566 434 bias-disable;
567 }; 435 };
568 }; 436 };
569 437
570 pdm_dclk_a14_p 438 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 439 mux {
572 440 groups = "pdm_dclk_a14";
573 441 function = "pdm";
574 442 bias-disable;
575 }; 443 };
576 }; 444 };
577 445
578 pdm_dclk_a19_p 446 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 447 mux {
580 448 groups = "pdm_dclk_a19";
581 449 function = "pdm";
582 450 bias-disable;
583 }; 451 };
584 }; 452 };
585 453
586 pdm_din0_pins: 454 pdm_din0_pins: pdm_din0 {
587 mux { 455 mux {
588 456 groups = "pdm_din0";
589 457 function = "pdm";
590 458 bias-disable;
591 }; 459 };
592 }; 460 };
593 461
594 pdm_din1_pins: 462 pdm_din1_pins: pdm_din1 {
595 mux { 463 mux {
596 464 groups = "pdm_din1";
597 465 function = "pdm";
598 466 bias-disable;
599 }; 467 };
600 }; 468 };
601 469
602 pdm_din2_pins: 470 pdm_din2_pins: pdm_din2 {
603 mux { 471 mux {
604 472 groups = "pdm_din2";
605 473 function = "pdm";
606 474 bias-disable;
607 }; 475 };
608 }; 476 };
609 477
610 pdm_din3_pins: 478 pdm_din3_pins: pdm_din3 {
611 mux { 479 mux {
612 480 groups = "pdm_din3";
613 481 function = "pdm";
614 482 bias-disable;
615 }; 483 };
616 }; 484 };
617 485
618 pwm_a_a_pins: 486 pwm_a_a_pins: pwm_a_a {
619 mux { 487 mux {
620 488 groups = "pwm_a_a";
621 489 function = "pwm_a";
622 490 bias-disable;
623 }; 491 };
624 }; 492 };
625 493
626 pwm_a_x18_pins 494 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 495 mux {
628 496 groups = "pwm_a_x18";
629 497 function = "pwm_a";
630 498 bias-disable;
631 }; 499 };
632 }; 500 };
633 501
634 pwm_a_x20_pins 502 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 503 mux {
636 504 groups = "pwm_a_x20";
637 505 function = "pwm_a";
638 506 bias-disable;
639 }; 507 };
640 }; 508 };
641 509
642 pwm_a_z_pins: 510 pwm_a_z_pins: pwm_a_z {
643 mux { 511 mux {
644 512 groups = "pwm_a_z";
645 513 function = "pwm_a";
646 514 bias-disable;
647 }; 515 };
648 }; 516 };
649 517
650 pwm_b_a_pins: 518 pwm_b_a_pins: pwm_b_a {
651 mux { 519 mux {
652 520 groups = "pwm_b_a";
653 521 function = "pwm_b";
654 522 bias-disable;
655 }; 523 };
656 }; 524 };
657 525
658 pwm_b_x_pins: 526 pwm_b_x_pins: pwm_b_x {
659 mux { 527 mux {
660 528 groups = "pwm_b_x";
661 529 function = "pwm_b";
662 530 bias-disable;
663 }; 531 };
664 }; 532 };
665 533
666 pwm_b_z_pins: 534 pwm_b_z_pins: pwm_b_z {
667 mux { 535 mux {
668 536 groups = "pwm_b_z";
669 537 function = "pwm_b";
670 538 bias-disable;
671 }; 539 };
672 }; 540 };
673 541
674 pwm_c_a_pins: 542 pwm_c_a_pins: pwm_c_a {
675 mux { 543 mux {
676 544 groups = "pwm_c_a";
677 545 function = "pwm_c";
678 546 bias-disable;
679 }; 547 };
680 }; 548 };
681 549
682 pwm_c_x10_pins 550 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 551 mux {
684 552 groups = "pwm_c_x10";
685 553 function = "pwm_c";
686 554 bias-disable;
687 }; 555 };
688 }; 556 };
689 557
690 pwm_c_x17_pins 558 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 559 mux {
692 560 groups = "pwm_c_x17";
693 561 function = "pwm_c";
694 562 bias-disable;
695 }; 563 };
696 }; 564 };
697 565
698 pwm_d_x11_pins 566 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 567 mux {
700 568 groups = "pwm_d_x11";
701 569 function = "pwm_d";
702 570 bias-disable;
703 }; 571 };
704 }; 572 };
705 573
706 pwm_d_x16_pins 574 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 575 mux {
708 576 groups = "pwm_d_x16";
709 577 function = "pwm_d";
710 578 bias-disable;
711 }; 579 };
712 }; 580 };
713 581
714 sdio_pins: sdi 582 sdio_pins: sdio {
715 mux-0 583 mux-0 {
716 584 groups = "sdio_d0",
717 585 "sdio_d1",
718 586 "sdio_d2",
719 587 "sdio_d3",
720 588 "sdio_cmd";
721 589 function = "sdio";
722 590 bias-pull-up;
723 }; 591 };
724 592
725 mux-1 593 mux-1 {
726 594 groups = "sdio_clk";
727 595 function = "sdio";
728 596 bias-disable;
729 }; 597 };
730 }; 598 };
731 599
732 sdio_clk_gate_ 600 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 601 mux {
734 602 groups = "GPIOX_4";
735 603 function = "gpio_periphs";
736 604 bias-pull-down;
737 }; 605 };
738 }; 606 };
739 607
740 spdif_in_z_pin 608 spdif_in_z_pins: spdif_in_z {
741 mux { 609 mux {
742 610 groups = "spdif_in_z";
743 611 function = "spdif_in";
744 612 bias-disable;
745 }; 613 };
746 }; 614 };
747 615
748 spdif_in_a1_pi 616 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 617 mux {
750 618 groups = "spdif_in_a1";
751 619 function = "spdif_in";
752 620 bias-disable;
753 }; 621 };
754 }; 622 };
755 623
756 spdif_in_a7_pi 624 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 625 mux {
758 626 groups = "spdif_in_a7";
759 627 function = "spdif_in";
760 628 bias-disable;
761 }; 629 };
762 }; 630 };
763 631
764 spdif_in_a19_p 632 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 633 mux {
766 634 groups = "spdif_in_a19";
767 635 function = "spdif_in";
768 636 bias-disable;
769 }; 637 };
770 }; 638 };
771 639
772 spdif_in_a20_p 640 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 641 mux {
774 642 groups = "spdif_in_a20";
775 643 function = "spdif_in";
776 644 bias-disable;
777 }; 645 };
778 }; 646 };
779 647
780 spdif_out_a1_p 648 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 649 mux {
782 650 groups = "spdif_out_a1";
783 651 function = "spdif_out";
784 652 bias-disable;
785 }; 653 };
786 }; 654 };
787 655
788 spdif_out_a11_ 656 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 657 mux {
790 658 groups = "spdif_out_a11";
791 659 function = "spdif_out";
792 660 bias-disable;
793 }; 661 };
794 }; 662 };
795 663
796 spdif_out_a19_ 664 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 665 mux {
798 666 groups = "spdif_out_a19";
799 667 function = "spdif_out";
800 668 bias-disable;
801 }; 669 };
802 }; 670 };
803 671
804 spdif_out_a20_ 672 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 673 mux {
806 674 groups = "spdif_out_a20";
807 675 function = "spdif_out";
808 676 bias-disable;
809 }; 677 };
810 }; 678 };
811 679
812 spdif_out_z_pi 680 spdif_out_z_pins: spdif_out_z {
813 mux { 681 mux {
814 682 groups = "spdif_out_z";
815 683 function = "spdif_out";
816 684 bias-disable;
817 }; 685 };
818 }; 686 };
819 687
820 spi0_pins: spi 688 spi0_pins: spi0 {
821 mux { 689 mux {
822 690 groups = "spi0_miso",
823 691 "spi0_mosi",
824 692 "spi0_clk";
825 693 function = "spi0";
826 694 bias-disable;
827 }; 695 };
828 }; 696 };
829 697
830 spi0_ss0_pins: 698 spi0_ss0_pins: spi0_ss0 {
831 mux { 699 mux {
832 700 groups = "spi0_ss0";
833 701 function = "spi0";
834 702 bias-disable;
835 }; 703 };
836 }; 704 };
837 705
838 spi0_ss1_pins: 706 spi0_ss1_pins: spi0_ss1 {
839 mux { 707 mux {
840 708 groups = "spi0_ss1";
841 709 function = "spi0";
842 710 bias-disable;
843 }; 711 };
844 }; 712 };
845 713
846 spi0_ss2_pins: 714 spi0_ss2_pins: spi0_ss2 {
847 mux { 715 mux {
848 716 groups = "spi0_ss2";
849 717 function = "spi0";
850 718 bias-disable;
851 }; 719 };
852 }; 720 };
853 721
854 spi1_a_pins: s 722 spi1_a_pins: spi1_a {
855 mux { 723 mux {
856 724 groups = "spi1_miso_a",
857 725 "spi1_mosi_a",
858 726 "spi1_clk_a";
859 727 function = "spi1";
860 728 bias-disable;
861 }; 729 };
862 }; 730 };
863 731
864 spi1_ss0_a_pin 732 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 733 mux {
866 734 groups = "spi1_ss0_a";
867 735 function = "spi1";
868 736 bias-disable;
869 }; 737 };
870 }; 738 };
871 739
872 spi1_ss1_pins: 740 spi1_ss1_pins: spi1_ss1 {
873 mux { 741 mux {
874 742 groups = "spi1_ss1";
875 743 function = "spi1";
876 744 bias-disable;
877 }; 745 };
878 }; 746 };
879 747
880 spi1_x_pins: s 748 spi1_x_pins: spi1_x {
881 mux { 749 mux {
882 750 groups = "spi1_miso_x",
883 751 "spi1_mosi_x",
884 752 "spi1_clk_x";
885 753 function = "spi1";
886 754 bias-disable;
887 }; 755 };
888 }; 756 };
889 757
890 spi1_ss0_x_pin 758 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 759 mux {
892 760 groups = "spi1_ss0_x";
893 761 function = "spi1";
894 762 bias-disable;
895 }; 763 };
896 }; 764 };
897 765
898 tdma_din0_pins 766 tdma_din0_pins: tdma_din0 {
899 mux { 767 mux {
900 768 groups = "tdma_din0";
901 769 function = "tdma";
902 770 bias-disable;
903 }; 771 };
904 }; 772 };
905 773
906 tdma_dout0_x14 774 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 775 mux {
908 776 groups = "tdma_dout0_x14";
909 777 function = "tdma";
910 778 bias-disable;
911 }; 779 };
912 }; 780 };
913 781
914 tdma_dout0_x15 782 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 783 mux {
916 784 groups = "tdma_dout0_x15";
917 785 function = "tdma";
918 786 bias-disable;
919 }; 787 };
920 }; 788 };
921 789
922 tdma_dout1_pin 790 tdma_dout1_pins: tdma_dout1 {
923 mux { 791 mux {
924 792 groups = "tdma_dout1";
925 793 function = "tdma";
926 794 bias-disable;
927 }; 795 };
928 }; 796 };
929 797
930 tdma_din1_pins 798 tdma_din1_pins: tdma_din1 {
931 mux { 799 mux {
932 800 groups = "tdma_din1";
933 801 function = "tdma";
934 802 bias-disable;
935 }; 803 };
936 }; 804 };
937 805
938 tdma_fs_pins: 806 tdma_fs_pins: tdma_fs {
939 mux { 807 mux {
940 808 groups = "tdma_fs";
941 809 function = "tdma";
942 810 bias-disable;
943 }; 811 };
944 }; 812 };
945 813
946 tdma_fs_slv_pi 814 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 815 mux {
948 816 groups = "tdma_fs_slv";
949 817 function = "tdma";
950 818 bias-disable;
951 }; 819 };
952 }; 820 };
953 821
954 tdma_sclk_pins 822 tdma_sclk_pins: tdma_sclk {
955 mux { 823 mux {
956 824 groups = "tdma_sclk";
957 825 function = "tdma";
958 826 bias-disable;
959 }; 827 };
960 }; 828 };
961 829
962 tdma_sclk_slv_ 830 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 831 mux {
964 832 groups = "tdma_sclk_slv";
965 833 function = "tdma";
966 834 bias-disable;
967 }; 835 };
968 }; 836 };
969 837
970 tdmb_din0_pins 838 tdmb_din0_pins: tdmb_din0 {
971 mux { 839 mux {
972 840 groups = "tdmb_din0";
973 841 function = "tdmb";
974 842 bias-disable;
975 }; 843 };
976 }; 844 };
977 845
978 tdmb_din1_pins 846 tdmb_din1_pins: tdmb_din1 {
979 mux { 847 mux {
980 848 groups = "tdmb_din1";
981 849 function = "tdmb";
982 850 bias-disable;
983 }; 851 };
984 }; 852 };
985 853
986 tdmb_din2_pins 854 tdmb_din2_pins: tdmb_din2 {
987 mux { 855 mux {
988 856 groups = "tdmb_din2";
989 857 function = "tdmb";
990 858 bias-disable;
991 }; 859 };
992 }; 860 };
993 861
994 tdmb_din3_pins 862 tdmb_din3_pins: tdmb_din3 {
995 mux { 863 mux {
996 864 groups = "tdmb_din3";
997 865 function = "tdmb";
998 866 bias-disable;
999 }; 867 };
1000 }; 868 };
1001 869
1002 tdmb_dout0_pi 870 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 871 mux {
1004 872 groups = "tdmb_dout0";
1005 873 function = "tdmb";
1006 874 bias-disable;
1007 }; 875 };
1008 }; 876 };
1009 877
1010 tdmb_dout1_pi 878 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 879 mux {
1012 880 groups = "tdmb_dout1";
1013 881 function = "tdmb";
1014 882 bias-disable;
1015 }; 883 };
1016 }; 884 };
1017 885
1018 tdmb_dout2_pi 886 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 887 mux {
1020 888 groups = "tdmb_dout2";
1021 889 function = "tdmb";
1022 890 bias-disable;
1023 }; 891 };
1024 }; 892 };
1025 893
1026 tdmb_dout3_pi 894 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 895 mux {
1028 896 groups = "tdmb_dout3";
1029 897 function = "tdmb";
1030 898 bias-disable;
1031 }; 899 };
1032 }; 900 };
1033 901
1034 tdmb_fs_pins: 902 tdmb_fs_pins: tdmb_fs {
1035 mux { 903 mux {
1036 904 groups = "tdmb_fs";
1037 905 function = "tdmb";
1038 906 bias-disable;
1039 }; 907 };
1040 }; 908 };
1041 909
1042 tdmb_fs_slv_p 910 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 911 mux {
1044 912 groups = "tdmb_fs_slv";
1045 913 function = "tdmb";
1046 914 bias-disable;
1047 }; 915 };
1048 }; 916 };
1049 917
1050 tdmb_sclk_pin 918 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 919 mux {
1052 920 groups = "tdmb_sclk";
1053 921 function = "tdmb";
1054 922 bias-disable;
1055 }; 923 };
1056 }; 924 };
1057 925
1058 tdmb_sclk_slv 926 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 927 mux {
1060 928 groups = "tdmb_sclk_slv";
1061 929 function = "tdmb";
1062 930 bias-disable;
1063 }; 931 };
1064 }; 932 };
1065 933
1066 tdmc_fs_pins: 934 tdmc_fs_pins: tdmc_fs {
1067 mux { 935 mux {
1068 936 groups = "tdmc_fs";
1069 937 function = "tdmc";
1070 938 bias-disable;
1071 }; 939 };
1072 }; 940 };
1073 941
1074 tdmc_fs_slv_p 942 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 943 mux {
1076 944 groups = "tdmc_fs_slv";
1077 945 function = "tdmc";
1078 946 bias-disable;
1079 }; 947 };
1080 }; 948 };
1081 949
1082 tdmc_sclk_pin 950 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 951 mux {
1084 952 groups = "tdmc_sclk";
1085 953 function = "tdmc";
1086 954 bias-disable;
1087 }; 955 };
1088 }; 956 };
1089 957
1090 tdmc_sclk_slv 958 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 959 mux {
1092 960 groups = "tdmc_sclk_slv";
1093 961 function = "tdmc";
1094 962 bias-disable;
1095 }; 963 };
1096 }; 964 };
1097 965
1098 tdmc_din0_pin 966 tdmc_din0_pins: tdmc_din0 {
1099 mux { 967 mux {
1100 968 groups = "tdmc_din0";
1101 969 function = "tdmc";
1102 970 bias-disable;
1103 }; 971 };
1104 }; 972 };
1105 973
1106 tdmc_din1_pin 974 tdmc_din1_pins: tdmc_din1 {
1107 mux { 975 mux {
1108 976 groups = "tdmc_din1";
1109 977 function = "tdmc";
1110 978 bias-disable;
1111 }; 979 };
1112 }; 980 };
1113 981
1114 tdmc_din2_pin 982 tdmc_din2_pins: tdmc_din2 {
1115 mux { 983 mux {
1116 984 groups = "tdmc_din2";
1117 985 function = "tdmc";
1118 986 bias-disable;
1119 }; 987 };
1120 }; 988 };
1121 989
1122 tdmc_din3_pin 990 tdmc_din3_pins: tdmc_din3 {
1123 mux { 991 mux {
1124 992 groups = "tdmc_din3";
1125 993 function = "tdmc";
1126 994 bias-disable;
1127 }; 995 };
1128 }; 996 };
1129 997
1130 tdmc_dout0_pi 998 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 999 mux {
1132 1000 groups = "tdmc_dout0";
1133 1001 function = "tdmc";
1134 1002 bias-disable;
1135 }; 1003 };
1136 }; 1004 };
1137 1005
1138 tdmc_dout1_pi 1006 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1007 mux {
1140 1008 groups = "tdmc_dout1";
1141 1009 function = "tdmc";
1142 1010 bias-disable;
1143 }; 1011 };
1144 }; 1012 };
1145 1013
1146 tdmc_dout2_pi 1014 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1015 mux {
1148 1016 groups = "tdmc_dout2";
1149 1017 function = "tdmc";
1150 1018 bias-disable;
1151 }; 1019 };
1152 }; 1020 };
1153 1021
1154 tdmc_dout3_pi 1022 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1023 mux {
1156 1024 groups = "tdmc_dout3";
1157 1025 function = "tdmc";
1158 1026 bias-disable;
1159 }; 1027 };
1160 }; 1028 };
1161 1029
1162 uart_a_pins: 1030 uart_a_pins: uart_a {
1163 mux { 1031 mux {
1164 1032 groups = "uart_tx_a",
1165 1033 "uart_rx_a";
1166 1034 function = "uart_a";
1167 1035 bias-disable;
1168 }; 1036 };
1169 }; 1037 };
1170 1038
1171 uart_a_cts_rt 1039 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1040 mux {
1173 1041 groups = "uart_cts_a",
1174 1042 "uart_rts_a";
1175 1043 function = "uart_a";
1176 1044 bias-disable;
1177 }; 1045 };
1178 }; 1046 };
1179 1047
1180 uart_b_x_pins 1048 uart_b_x_pins: uart_b_x {
1181 mux { 1049 mux {
1182 1050 groups = "uart_tx_b_x",
1183 1051 "uart_rx_b_x";
1184 1052 function = "uart_b";
1185 1053 bias-disable;
1186 }; 1054 };
1187 }; 1055 };
1188 1056
1189 uart_b_x_cts_ 1057 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1058 mux {
1191 1059 groups = "uart_cts_b_x",
1192 1060 "uart_rts_b_x";
1193 1061 function = "uart_b";
1194 1062 bias-disable;
1195 }; 1063 };
1196 }; 1064 };
1197 1065
1198 uart_b_z_pins 1066 uart_b_z_pins: uart_b_z {
1199 mux { 1067 mux {
1200 1068 groups = "uart_tx_b_z",
1201 1069 "uart_rx_b_z";
1202 1070 function = "uart_b";
1203 1071 bias-disable;
1204 }; 1072 };
1205 }; 1073 };
1206 1074
1207 uart_b_z_cts_ 1075 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1076 mux {
1209 1077 groups = "uart_cts_b_z",
1210 1078 "uart_rts_b_z";
1211 1079 function = "uart_b";
1212 1080 bias-disable;
1213 }; 1081 };
1214 }; 1082 };
1215 1083
1216 uart_ao_b_z_p 1084 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1085 mux {
1218 1086 groups = "uart_ao_tx_b_z",
1219 1087 "uart_ao_rx_b_z";
1220 1088 function = "uart_ao_b_z";
1221 1089 bias-disable;
1222 }; 1090 };
1223 }; 1091 };
1224 1092
1225 uart_ao_b_z_c 1093 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1094 mux {
1227 1095 groups = "uart_ao_cts_b_z",
1228 1096 "uart_ao_rts_b_z";
1229 1097 function = "uart_ao_b_z";
1230 1098 bias-disable;
1231 }; 1099 };
1232 }; 1100 };
1233 }; 1101 };
1234 }; 1102 };
1235 1103
1236 hiubus: bus@ff63c000 { 1104 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1105 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1106 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1107 #address-cells = <2>;
1240 #size-cells = <2>; 1108 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1109 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1110
1243 sysctrl: system-contr 1111 sysctrl: system-controller@0 {
1244 compatible = 1112 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1113 "simple-mfd", "syscon";
1246 reg = <0 0 0 1114 reg = <0 0 0 0x400>;
1247 1115
1248 clkc: clock-c 1116 clkc: clock-controller {
1249 compa 1117 compatible = "amlogic,axg-clkc";
1250 #cloc 1118 #clock-cells = <1>;
1251 clock 1119 clocks = <&xtal>;
1252 clock 1120 clock-names = "xtal";
1253 }; 1121 };
1254 <<
1255 pwrc: power-c <<
1256 compa <<
1257 #powe <<
1258 amlog <<
1259 reset <<
1260 <<
1261 <<
1262 <<
1263 <<
1264 reset <<
1265 <<
1266 clock <<
1267 <<
1268 clock <<
1269 /* <<
1270 * VP <<
1271 * VP <<
1272 * fr <<
1273 * Sa <<
1274 */ <<
1275 assig <<
1276 <<
1277 <<
1278 <<
1279 <<
1280 <<
1281 assig <<
1282 <<
1283 <<
1284 <<
1285 <<
1286 <<
1287 assig <<
1288 <<
1289 <<
1290 <<
1291 <<
1292 <<
1293 }; <<
1294 <<
1295 mipi_pcie_ana <<
1296 compa <<
1297 #phy- <<
1298 statu <<
1299 }; <<
1300 }; 1122 };
1301 }; 1123 };
1302 1124
1303 mailbox: mailbox@ff63c404 { 1125 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1126 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1127 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1128 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1129 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1130 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1131 #mbox-cells = <1>;
1310 }; 1132 };
1311 1133
1312 mipi_dphy: phy@ff640000 { <<
1313 compatible = "amlogic <<
1314 reg = <0x0 0xff640000 <<
1315 clocks = <&clkc CLKID <<
1316 clock-names = "pclk"; <<
1317 resets = <&reset RESE <<
1318 reset-names = "phy"; <<
1319 phys = <&mipi_pcie_an <<
1320 phy-names = "analog"; <<
1321 #phy-cells = <0>; <<
1322 status = "disabled"; <<
1323 }; <<
1324 <<
1325 audio: bus@ff642000 { 1134 audio: bus@ff642000 {
1326 compatible = "simple- 1135 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1136 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1137 #address-cells = <2>;
1329 #size-cells = <2>; 1138 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1139 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1140
1332 clkc_audio: clock-con 1141 clkc_audio: clock-controller@0 {
1333 compatible = 1142 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1143 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1144 #clock-cells = <1>;
1336 1145
1337 clocks = <&cl 1146 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1147 <&clkc CLKID_MPLL0>,
1339 <&cl 1148 <&clkc CLKID_MPLL1>,
1340 <&cl 1149 <&clkc CLKID_MPLL2>,
1341 <&cl 1150 <&clkc CLKID_MPLL3>,
1342 <&cl 1151 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1152 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1153 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1154 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1155 clock-names = "pclk",
1347 1156 "mst_in0",
1348 1157 "mst_in1",
1349 1158 "mst_in2",
1350 1159 "mst_in3",
1351 1160 "mst_in4",
1352 1161 "mst_in5",
1353 1162 "mst_in6",
1354 1163 "mst_in7";
1355 1164
1356 resets = <&re 1165 resets = <&reset RESET_AUDIO>;
1357 }; 1166 };
1358 1167
1359 toddr_a: audio-contro 1168 toddr_a: audio-controller@100 {
1360 compatible = 1169 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1170 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1171 #sound-dai-cells = <0>;
1363 sound-name-pr 1172 sound-name-prefix = "TODDR_A";
1364 interrupts = 1173 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1174 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1175 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1176 amlogic,fifo-depth = <512>;
1368 status = "dis 1177 status = "disabled";
1369 }; 1178 };
1370 1179
1371 toddr_b: audio-contro 1180 toddr_b: audio-controller@140 {
1372 compatible = 1181 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1182 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1183 #sound-dai-cells = <0>;
1375 sound-name-pr 1184 sound-name-prefix = "TODDR_B";
1376 interrupts = 1185 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1186 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1187 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1188 amlogic,fifo-depth = <256>;
1380 status = "dis 1189 status = "disabled";
1381 }; 1190 };
1382 1191
1383 toddr_c: audio-contro 1192 toddr_c: audio-controller@180 {
1384 compatible = 1193 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1194 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1195 #sound-dai-cells = <0>;
1387 sound-name-pr 1196 sound-name-prefix = "TODDR_C";
1388 interrupts = 1197 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1198 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1199 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1200 amlogic,fifo-depth = <256>;
1392 status = "dis 1201 status = "disabled";
1393 }; 1202 };
1394 1203
1395 frddr_a: audio-contro 1204 frddr_a: audio-controller@1c0 {
1396 compatible = 1205 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1206 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1207 #sound-dai-cells = <0>;
1399 sound-name-pr 1208 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1209 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1210 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1211 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1212 amlogic,fifo-depth = <512>;
1404 status = "dis 1213 status = "disabled";
1405 }; 1214 };
1406 1215
1407 frddr_b: audio-contro 1216 frddr_b: audio-controller@200 {
1408 compatible = 1217 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1218 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1219 #sound-dai-cells = <0>;
1411 sound-name-pr 1220 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1221 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1222 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1223 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1224 amlogic,fifo-depth = <256>;
1416 status = "dis 1225 status = "disabled";
1417 }; 1226 };
1418 1227
1419 frddr_c: audio-contro 1228 frddr_c: audio-controller@240 {
1420 compatible = 1229 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1230 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1231 #sound-dai-cells = <0>;
1423 sound-name-pr 1232 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1233 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1234 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1235 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1236 amlogic,fifo-depth = <256>;
1428 status = "dis 1237 status = "disabled";
1429 }; 1238 };
1430 1239
1431 arb: reset-controller 1240 arb: reset-controller@280 {
1432 compatible = 1241 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1242 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1243 #reset-cells = <1>;
1435 clocks = <&cl 1244 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1245 };
1437 1246
1438 tdmin_a: audio-contro 1247 tdmin_a: audio-controller@300 {
1439 compatible = 1248 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1249 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1250 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1251 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1252 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1253 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1254 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1255 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1256 clock-names = "pclk", "sclk", "sclk_sel",
1448 1257 "lrclk", "lrclk_sel";
1449 status = "dis 1258 status = "disabled";
1450 }; 1259 };
1451 1260
1452 tdmin_b: audio-contro 1261 tdmin_b: audio-controller@340 {
1453 compatible = 1262 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1263 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1264 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1265 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1266 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1267 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1268 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1269 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1270 clock-names = "pclk", "sclk", "sclk_sel",
1462 1271 "lrclk", "lrclk_sel";
1463 status = "dis 1272 status = "disabled";
1464 }; 1273 };
1465 1274
1466 tdmin_c: audio-contro 1275 tdmin_c: audio-controller@380 {
1467 compatible = 1276 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1277 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1278 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1279 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1280 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1281 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1282 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1283 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1284 clock-names = "pclk", "sclk", "sclk_sel",
1476 1285 "lrclk", "lrclk_sel";
1477 status = "dis 1286 status = "disabled";
1478 }; 1287 };
1479 1288
1480 tdmin_lb: audio-contr 1289 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1290 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1291 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1292 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1293 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1294 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1295 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1296 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1297 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1298 clock-names = "pclk", "sclk", "sclk_sel",
1490 1299 "lrclk", "lrclk_sel";
1491 status = "dis 1300 status = "disabled";
1492 }; 1301 };
1493 1302
1494 spdifin: audio-contro 1303 spdifin: audio-controller@400 {
1495 compatible = 1304 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1305 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1306 #sound-dai-cells = <0>;
1498 sound-name-pr 1307 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1308 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1309 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1310 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1311 clock-names = "pclk", "refclk";
1503 status = "dis 1312 status = "disabled";
1504 }; 1313 };
1505 1314
1506 spdifout: audio-contr 1315 spdifout: audio-controller@480 {
1507 compatible = 1316 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1317 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1318 #sound-dai-cells = <0>;
1510 sound-name-pr 1319 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1320 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1321 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1322 clock-names = "pclk", "mclk";
1514 status = "dis 1323 status = "disabled";
1515 }; 1324 };
1516 1325
1517 tdmout_a: audio-contr 1326 tdmout_a: audio-controller@500 {
1518 compatible = 1327 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1328 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1329 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1330 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1331 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1332 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1333 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1334 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1335 clock-names = "pclk", "sclk", "sclk_sel",
1527 1336 "lrclk", "lrclk_sel";
1528 status = "dis 1337 status = "disabled";
1529 }; 1338 };
1530 1339
1531 tdmout_b: audio-contr 1340 tdmout_b: audio-controller@540 {
1532 compatible = 1341 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1342 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1343 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1344 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1345 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1346 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1347 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1348 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1349 clock-names = "pclk", "sclk", "sclk_sel",
1541 1350 "lrclk", "lrclk_sel";
1542 status = "dis 1351 status = "disabled";
1543 }; 1352 };
1544 1353
1545 tdmout_c: audio-contr 1354 tdmout_c: audio-controller@580 {
1546 compatible = 1355 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1356 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1357 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1358 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1359 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1360 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1361 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1362 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1363 clock-names = "pclk", "sclk", "sclk_sel",
1555 1364 "lrclk", "lrclk_sel";
1556 status = "dis 1365 status = "disabled";
1557 }; 1366 };
1558 }; 1367 };
1559 1368
1560 aobus: bus@ff800000 { 1369 aobus: bus@ff800000 {
1561 compatible = "simple- 1370 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1371 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1372 #address-cells = <2>;
1564 #size-cells = <2>; 1373 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1374 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1375
1567 sysctrl_AO: sys-ctrl@ 1376 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1377 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x !! 1378 reg = <0x0 0x0 0x0 0x100>;
1570 1379
1571 clkc_AO: cloc 1380 clkc_AO: clock-controller {
1572 compa 1381 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1382 #clock-cells = <1>;
1574 #rese 1383 #reset-cells = <1>;
1575 clock 1384 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1385 clock-names = "xtal", "mpeg-clk";
1577 }; 1386 };
1578 }; 1387 };
1579 1388
1580 pinctrl_aobus: pinctr 1389 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1390 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1391 #address-cells = <2>;
1583 #size-cells = 1392 #size-cells = <2>;
1584 ranges; 1393 ranges;
1585 1394
1586 gpio_ao: bank 1395 gpio_ao: bank@14 {
1587 reg = 1396 reg = <0x0 0x00014 0x0 0x8>,
1588 1397 <0x0 0x0002c 0x0 0x4>,
1589 1398 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1399 reg-names = "mux", "pull", "gpio";
1591 gpio- 1400 gpio-controller;
1592 #gpio 1401 #gpio-cells = <2>;
1593 gpio- 1402 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1403 };
1595 1404
1596 i2c_ao_sck_4_ 1405 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1406 mux {
1598 1407 groups = "i2c_ao_sck_4";
1599 1408 function = "i2c_ao";
1600 1409 bias-disable;
1601 }; 1410 };
1602 }; 1411 };
1603 1412
1604 i2c_ao_sck_8_ 1413 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1414 mux {
1606 1415 groups = "i2c_ao_sck_8";
1607 1416 function = "i2c_ao";
1608 1417 bias-disable;
1609 }; 1418 };
1610 }; 1419 };
1611 1420
1612 i2c_ao_sck_10 1421 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1422 mux {
1614 1423 groups = "i2c_ao_sck_10";
1615 1424 function = "i2c_ao";
1616 1425 bias-disable;
1617 }; 1426 };
1618 }; 1427 };
1619 1428
1620 i2c_ao_sda_5_ 1429 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1430 mux {
1622 1431 groups = "i2c_ao_sda_5";
1623 1432 function = "i2c_ao";
1624 1433 bias-disable;
1625 }; 1434 };
1626 }; 1435 };
1627 1436
1628 i2c_ao_sda_9_ 1437 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1438 mux {
1630 1439 groups = "i2c_ao_sda_9";
1631 1440 function = "i2c_ao";
1632 1441 bias-disable;
1633 }; 1442 };
1634 }; 1443 };
1635 1444
1636 i2c_ao_sda_11 1445 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1446 mux {
1638 1447 groups = "i2c_ao_sda_11";
1639 1448 function = "i2c_ao";
1640 1449 bias-disable;
1641 }; 1450 };
1642 }; 1451 };
1643 1452
1644 remote_input_ 1453 remote_input_ao_pins: remote_input_ao {
1645 mux { 1454 mux {
1646 1455 groups = "remote_input_ao";
1647 1456 function = "remote_input_ao";
1648 1457 bias-disable;
1649 }; 1458 };
1650 }; 1459 };
1651 1460
1652 uart_ao_a_pin 1461 uart_ao_a_pins: uart_ao_a {
1653 mux { 1462 mux {
1654 1463 groups = "uart_ao_tx_a",
1655 1464 "uart_ao_rx_a";
1656 1465 function = "uart_ao_a";
1657 1466 bias-disable;
1658 }; 1467 };
1659 }; 1468 };
1660 1469
1661 uart_ao_a_cts 1470 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1471 mux {
1663 1472 groups = "uart_ao_cts_a",
1664 1473 "uart_ao_rts_a";
1665 1474 function = "uart_ao_a";
1666 1475 bias-disable;
1667 }; 1476 };
1668 }; 1477 };
1669 1478
1670 uart_ao_b_pin 1479 uart_ao_b_pins: uart_ao_b {
1671 mux { 1480 mux {
1672 1481 groups = "uart_ao_tx_b",
1673 1482 "uart_ao_rx_b";
1674 1483 function = "uart_ao_b";
1675 1484 bias-disable;
1676 }; 1485 };
1677 }; 1486 };
1678 1487
1679 uart_ao_b_cts 1488 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1489 mux {
1681 1490 groups = "uart_ao_cts_b",
1682 1491 "uart_ao_rts_b";
1683 1492 function = "uart_ao_b";
1684 1493 bias-disable;
1685 }; 1494 };
1686 }; 1495 };
1687 }; 1496 };
1688 1497
1689 sec_AO: ao-secure@140 1498 sec_AO: ao-secure@140 {
1690 compatible = 1499 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1500 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1501 amlogic,has-chip-id;
1693 }; 1502 };
1694 1503
1695 pwm_AO_cd: pwm@2000 { 1504 pwm_AO_cd: pwm@2000 {
1696 compatible = 1505 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1506 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1507 #pwm-cells = <3>;
1699 status = "dis 1508 status = "disabled";
1700 }; 1509 };
1701 1510
1702 uart_AO: serial@3000 1511 uart_AO: serial@3000 {
1703 compatible = 1512 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1513 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1514 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1515 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1516 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1517 status = "disabled";
1709 }; 1518 };
1710 1519
1711 uart_AO_B: serial@400 1520 uart_AO_B: serial@4000 {
1712 compatible = 1521 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1522 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1523 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1524 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1525 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1526 status = "disabled";
1718 }; 1527 };
1719 1528
1720 i2c_AO: i2c@5000 { 1529 i2c_AO: i2c@5000 {
1721 compatible = 1530 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1531 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1532 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1533 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1534 #address-cells = <1>;
1726 #size-cells = 1535 #size-cells = <0>;
1727 status = "dis 1536 status = "disabled";
1728 }; 1537 };
1729 1538
1730 pwm_AO_ab: pwm@7000 { 1539 pwm_AO_ab: pwm@7000 {
1731 compatible = 1540 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1541 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1542 #pwm-cells = <3>;
1734 status = "dis 1543 status = "disabled";
1735 }; 1544 };
1736 1545
1737 ir: ir@8000 { 1546 ir: ir@8000 {
1738 compatible = 1547 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1548 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1549 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1550 status = "disabled";
1742 }; 1551 };
1743 1552
1744 saradc: adc@9000 { 1553 saradc: adc@9000 {
1745 compatible = 1554 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1555 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1556 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1557 #io-channel-cells = <1>;
1749 interrupts = 1558 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1559 clocks = <&xtal>,
1751 <&cl 1560 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1561 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1562 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1563 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1564 status = "disabled";
1756 }; 1565 };
1757 }; 1566 };
1758 1567
1759 ge2d: ge2d@ff940000 { <<
1760 compatible = "amlogic <<
1761 reg = <0x0 0xff940000 <<
1762 interrupts = <GIC_SPI <<
1763 clocks = <&clkc CLKID <<
1764 resets = <&reset RESE <<
1765 }; <<
1766 <<
1767 gic: interrupt-controller@ffc 1568 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1569 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1570 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1571 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1572 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1573 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1574 interrupt-controller;
1774 interrupts = <GIC_PPI 1575 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1576 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1577 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1578 #address-cells = <0>;
1778 }; 1579 };
1779 1580
1780 cbus: bus@ffd00000 { 1581 cbus: bus@ffd00000 {
1781 compatible = "simple- 1582 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1583 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1584 #address-cells = <2>;
1784 #size-cells = <2>; 1585 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1586 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1587
1787 reset: reset-controll 1588 reset: reset-controller@1004 {
1788 compatible = 1589 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1590 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1591 #reset-cells = <1>;
1791 }; 1592 };
1792 1593
1793 gpio_intc: interrupt- 1594 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1595 compatible = "amlogic,meson-axg-gpio-intc",
1795 1596 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1597 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1598 interrupt-controller;
1798 #interrupt-ce 1599 #interrupt-cells = <2>;
1799 amlogic,chann 1600 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1601 };
1801 1602
1802 watchdog@f0d0 { 1603 watchdog@f0d0 {
1803 compatible = 1604 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1605 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1606 clocks = <&xtal>;
1806 }; 1607 };
1807 1608
1808 pwm_ab: pwm@1b000 { 1609 pwm_ab: pwm@1b000 {
1809 compatible = 1610 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1611 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1612 #pwm-cells = <3>;
1812 status = "dis 1613 status = "disabled";
1813 }; 1614 };
1814 1615
1815 pwm_cd: pwm@1a000 { 1616 pwm_cd: pwm@1a000 {
1816 compatible = 1617 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1618 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1619 #pwm-cells = <3>;
1819 status = "dis 1620 status = "disabled";
1820 }; 1621 };
1821 1622
1822 spicc0: spi@13000 { 1623 spicc0: spi@13000 {
1823 compatible = 1624 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1625 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1626 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1627 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1628 clock-names = "core";
1828 #address-cell 1629 #address-cells = <1>;
1829 #size-cells = 1630 #size-cells = <0>;
1830 status = "dis 1631 status = "disabled";
1831 }; 1632 };
1832 1633
1833 spicc1: spi@15000 { 1634 spicc1: spi@15000 {
1834 compatible = 1635 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1636 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1637 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1638 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1639 clock-names = "core";
1839 #address-cell 1640 #address-cells = <1>;
1840 #size-cells = 1641 #size-cells = <0>;
1841 status = "dis 1642 status = "disabled";
1842 }; 1643 };
1843 1644
1844 clk_msr: clock-measur 1645 clk_msr: clock-measure@18000 {
1845 compatible = 1646 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1647 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1648 };
1848 1649
1849 i2c3: i2c@1c000 { 1650 i2c3: i2c@1c000 {
1850 compatible = 1651 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1652 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1653 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1654 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1655 #address-cells = <1>;
1855 #size-cells = 1656 #size-cells = <0>;
1856 status = "dis 1657 status = "disabled";
1857 }; 1658 };
1858 1659
1859 i2c2: i2c@1d000 { 1660 i2c2: i2c@1d000 {
1860 compatible = 1661 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1662 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1663 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1664 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1665 #address-cells = <1>;
1865 #size-cells = 1666 #size-cells = <0>;
1866 status = "dis 1667 status = "disabled";
1867 }; 1668 };
1868 1669
1869 i2c1: i2c@1e000 { 1670 i2c1: i2c@1e000 {
1870 compatible = 1671 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1672 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1673 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1674 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1675 #address-cells = <1>;
1875 #size-cells = 1676 #size-cells = <0>;
1876 status = "dis 1677 status = "disabled";
1877 }; 1678 };
1878 1679
1879 i2c0: i2c@1f000 { 1680 i2c0: i2c@1f000 {
1880 compatible = 1681 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1682 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1683 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1684 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1685 #address-cells = <1>;
1885 #size-cells = 1686 #size-cells = <0>;
1886 status = "dis 1687 status = "disabled";
1887 }; 1688 };
1888 1689
1889 uart_B: serial@23000 1690 uart_B: serial@23000 {
1890 compatible = 1691 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1692 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1693 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1694 status = "disabled";
1894 clocks = <&xt 1695 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1696 clock-names = "xtal", "pclk", "baud";
1896 }; 1697 };
1897 1698
1898 uart_A: serial@24000 1699 uart_A: serial@24000 {
1899 compatible = 1700 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1701 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1702 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1703 status = "disabled";
1903 clocks = <&xt 1704 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1705 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < <<
1906 }; 1706 };
1907 }; 1707 };
1908 1708
1909 apb: bus@ffe00000 { 1709 apb: bus@ffe00000 {
1910 compatible = "simple- 1710 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1711 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1712 #address-cells = <2>;
1913 #size-cells = <2>; 1713 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1714 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1715
1916 sd_emmc_b: mmc@5000 { !! 1716 sd_emmc_b: sd@5000 {
1917 compatible = 1717 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1718 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = !! 1719 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1920 status = "dis 1720 status = "disabled";
1921 clocks = <&cl 1721 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1722 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1723 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1724 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1725 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1726 };
1927 1727
1928 sd_emmc_c: mmc@7000 { 1728 sd_emmc_c: mmc@7000 {
1929 compatible = 1729 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1730 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = !! 1731 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1932 status = "dis 1732 status = "disabled";
1933 clocks = <&cl 1733 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1734 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1735 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1736 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1737 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; <<
1954 <<
1955 usb2_phy1: phy@9020 { <<
1956 compatible = <<
1957 #phy-cells = <<
1958 reg = <0x0 0x <<
1959 clocks = <&cl <<
1960 clock-names = <<
1961 resets = <&re <<
1962 reset-names = <<
1963 }; 1738 };
1964 }; 1739 };
1965 1740
1966 sram: sram@fffc0000 { 1741 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1742 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1743 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1744 #address-cells = <1>;
1970 #size-cells = <1>; 1745 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1746 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1747
1973 cpu_scp_lpri: scp-sra 1748 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1749 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1750 reg = <0x13000 0x400>;
1976 }; 1751 };
1977 1752
1978 cpu_scp_hpri: scp-sra 1753 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1754 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1755 reg = <0x13400 0x400>;
1981 }; 1756 };
1982 }; 1757 };
1983 }; 1758 };
1984 1759
1985 timer { 1760 timer {
1986 compatible = "arm,armv8-timer 1761 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1762 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1763 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1764 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1765 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1766 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1767 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1768 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1769 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1770 };
1996 1771
1997 xtal: xtal-clk { 1772 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1773 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1774 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1775 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1776 #clock-cells = <0>;
2002 }; 1777 };
2003 }; 1778 };
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