1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> 15 #include <dt-bindings/power/meson-axg-power.h>
16 16
17 / { 17 / {
18 compatible = "amlogic,meson-axg"; 18 compatible = "amlogic,meson-axg";
19 19
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 tdmif_a: audio-controller-0 { 24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 25 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 28 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 30 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 31 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 tdmif_b: audio-controller-1 { 35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 36 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 39 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 41 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 42 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 tdmif_c: audio-controller-2 { 46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 47 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 50 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 52 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 53 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 54 status = "disabled";
55 }; 55 };
56 56
57 arm-pmu { 57 arm-pmu {
58 compatible = "arm,cortex-a53-p 58 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 64 };
65 65
66 cpus { 66 cpus {
67 #address-cells = <0x2>; 67 #address-cells = <0x2>;
68 #size-cells = <0x0>; 68 #size-cells = <0x0>;
69 69
70 cpu0: cpu@0 { 70 cpu0: cpu@0 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 73 reg = <0x0 0x0>;
74 enable-method = "psci" 74 enable-method = "psci";
75 next-level-cache = <&l 75 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 76 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 77 };
80 78
81 cpu1: cpu@1 { 79 cpu1: cpu@1 {
82 device_type = "cpu"; 80 device_type = "cpu";
83 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 82 reg = <0x0 0x1>;
85 enable-method = "psci" 83 enable-method = "psci";
86 next-level-cache = <&l 84 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 85 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 86 };
91 87
92 cpu2: cpu@2 { 88 cpu2: cpu@2 {
93 device_type = "cpu"; 89 device_type = "cpu";
94 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 91 reg = <0x0 0x2>;
96 enable-method = "psci" 92 enable-method = "psci";
97 next-level-cache = <&l 93 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 94 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 95 };
102 96
103 cpu3: cpu@3 { 97 cpu3: cpu@3 {
104 device_type = "cpu"; 98 device_type = "cpu";
105 compatible = "arm,cort 99 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 100 reg = <0x0 0x3>;
107 enable-method = "psci" 101 enable-method = "psci";
108 next-level-cache = <&l 102 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 103 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 104 };
113 105
114 l2: l2-cache0 { 106 l2: l2-cache0 {
115 compatible = "cache"; 107 compatible = "cache";
116 cache-level = <2>; 108 cache-level = <2>;
117 cache-unified; <<
118 }; 109 };
119 }; 110 };
120 111
121 sm: secure-monitor { 112 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 113 compatible = "amlogic,meson-gxbb-sm";
123 }; 114 };
124 115
125 efuse: efuse { 116 efuse: efuse {
126 compatible = "amlogic,meson-gx 117 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 118 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 119 #address-cells = <1>;
129 #size-cells = <1>; 120 #size-cells = <1>;
130 read-only; 121 read-only;
131 secure-monitor = <&sm>; 122 secure-monitor = <&sm>;
132 }; 123 };
133 124
134 psci { 125 psci {
135 compatible = "arm,psci-1.0"; 126 compatible = "arm,psci-1.0";
136 method = "smc"; 127 method = "smc";
137 }; 128 };
138 129
139 reserved-memory { 130 reserved-memory {
140 #address-cells = <2>; 131 #address-cells = <2>;
141 #size-cells = <2>; 132 #size-cells = <2>;
142 ranges; 133 ranges;
143 134
144 /* 16 MiB reserved for Hardwar 135 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 136 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 137 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 138 no-map;
148 }; 139 };
149 140
150 /* Alternate 3 MiB reserved fo 141 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 142 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 143 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 144 no-map;
154 }; 145 };
155 }; 146 };
156 147
157 scpi { 148 scpi {
158 compatible = "arm,scpi-pre-1.0 149 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 150 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 151 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 152
162 scpi_clocks: clocks { 153 scpi_clocks: clocks {
163 compatible = "arm,scpi 154 compatible = "arm,scpi-clocks";
164 155
165 scpi_dvfs: clocks-0 { 156 scpi_dvfs: clocks-0 {
166 compatible = " 157 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 158 #clock-cells = <1>;
168 clock-indices 159 clock-indices = <0>;
169 clock-output-n 160 clock-output-names = "vcpu";
170 }; 161 };
171 }; 162 };
172 163
173 scpi_sensors: sensors { 164 scpi_sensors: sensors {
174 compatible = "amlogic, 165 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 166 #thermal-sensor-cells = <1>;
176 }; 167 };
177 }; 168 };
178 169
179 soc { 170 soc {
180 compatible = "simple-bus"; 171 compatible = "simple-bus";
181 #address-cells = <2>; 172 #address-cells = <2>;
182 #size-cells = <2>; 173 #size-cells = <2>;
183 ranges; 174 ranges;
184 175
185 pcieA: pcie@f9800000 { 176 pcieA: pcie@f9800000 {
186 compatible = "amlogic, 177 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
187 reg = <0x0 0xf9800000 178 reg = <0x0 0xf9800000 0x0 0x400000>,
188 <0x0 0xff646000 179 <0x0 0xff646000 0x0 0x2000>,
189 <0x0 0xf9f00000 180 <0x0 0xf9f00000 0x0 0x100000>;
190 reg-names = "elbi", "c 181 reg-names = "elbi", "cfg", "config";
191 interrupts = <GIC_SPI 182 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
192 #interrupt-cells = <1> 183 #interrupt-cells = <1>;
193 interrupt-map-mask = < 184 interrupt-map-mask = <0 0 0 0>;
194 interrupt-map = <0 0 0 185 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
195 bus-range = <0x0 0xff> 186 bus-range = <0x0 0xff>;
196 #address-cells = <3>; 187 #address-cells = <3>;
197 #size-cells = <2>; 188 #size-cells = <2>;
198 device_type = "pci"; 189 device_type = "pci";
199 ranges = <0x82000000 0 190 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
200 191
201 clocks = <&clkc CLKID_ 192 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
202 clock-names = "general 193 clock-names = "general", "pclk", "port";
203 resets = <&reset RESET 194 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
204 reset-names = "port", 195 reset-names = "port", "apb";
205 num-lanes = <1>; 196 num-lanes = <1>;
206 phys = <&pcie_phy>; 197 phys = <&pcie_phy>;
207 phy-names = "pcie"; 198 phy-names = "pcie";
208 status = "disabled"; 199 status = "disabled";
209 }; 200 };
210 201
211 pcieB: pcie@fa000000 { 202 pcieB: pcie@fa000000 {
212 compatible = "amlogic, 203 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
213 reg = <0x0 0xfa000000 204 reg = <0x0 0xfa000000 0x0 0x400000>,
214 <0x0 0xff648000 205 <0x0 0xff648000 0x0 0x2000>,
215 <0x0 0xfa400000 206 <0x0 0xfa400000 0x0 0x100000>;
216 reg-names = "elbi", "c 207 reg-names = "elbi", "cfg", "config";
217 interrupts = <GIC_SPI 208 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
218 #interrupt-cells = <1> 209 #interrupt-cells = <1>;
219 interrupt-map-mask = < 210 interrupt-map-mask = <0 0 0 0>;
220 interrupt-map = <0 0 0 211 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
221 bus-range = <0x0 0xff> 212 bus-range = <0x0 0xff>;
222 #address-cells = <3>; 213 #address-cells = <3>;
223 #size-cells = <2>; 214 #size-cells = <2>;
224 device_type = "pci"; 215 device_type = "pci";
225 ranges = <0x82000000 0 216 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
226 217
227 clocks = <&clkc CLKID_ 218 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
228 clock-names = "general 219 clock-names = "general", "pclk", "port";
229 resets = <&reset RESET 220 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
230 reset-names = "port", 221 reset-names = "port", "apb";
231 num-lanes = <1>; 222 num-lanes = <1>;
232 phys = <&pcie_phy>; 223 phys = <&pcie_phy>;
233 phy-names = "pcie"; 224 phy-names = "pcie";
234 status = "disabled"; 225 status = "disabled";
235 }; 226 };
236 227
237 usb: usb@ffe09080 { 228 usb: usb@ffe09080 {
238 compatible = "amlogic, 229 compatible = "amlogic,meson-axg-usb-ctrl";
239 reg = <0x0 0xffe09080 230 reg = <0x0 0xffe09080 0x0 0x20>;
240 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; 232 #address-cells = <2>;
242 #size-cells = <2>; 233 #size-cells = <2>;
243 ranges; 234 ranges;
244 235
245 clocks = <&clkc CLKID_ 236 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
246 clock-names = "usb_ctr 237 clock-names = "usb_ctrl", "ddr";
247 resets = <&reset RESET 238 resets = <&reset RESET_USB_OTG>;
248 239
249 dr_mode = "otg"; 240 dr_mode = "otg";
250 241
251 phys = <&usb2_phy1>; 242 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1 243 phy-names = "usb2-phy1";
253 244
254 dwc2: usb@ff400000 { 245 dwc2: usb@ff400000 {
255 compatible = " 246 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
256 reg = <0x0 0xf 247 reg = <0x0 0xff400000 0x0 0x40000>;
257 interrupts = < 248 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk 249 clocks = <&clkc CLKID_USB1>;
259 clock-names = 250 clock-names = "otg";
260 phys = <&usb2_ 251 phys = <&usb2_phy1>;
261 dr_mode = "per 252 dr_mode = "peripheral";
262 g-rx-fifo-size 253 g-rx-fifo-size = <192>;
263 g-np-tx-fifo-s 254 g-np-tx-fifo-size = <128>;
264 g-tx-fifo-size 255 g-tx-fifo-size = <128 128 16 16 16>;
265 }; 256 };
266 257
267 dwc3: usb@ff500000 { 258 dwc3: usb@ff500000 {
268 compatible = " 259 compatible = "snps,dwc3";
269 reg = <0x0 0xf 260 reg = <0x0 0xff500000 0x0 0x100000>;
270 interrupts = < 261 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
271 dr_mode = "hos 262 dr_mode = "host";
272 maximum-speed 263 maximum-speed = "high-speed";
273 snps,dis_u2_su 264 snps,dis_u2_susphy_quirk;
274 }; 265 };
275 }; 266 };
276 267
277 ethmac: ethernet@ff3f0000 { 268 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 269 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 270 "snps,dwmac-3.70a",
280 "snps,dwm 271 "snps,dwmac";
281 reg = <0x0 0xff3f0000 272 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 273 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 275 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 276 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 277 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 278 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 279 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 280 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 281 "timing-adjustment";
291 rx-fifo-depth = <4096> 282 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 283 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc 284 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
294 status = "disabled"; 285 status = "disabled";
295 }; 286 };
296 287
297 pcie_phy: phy@ff644000 { 288 pcie_phy: phy@ff644000 {
298 compatible = "amlogic, 289 compatible = "amlogic,axg-pcie-phy";
299 reg = <0x0 0xff644000 290 reg = <0x0 0xff644000 0x0 0x1c>;
300 resets = <&reset RESET 291 resets = <&reset RESET_PCIE_PHY>;
301 phys = <&mipi_pcie_ana 292 phys = <&mipi_pcie_analog_dphy>;
302 phy-names = "analog"; 293 phy-names = "analog";
303 #phy-cells = <0>; 294 #phy-cells = <0>;
304 }; 295 };
305 296
306 pdm: audio-controller@ff632000 297 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 298 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 299 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 300 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 301 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 302 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 303 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 304 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 305 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 306 status = "disabled";
316 }; 307 };
317 308
318 periphs: bus@ff634000 { 309 periphs: bus@ff634000 {
319 compatible = "simple-b 310 compatible = "simple-bus";
320 reg = <0x0 0xff634000 311 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 312 #address-cells = <2>;
322 #size-cells = <2>; 313 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 314 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 315
325 hwrng: rng@18 { 316 hwrng: rng@18 {
326 compatible = " 317 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 318 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 319 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 320 clock-names = "core";
330 }; 321 };
331 322
332 pinctrl_periphs: pinct 323 pinctrl_periphs: pinctrl@480 {
333 compatible = " 324 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 325 #address-cells = <2>;
335 #size-cells = 326 #size-cells = <2>;
336 ranges; 327 ranges;
337 328
338 gpio: bank@480 329 gpio: bank@480 {
339 reg = 330 reg = <0x0 0x00480 0x0 0x40>,
340 331 <0x0 0x004e8 0x0 0x14>,
341 332 <0x0 0x00520 0x0 0x14>,
342 333 <0x0 0x00430 0x0 0x3c>;
343 reg-na 334 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 335 gpio-controller;
345 #gpio- 336 #gpio-cells = <2>;
346 gpio-r 337 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 338 };
348 339
349 i2c0_pins: i2c 340 i2c0_pins: i2c0 {
350 mux { 341 mux {
351 342 groups = "i2c0_sck",
352 343 "i2c0_sda";
353 344 function = "i2c0";
354 345 bias-disable;
355 }; 346 };
356 }; 347 };
357 348
358 i2c1_x_pins: i 349 i2c1_x_pins: i2c1_x {
359 mux { 350 mux {
360 351 groups = "i2c1_sck_x",
361 352 "i2c1_sda_x";
362 353 function = "i2c1";
363 354 bias-disable;
364 }; 355 };
365 }; 356 };
366 357
367 i2c1_z_pins: i 358 i2c1_z_pins: i2c1_z {
368 mux { 359 mux {
369 360 groups = "i2c1_sck_z",
370 361 "i2c1_sda_z";
371 362 function = "i2c1";
372 363 bias-disable;
373 }; 364 };
374 }; 365 };
375 366
376 i2c2_a_pins: i 367 i2c2_a_pins: i2c2_a {
377 mux { 368 mux {
378 369 groups = "i2c2_sck_a",
379 370 "i2c2_sda_a";
380 371 function = "i2c2";
381 372 bias-disable;
382 }; 373 };
383 }; 374 };
384 375
385 i2c2_x_pins: i 376 i2c2_x_pins: i2c2_x {
386 mux { 377 mux {
387 378 groups = "i2c2_sck_x",
388 379 "i2c2_sda_x";
389 380 function = "i2c2";
390 381 bias-disable;
391 }; 382 };
392 }; 383 };
393 384
394 i2c3_a6_pins: 385 i2c3_a6_pins: i2c3_a6 {
395 mux { 386 mux {
396 387 groups = "i2c3_sda_a6",
397 388 "i2c3_sck_a7";
398 389 function = "i2c3";
399 390 bias-disable;
400 }; 391 };
401 }; 392 };
402 393
403 i2c3_a12_pins: 394 i2c3_a12_pins: i2c3_a12 {
404 mux { 395 mux {
405 396 groups = "i2c3_sda_a12",
406 397 "i2c3_sck_a13";
407 398 function = "i2c3";
408 399 bias-disable;
409 }; 400 };
410 }; 401 };
411 402
412 i2c3_a19_pins: 403 i2c3_a19_pins: i2c3_a19 {
413 mux { 404 mux {
414 405 groups = "i2c3_sda_a19",
415 406 "i2c3_sck_a20";
416 407 function = "i2c3";
417 408 bias-disable;
418 }; 409 };
419 }; 410 };
420 411
421 emmc_pins: emm 412 emmc_pins: emmc {
422 mux-0 413 mux-0 {
423 414 groups = "emmc_nand_d0",
424 415 "emmc_nand_d1",
425 416 "emmc_nand_d2",
426 417 "emmc_nand_d3",
427 418 "emmc_nand_d4",
428 419 "emmc_nand_d5",
429 420 "emmc_nand_d6",
430 421 "emmc_nand_d7",
431 422 "emmc_cmd";
432 423 function = "emmc";
433 424 bias-pull-up;
434 }; 425 };
435 426
436 mux-1 427 mux-1 {
437 428 groups = "emmc_clk";
438 429 function = "emmc";
439 430 bias-disable;
440 }; 431 };
441 }; 432 };
442 433
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 434 emmc_ds_pins: emmc_ds {
465 mux { 435 mux {
466 436 groups = "emmc_ds";
467 437 function = "emmc";
468 438 bias-pull-down;
469 }; 439 };
470 }; 440 };
471 441
472 emmc_clk_gate_ 442 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 443 mux {
474 444 groups = "BOOT_8";
475 445 function = "gpio_periphs";
476 446 bias-pull-down;
477 }; 447 };
478 }; 448 };
479 449
480 eth_rgmii_x_pi 450 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 451 mux {
482 452 groups = "eth_mdio_x",
483 453 "eth_mdc_x",
484 454 "eth_rgmii_rx_clk_x",
485 455 "eth_rx_dv_x",
486 456 "eth_rxd0_x",
487 457 "eth_rxd1_x",
488 458 "eth_rxd2_rgmii",
489 459 "eth_rxd3_rgmii",
490 460 "eth_rgmii_tx_clk",
491 461 "eth_txen_x",
492 462 "eth_txd0_x",
493 463 "eth_txd1_x",
494 464 "eth_txd2_rgmii",
495 465 "eth_txd3_rgmii";
496 466 function = "eth";
497 467 bias-disable;
498 }; 468 };
499 }; 469 };
500 470
501 eth_rgmii_y_pi 471 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 472 mux {
503 473 groups = "eth_mdio_y",
504 474 "eth_mdc_y",
505 475 "eth_rgmii_rx_clk_y",
506 476 "eth_rx_dv_y",
507 477 "eth_rxd0_y",
508 478 "eth_rxd1_y",
509 479 "eth_rxd2_rgmii",
510 480 "eth_rxd3_rgmii",
511 481 "eth_rgmii_tx_clk",
512 482 "eth_txen_y",
513 483 "eth_txd0_y",
514 484 "eth_txd1_y",
515 485 "eth_txd2_rgmii",
516 486 "eth_txd3_rgmii";
517 487 function = "eth";
518 488 bias-disable;
519 }; 489 };
520 }; 490 };
521 491
522 eth_rmii_x_pin 492 eth_rmii_x_pins: eth-x-rmii {
523 mux { 493 mux {
524 494 groups = "eth_mdio_x",
525 495 "eth_mdc_x",
526 496 "eth_rgmii_rx_clk_x",
527 497 "eth_rx_dv_x",
528 498 "eth_rxd0_x",
529 499 "eth_rxd1_x",
530 500 "eth_txen_x",
531 501 "eth_txd0_x",
532 502 "eth_txd1_x";
533 503 function = "eth";
534 504 bias-disable;
535 }; 505 };
536 }; 506 };
537 507
538 eth_rmii_y_pin 508 eth_rmii_y_pins: eth-y-rmii {
539 mux { 509 mux {
540 510 groups = "eth_mdio_y",
541 511 "eth_mdc_y",
542 512 "eth_rgmii_rx_clk_y",
543 513 "eth_rx_dv_y",
544 514 "eth_rxd0_y",
545 515 "eth_rxd1_y",
546 516 "eth_txen_y",
547 517 "eth_txd0_y",
548 518 "eth_txd1_y";
549 519 function = "eth";
550 520 bias-disable;
551 }; 521 };
552 }; 522 };
553 523
554 mclk_b_pins: m 524 mclk_b_pins: mclk_b {
555 mux { 525 mux {
556 526 groups = "mclk_b";
557 527 function = "mclk_b";
558 528 bias-disable;
559 }; 529 };
560 }; 530 };
561 531
562 mclk_c_pins: m 532 mclk_c_pins: mclk_c {
563 mux { 533 mux {
564 534 groups = "mclk_c";
565 535 function = "mclk_c";
566 536 bias-disable;
567 }; 537 };
568 }; 538 };
569 539
570 pdm_dclk_a14_p 540 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 541 mux {
572 542 groups = "pdm_dclk_a14";
573 543 function = "pdm";
574 544 bias-disable;
575 }; 545 };
576 }; 546 };
577 547
578 pdm_dclk_a19_p 548 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 549 mux {
580 550 groups = "pdm_dclk_a19";
581 551 function = "pdm";
582 552 bias-disable;
583 }; 553 };
584 }; 554 };
585 555
586 pdm_din0_pins: 556 pdm_din0_pins: pdm_din0 {
587 mux { 557 mux {
588 558 groups = "pdm_din0";
589 559 function = "pdm";
590 560 bias-disable;
591 }; 561 };
592 }; 562 };
593 563
594 pdm_din1_pins: 564 pdm_din1_pins: pdm_din1 {
595 mux { 565 mux {
596 566 groups = "pdm_din1";
597 567 function = "pdm";
598 568 bias-disable;
599 }; 569 };
600 }; 570 };
601 571
602 pdm_din2_pins: 572 pdm_din2_pins: pdm_din2 {
603 mux { 573 mux {
604 574 groups = "pdm_din2";
605 575 function = "pdm";
606 576 bias-disable;
607 }; 577 };
608 }; 578 };
609 579
610 pdm_din3_pins: 580 pdm_din3_pins: pdm_din3 {
611 mux { 581 mux {
612 582 groups = "pdm_din3";
613 583 function = "pdm";
614 584 bias-disable;
615 }; 585 };
616 }; 586 };
617 587
618 pwm_a_a_pins: 588 pwm_a_a_pins: pwm_a_a {
619 mux { 589 mux {
620 590 groups = "pwm_a_a";
621 591 function = "pwm_a";
622 592 bias-disable;
623 }; 593 };
624 }; 594 };
625 595
626 pwm_a_x18_pins 596 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 597 mux {
628 598 groups = "pwm_a_x18";
629 599 function = "pwm_a";
630 600 bias-disable;
631 }; 601 };
632 }; 602 };
633 603
634 pwm_a_x20_pins 604 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 605 mux {
636 606 groups = "pwm_a_x20";
637 607 function = "pwm_a";
638 608 bias-disable;
639 }; 609 };
640 }; 610 };
641 611
642 pwm_a_z_pins: 612 pwm_a_z_pins: pwm_a_z {
643 mux { 613 mux {
644 614 groups = "pwm_a_z";
645 615 function = "pwm_a";
646 616 bias-disable;
647 }; 617 };
648 }; 618 };
649 619
650 pwm_b_a_pins: 620 pwm_b_a_pins: pwm_b_a {
651 mux { 621 mux {
652 622 groups = "pwm_b_a";
653 623 function = "pwm_b";
654 624 bias-disable;
655 }; 625 };
656 }; 626 };
657 627
658 pwm_b_x_pins: 628 pwm_b_x_pins: pwm_b_x {
659 mux { 629 mux {
660 630 groups = "pwm_b_x";
661 631 function = "pwm_b";
662 632 bias-disable;
663 }; 633 };
664 }; 634 };
665 635
666 pwm_b_z_pins: 636 pwm_b_z_pins: pwm_b_z {
667 mux { 637 mux {
668 638 groups = "pwm_b_z";
669 639 function = "pwm_b";
670 640 bias-disable;
671 }; 641 };
672 }; 642 };
673 643
674 pwm_c_a_pins: 644 pwm_c_a_pins: pwm_c_a {
675 mux { 645 mux {
676 646 groups = "pwm_c_a";
677 647 function = "pwm_c";
678 648 bias-disable;
679 }; 649 };
680 }; 650 };
681 651
682 pwm_c_x10_pins 652 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 653 mux {
684 654 groups = "pwm_c_x10";
685 655 function = "pwm_c";
686 656 bias-disable;
687 }; 657 };
688 }; 658 };
689 659
690 pwm_c_x17_pins 660 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 661 mux {
692 662 groups = "pwm_c_x17";
693 663 function = "pwm_c";
694 664 bias-disable;
695 }; 665 };
696 }; 666 };
697 667
698 pwm_d_x11_pins 668 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 669 mux {
700 670 groups = "pwm_d_x11";
701 671 function = "pwm_d";
702 672 bias-disable;
703 }; 673 };
704 }; 674 };
705 675
706 pwm_d_x16_pins 676 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 677 mux {
708 678 groups = "pwm_d_x16";
709 679 function = "pwm_d";
710 680 bias-disable;
711 }; 681 };
712 }; 682 };
713 683
714 sdio_pins: sdi 684 sdio_pins: sdio {
715 mux-0 685 mux-0 {
716 686 groups = "sdio_d0",
717 687 "sdio_d1",
718 688 "sdio_d2",
719 689 "sdio_d3",
720 690 "sdio_cmd";
721 691 function = "sdio";
722 692 bias-pull-up;
723 }; 693 };
724 694
725 mux-1 695 mux-1 {
726 696 groups = "sdio_clk";
727 697 function = "sdio";
728 698 bias-disable;
729 }; 699 };
730 }; 700 };
731 701
732 sdio_clk_gate_ 702 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 703 mux {
734 704 groups = "GPIOX_4";
735 705 function = "gpio_periphs";
736 706 bias-pull-down;
737 }; 707 };
738 }; 708 };
739 709
740 spdif_in_z_pin 710 spdif_in_z_pins: spdif_in_z {
741 mux { 711 mux {
742 712 groups = "spdif_in_z";
743 713 function = "spdif_in";
744 714 bias-disable;
745 }; 715 };
746 }; 716 };
747 717
748 spdif_in_a1_pi 718 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 719 mux {
750 720 groups = "spdif_in_a1";
751 721 function = "spdif_in";
752 722 bias-disable;
753 }; 723 };
754 }; 724 };
755 725
756 spdif_in_a7_pi 726 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 727 mux {
758 728 groups = "spdif_in_a7";
759 729 function = "spdif_in";
760 730 bias-disable;
761 }; 731 };
762 }; 732 };
763 733
764 spdif_in_a19_p 734 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 735 mux {
766 736 groups = "spdif_in_a19";
767 737 function = "spdif_in";
768 738 bias-disable;
769 }; 739 };
770 }; 740 };
771 741
772 spdif_in_a20_p 742 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 743 mux {
774 744 groups = "spdif_in_a20";
775 745 function = "spdif_in";
776 746 bias-disable;
777 }; 747 };
778 }; 748 };
779 749
780 spdif_out_a1_p 750 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 751 mux {
782 752 groups = "spdif_out_a1";
783 753 function = "spdif_out";
784 754 bias-disable;
785 }; 755 };
786 }; 756 };
787 757
788 spdif_out_a11_ 758 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 759 mux {
790 760 groups = "spdif_out_a11";
791 761 function = "spdif_out";
792 762 bias-disable;
793 }; 763 };
794 }; 764 };
795 765
796 spdif_out_a19_ 766 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 767 mux {
798 768 groups = "spdif_out_a19";
799 769 function = "spdif_out";
800 770 bias-disable;
801 }; 771 };
802 }; 772 };
803 773
804 spdif_out_a20_ 774 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 775 mux {
806 776 groups = "spdif_out_a20";
807 777 function = "spdif_out";
808 778 bias-disable;
809 }; 779 };
810 }; 780 };
811 781
812 spdif_out_z_pi 782 spdif_out_z_pins: spdif_out_z {
813 mux { 783 mux {
814 784 groups = "spdif_out_z";
815 785 function = "spdif_out";
816 786 bias-disable;
817 }; 787 };
818 }; 788 };
819 789
820 spi0_pins: spi 790 spi0_pins: spi0 {
821 mux { 791 mux {
822 792 groups = "spi0_miso",
823 793 "spi0_mosi",
824 794 "spi0_clk";
825 795 function = "spi0";
826 796 bias-disable;
827 }; 797 };
828 }; 798 };
829 799
830 spi0_ss0_pins: 800 spi0_ss0_pins: spi0_ss0 {
831 mux { 801 mux {
832 802 groups = "spi0_ss0";
833 803 function = "spi0";
834 804 bias-disable;
835 }; 805 };
836 }; 806 };
837 807
838 spi0_ss1_pins: 808 spi0_ss1_pins: spi0_ss1 {
839 mux { 809 mux {
840 810 groups = "spi0_ss1";
841 811 function = "spi0";
842 812 bias-disable;
843 }; 813 };
844 }; 814 };
845 815
846 spi0_ss2_pins: 816 spi0_ss2_pins: spi0_ss2 {
847 mux { 817 mux {
848 818 groups = "spi0_ss2";
849 819 function = "spi0";
850 820 bias-disable;
851 }; 821 };
852 }; 822 };
853 823
854 spi1_a_pins: s 824 spi1_a_pins: spi1_a {
855 mux { 825 mux {
856 826 groups = "spi1_miso_a",
857 827 "spi1_mosi_a",
858 828 "spi1_clk_a";
859 829 function = "spi1";
860 830 bias-disable;
861 }; 831 };
862 }; 832 };
863 833
864 spi1_ss0_a_pin 834 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 835 mux {
866 836 groups = "spi1_ss0_a";
867 837 function = "spi1";
868 838 bias-disable;
869 }; 839 };
870 }; 840 };
871 841
872 spi1_ss1_pins: 842 spi1_ss1_pins: spi1_ss1 {
873 mux { 843 mux {
874 844 groups = "spi1_ss1";
875 845 function = "spi1";
876 846 bias-disable;
877 }; 847 };
878 }; 848 };
879 849
880 spi1_x_pins: s 850 spi1_x_pins: spi1_x {
881 mux { 851 mux {
882 852 groups = "spi1_miso_x",
883 853 "spi1_mosi_x",
884 854 "spi1_clk_x";
885 855 function = "spi1";
886 856 bias-disable;
887 }; 857 };
888 }; 858 };
889 859
890 spi1_ss0_x_pin 860 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 861 mux {
892 862 groups = "spi1_ss0_x";
893 863 function = "spi1";
894 864 bias-disable;
895 }; 865 };
896 }; 866 };
897 867
898 tdma_din0_pins 868 tdma_din0_pins: tdma_din0 {
899 mux { 869 mux {
900 870 groups = "tdma_din0";
901 871 function = "tdma";
902 872 bias-disable;
903 }; 873 };
904 }; 874 };
905 875
906 tdma_dout0_x14 876 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 877 mux {
908 878 groups = "tdma_dout0_x14";
909 879 function = "tdma";
910 880 bias-disable;
911 }; 881 };
912 }; 882 };
913 883
914 tdma_dout0_x15 884 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 885 mux {
916 886 groups = "tdma_dout0_x15";
917 887 function = "tdma";
918 888 bias-disable;
919 }; 889 };
920 }; 890 };
921 891
922 tdma_dout1_pin 892 tdma_dout1_pins: tdma_dout1 {
923 mux { 893 mux {
924 894 groups = "tdma_dout1";
925 895 function = "tdma";
926 896 bias-disable;
927 }; 897 };
928 }; 898 };
929 899
930 tdma_din1_pins 900 tdma_din1_pins: tdma_din1 {
931 mux { 901 mux {
932 902 groups = "tdma_din1";
933 903 function = "tdma";
934 904 bias-disable;
935 }; 905 };
936 }; 906 };
937 907
938 tdma_fs_pins: 908 tdma_fs_pins: tdma_fs {
939 mux { 909 mux {
940 910 groups = "tdma_fs";
941 911 function = "tdma";
942 912 bias-disable;
943 }; 913 };
944 }; 914 };
945 915
946 tdma_fs_slv_pi 916 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 917 mux {
948 918 groups = "tdma_fs_slv";
949 919 function = "tdma";
950 920 bias-disable;
951 }; 921 };
952 }; 922 };
953 923
954 tdma_sclk_pins 924 tdma_sclk_pins: tdma_sclk {
955 mux { 925 mux {
956 926 groups = "tdma_sclk";
957 927 function = "tdma";
958 928 bias-disable;
959 }; 929 };
960 }; 930 };
961 931
962 tdma_sclk_slv_ 932 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 933 mux {
964 934 groups = "tdma_sclk_slv";
965 935 function = "tdma";
966 936 bias-disable;
967 }; 937 };
968 }; 938 };
969 939
970 tdmb_din0_pins 940 tdmb_din0_pins: tdmb_din0 {
971 mux { 941 mux {
972 942 groups = "tdmb_din0";
973 943 function = "tdmb";
974 944 bias-disable;
975 }; 945 };
976 }; 946 };
977 947
978 tdmb_din1_pins 948 tdmb_din1_pins: tdmb_din1 {
979 mux { 949 mux {
980 950 groups = "tdmb_din1";
981 951 function = "tdmb";
982 952 bias-disable;
983 }; 953 };
984 }; 954 };
985 955
986 tdmb_din2_pins 956 tdmb_din2_pins: tdmb_din2 {
987 mux { 957 mux {
988 958 groups = "tdmb_din2";
989 959 function = "tdmb";
990 960 bias-disable;
991 }; 961 };
992 }; 962 };
993 963
994 tdmb_din3_pins 964 tdmb_din3_pins: tdmb_din3 {
995 mux { 965 mux {
996 966 groups = "tdmb_din3";
997 967 function = "tdmb";
998 968 bias-disable;
999 }; 969 };
1000 }; 970 };
1001 971
1002 tdmb_dout0_pi 972 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 973 mux {
1004 974 groups = "tdmb_dout0";
1005 975 function = "tdmb";
1006 976 bias-disable;
1007 }; 977 };
1008 }; 978 };
1009 979
1010 tdmb_dout1_pi 980 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 981 mux {
1012 982 groups = "tdmb_dout1";
1013 983 function = "tdmb";
1014 984 bias-disable;
1015 }; 985 };
1016 }; 986 };
1017 987
1018 tdmb_dout2_pi 988 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 989 mux {
1020 990 groups = "tdmb_dout2";
1021 991 function = "tdmb";
1022 992 bias-disable;
1023 }; 993 };
1024 }; 994 };
1025 995
1026 tdmb_dout3_pi 996 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 997 mux {
1028 998 groups = "tdmb_dout3";
1029 999 function = "tdmb";
1030 1000 bias-disable;
1031 }; 1001 };
1032 }; 1002 };
1033 1003
1034 tdmb_fs_pins: 1004 tdmb_fs_pins: tdmb_fs {
1035 mux { 1005 mux {
1036 1006 groups = "tdmb_fs";
1037 1007 function = "tdmb";
1038 1008 bias-disable;
1039 }; 1009 };
1040 }; 1010 };
1041 1011
1042 tdmb_fs_slv_p 1012 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 1013 mux {
1044 1014 groups = "tdmb_fs_slv";
1045 1015 function = "tdmb";
1046 1016 bias-disable;
1047 }; 1017 };
1048 }; 1018 };
1049 1019
1050 tdmb_sclk_pin 1020 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 1021 mux {
1052 1022 groups = "tdmb_sclk";
1053 1023 function = "tdmb";
1054 1024 bias-disable;
1055 }; 1025 };
1056 }; 1026 };
1057 1027
1058 tdmb_sclk_slv 1028 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 1029 mux {
1060 1030 groups = "tdmb_sclk_slv";
1061 1031 function = "tdmb";
1062 1032 bias-disable;
1063 }; 1033 };
1064 }; 1034 };
1065 1035
1066 tdmc_fs_pins: 1036 tdmc_fs_pins: tdmc_fs {
1067 mux { 1037 mux {
1068 1038 groups = "tdmc_fs";
1069 1039 function = "tdmc";
1070 1040 bias-disable;
1071 }; 1041 };
1072 }; 1042 };
1073 1043
1074 tdmc_fs_slv_p 1044 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 1045 mux {
1076 1046 groups = "tdmc_fs_slv";
1077 1047 function = "tdmc";
1078 1048 bias-disable;
1079 }; 1049 };
1080 }; 1050 };
1081 1051
1082 tdmc_sclk_pin 1052 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 1053 mux {
1084 1054 groups = "tdmc_sclk";
1085 1055 function = "tdmc";
1086 1056 bias-disable;
1087 }; 1057 };
1088 }; 1058 };
1089 1059
1090 tdmc_sclk_slv 1060 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 1061 mux {
1092 1062 groups = "tdmc_sclk_slv";
1093 1063 function = "tdmc";
1094 1064 bias-disable;
1095 }; 1065 };
1096 }; 1066 };
1097 1067
1098 tdmc_din0_pin 1068 tdmc_din0_pins: tdmc_din0 {
1099 mux { 1069 mux {
1100 1070 groups = "tdmc_din0";
1101 1071 function = "tdmc";
1102 1072 bias-disable;
1103 }; 1073 };
1104 }; 1074 };
1105 1075
1106 tdmc_din1_pin 1076 tdmc_din1_pins: tdmc_din1 {
1107 mux { 1077 mux {
1108 1078 groups = "tdmc_din1";
1109 1079 function = "tdmc";
1110 1080 bias-disable;
1111 }; 1081 };
1112 }; 1082 };
1113 1083
1114 tdmc_din2_pin 1084 tdmc_din2_pins: tdmc_din2 {
1115 mux { 1085 mux {
1116 1086 groups = "tdmc_din2";
1117 1087 function = "tdmc";
1118 1088 bias-disable;
1119 }; 1089 };
1120 }; 1090 };
1121 1091
1122 tdmc_din3_pin 1092 tdmc_din3_pins: tdmc_din3 {
1123 mux { 1093 mux {
1124 1094 groups = "tdmc_din3";
1125 1095 function = "tdmc";
1126 1096 bias-disable;
1127 }; 1097 };
1128 }; 1098 };
1129 1099
1130 tdmc_dout0_pi 1100 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 1101 mux {
1132 1102 groups = "tdmc_dout0";
1133 1103 function = "tdmc";
1134 1104 bias-disable;
1135 }; 1105 };
1136 }; 1106 };
1137 1107
1138 tdmc_dout1_pi 1108 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1109 mux {
1140 1110 groups = "tdmc_dout1";
1141 1111 function = "tdmc";
1142 1112 bias-disable;
1143 }; 1113 };
1144 }; 1114 };
1145 1115
1146 tdmc_dout2_pi 1116 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1117 mux {
1148 1118 groups = "tdmc_dout2";
1149 1119 function = "tdmc";
1150 1120 bias-disable;
1151 }; 1121 };
1152 }; 1122 };
1153 1123
1154 tdmc_dout3_pi 1124 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1125 mux {
1156 1126 groups = "tdmc_dout3";
1157 1127 function = "tdmc";
1158 1128 bias-disable;
1159 }; 1129 };
1160 }; 1130 };
1161 1131
1162 uart_a_pins: 1132 uart_a_pins: uart_a {
1163 mux { 1133 mux {
1164 1134 groups = "uart_tx_a",
1165 1135 "uart_rx_a";
1166 1136 function = "uart_a";
1167 1137 bias-disable;
1168 }; 1138 };
1169 }; 1139 };
1170 1140
1171 uart_a_cts_rt 1141 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1142 mux {
1173 1143 groups = "uart_cts_a",
1174 1144 "uart_rts_a";
1175 1145 function = "uart_a";
1176 1146 bias-disable;
1177 }; 1147 };
1178 }; 1148 };
1179 1149
1180 uart_b_x_pins 1150 uart_b_x_pins: uart_b_x {
1181 mux { 1151 mux {
1182 1152 groups = "uart_tx_b_x",
1183 1153 "uart_rx_b_x";
1184 1154 function = "uart_b";
1185 1155 bias-disable;
1186 }; 1156 };
1187 }; 1157 };
1188 1158
1189 uart_b_x_cts_ 1159 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1160 mux {
1191 1161 groups = "uart_cts_b_x",
1192 1162 "uart_rts_b_x";
1193 1163 function = "uart_b";
1194 1164 bias-disable;
1195 }; 1165 };
1196 }; 1166 };
1197 1167
1198 uart_b_z_pins 1168 uart_b_z_pins: uart_b_z {
1199 mux { 1169 mux {
1200 1170 groups = "uart_tx_b_z",
1201 1171 "uart_rx_b_z";
1202 1172 function = "uart_b";
1203 1173 bias-disable;
1204 }; 1174 };
1205 }; 1175 };
1206 1176
1207 uart_b_z_cts_ 1177 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1178 mux {
1209 1179 groups = "uart_cts_b_z",
1210 1180 "uart_rts_b_z";
1211 1181 function = "uart_b";
1212 1182 bias-disable;
1213 }; 1183 };
1214 }; 1184 };
1215 1185
1216 uart_ao_b_z_p 1186 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1187 mux {
1218 1188 groups = "uart_ao_tx_b_z",
1219 1189 "uart_ao_rx_b_z";
1220 1190 function = "uart_ao_b_z";
1221 1191 bias-disable;
1222 }; 1192 };
1223 }; 1193 };
1224 1194
1225 uart_ao_b_z_c 1195 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1196 mux {
1227 1197 groups = "uart_ao_cts_b_z",
1228 1198 "uart_ao_rts_b_z";
1229 1199 function = "uart_ao_b_z";
1230 1200 bias-disable;
1231 }; 1201 };
1232 }; 1202 };
1233 }; 1203 };
1234 }; 1204 };
1235 1205
1236 hiubus: bus@ff63c000 { 1206 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1207 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1208 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1209 #address-cells = <2>;
1240 #size-cells = <2>; 1210 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1211 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1212
1243 sysctrl: system-contr 1213 sysctrl: system-controller@0 {
1244 compatible = 1214 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1215 "simple-mfd", "syscon";
1246 reg = <0 0 0 1216 reg = <0 0 0 0x400>;
1247 1217
1248 clkc: clock-c 1218 clkc: clock-controller {
1249 compa 1219 compatible = "amlogic,axg-clkc";
1250 #cloc 1220 #clock-cells = <1>;
1251 clock 1221 clocks = <&xtal>;
1252 clock 1222 clock-names = "xtal";
1253 }; 1223 };
1254 1224
1255 pwrc: power-c 1225 pwrc: power-controller {
1256 compa 1226 compatible = "amlogic,meson-axg-pwrc";
1257 #powe 1227 #power-domain-cells = <1>;
1258 amlog 1228 amlogic,ao-sysctrl = <&sysctrl_AO>;
1259 reset 1229 resets = <&reset RESET_VIU>,
1260 1230 <&reset RESET_VENC>,
1261 1231 <&reset RESET_VCBUS>,
1262 1232 <&reset RESET_VENCL>,
1263 1233 <&reset RESET_VID_LOCK>;
1264 reset 1234 reset-names = "viu", "venc", "vcbus",
1265 1235 "vencl", "vid_lock";
1266 clock 1236 clocks = <&clkc CLKID_VPU>,
1267 1237 <&clkc CLKID_VAPB>;
1268 clock 1238 clock-names = "vpu", "vapb";
1269 /* 1239 /*
1270 * VP 1240 * VPU clocking is provided by two identical clock paths
1271 * VP 1241 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1272 * fr 1242 * free mux to safely change frequency while running.
1273 * Sa 1243 * Same for VAPB but with a final gate after the glitch free mux.
1274 */ 1244 */
1275 assig 1245 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1276 1246 <&clkc CLKID_VPU_0>,
1277 1247 <&clkc CLKID_VPU>, /* Glitch free mux */
1278 1248 <&clkc CLKID_VAPB_0_SEL>,
1279 1249 <&clkc CLKID_VAPB_0>,
1280 1250 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1281 assig 1251 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1282 1252 <0>, /* Do Nothing */
1283 1253 <&clkc CLKID_VPU_0>,
1284 1254 <&clkc CLKID_FCLK_DIV4>,
1285 1255 <0>, /* Do Nothing */
1286 1256 <&clkc CLKID_VAPB_0>;
1287 assig 1257 assigned-clock-rates = <0>, /* Do Nothing */
1288 1258 <250000000>,
1289 1259 <0>, /* Do Nothing */
1290 1260 <0>, /* Do Nothing */
1291 1261 <250000000>,
1292 1262 <0>; /* Do Nothing */
1293 }; 1263 };
1294 1264
1295 mipi_pcie_ana 1265 mipi_pcie_analog_dphy: phy {
1296 compa 1266 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1297 #phy- 1267 #phy-cells = <0>;
1298 statu 1268 status = "disabled";
1299 }; 1269 };
1300 }; 1270 };
1301 }; 1271 };
1302 1272
1303 mailbox: mailbox@ff63c404 { 1273 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1274 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1275 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1276 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1277 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1278 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1279 #mbox-cells = <1>;
1310 }; 1280 };
1311 1281
1312 mipi_dphy: phy@ff640000 { 1282 mipi_dphy: phy@ff640000 {
1313 compatible = "amlogic 1283 compatible = "amlogic,axg-mipi-dphy";
1314 reg = <0x0 0xff640000 1284 reg = <0x0 0xff640000 0x0 0x100>;
1315 clocks = <&clkc CLKID 1285 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1316 clock-names = "pclk"; 1286 clock-names = "pclk";
1317 resets = <&reset RESE 1287 resets = <&reset RESET_MIPI_PHY>;
1318 reset-names = "phy"; 1288 reset-names = "phy";
1319 phys = <&mipi_pcie_an 1289 phys = <&mipi_pcie_analog_dphy>;
1320 phy-names = "analog"; 1290 phy-names = "analog";
1321 #phy-cells = <0>; 1291 #phy-cells = <0>;
1322 status = "disabled"; 1292 status = "disabled";
1323 }; 1293 };
1324 1294
1325 audio: bus@ff642000 { 1295 audio: bus@ff642000 {
1326 compatible = "simple- 1296 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1297 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1298 #address-cells = <2>;
1329 #size-cells = <2>; 1299 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1300 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1301
1332 clkc_audio: clock-con 1302 clkc_audio: clock-controller@0 {
1333 compatible = 1303 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1304 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1305 #clock-cells = <1>;
1336 1306
1337 clocks = <&cl 1307 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1308 <&clkc CLKID_MPLL0>,
1339 <&cl 1309 <&clkc CLKID_MPLL1>,
1340 <&cl 1310 <&clkc CLKID_MPLL2>,
1341 <&cl 1311 <&clkc CLKID_MPLL3>,
1342 <&cl 1312 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1313 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1314 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1315 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1316 clock-names = "pclk",
1347 1317 "mst_in0",
1348 1318 "mst_in1",
1349 1319 "mst_in2",
1350 1320 "mst_in3",
1351 1321 "mst_in4",
1352 1322 "mst_in5",
1353 1323 "mst_in6",
1354 1324 "mst_in7";
1355 1325
1356 resets = <&re 1326 resets = <&reset RESET_AUDIO>;
1357 }; 1327 };
1358 1328
1359 toddr_a: audio-contro 1329 toddr_a: audio-controller@100 {
1360 compatible = 1330 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1331 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1332 #sound-dai-cells = <0>;
1363 sound-name-pr 1333 sound-name-prefix = "TODDR_A";
1364 interrupts = 1334 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1335 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1336 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1337 amlogic,fifo-depth = <512>;
1368 status = "dis 1338 status = "disabled";
1369 }; 1339 };
1370 1340
1371 toddr_b: audio-contro 1341 toddr_b: audio-controller@140 {
1372 compatible = 1342 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1343 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1344 #sound-dai-cells = <0>;
1375 sound-name-pr 1345 sound-name-prefix = "TODDR_B";
1376 interrupts = 1346 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1347 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1348 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1349 amlogic,fifo-depth = <256>;
1380 status = "dis 1350 status = "disabled";
1381 }; 1351 };
1382 1352
1383 toddr_c: audio-contro 1353 toddr_c: audio-controller@180 {
1384 compatible = 1354 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1355 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1356 #sound-dai-cells = <0>;
1387 sound-name-pr 1357 sound-name-prefix = "TODDR_C";
1388 interrupts = 1358 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1359 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1360 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1361 amlogic,fifo-depth = <256>;
1392 status = "dis 1362 status = "disabled";
1393 }; 1363 };
1394 1364
1395 frddr_a: audio-contro 1365 frddr_a: audio-controller@1c0 {
1396 compatible = 1366 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1367 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1368 #sound-dai-cells = <0>;
1399 sound-name-pr 1369 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1370 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1371 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1372 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1373 amlogic,fifo-depth = <512>;
1404 status = "dis 1374 status = "disabled";
1405 }; 1375 };
1406 1376
1407 frddr_b: audio-contro 1377 frddr_b: audio-controller@200 {
1408 compatible = 1378 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1379 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1380 #sound-dai-cells = <0>;
1411 sound-name-pr 1381 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1382 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1383 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1384 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1385 amlogic,fifo-depth = <256>;
1416 status = "dis 1386 status = "disabled";
1417 }; 1387 };
1418 1388
1419 frddr_c: audio-contro 1389 frddr_c: audio-controller@240 {
1420 compatible = 1390 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1391 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1392 #sound-dai-cells = <0>;
1423 sound-name-pr 1393 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1394 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1395 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1396 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1397 amlogic,fifo-depth = <256>;
1428 status = "dis 1398 status = "disabled";
1429 }; 1399 };
1430 1400
1431 arb: reset-controller 1401 arb: reset-controller@280 {
1432 compatible = 1402 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1403 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1404 #reset-cells = <1>;
1435 clocks = <&cl 1405 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1406 };
1437 1407
1438 tdmin_a: audio-contro 1408 tdmin_a: audio-controller@300 {
1439 compatible = 1409 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1410 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1411 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1412 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1413 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1414 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1415 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1416 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1417 clock-names = "pclk", "sclk", "sclk_sel",
1448 1418 "lrclk", "lrclk_sel";
1449 status = "dis 1419 status = "disabled";
1450 }; 1420 };
1451 1421
1452 tdmin_b: audio-contro 1422 tdmin_b: audio-controller@340 {
1453 compatible = 1423 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1424 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1425 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1426 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1427 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1428 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1429 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1430 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1431 clock-names = "pclk", "sclk", "sclk_sel",
1462 1432 "lrclk", "lrclk_sel";
1463 status = "dis 1433 status = "disabled";
1464 }; 1434 };
1465 1435
1466 tdmin_c: audio-contro 1436 tdmin_c: audio-controller@380 {
1467 compatible = 1437 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1438 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1439 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1440 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1441 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1442 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1443 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1444 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1445 clock-names = "pclk", "sclk", "sclk_sel",
1476 1446 "lrclk", "lrclk_sel";
1477 status = "dis 1447 status = "disabled";
1478 }; 1448 };
1479 1449
1480 tdmin_lb: audio-contr 1450 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1451 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1452 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1453 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1454 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1455 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1456 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1457 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1458 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1459 clock-names = "pclk", "sclk", "sclk_sel",
1490 1460 "lrclk", "lrclk_sel";
1491 status = "dis 1461 status = "disabled";
1492 }; 1462 };
1493 1463
1494 spdifin: audio-contro 1464 spdifin: audio-controller@400 {
1495 compatible = 1465 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1466 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1467 #sound-dai-cells = <0>;
1498 sound-name-pr 1468 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1469 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1470 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1471 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1472 clock-names = "pclk", "refclk";
1503 status = "dis 1473 status = "disabled";
1504 }; 1474 };
1505 1475
1506 spdifout: audio-contr 1476 spdifout: audio-controller@480 {
1507 compatible = 1477 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1478 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1479 #sound-dai-cells = <0>;
1510 sound-name-pr 1480 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1481 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1482 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1483 clock-names = "pclk", "mclk";
1514 status = "dis 1484 status = "disabled";
1515 }; 1485 };
1516 1486
1517 tdmout_a: audio-contr 1487 tdmout_a: audio-controller@500 {
1518 compatible = 1488 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1489 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1490 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1491 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1492 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1493 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1494 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1495 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1496 clock-names = "pclk", "sclk", "sclk_sel",
1527 1497 "lrclk", "lrclk_sel";
1528 status = "dis 1498 status = "disabled";
1529 }; 1499 };
1530 1500
1531 tdmout_b: audio-contr 1501 tdmout_b: audio-controller@540 {
1532 compatible = 1502 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1503 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1504 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1505 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1506 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1507 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1508 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1509 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1510 clock-names = "pclk", "sclk", "sclk_sel",
1541 1511 "lrclk", "lrclk_sel";
1542 status = "dis 1512 status = "disabled";
1543 }; 1513 };
1544 1514
1545 tdmout_c: audio-contr 1515 tdmout_c: audio-controller@580 {
1546 compatible = 1516 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1517 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1518 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1519 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1520 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1521 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1522 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1523 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1524 clock-names = "pclk", "sclk", "sclk_sel",
1555 1525 "lrclk", "lrclk_sel";
1556 status = "dis 1526 status = "disabled";
1557 }; 1527 };
1558 }; 1528 };
1559 1529
1560 aobus: bus@ff800000 { 1530 aobus: bus@ff800000 {
1561 compatible = "simple- 1531 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1532 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1533 #address-cells = <2>;
1564 #size-cells = <2>; 1534 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1535 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1536
1567 sysctrl_AO: sys-ctrl@ 1537 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1538 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x 1539 reg = <0x0 0x0 0x0 0x100>;
1570 1540
1571 clkc_AO: cloc 1541 clkc_AO: clock-controller {
1572 compa 1542 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1543 #clock-cells = <1>;
1574 #rese 1544 #reset-cells = <1>;
1575 clock 1545 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1546 clock-names = "xtal", "mpeg-clk";
1577 }; 1547 };
1578 }; 1548 };
1579 1549
1580 pinctrl_aobus: pinctr 1550 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1551 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1552 #address-cells = <2>;
1583 #size-cells = 1553 #size-cells = <2>;
1584 ranges; 1554 ranges;
1585 1555
1586 gpio_ao: bank 1556 gpio_ao: bank@14 {
1587 reg = 1557 reg = <0x0 0x00014 0x0 0x8>,
1588 1558 <0x0 0x0002c 0x0 0x4>,
1589 1559 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1560 reg-names = "mux", "pull", "gpio";
1591 gpio- 1561 gpio-controller;
1592 #gpio 1562 #gpio-cells = <2>;
1593 gpio- 1563 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1564 };
1595 1565
1596 i2c_ao_sck_4_ 1566 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1567 mux {
1598 1568 groups = "i2c_ao_sck_4";
1599 1569 function = "i2c_ao";
1600 1570 bias-disable;
1601 }; 1571 };
1602 }; 1572 };
1603 1573
1604 i2c_ao_sck_8_ 1574 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1575 mux {
1606 1576 groups = "i2c_ao_sck_8";
1607 1577 function = "i2c_ao";
1608 1578 bias-disable;
1609 }; 1579 };
1610 }; 1580 };
1611 1581
1612 i2c_ao_sck_10 1582 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1583 mux {
1614 1584 groups = "i2c_ao_sck_10";
1615 1585 function = "i2c_ao";
1616 1586 bias-disable;
1617 }; 1587 };
1618 }; 1588 };
1619 1589
1620 i2c_ao_sda_5_ 1590 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1591 mux {
1622 1592 groups = "i2c_ao_sda_5";
1623 1593 function = "i2c_ao";
1624 1594 bias-disable;
1625 }; 1595 };
1626 }; 1596 };
1627 1597
1628 i2c_ao_sda_9_ 1598 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1599 mux {
1630 1600 groups = "i2c_ao_sda_9";
1631 1601 function = "i2c_ao";
1632 1602 bias-disable;
1633 }; 1603 };
1634 }; 1604 };
1635 1605
1636 i2c_ao_sda_11 1606 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1607 mux {
1638 1608 groups = "i2c_ao_sda_11";
1639 1609 function = "i2c_ao";
1640 1610 bias-disable;
1641 }; 1611 };
1642 }; 1612 };
1643 1613
1644 remote_input_ 1614 remote_input_ao_pins: remote_input_ao {
1645 mux { 1615 mux {
1646 1616 groups = "remote_input_ao";
1647 1617 function = "remote_input_ao";
1648 1618 bias-disable;
1649 }; 1619 };
1650 }; 1620 };
1651 1621
1652 uart_ao_a_pin 1622 uart_ao_a_pins: uart_ao_a {
1653 mux { 1623 mux {
1654 1624 groups = "uart_ao_tx_a",
1655 1625 "uart_ao_rx_a";
1656 1626 function = "uart_ao_a";
1657 1627 bias-disable;
1658 }; 1628 };
1659 }; 1629 };
1660 1630
1661 uart_ao_a_cts 1631 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1632 mux {
1663 1633 groups = "uart_ao_cts_a",
1664 1634 "uart_ao_rts_a";
1665 1635 function = "uart_ao_a";
1666 1636 bias-disable;
1667 }; 1637 };
1668 }; 1638 };
1669 1639
1670 uart_ao_b_pin 1640 uart_ao_b_pins: uart_ao_b {
1671 mux { 1641 mux {
1672 1642 groups = "uart_ao_tx_b",
1673 1643 "uart_ao_rx_b";
1674 1644 function = "uart_ao_b";
1675 1645 bias-disable;
1676 }; 1646 };
1677 }; 1647 };
1678 1648
1679 uart_ao_b_cts 1649 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1650 mux {
1681 1651 groups = "uart_ao_cts_b",
1682 1652 "uart_ao_rts_b";
1683 1653 function = "uart_ao_b";
1684 1654 bias-disable;
1685 }; 1655 };
1686 }; 1656 };
1687 }; 1657 };
1688 1658
1689 sec_AO: ao-secure@140 1659 sec_AO: ao-secure@140 {
1690 compatible = 1660 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1661 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1662 amlogic,has-chip-id;
1693 }; 1663 };
1694 1664
1695 pwm_AO_cd: pwm@2000 { 1665 pwm_AO_cd: pwm@2000 {
1696 compatible = 1666 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1667 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1668 #pwm-cells = <3>;
1699 status = "dis 1669 status = "disabled";
1700 }; 1670 };
1701 1671
1702 uart_AO: serial@3000 1672 uart_AO: serial@3000 {
1703 compatible = 1673 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1674 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1675 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1676 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1677 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1678 status = "disabled";
1709 }; 1679 };
1710 1680
1711 uart_AO_B: serial@400 1681 uart_AO_B: serial@4000 {
1712 compatible = 1682 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1683 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1684 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1685 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1686 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1687 status = "disabled";
1718 }; 1688 };
1719 1689
1720 i2c_AO: i2c@5000 { 1690 i2c_AO: i2c@5000 {
1721 compatible = 1691 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1692 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1693 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1694 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1695 #address-cells = <1>;
1726 #size-cells = 1696 #size-cells = <0>;
1727 status = "dis 1697 status = "disabled";
1728 }; 1698 };
1729 1699
1730 pwm_AO_ab: pwm@7000 { 1700 pwm_AO_ab: pwm@7000 {
1731 compatible = 1701 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1702 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1703 #pwm-cells = <3>;
1734 status = "dis 1704 status = "disabled";
1735 }; 1705 };
1736 1706
1737 ir: ir@8000 { 1707 ir: ir@8000 {
1738 compatible = 1708 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1709 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1710 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1711 status = "disabled";
1742 }; 1712 };
1743 1713
1744 saradc: adc@9000 { 1714 saradc: adc@9000 {
1745 compatible = 1715 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1716 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1717 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1718 #io-channel-cells = <1>;
1749 interrupts = 1719 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1720 clocks = <&xtal>,
1751 <&cl 1721 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1722 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1723 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1724 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1725 status = "disabled";
1756 }; 1726 };
1757 }; 1727 };
1758 1728
1759 ge2d: ge2d@ff940000 { 1729 ge2d: ge2d@ff940000 {
1760 compatible = "amlogic 1730 compatible = "amlogic,axg-ge2d";
1761 reg = <0x0 0xff940000 1731 reg = <0x0 0xff940000 0x0 0x10000>;
1762 interrupts = <GIC_SPI 1732 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1763 clocks = <&clkc CLKID 1733 clocks = <&clkc CLKID_VAPB>;
1764 resets = <&reset RESE 1734 resets = <&reset RESET_GE2D>;
1765 }; 1735 };
1766 1736
1767 gic: interrupt-controller@ffc 1737 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1738 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1739 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1740 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1741 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1742 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1743 interrupt-controller;
1774 interrupts = <GIC_PPI 1744 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1745 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1746 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1747 #address-cells = <0>;
1778 }; 1748 };
1779 1749
1780 cbus: bus@ffd00000 { 1750 cbus: bus@ffd00000 {
1781 compatible = "simple- 1751 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1752 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1753 #address-cells = <2>;
1784 #size-cells = <2>; 1754 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1755 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1756
1787 reset: reset-controll 1757 reset: reset-controller@1004 {
1788 compatible = 1758 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1759 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1760 #reset-cells = <1>;
1791 }; 1761 };
1792 1762
1793 gpio_intc: interrupt- 1763 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1764 compatible = "amlogic,meson-axg-gpio-intc",
1795 1765 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1766 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1767 interrupt-controller;
1798 #interrupt-ce 1768 #interrupt-cells = <2>;
1799 amlogic,chann 1769 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1770 };
1801 1771
1802 watchdog@f0d0 { 1772 watchdog@f0d0 {
1803 compatible = 1773 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1774 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1775 clocks = <&xtal>;
1806 }; 1776 };
1807 1777
1808 pwm_ab: pwm@1b000 { 1778 pwm_ab: pwm@1b000 {
1809 compatible = 1779 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1780 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1781 #pwm-cells = <3>;
1812 status = "dis 1782 status = "disabled";
1813 }; 1783 };
1814 1784
1815 pwm_cd: pwm@1a000 { 1785 pwm_cd: pwm@1a000 {
1816 compatible = 1786 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1787 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1788 #pwm-cells = <3>;
1819 status = "dis 1789 status = "disabled";
1820 }; 1790 };
1821 1791
1822 spicc0: spi@13000 { 1792 spicc0: spi@13000 {
1823 compatible = 1793 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1794 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1795 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1796 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1797 clock-names = "core";
1828 #address-cell 1798 #address-cells = <1>;
1829 #size-cells = 1799 #size-cells = <0>;
1830 status = "dis 1800 status = "disabled";
1831 }; 1801 };
1832 1802
1833 spicc1: spi@15000 { 1803 spicc1: spi@15000 {
1834 compatible = 1804 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1805 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1806 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1807 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1808 clock-names = "core";
1839 #address-cell 1809 #address-cells = <1>;
1840 #size-cells = 1810 #size-cells = <0>;
1841 status = "dis 1811 status = "disabled";
1842 }; 1812 };
1843 1813
1844 clk_msr: clock-measur 1814 clk_msr: clock-measure@18000 {
1845 compatible = 1815 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1816 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1817 };
1848 1818
1849 i2c3: i2c@1c000 { 1819 i2c3: i2c@1c000 {
1850 compatible = 1820 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1821 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1822 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1823 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1824 #address-cells = <1>;
1855 #size-cells = 1825 #size-cells = <0>;
1856 status = "dis 1826 status = "disabled";
1857 }; 1827 };
1858 1828
1859 i2c2: i2c@1d000 { 1829 i2c2: i2c@1d000 {
1860 compatible = 1830 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1831 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1832 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1833 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1834 #address-cells = <1>;
1865 #size-cells = 1835 #size-cells = <0>;
1866 status = "dis 1836 status = "disabled";
1867 }; 1837 };
1868 1838
1869 i2c1: i2c@1e000 { 1839 i2c1: i2c@1e000 {
1870 compatible = 1840 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1841 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1842 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1843 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1844 #address-cells = <1>;
1875 #size-cells = 1845 #size-cells = <0>;
1876 status = "dis 1846 status = "disabled";
1877 }; 1847 };
1878 1848
1879 i2c0: i2c@1f000 { 1849 i2c0: i2c@1f000 {
1880 compatible = 1850 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1851 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1852 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1853 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1854 #address-cells = <1>;
1885 #size-cells = 1855 #size-cells = <0>;
1886 status = "dis 1856 status = "disabled";
1887 }; 1857 };
1888 1858
1889 uart_B: serial@23000 1859 uart_B: serial@23000 {
1890 compatible = 1860 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1861 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1862 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1863 status = "disabled";
1894 clocks = <&xt 1864 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1865 clock-names = "xtal", "pclk", "baud";
1896 }; 1866 };
1897 1867
1898 uart_A: serial@24000 1868 uart_A: serial@24000 {
1899 compatible = 1869 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1870 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1871 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1872 status = "disabled";
1903 clocks = <&xt 1873 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1874 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < 1875 fifo-size = <128>;
1906 }; 1876 };
1907 }; 1877 };
1908 1878
1909 apb: bus@ffe00000 { 1879 apb: bus@ffe00000 {
1910 compatible = "simple- 1880 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1881 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1882 #address-cells = <2>;
1913 #size-cells = <2>; 1883 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1884 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1885
1916 sd_emmc_b: mmc@5000 { 1886 sd_emmc_b: mmc@5000 {
1917 compatible = 1887 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1888 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1889 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1890 status = "disabled";
1921 clocks = <&cl 1891 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1892 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1893 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1894 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1895 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1896 };
1927 1897
1928 sd_emmc_c: mmc@7000 { 1898 sd_emmc_c: mmc@7000 {
1929 compatible = 1899 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1900 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1901 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1902 status = "disabled";
1933 clocks = <&cl 1903 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1904 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1905 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1906 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1907 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; 1908 };
1954 1909
1955 usb2_phy1: phy@9020 { 1910 usb2_phy1: phy@9020 {
1956 compatible = 1911 compatible = "amlogic,meson-gxl-usb2-phy";
1957 #phy-cells = 1912 #phy-cells = <0>;
1958 reg = <0x0 0x 1913 reg = <0x0 0x9020 0x0 0x20>;
1959 clocks = <&cl 1914 clocks = <&clkc CLKID_USB>;
1960 clock-names = 1915 clock-names = "phy";
1961 resets = <&re 1916 resets = <&reset RESET_USB_OTG>;
1962 reset-names = 1917 reset-names = "phy";
1963 }; 1918 };
1964 }; 1919 };
1965 1920
1966 sram: sram@fffc0000 { 1921 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1922 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1923 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1924 #address-cells = <1>;
1970 #size-cells = <1>; 1925 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1926 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1927
1973 cpu_scp_lpri: scp-sra 1928 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1929 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1930 reg = <0x13000 0x400>;
1976 }; 1931 };
1977 1932
1978 cpu_scp_hpri: scp-sra 1933 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1934 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1935 reg = <0x13400 0x400>;
1981 }; 1936 };
1982 }; 1937 };
1983 }; 1938 };
1984 1939
1985 timer { 1940 timer {
1986 compatible = "arm,armv8-timer 1941 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1942 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1943 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1944 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1945 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1946 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1947 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1948 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1949 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1950 };
1996 1951
1997 xtal: xtal-clk { 1952 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1953 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1954 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1955 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1956 #clock-cells = <0>;
2002 }; 1957 };
2003 }; 1958 };
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