1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> 15 #include <dt-bindings/power/meson-axg-power.h>
16 16
17 / { 17 / {
18 compatible = "amlogic,meson-axg"; 18 compatible = "amlogic,meson-axg";
19 19
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 tdmif_a: audio-controller-0 { 24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 25 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI !! 28 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKI !! 29 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKI !! 30 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "sclk", "lrclk", !! 31 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 tdmif_b: audio-controller-1 { 35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 36 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI !! 39 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKI !! 40 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKI !! 41 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "sclk", "lrclk", !! 42 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 tdmif_c: audio-controller-2 { 46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 47 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI !! 50 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKI !! 51 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKI !! 52 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "sclk", "lrclk", !! 53 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled"; 54 status = "disabled";
55 }; 55 };
56 56
57 arm-pmu { 57 arm-pmu {
58 compatible = "arm,cortex-a53-p 58 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 64 };
65 65
66 cpus { 66 cpus {
67 #address-cells = <0x2>; 67 #address-cells = <0x2>;
68 #size-cells = <0x0>; 68 #size-cells = <0x0>;
69 69
70 cpu0: cpu@0 { 70 cpu0: cpu@0 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 73 reg = <0x0 0x0>;
74 enable-method = "psci" 74 enable-method = "psci";
75 next-level-cache = <&l 75 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 76 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici <<
78 #cooling-cells = <2>; <<
79 }; 77 };
80 78
81 cpu1: cpu@1 { 79 cpu1: cpu@1 {
82 device_type = "cpu"; 80 device_type = "cpu";
83 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 82 reg = <0x0 0x1>;
85 enable-method = "psci" 83 enable-method = "psci";
86 next-level-cache = <&l 84 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 85 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici <<
89 #cooling-cells = <2>; <<
90 }; 86 };
91 87
92 cpu2: cpu@2 { 88 cpu2: cpu@2 {
93 device_type = "cpu"; 89 device_type = "cpu";
94 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 91 reg = <0x0 0x2>;
96 enable-method = "psci" 92 enable-method = "psci";
97 next-level-cache = <&l 93 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 94 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici <<
100 #cooling-cells = <2>; <<
101 }; 95 };
102 96
103 cpu3: cpu@3 { 97 cpu3: cpu@3 {
104 device_type = "cpu"; 98 device_type = "cpu";
105 compatible = "arm,cort 99 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 100 reg = <0x0 0x3>;
107 enable-method = "psci" 101 enable-method = "psci";
108 next-level-cache = <&l 102 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 103 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici <<
111 #cooling-cells = <2>; <<
112 }; 104 };
113 105
114 l2: l2-cache0 { 106 l2: l2-cache0 {
115 compatible = "cache"; 107 compatible = "cache";
116 cache-level = <2>; 108 cache-level = <2>;
117 cache-unified; 109 cache-unified;
118 }; 110 };
119 }; 111 };
120 112
121 sm: secure-monitor { 113 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 114 compatible = "amlogic,meson-gxbb-sm";
123 }; 115 };
124 116
125 efuse: efuse { 117 efuse: efuse {
126 compatible = "amlogic,meson-gx 118 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 119 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 120 #address-cells = <1>;
129 #size-cells = <1>; 121 #size-cells = <1>;
130 read-only; 122 read-only;
131 secure-monitor = <&sm>; 123 secure-monitor = <&sm>;
132 }; 124 };
133 125
134 psci { 126 psci {
135 compatible = "arm,psci-1.0"; 127 compatible = "arm,psci-1.0";
136 method = "smc"; 128 method = "smc";
137 }; 129 };
138 130
139 reserved-memory { 131 reserved-memory {
140 #address-cells = <2>; 132 #address-cells = <2>;
141 #size-cells = <2>; 133 #size-cells = <2>;
142 ranges; 134 ranges;
143 135
144 /* 16 MiB reserved for Hardwar 136 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 137 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 138 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 139 no-map;
148 }; 140 };
149 141
150 /* Alternate 3 MiB reserved fo 142 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 143 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 144 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 145 no-map;
154 }; 146 };
155 }; 147 };
156 148
157 scpi { 149 scpi {
158 compatible = "arm,scpi-pre-1.0 150 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 151 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 152 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 153
162 scpi_clocks: clocks { 154 scpi_clocks: clocks {
163 compatible = "arm,scpi 155 compatible = "arm,scpi-clocks";
164 156
165 scpi_dvfs: clocks-0 { 157 scpi_dvfs: clocks-0 {
166 compatible = " 158 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 159 #clock-cells = <1>;
168 clock-indices 160 clock-indices = <0>;
169 clock-output-n 161 clock-output-names = "vcpu";
170 }; 162 };
171 }; 163 };
172 164
173 scpi_sensors: sensors { 165 scpi_sensors: sensors {
174 compatible = "amlogic, 166 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 167 #thermal-sensor-cells = <1>;
176 }; 168 };
177 }; 169 };
178 170
179 soc { 171 soc {
180 compatible = "simple-bus"; 172 compatible = "simple-bus";
181 #address-cells = <2>; 173 #address-cells = <2>;
182 #size-cells = <2>; 174 #size-cells = <2>;
183 ranges; 175 ranges;
184 176
185 pcieA: pcie@f9800000 { 177 pcieA: pcie@f9800000 {
186 compatible = "amlogic, 178 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
187 reg = <0x0 0xf9800000 179 reg = <0x0 0xf9800000 0x0 0x400000>,
188 <0x0 0xff646000 180 <0x0 0xff646000 0x0 0x2000>,
189 <0x0 0xf9f00000 181 <0x0 0xf9f00000 0x0 0x100000>;
190 reg-names = "elbi", "c 182 reg-names = "elbi", "cfg", "config";
191 interrupts = <GIC_SPI 183 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
192 #interrupt-cells = <1> 184 #interrupt-cells = <1>;
193 interrupt-map-mask = < 185 interrupt-map-mask = <0 0 0 0>;
194 interrupt-map = <0 0 0 186 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
195 bus-range = <0x0 0xff> 187 bus-range = <0x0 0xff>;
196 #address-cells = <3>; 188 #address-cells = <3>;
197 #size-cells = <2>; 189 #size-cells = <2>;
198 device_type = "pci"; 190 device_type = "pci";
199 ranges = <0x82000000 0 191 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
200 192
201 clocks = <&clkc CLKID_ 193 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
202 clock-names = "general 194 clock-names = "general", "pclk", "port";
203 resets = <&reset RESET 195 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
204 reset-names = "port", 196 reset-names = "port", "apb";
205 num-lanes = <1>; 197 num-lanes = <1>;
206 phys = <&pcie_phy>; 198 phys = <&pcie_phy>;
207 phy-names = "pcie"; 199 phy-names = "pcie";
208 status = "disabled"; 200 status = "disabled";
209 }; 201 };
210 202
211 pcieB: pcie@fa000000 { 203 pcieB: pcie@fa000000 {
212 compatible = "amlogic, 204 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
213 reg = <0x0 0xfa000000 205 reg = <0x0 0xfa000000 0x0 0x400000>,
214 <0x0 0xff648000 206 <0x0 0xff648000 0x0 0x2000>,
215 <0x0 0xfa400000 207 <0x0 0xfa400000 0x0 0x100000>;
216 reg-names = "elbi", "c 208 reg-names = "elbi", "cfg", "config";
217 interrupts = <GIC_SPI 209 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
218 #interrupt-cells = <1> 210 #interrupt-cells = <1>;
219 interrupt-map-mask = < 211 interrupt-map-mask = <0 0 0 0>;
220 interrupt-map = <0 0 0 212 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
221 bus-range = <0x0 0xff> 213 bus-range = <0x0 0xff>;
222 #address-cells = <3>; 214 #address-cells = <3>;
223 #size-cells = <2>; 215 #size-cells = <2>;
224 device_type = "pci"; 216 device_type = "pci";
225 ranges = <0x82000000 0 217 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
226 218
227 clocks = <&clkc CLKID_ 219 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
228 clock-names = "general 220 clock-names = "general", "pclk", "port";
229 resets = <&reset RESET 221 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
230 reset-names = "port", 222 reset-names = "port", "apb";
231 num-lanes = <1>; 223 num-lanes = <1>;
232 phys = <&pcie_phy>; 224 phys = <&pcie_phy>;
233 phy-names = "pcie"; 225 phy-names = "pcie";
234 status = "disabled"; 226 status = "disabled";
235 }; 227 };
236 228
237 usb: usb@ffe09080 { 229 usb: usb@ffe09080 {
238 compatible = "amlogic, 230 compatible = "amlogic,meson-axg-usb-ctrl";
239 reg = <0x0 0xffe09080 231 reg = <0x0 0xffe09080 0x0 0x20>;
240 interrupts = <GIC_SPI 232 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; 233 #address-cells = <2>;
242 #size-cells = <2>; 234 #size-cells = <2>;
243 ranges; 235 ranges;
244 236
245 clocks = <&clkc CLKID_ 237 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
246 clock-names = "usb_ctr 238 clock-names = "usb_ctrl", "ddr";
247 resets = <&reset RESET 239 resets = <&reset RESET_USB_OTG>;
248 240
249 dr_mode = "otg"; 241 dr_mode = "otg";
250 242
251 phys = <&usb2_phy1>; 243 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1 244 phy-names = "usb2-phy1";
253 245
254 dwc2: usb@ff400000 { 246 dwc2: usb@ff400000 {
255 compatible = " 247 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
256 reg = <0x0 0xf 248 reg = <0x0 0xff400000 0x0 0x40000>;
257 interrupts = < 249 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk 250 clocks = <&clkc CLKID_USB1>;
259 clock-names = 251 clock-names = "otg";
260 phys = <&usb2_ 252 phys = <&usb2_phy1>;
261 dr_mode = "per 253 dr_mode = "peripheral";
262 g-rx-fifo-size 254 g-rx-fifo-size = <192>;
263 g-np-tx-fifo-s 255 g-np-tx-fifo-size = <128>;
264 g-tx-fifo-size 256 g-tx-fifo-size = <128 128 16 16 16>;
265 }; 257 };
266 258
267 dwc3: usb@ff500000 { 259 dwc3: usb@ff500000 {
268 compatible = " 260 compatible = "snps,dwc3";
269 reg = <0x0 0xf 261 reg = <0x0 0xff500000 0x0 0x100000>;
270 interrupts = < 262 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
271 dr_mode = "hos 263 dr_mode = "host";
272 maximum-speed 264 maximum-speed = "high-speed";
273 snps,dis_u2_su 265 snps,dis_u2_susphy_quirk;
274 }; 266 };
275 }; 267 };
276 268
277 ethmac: ethernet@ff3f0000 { 269 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 270 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 271 "snps,dwmac-3.70a",
280 "snps,dwm 272 "snps,dwmac";
281 reg = <0x0 0xff3f0000 273 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 274 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 275 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 276 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 277 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 278 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 279 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 280 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 281 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 282 "timing-adjustment";
291 rx-fifo-depth = <4096> 283 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 284 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc 285 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
294 status = "disabled"; 286 status = "disabled";
295 }; 287 };
296 288
297 pcie_phy: phy@ff644000 { 289 pcie_phy: phy@ff644000 {
298 compatible = "amlogic, 290 compatible = "amlogic,axg-pcie-phy";
299 reg = <0x0 0xff644000 291 reg = <0x0 0xff644000 0x0 0x1c>;
300 resets = <&reset RESET 292 resets = <&reset RESET_PCIE_PHY>;
301 phys = <&mipi_pcie_ana 293 phys = <&mipi_pcie_analog_dphy>;
302 phy-names = "analog"; 294 phy-names = "analog";
303 #phy-cells = <0>; 295 #phy-cells = <0>;
304 }; 296 };
305 297
306 pdm: audio-controller@ff632000 298 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 299 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 300 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 301 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 302 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 303 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 304 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 305 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 306 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 307 status = "disabled";
316 }; 308 };
317 309
318 periphs: bus@ff634000 { 310 periphs: bus@ff634000 {
319 compatible = "simple-b 311 compatible = "simple-bus";
320 reg = <0x0 0xff634000 312 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 313 #address-cells = <2>;
322 #size-cells = <2>; 314 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 315 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 316
325 hwrng: rng@18 { 317 hwrng: rng@18 {
326 compatible = " 318 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 319 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 320 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 321 clock-names = "core";
330 }; 322 };
331 323
332 pinctrl_periphs: pinct 324 pinctrl_periphs: pinctrl@480 {
333 compatible = " 325 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 326 #address-cells = <2>;
335 #size-cells = 327 #size-cells = <2>;
336 ranges; 328 ranges;
337 329
338 gpio: bank@480 330 gpio: bank@480 {
339 reg = 331 reg = <0x0 0x00480 0x0 0x40>,
340 332 <0x0 0x004e8 0x0 0x14>,
341 333 <0x0 0x00520 0x0 0x14>,
342 334 <0x0 0x00430 0x0 0x3c>;
343 reg-na 335 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 336 gpio-controller;
345 #gpio- 337 #gpio-cells = <2>;
346 gpio-r 338 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 339 };
348 340
349 i2c0_pins: i2c 341 i2c0_pins: i2c0 {
350 mux { 342 mux {
351 343 groups = "i2c0_sck",
352 344 "i2c0_sda";
353 345 function = "i2c0";
354 346 bias-disable;
355 }; 347 };
356 }; 348 };
357 349
358 i2c1_x_pins: i 350 i2c1_x_pins: i2c1_x {
359 mux { 351 mux {
360 352 groups = "i2c1_sck_x",
361 353 "i2c1_sda_x";
362 354 function = "i2c1";
363 355 bias-disable;
364 }; 356 };
365 }; 357 };
366 358
367 i2c1_z_pins: i 359 i2c1_z_pins: i2c1_z {
368 mux { 360 mux {
369 361 groups = "i2c1_sck_z",
370 362 "i2c1_sda_z";
371 363 function = "i2c1";
372 364 bias-disable;
373 }; 365 };
374 }; 366 };
375 367
376 i2c2_a_pins: i 368 i2c2_a_pins: i2c2_a {
377 mux { 369 mux {
378 370 groups = "i2c2_sck_a",
379 371 "i2c2_sda_a";
380 372 function = "i2c2";
381 373 bias-disable;
382 }; 374 };
383 }; 375 };
384 376
385 i2c2_x_pins: i 377 i2c2_x_pins: i2c2_x {
386 mux { 378 mux {
387 379 groups = "i2c2_sck_x",
388 380 "i2c2_sda_x";
389 381 function = "i2c2";
390 382 bias-disable;
391 }; 383 };
392 }; 384 };
393 385
394 i2c3_a6_pins: 386 i2c3_a6_pins: i2c3_a6 {
395 mux { 387 mux {
396 388 groups = "i2c3_sda_a6",
397 389 "i2c3_sck_a7";
398 390 function = "i2c3";
399 391 bias-disable;
400 }; 392 };
401 }; 393 };
402 394
403 i2c3_a12_pins: 395 i2c3_a12_pins: i2c3_a12 {
404 mux { 396 mux {
405 397 groups = "i2c3_sda_a12",
406 398 "i2c3_sck_a13";
407 399 function = "i2c3";
408 400 bias-disable;
409 }; 401 };
410 }; 402 };
411 403
412 i2c3_a19_pins: 404 i2c3_a19_pins: i2c3_a19 {
413 mux { 405 mux {
414 406 groups = "i2c3_sda_a19",
415 407 "i2c3_sck_a20";
416 408 function = "i2c3";
417 409 bias-disable;
418 }; 410 };
419 }; 411 };
420 412
421 emmc_pins: emm 413 emmc_pins: emmc {
422 mux-0 414 mux-0 {
423 415 groups = "emmc_nand_d0",
424 416 "emmc_nand_d1",
425 417 "emmc_nand_d2",
426 418 "emmc_nand_d3",
427 419 "emmc_nand_d4",
428 420 "emmc_nand_d5",
429 421 "emmc_nand_d6",
430 422 "emmc_nand_d7",
431 423 "emmc_cmd";
432 424 function = "emmc";
433 425 bias-pull-up;
434 }; 426 };
435 427
436 mux-1 428 mux-1 {
437 429 groups = "emmc_clk";
438 430 function = "emmc";
439 431 bias-disable;
440 }; 432 };
441 }; 433 };
442 434
443 nand_all_pins: <<
444 mux { <<
445 <<
446 <<
447 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 <<
454 <<
455 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 }; <<
463 <<
464 emmc_ds_pins: 435 emmc_ds_pins: emmc_ds {
465 mux { 436 mux {
466 437 groups = "emmc_ds";
467 438 function = "emmc";
468 439 bias-pull-down;
469 }; 440 };
470 }; 441 };
471 442
472 emmc_clk_gate_ 443 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 444 mux {
474 445 groups = "BOOT_8";
475 446 function = "gpio_periphs";
476 447 bias-pull-down;
477 }; 448 };
478 }; 449 };
479 450
480 eth_rgmii_x_pi 451 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 452 mux {
482 453 groups = "eth_mdio_x",
483 454 "eth_mdc_x",
484 455 "eth_rgmii_rx_clk_x",
485 456 "eth_rx_dv_x",
486 457 "eth_rxd0_x",
487 458 "eth_rxd1_x",
488 459 "eth_rxd2_rgmii",
489 460 "eth_rxd3_rgmii",
490 461 "eth_rgmii_tx_clk",
491 462 "eth_txen_x",
492 463 "eth_txd0_x",
493 464 "eth_txd1_x",
494 465 "eth_txd2_rgmii",
495 466 "eth_txd3_rgmii";
496 467 function = "eth";
497 468 bias-disable;
498 }; 469 };
499 }; 470 };
500 471
501 eth_rgmii_y_pi 472 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 473 mux {
503 474 groups = "eth_mdio_y",
504 475 "eth_mdc_y",
505 476 "eth_rgmii_rx_clk_y",
506 477 "eth_rx_dv_y",
507 478 "eth_rxd0_y",
508 479 "eth_rxd1_y",
509 480 "eth_rxd2_rgmii",
510 481 "eth_rxd3_rgmii",
511 482 "eth_rgmii_tx_clk",
512 483 "eth_txen_y",
513 484 "eth_txd0_y",
514 485 "eth_txd1_y",
515 486 "eth_txd2_rgmii",
516 487 "eth_txd3_rgmii";
517 488 function = "eth";
518 489 bias-disable;
519 }; 490 };
520 }; 491 };
521 492
522 eth_rmii_x_pin 493 eth_rmii_x_pins: eth-x-rmii {
523 mux { 494 mux {
524 495 groups = "eth_mdio_x",
525 496 "eth_mdc_x",
526 497 "eth_rgmii_rx_clk_x",
527 498 "eth_rx_dv_x",
528 499 "eth_rxd0_x",
529 500 "eth_rxd1_x",
530 501 "eth_txen_x",
531 502 "eth_txd0_x",
532 503 "eth_txd1_x";
533 504 function = "eth";
534 505 bias-disable;
535 }; 506 };
536 }; 507 };
537 508
538 eth_rmii_y_pin 509 eth_rmii_y_pins: eth-y-rmii {
539 mux { 510 mux {
540 511 groups = "eth_mdio_y",
541 512 "eth_mdc_y",
542 513 "eth_rgmii_rx_clk_y",
543 514 "eth_rx_dv_y",
544 515 "eth_rxd0_y",
545 516 "eth_rxd1_y",
546 517 "eth_txen_y",
547 518 "eth_txd0_y",
548 519 "eth_txd1_y";
549 520 function = "eth";
550 521 bias-disable;
551 }; 522 };
552 }; 523 };
553 524
554 mclk_b_pins: m 525 mclk_b_pins: mclk_b {
555 mux { 526 mux {
556 527 groups = "mclk_b";
557 528 function = "mclk_b";
558 529 bias-disable;
559 }; 530 };
560 }; 531 };
561 532
562 mclk_c_pins: m 533 mclk_c_pins: mclk_c {
563 mux { 534 mux {
564 535 groups = "mclk_c";
565 536 function = "mclk_c";
566 537 bias-disable;
567 }; 538 };
568 }; 539 };
569 540
570 pdm_dclk_a14_p 541 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 542 mux {
572 543 groups = "pdm_dclk_a14";
573 544 function = "pdm";
574 545 bias-disable;
575 }; 546 };
576 }; 547 };
577 548
578 pdm_dclk_a19_p 549 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 550 mux {
580 551 groups = "pdm_dclk_a19";
581 552 function = "pdm";
582 553 bias-disable;
583 }; 554 };
584 }; 555 };
585 556
586 pdm_din0_pins: 557 pdm_din0_pins: pdm_din0 {
587 mux { 558 mux {
588 559 groups = "pdm_din0";
589 560 function = "pdm";
590 561 bias-disable;
591 }; 562 };
592 }; 563 };
593 564
594 pdm_din1_pins: 565 pdm_din1_pins: pdm_din1 {
595 mux { 566 mux {
596 567 groups = "pdm_din1";
597 568 function = "pdm";
598 569 bias-disable;
599 }; 570 };
600 }; 571 };
601 572
602 pdm_din2_pins: 573 pdm_din2_pins: pdm_din2 {
603 mux { 574 mux {
604 575 groups = "pdm_din2";
605 576 function = "pdm";
606 577 bias-disable;
607 }; 578 };
608 }; 579 };
609 580
610 pdm_din3_pins: 581 pdm_din3_pins: pdm_din3 {
611 mux { 582 mux {
612 583 groups = "pdm_din3";
613 584 function = "pdm";
614 585 bias-disable;
615 }; 586 };
616 }; 587 };
617 588
618 pwm_a_a_pins: 589 pwm_a_a_pins: pwm_a_a {
619 mux { 590 mux {
620 591 groups = "pwm_a_a";
621 592 function = "pwm_a";
622 593 bias-disable;
623 }; 594 };
624 }; 595 };
625 596
626 pwm_a_x18_pins 597 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 598 mux {
628 599 groups = "pwm_a_x18";
629 600 function = "pwm_a";
630 601 bias-disable;
631 }; 602 };
632 }; 603 };
633 604
634 pwm_a_x20_pins 605 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 606 mux {
636 607 groups = "pwm_a_x20";
637 608 function = "pwm_a";
638 609 bias-disable;
639 }; 610 };
640 }; 611 };
641 612
642 pwm_a_z_pins: 613 pwm_a_z_pins: pwm_a_z {
643 mux { 614 mux {
644 615 groups = "pwm_a_z";
645 616 function = "pwm_a";
646 617 bias-disable;
647 }; 618 };
648 }; 619 };
649 620
650 pwm_b_a_pins: 621 pwm_b_a_pins: pwm_b_a {
651 mux { 622 mux {
652 623 groups = "pwm_b_a";
653 624 function = "pwm_b";
654 625 bias-disable;
655 }; 626 };
656 }; 627 };
657 628
658 pwm_b_x_pins: 629 pwm_b_x_pins: pwm_b_x {
659 mux { 630 mux {
660 631 groups = "pwm_b_x";
661 632 function = "pwm_b";
662 633 bias-disable;
663 }; 634 };
664 }; 635 };
665 636
666 pwm_b_z_pins: 637 pwm_b_z_pins: pwm_b_z {
667 mux { 638 mux {
668 639 groups = "pwm_b_z";
669 640 function = "pwm_b";
670 641 bias-disable;
671 }; 642 };
672 }; 643 };
673 644
674 pwm_c_a_pins: 645 pwm_c_a_pins: pwm_c_a {
675 mux { 646 mux {
676 647 groups = "pwm_c_a";
677 648 function = "pwm_c";
678 649 bias-disable;
679 }; 650 };
680 }; 651 };
681 652
682 pwm_c_x10_pins 653 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 654 mux {
684 655 groups = "pwm_c_x10";
685 656 function = "pwm_c";
686 657 bias-disable;
687 }; 658 };
688 }; 659 };
689 660
690 pwm_c_x17_pins 661 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 662 mux {
692 663 groups = "pwm_c_x17";
693 664 function = "pwm_c";
694 665 bias-disable;
695 }; 666 };
696 }; 667 };
697 668
698 pwm_d_x11_pins 669 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 670 mux {
700 671 groups = "pwm_d_x11";
701 672 function = "pwm_d";
702 673 bias-disable;
703 }; 674 };
704 }; 675 };
705 676
706 pwm_d_x16_pins 677 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 678 mux {
708 679 groups = "pwm_d_x16";
709 680 function = "pwm_d";
710 681 bias-disable;
711 }; 682 };
712 }; 683 };
713 684
714 sdio_pins: sdi 685 sdio_pins: sdio {
715 mux-0 686 mux-0 {
716 687 groups = "sdio_d0",
717 688 "sdio_d1",
718 689 "sdio_d2",
719 690 "sdio_d3",
720 691 "sdio_cmd";
721 692 function = "sdio";
722 693 bias-pull-up;
723 }; 694 };
724 695
725 mux-1 696 mux-1 {
726 697 groups = "sdio_clk";
727 698 function = "sdio";
728 699 bias-disable;
729 }; 700 };
730 }; 701 };
731 702
732 sdio_clk_gate_ 703 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 704 mux {
734 705 groups = "GPIOX_4";
735 706 function = "gpio_periphs";
736 707 bias-pull-down;
737 }; 708 };
738 }; 709 };
739 710
740 spdif_in_z_pin 711 spdif_in_z_pins: spdif_in_z {
741 mux { 712 mux {
742 713 groups = "spdif_in_z";
743 714 function = "spdif_in";
744 715 bias-disable;
745 }; 716 };
746 }; 717 };
747 718
748 spdif_in_a1_pi 719 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 720 mux {
750 721 groups = "spdif_in_a1";
751 722 function = "spdif_in";
752 723 bias-disable;
753 }; 724 };
754 }; 725 };
755 726
756 spdif_in_a7_pi 727 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 728 mux {
758 729 groups = "spdif_in_a7";
759 730 function = "spdif_in";
760 731 bias-disable;
761 }; 732 };
762 }; 733 };
763 734
764 spdif_in_a19_p 735 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 736 mux {
766 737 groups = "spdif_in_a19";
767 738 function = "spdif_in";
768 739 bias-disable;
769 }; 740 };
770 }; 741 };
771 742
772 spdif_in_a20_p 743 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 744 mux {
774 745 groups = "spdif_in_a20";
775 746 function = "spdif_in";
776 747 bias-disable;
777 }; 748 };
778 }; 749 };
779 750
780 spdif_out_a1_p 751 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 752 mux {
782 753 groups = "spdif_out_a1";
783 754 function = "spdif_out";
784 755 bias-disable;
785 }; 756 };
786 }; 757 };
787 758
788 spdif_out_a11_ 759 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 760 mux {
790 761 groups = "spdif_out_a11";
791 762 function = "spdif_out";
792 763 bias-disable;
793 }; 764 };
794 }; 765 };
795 766
796 spdif_out_a19_ 767 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 768 mux {
798 769 groups = "spdif_out_a19";
799 770 function = "spdif_out";
800 771 bias-disable;
801 }; 772 };
802 }; 773 };
803 774
804 spdif_out_a20_ 775 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 776 mux {
806 777 groups = "spdif_out_a20";
807 778 function = "spdif_out";
808 779 bias-disable;
809 }; 780 };
810 }; 781 };
811 782
812 spdif_out_z_pi 783 spdif_out_z_pins: spdif_out_z {
813 mux { 784 mux {
814 785 groups = "spdif_out_z";
815 786 function = "spdif_out";
816 787 bias-disable;
817 }; 788 };
818 }; 789 };
819 790
820 spi0_pins: spi 791 spi0_pins: spi0 {
821 mux { 792 mux {
822 793 groups = "spi0_miso",
823 794 "spi0_mosi",
824 795 "spi0_clk";
825 796 function = "spi0";
826 797 bias-disable;
827 }; 798 };
828 }; 799 };
829 800
830 spi0_ss0_pins: 801 spi0_ss0_pins: spi0_ss0 {
831 mux { 802 mux {
832 803 groups = "spi0_ss0";
833 804 function = "spi0";
834 805 bias-disable;
835 }; 806 };
836 }; 807 };
837 808
838 spi0_ss1_pins: 809 spi0_ss1_pins: spi0_ss1 {
839 mux { 810 mux {
840 811 groups = "spi0_ss1";
841 812 function = "spi0";
842 813 bias-disable;
843 }; 814 };
844 }; 815 };
845 816
846 spi0_ss2_pins: 817 spi0_ss2_pins: spi0_ss2 {
847 mux { 818 mux {
848 819 groups = "spi0_ss2";
849 820 function = "spi0";
850 821 bias-disable;
851 }; 822 };
852 }; 823 };
853 824
854 spi1_a_pins: s 825 spi1_a_pins: spi1_a {
855 mux { 826 mux {
856 827 groups = "spi1_miso_a",
857 828 "spi1_mosi_a",
858 829 "spi1_clk_a";
859 830 function = "spi1";
860 831 bias-disable;
861 }; 832 };
862 }; 833 };
863 834
864 spi1_ss0_a_pin 835 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 836 mux {
866 837 groups = "spi1_ss0_a";
867 838 function = "spi1";
868 839 bias-disable;
869 }; 840 };
870 }; 841 };
871 842
872 spi1_ss1_pins: 843 spi1_ss1_pins: spi1_ss1 {
873 mux { 844 mux {
874 845 groups = "spi1_ss1";
875 846 function = "spi1";
876 847 bias-disable;
877 }; 848 };
878 }; 849 };
879 850
880 spi1_x_pins: s 851 spi1_x_pins: spi1_x {
881 mux { 852 mux {
882 853 groups = "spi1_miso_x",
883 854 "spi1_mosi_x",
884 855 "spi1_clk_x";
885 856 function = "spi1";
886 857 bias-disable;
887 }; 858 };
888 }; 859 };
889 860
890 spi1_ss0_x_pin 861 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 862 mux {
892 863 groups = "spi1_ss0_x";
893 864 function = "spi1";
894 865 bias-disable;
895 }; 866 };
896 }; 867 };
897 868
898 tdma_din0_pins 869 tdma_din0_pins: tdma_din0 {
899 mux { 870 mux {
900 871 groups = "tdma_din0";
901 872 function = "tdma";
902 873 bias-disable;
903 }; 874 };
904 }; 875 };
905 876
906 tdma_dout0_x14 877 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 878 mux {
908 879 groups = "tdma_dout0_x14";
909 880 function = "tdma";
910 881 bias-disable;
911 }; 882 };
912 }; 883 };
913 884
914 tdma_dout0_x15 885 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 886 mux {
916 887 groups = "tdma_dout0_x15";
917 888 function = "tdma";
918 889 bias-disable;
919 }; 890 };
920 }; 891 };
921 892
922 tdma_dout1_pin 893 tdma_dout1_pins: tdma_dout1 {
923 mux { 894 mux {
924 895 groups = "tdma_dout1";
925 896 function = "tdma";
926 897 bias-disable;
927 }; 898 };
928 }; 899 };
929 900
930 tdma_din1_pins 901 tdma_din1_pins: tdma_din1 {
931 mux { 902 mux {
932 903 groups = "tdma_din1";
933 904 function = "tdma";
934 905 bias-disable;
935 }; 906 };
936 }; 907 };
937 908
938 tdma_fs_pins: 909 tdma_fs_pins: tdma_fs {
939 mux { 910 mux {
940 911 groups = "tdma_fs";
941 912 function = "tdma";
942 913 bias-disable;
943 }; 914 };
944 }; 915 };
945 916
946 tdma_fs_slv_pi 917 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 918 mux {
948 919 groups = "tdma_fs_slv";
949 920 function = "tdma";
950 921 bias-disable;
951 }; 922 };
952 }; 923 };
953 924
954 tdma_sclk_pins 925 tdma_sclk_pins: tdma_sclk {
955 mux { 926 mux {
956 927 groups = "tdma_sclk";
957 928 function = "tdma";
958 929 bias-disable;
959 }; 930 };
960 }; 931 };
961 932
962 tdma_sclk_slv_ 933 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 934 mux {
964 935 groups = "tdma_sclk_slv";
965 936 function = "tdma";
966 937 bias-disable;
967 }; 938 };
968 }; 939 };
969 940
970 tdmb_din0_pins 941 tdmb_din0_pins: tdmb_din0 {
971 mux { 942 mux {
972 943 groups = "tdmb_din0";
973 944 function = "tdmb";
974 945 bias-disable;
975 }; 946 };
976 }; 947 };
977 948
978 tdmb_din1_pins 949 tdmb_din1_pins: tdmb_din1 {
979 mux { 950 mux {
980 951 groups = "tdmb_din1";
981 952 function = "tdmb";
982 953 bias-disable;
983 }; 954 };
984 }; 955 };
985 956
986 tdmb_din2_pins 957 tdmb_din2_pins: tdmb_din2 {
987 mux { 958 mux {
988 959 groups = "tdmb_din2";
989 960 function = "tdmb";
990 961 bias-disable;
991 }; 962 };
992 }; 963 };
993 964
994 tdmb_din3_pins 965 tdmb_din3_pins: tdmb_din3 {
995 mux { 966 mux {
996 967 groups = "tdmb_din3";
997 968 function = "tdmb";
998 969 bias-disable;
999 }; 970 };
1000 }; 971 };
1001 972
1002 tdmb_dout0_pi 973 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 974 mux {
1004 975 groups = "tdmb_dout0";
1005 976 function = "tdmb";
1006 977 bias-disable;
1007 }; 978 };
1008 }; 979 };
1009 980
1010 tdmb_dout1_pi 981 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 982 mux {
1012 983 groups = "tdmb_dout1";
1013 984 function = "tdmb";
1014 985 bias-disable;
1015 }; 986 };
1016 }; 987 };
1017 988
1018 tdmb_dout2_pi 989 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 990 mux {
1020 991 groups = "tdmb_dout2";
1021 992 function = "tdmb";
1022 993 bias-disable;
1023 }; 994 };
1024 }; 995 };
1025 996
1026 tdmb_dout3_pi 997 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 998 mux {
1028 999 groups = "tdmb_dout3";
1029 1000 function = "tdmb";
1030 1001 bias-disable;
1031 }; 1002 };
1032 }; 1003 };
1033 1004
1034 tdmb_fs_pins: 1005 tdmb_fs_pins: tdmb_fs {
1035 mux { 1006 mux {
1036 1007 groups = "tdmb_fs";
1037 1008 function = "tdmb";
1038 1009 bias-disable;
1039 }; 1010 };
1040 }; 1011 };
1041 1012
1042 tdmb_fs_slv_p 1013 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 1014 mux {
1044 1015 groups = "tdmb_fs_slv";
1045 1016 function = "tdmb";
1046 1017 bias-disable;
1047 }; 1018 };
1048 }; 1019 };
1049 1020
1050 tdmb_sclk_pin 1021 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 1022 mux {
1052 1023 groups = "tdmb_sclk";
1053 1024 function = "tdmb";
1054 1025 bias-disable;
1055 }; 1026 };
1056 }; 1027 };
1057 1028
1058 tdmb_sclk_slv 1029 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 1030 mux {
1060 1031 groups = "tdmb_sclk_slv";
1061 1032 function = "tdmb";
1062 1033 bias-disable;
1063 }; 1034 };
1064 }; 1035 };
1065 1036
1066 tdmc_fs_pins: 1037 tdmc_fs_pins: tdmc_fs {
1067 mux { 1038 mux {
1068 1039 groups = "tdmc_fs";
1069 1040 function = "tdmc";
1070 1041 bias-disable;
1071 }; 1042 };
1072 }; 1043 };
1073 1044
1074 tdmc_fs_slv_p 1045 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 1046 mux {
1076 1047 groups = "tdmc_fs_slv";
1077 1048 function = "tdmc";
1078 1049 bias-disable;
1079 }; 1050 };
1080 }; 1051 };
1081 1052
1082 tdmc_sclk_pin 1053 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 1054 mux {
1084 1055 groups = "tdmc_sclk";
1085 1056 function = "tdmc";
1086 1057 bias-disable;
1087 }; 1058 };
1088 }; 1059 };
1089 1060
1090 tdmc_sclk_slv 1061 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 1062 mux {
1092 1063 groups = "tdmc_sclk_slv";
1093 1064 function = "tdmc";
1094 1065 bias-disable;
1095 }; 1066 };
1096 }; 1067 };
1097 1068
1098 tdmc_din0_pin 1069 tdmc_din0_pins: tdmc_din0 {
1099 mux { 1070 mux {
1100 1071 groups = "tdmc_din0";
1101 1072 function = "tdmc";
1102 1073 bias-disable;
1103 }; 1074 };
1104 }; 1075 };
1105 1076
1106 tdmc_din1_pin 1077 tdmc_din1_pins: tdmc_din1 {
1107 mux { 1078 mux {
1108 1079 groups = "tdmc_din1";
1109 1080 function = "tdmc";
1110 1081 bias-disable;
1111 }; 1082 };
1112 }; 1083 };
1113 1084
1114 tdmc_din2_pin 1085 tdmc_din2_pins: tdmc_din2 {
1115 mux { 1086 mux {
1116 1087 groups = "tdmc_din2";
1117 1088 function = "tdmc";
1118 1089 bias-disable;
1119 }; 1090 };
1120 }; 1091 };
1121 1092
1122 tdmc_din3_pin 1093 tdmc_din3_pins: tdmc_din3 {
1123 mux { 1094 mux {
1124 1095 groups = "tdmc_din3";
1125 1096 function = "tdmc";
1126 1097 bias-disable;
1127 }; 1098 };
1128 }; 1099 };
1129 1100
1130 tdmc_dout0_pi 1101 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 1102 mux {
1132 1103 groups = "tdmc_dout0";
1133 1104 function = "tdmc";
1134 1105 bias-disable;
1135 }; 1106 };
1136 }; 1107 };
1137 1108
1138 tdmc_dout1_pi 1109 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1110 mux {
1140 1111 groups = "tdmc_dout1";
1141 1112 function = "tdmc";
1142 1113 bias-disable;
1143 }; 1114 };
1144 }; 1115 };
1145 1116
1146 tdmc_dout2_pi 1117 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1118 mux {
1148 1119 groups = "tdmc_dout2";
1149 1120 function = "tdmc";
1150 1121 bias-disable;
1151 }; 1122 };
1152 }; 1123 };
1153 1124
1154 tdmc_dout3_pi 1125 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1126 mux {
1156 1127 groups = "tdmc_dout3";
1157 1128 function = "tdmc";
1158 1129 bias-disable;
1159 }; 1130 };
1160 }; 1131 };
1161 1132
1162 uart_a_pins: 1133 uart_a_pins: uart_a {
1163 mux { 1134 mux {
1164 1135 groups = "uart_tx_a",
1165 1136 "uart_rx_a";
1166 1137 function = "uart_a";
1167 1138 bias-disable;
1168 }; 1139 };
1169 }; 1140 };
1170 1141
1171 uart_a_cts_rt 1142 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1143 mux {
1173 1144 groups = "uart_cts_a",
1174 1145 "uart_rts_a";
1175 1146 function = "uart_a";
1176 1147 bias-disable;
1177 }; 1148 };
1178 }; 1149 };
1179 1150
1180 uart_b_x_pins 1151 uart_b_x_pins: uart_b_x {
1181 mux { 1152 mux {
1182 1153 groups = "uart_tx_b_x",
1183 1154 "uart_rx_b_x";
1184 1155 function = "uart_b";
1185 1156 bias-disable;
1186 }; 1157 };
1187 }; 1158 };
1188 1159
1189 uart_b_x_cts_ 1160 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1161 mux {
1191 1162 groups = "uart_cts_b_x",
1192 1163 "uart_rts_b_x";
1193 1164 function = "uart_b";
1194 1165 bias-disable;
1195 }; 1166 };
1196 }; 1167 };
1197 1168
1198 uart_b_z_pins 1169 uart_b_z_pins: uart_b_z {
1199 mux { 1170 mux {
1200 1171 groups = "uart_tx_b_z",
1201 1172 "uart_rx_b_z";
1202 1173 function = "uart_b";
1203 1174 bias-disable;
1204 }; 1175 };
1205 }; 1176 };
1206 1177
1207 uart_b_z_cts_ 1178 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1179 mux {
1209 1180 groups = "uart_cts_b_z",
1210 1181 "uart_rts_b_z";
1211 1182 function = "uart_b";
1212 1183 bias-disable;
1213 }; 1184 };
1214 }; 1185 };
1215 1186
1216 uart_ao_b_z_p 1187 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1188 mux {
1218 1189 groups = "uart_ao_tx_b_z",
1219 1190 "uart_ao_rx_b_z";
1220 1191 function = "uart_ao_b_z";
1221 1192 bias-disable;
1222 }; 1193 };
1223 }; 1194 };
1224 1195
1225 uart_ao_b_z_c 1196 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1197 mux {
1227 1198 groups = "uart_ao_cts_b_z",
1228 1199 "uart_ao_rts_b_z";
1229 1200 function = "uart_ao_b_z";
1230 1201 bias-disable;
1231 }; 1202 };
1232 }; 1203 };
1233 }; 1204 };
1234 }; 1205 };
1235 1206
1236 hiubus: bus@ff63c000 { 1207 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1208 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1209 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1210 #address-cells = <2>;
1240 #size-cells = <2>; 1211 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1212 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1213
1243 sysctrl: system-contr 1214 sysctrl: system-controller@0 {
1244 compatible = 1215 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1216 "simple-mfd", "syscon";
1246 reg = <0 0 0 1217 reg = <0 0 0 0x400>;
1247 1218
1248 clkc: clock-c 1219 clkc: clock-controller {
1249 compa 1220 compatible = "amlogic,axg-clkc";
1250 #cloc 1221 #clock-cells = <1>;
1251 clock 1222 clocks = <&xtal>;
1252 clock 1223 clock-names = "xtal";
1253 }; 1224 };
1254 1225
1255 pwrc: power-c 1226 pwrc: power-controller {
1256 compa 1227 compatible = "amlogic,meson-axg-pwrc";
1257 #powe 1228 #power-domain-cells = <1>;
1258 amlog 1229 amlogic,ao-sysctrl = <&sysctrl_AO>;
1259 reset 1230 resets = <&reset RESET_VIU>,
1260 1231 <&reset RESET_VENC>,
1261 1232 <&reset RESET_VCBUS>,
1262 1233 <&reset RESET_VENCL>,
1263 1234 <&reset RESET_VID_LOCK>;
1264 reset 1235 reset-names = "viu", "venc", "vcbus",
1265 1236 "vencl", "vid_lock";
1266 clock 1237 clocks = <&clkc CLKID_VPU>,
1267 1238 <&clkc CLKID_VAPB>;
1268 clock 1239 clock-names = "vpu", "vapb";
1269 /* 1240 /*
1270 * VP 1241 * VPU clocking is provided by two identical clock paths
1271 * VP 1242 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1272 * fr 1243 * free mux to safely change frequency while running.
1273 * Sa 1244 * Same for VAPB but with a final gate after the glitch free mux.
1274 */ 1245 */
1275 assig 1246 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1276 1247 <&clkc CLKID_VPU_0>,
1277 1248 <&clkc CLKID_VPU>, /* Glitch free mux */
1278 1249 <&clkc CLKID_VAPB_0_SEL>,
1279 1250 <&clkc CLKID_VAPB_0>,
1280 1251 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1281 assig 1252 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1282 1253 <0>, /* Do Nothing */
1283 1254 <&clkc CLKID_VPU_0>,
1284 1255 <&clkc CLKID_FCLK_DIV4>,
1285 1256 <0>, /* Do Nothing */
1286 1257 <&clkc CLKID_VAPB_0>;
1287 assig 1258 assigned-clock-rates = <0>, /* Do Nothing */
1288 1259 <250000000>,
1289 1260 <0>, /* Do Nothing */
1290 1261 <0>, /* Do Nothing */
1291 1262 <250000000>,
1292 1263 <0>; /* Do Nothing */
1293 }; 1264 };
1294 1265
1295 mipi_pcie_ana 1266 mipi_pcie_analog_dphy: phy {
1296 compa 1267 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1297 #phy- 1268 #phy-cells = <0>;
1298 statu 1269 status = "disabled";
1299 }; 1270 };
1300 }; 1271 };
1301 }; 1272 };
1302 1273
1303 mailbox: mailbox@ff63c404 { 1274 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1275 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1276 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1277 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1278 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1279 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1280 #mbox-cells = <1>;
1310 }; 1281 };
1311 1282
1312 mipi_dphy: phy@ff640000 { 1283 mipi_dphy: phy@ff640000 {
1313 compatible = "amlogic 1284 compatible = "amlogic,axg-mipi-dphy";
1314 reg = <0x0 0xff640000 1285 reg = <0x0 0xff640000 0x0 0x100>;
1315 clocks = <&clkc CLKID 1286 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1316 clock-names = "pclk"; 1287 clock-names = "pclk";
1317 resets = <&reset RESE 1288 resets = <&reset RESET_MIPI_PHY>;
1318 reset-names = "phy"; 1289 reset-names = "phy";
1319 phys = <&mipi_pcie_an 1290 phys = <&mipi_pcie_analog_dphy>;
1320 phy-names = "analog"; 1291 phy-names = "analog";
1321 #phy-cells = <0>; 1292 #phy-cells = <0>;
1322 status = "disabled"; 1293 status = "disabled";
1323 }; 1294 };
1324 1295
1325 audio: bus@ff642000 { 1296 audio: bus@ff642000 {
1326 compatible = "simple- 1297 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1298 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1299 #address-cells = <2>;
1329 #size-cells = <2>; 1300 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1301 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1302
1332 clkc_audio: clock-con 1303 clkc_audio: clock-controller@0 {
1333 compatible = 1304 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1305 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1306 #clock-cells = <1>;
1336 1307
1337 clocks = <&cl 1308 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1309 <&clkc CLKID_MPLL0>,
1339 <&cl 1310 <&clkc CLKID_MPLL1>,
1340 <&cl 1311 <&clkc CLKID_MPLL2>,
1341 <&cl 1312 <&clkc CLKID_MPLL3>,
1342 <&cl 1313 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1314 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1315 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1316 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1317 clock-names = "pclk",
1347 1318 "mst_in0",
1348 1319 "mst_in1",
1349 1320 "mst_in2",
1350 1321 "mst_in3",
1351 1322 "mst_in4",
1352 1323 "mst_in5",
1353 1324 "mst_in6",
1354 1325 "mst_in7";
1355 1326
1356 resets = <&re 1327 resets = <&reset RESET_AUDIO>;
1357 }; 1328 };
1358 1329
1359 toddr_a: audio-contro 1330 toddr_a: audio-controller@100 {
1360 compatible = 1331 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1332 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1333 #sound-dai-cells = <0>;
1363 sound-name-pr 1334 sound-name-prefix = "TODDR_A";
1364 interrupts = 1335 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1336 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1337 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1338 amlogic,fifo-depth = <512>;
1368 status = "dis 1339 status = "disabled";
1369 }; 1340 };
1370 1341
1371 toddr_b: audio-contro 1342 toddr_b: audio-controller@140 {
1372 compatible = 1343 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1344 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1345 #sound-dai-cells = <0>;
1375 sound-name-pr 1346 sound-name-prefix = "TODDR_B";
1376 interrupts = 1347 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1348 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1349 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1350 amlogic,fifo-depth = <256>;
1380 status = "dis 1351 status = "disabled";
1381 }; 1352 };
1382 1353
1383 toddr_c: audio-contro 1354 toddr_c: audio-controller@180 {
1384 compatible = 1355 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1356 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1357 #sound-dai-cells = <0>;
1387 sound-name-pr 1358 sound-name-prefix = "TODDR_C";
1388 interrupts = 1359 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1360 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1361 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1362 amlogic,fifo-depth = <256>;
1392 status = "dis 1363 status = "disabled";
1393 }; 1364 };
1394 1365
1395 frddr_a: audio-contro 1366 frddr_a: audio-controller@1c0 {
1396 compatible = 1367 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1368 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1369 #sound-dai-cells = <0>;
1399 sound-name-pr 1370 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1371 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1372 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1373 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1374 amlogic,fifo-depth = <512>;
1404 status = "dis 1375 status = "disabled";
1405 }; 1376 };
1406 1377
1407 frddr_b: audio-contro 1378 frddr_b: audio-controller@200 {
1408 compatible = 1379 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1380 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1381 #sound-dai-cells = <0>;
1411 sound-name-pr 1382 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1383 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1384 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1385 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1386 amlogic,fifo-depth = <256>;
1416 status = "dis 1387 status = "disabled";
1417 }; 1388 };
1418 1389
1419 frddr_c: audio-contro 1390 frddr_c: audio-controller@240 {
1420 compatible = 1391 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1392 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1393 #sound-dai-cells = <0>;
1423 sound-name-pr 1394 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1395 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1396 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1397 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1398 amlogic,fifo-depth = <256>;
1428 status = "dis 1399 status = "disabled";
1429 }; 1400 };
1430 1401
1431 arb: reset-controller 1402 arb: reset-controller@280 {
1432 compatible = 1403 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1404 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1405 #reset-cells = <1>;
1435 clocks = <&cl 1406 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1407 };
1437 1408
1438 tdmin_a: audio-contro 1409 tdmin_a: audio-controller@300 {
1439 compatible = 1410 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1411 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1412 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1413 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1414 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1415 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1416 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1417 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1418 clock-names = "pclk", "sclk", "sclk_sel",
1448 1419 "lrclk", "lrclk_sel";
1449 status = "dis 1420 status = "disabled";
1450 }; 1421 };
1451 1422
1452 tdmin_b: audio-contro 1423 tdmin_b: audio-controller@340 {
1453 compatible = 1424 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1425 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1426 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1427 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1428 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1429 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1430 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1431 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1432 clock-names = "pclk", "sclk", "sclk_sel",
1462 1433 "lrclk", "lrclk_sel";
1463 status = "dis 1434 status = "disabled";
1464 }; 1435 };
1465 1436
1466 tdmin_c: audio-contro 1437 tdmin_c: audio-controller@380 {
1467 compatible = 1438 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1439 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1440 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1441 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1442 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1443 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1444 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1445 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1446 clock-names = "pclk", "sclk", "sclk_sel",
1476 1447 "lrclk", "lrclk_sel";
1477 status = "dis 1448 status = "disabled";
1478 }; 1449 };
1479 1450
1480 tdmin_lb: audio-contr 1451 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1452 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1453 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1454 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1455 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1456 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1457 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1458 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1459 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1460 clock-names = "pclk", "sclk", "sclk_sel",
1490 1461 "lrclk", "lrclk_sel";
1491 status = "dis 1462 status = "disabled";
1492 }; 1463 };
1493 1464
1494 spdifin: audio-contro 1465 spdifin: audio-controller@400 {
1495 compatible = 1466 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1467 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1468 #sound-dai-cells = <0>;
1498 sound-name-pr 1469 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1470 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1471 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1472 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1473 clock-names = "pclk", "refclk";
1503 status = "dis 1474 status = "disabled";
1504 }; 1475 };
1505 1476
1506 spdifout: audio-contr 1477 spdifout: audio-controller@480 {
1507 compatible = 1478 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1479 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1480 #sound-dai-cells = <0>;
1510 sound-name-pr 1481 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1482 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1483 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1484 clock-names = "pclk", "mclk";
1514 status = "dis 1485 status = "disabled";
1515 }; 1486 };
1516 1487
1517 tdmout_a: audio-contr 1488 tdmout_a: audio-controller@500 {
1518 compatible = 1489 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1490 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1491 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1492 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1493 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1494 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1495 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1496 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1497 clock-names = "pclk", "sclk", "sclk_sel",
1527 1498 "lrclk", "lrclk_sel";
1528 status = "dis 1499 status = "disabled";
1529 }; 1500 };
1530 1501
1531 tdmout_b: audio-contr 1502 tdmout_b: audio-controller@540 {
1532 compatible = 1503 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1504 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1505 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1506 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1507 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1508 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1509 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1510 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1511 clock-names = "pclk", "sclk", "sclk_sel",
1541 1512 "lrclk", "lrclk_sel";
1542 status = "dis 1513 status = "disabled";
1543 }; 1514 };
1544 1515
1545 tdmout_c: audio-contr 1516 tdmout_c: audio-controller@580 {
1546 compatible = 1517 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1518 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1519 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1520 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1521 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1522 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1523 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1524 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1525 clock-names = "pclk", "sclk", "sclk_sel",
1555 1526 "lrclk", "lrclk_sel";
1556 status = "dis 1527 status = "disabled";
1557 }; 1528 };
1558 }; 1529 };
1559 1530
1560 aobus: bus@ff800000 { 1531 aobus: bus@ff800000 {
1561 compatible = "simple- 1532 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1533 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1534 #address-cells = <2>;
1564 #size-cells = <2>; 1535 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1536 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1537
1567 sysctrl_AO: sys-ctrl@ 1538 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1539 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x 1540 reg = <0x0 0x0 0x0 0x100>;
1570 1541
1571 clkc_AO: cloc 1542 clkc_AO: clock-controller {
1572 compa 1543 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1544 #clock-cells = <1>;
1574 #rese 1545 #reset-cells = <1>;
1575 clock 1546 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1547 clock-names = "xtal", "mpeg-clk";
1577 }; 1548 };
1578 }; 1549 };
1579 1550
1580 pinctrl_aobus: pinctr 1551 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1552 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1553 #address-cells = <2>;
1583 #size-cells = 1554 #size-cells = <2>;
1584 ranges; 1555 ranges;
1585 1556
1586 gpio_ao: bank 1557 gpio_ao: bank@14 {
1587 reg = 1558 reg = <0x0 0x00014 0x0 0x8>,
1588 1559 <0x0 0x0002c 0x0 0x4>,
1589 1560 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1561 reg-names = "mux", "pull", "gpio";
1591 gpio- 1562 gpio-controller;
1592 #gpio 1563 #gpio-cells = <2>;
1593 gpio- 1564 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1565 };
1595 1566
1596 i2c_ao_sck_4_ 1567 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1568 mux {
1598 1569 groups = "i2c_ao_sck_4";
1599 1570 function = "i2c_ao";
1600 1571 bias-disable;
1601 }; 1572 };
1602 }; 1573 };
1603 1574
1604 i2c_ao_sck_8_ 1575 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1576 mux {
1606 1577 groups = "i2c_ao_sck_8";
1607 1578 function = "i2c_ao";
1608 1579 bias-disable;
1609 }; 1580 };
1610 }; 1581 };
1611 1582
1612 i2c_ao_sck_10 1583 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1584 mux {
1614 1585 groups = "i2c_ao_sck_10";
1615 1586 function = "i2c_ao";
1616 1587 bias-disable;
1617 }; 1588 };
1618 }; 1589 };
1619 1590
1620 i2c_ao_sda_5_ 1591 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1592 mux {
1622 1593 groups = "i2c_ao_sda_5";
1623 1594 function = "i2c_ao";
1624 1595 bias-disable;
1625 }; 1596 };
1626 }; 1597 };
1627 1598
1628 i2c_ao_sda_9_ 1599 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1600 mux {
1630 1601 groups = "i2c_ao_sda_9";
1631 1602 function = "i2c_ao";
1632 1603 bias-disable;
1633 }; 1604 };
1634 }; 1605 };
1635 1606
1636 i2c_ao_sda_11 1607 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1608 mux {
1638 1609 groups = "i2c_ao_sda_11";
1639 1610 function = "i2c_ao";
1640 1611 bias-disable;
1641 }; 1612 };
1642 }; 1613 };
1643 1614
1644 remote_input_ 1615 remote_input_ao_pins: remote_input_ao {
1645 mux { 1616 mux {
1646 1617 groups = "remote_input_ao";
1647 1618 function = "remote_input_ao";
1648 1619 bias-disable;
1649 }; 1620 };
1650 }; 1621 };
1651 1622
1652 uart_ao_a_pin 1623 uart_ao_a_pins: uart_ao_a {
1653 mux { 1624 mux {
1654 1625 groups = "uart_ao_tx_a",
1655 1626 "uart_ao_rx_a";
1656 1627 function = "uart_ao_a";
1657 1628 bias-disable;
1658 }; 1629 };
1659 }; 1630 };
1660 1631
1661 uart_ao_a_cts 1632 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1633 mux {
1663 1634 groups = "uart_ao_cts_a",
1664 1635 "uart_ao_rts_a";
1665 1636 function = "uart_ao_a";
1666 1637 bias-disable;
1667 }; 1638 };
1668 }; 1639 };
1669 1640
1670 uart_ao_b_pin 1641 uart_ao_b_pins: uart_ao_b {
1671 mux { 1642 mux {
1672 1643 groups = "uart_ao_tx_b",
1673 1644 "uart_ao_rx_b";
1674 1645 function = "uart_ao_b";
1675 1646 bias-disable;
1676 }; 1647 };
1677 }; 1648 };
1678 1649
1679 uart_ao_b_cts 1650 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1651 mux {
1681 1652 groups = "uart_ao_cts_b",
1682 1653 "uart_ao_rts_b";
1683 1654 function = "uart_ao_b";
1684 1655 bias-disable;
1685 }; 1656 };
1686 }; 1657 };
1687 }; 1658 };
1688 1659
1689 sec_AO: ao-secure@140 1660 sec_AO: ao-secure@140 {
1690 compatible = 1661 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1662 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1663 amlogic,has-chip-id;
1693 }; 1664 };
1694 1665
1695 pwm_AO_cd: pwm@2000 { 1666 pwm_AO_cd: pwm@2000 {
1696 compatible = 1667 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1668 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1669 #pwm-cells = <3>;
1699 status = "dis 1670 status = "disabled";
1700 }; 1671 };
1701 1672
1702 uart_AO: serial@3000 1673 uart_AO: serial@3000 {
1703 compatible = 1674 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1675 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1676 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1677 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1678 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1679 status = "disabled";
1709 }; 1680 };
1710 1681
1711 uart_AO_B: serial@400 1682 uart_AO_B: serial@4000 {
1712 compatible = 1683 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1684 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1685 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1686 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1687 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1688 status = "disabled";
1718 }; 1689 };
1719 1690
1720 i2c_AO: i2c@5000 { 1691 i2c_AO: i2c@5000 {
1721 compatible = 1692 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1693 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1694 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1695 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1696 #address-cells = <1>;
1726 #size-cells = 1697 #size-cells = <0>;
1727 status = "dis 1698 status = "disabled";
1728 }; 1699 };
1729 1700
1730 pwm_AO_ab: pwm@7000 { 1701 pwm_AO_ab: pwm@7000 {
1731 compatible = 1702 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1703 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1704 #pwm-cells = <3>;
1734 status = "dis 1705 status = "disabled";
1735 }; 1706 };
1736 1707
1737 ir: ir@8000 { 1708 ir: ir@8000 {
1738 compatible = 1709 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1710 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1711 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1712 status = "disabled";
1742 }; 1713 };
1743 1714
1744 saradc: adc@9000 { 1715 saradc: adc@9000 {
1745 compatible = 1716 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1717 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1718 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1719 #io-channel-cells = <1>;
1749 interrupts = 1720 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1721 clocks = <&xtal>,
1751 <&cl 1722 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1723 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1724 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1725 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1726 status = "disabled";
1756 }; 1727 };
1757 }; 1728 };
1758 1729
1759 ge2d: ge2d@ff940000 { 1730 ge2d: ge2d@ff940000 {
1760 compatible = "amlogic 1731 compatible = "amlogic,axg-ge2d";
1761 reg = <0x0 0xff940000 1732 reg = <0x0 0xff940000 0x0 0x10000>;
1762 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1763 clocks = <&clkc CLKID 1734 clocks = <&clkc CLKID_VAPB>;
1764 resets = <&reset RESE 1735 resets = <&reset RESET_GE2D>;
1765 }; 1736 };
1766 1737
1767 gic: interrupt-controller@ffc 1738 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1739 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1740 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1741 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1742 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1743 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1744 interrupt-controller;
1774 interrupts = <GIC_PPI 1745 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1746 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1747 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1748 #address-cells = <0>;
1778 }; 1749 };
1779 1750
1780 cbus: bus@ffd00000 { 1751 cbus: bus@ffd00000 {
1781 compatible = "simple- 1752 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1753 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1754 #address-cells = <2>;
1784 #size-cells = <2>; 1755 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1756 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1757
1787 reset: reset-controll 1758 reset: reset-controller@1004 {
1788 compatible = 1759 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1760 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1761 #reset-cells = <1>;
1791 }; 1762 };
1792 1763
1793 gpio_intc: interrupt- 1764 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1765 compatible = "amlogic,meson-axg-gpio-intc",
1795 1766 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1767 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1768 interrupt-controller;
1798 #interrupt-ce 1769 #interrupt-cells = <2>;
1799 amlogic,chann 1770 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1771 };
1801 1772
1802 watchdog@f0d0 { 1773 watchdog@f0d0 {
1803 compatible = 1774 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1775 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1776 clocks = <&xtal>;
1806 }; 1777 };
1807 1778
1808 pwm_ab: pwm@1b000 { 1779 pwm_ab: pwm@1b000 {
1809 compatible = 1780 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1781 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1782 #pwm-cells = <3>;
1812 status = "dis 1783 status = "disabled";
1813 }; 1784 };
1814 1785
1815 pwm_cd: pwm@1a000 { 1786 pwm_cd: pwm@1a000 {
1816 compatible = 1787 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1788 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1789 #pwm-cells = <3>;
1819 status = "dis 1790 status = "disabled";
1820 }; 1791 };
1821 1792
1822 spicc0: spi@13000 { 1793 spicc0: spi@13000 {
1823 compatible = 1794 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1795 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1796 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1797 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1798 clock-names = "core";
1828 #address-cell 1799 #address-cells = <1>;
1829 #size-cells = 1800 #size-cells = <0>;
1830 status = "dis 1801 status = "disabled";
1831 }; 1802 };
1832 1803
1833 spicc1: spi@15000 { 1804 spicc1: spi@15000 {
1834 compatible = 1805 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1806 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1807 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1808 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1809 clock-names = "core";
1839 #address-cell 1810 #address-cells = <1>;
1840 #size-cells = 1811 #size-cells = <0>;
1841 status = "dis 1812 status = "disabled";
1842 }; 1813 };
1843 1814
1844 clk_msr: clock-measur 1815 clk_msr: clock-measure@18000 {
1845 compatible = 1816 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1817 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1818 };
1848 1819
1849 i2c3: i2c@1c000 { 1820 i2c3: i2c@1c000 {
1850 compatible = 1821 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1822 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1823 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1824 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1825 #address-cells = <1>;
1855 #size-cells = 1826 #size-cells = <0>;
1856 status = "dis 1827 status = "disabled";
1857 }; 1828 };
1858 1829
1859 i2c2: i2c@1d000 { 1830 i2c2: i2c@1d000 {
1860 compatible = 1831 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1832 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1833 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1834 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1835 #address-cells = <1>;
1865 #size-cells = 1836 #size-cells = <0>;
1866 status = "dis 1837 status = "disabled";
1867 }; 1838 };
1868 1839
1869 i2c1: i2c@1e000 { 1840 i2c1: i2c@1e000 {
1870 compatible = 1841 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1842 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1843 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1844 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1845 #address-cells = <1>;
1875 #size-cells = 1846 #size-cells = <0>;
1876 status = "dis 1847 status = "disabled";
1877 }; 1848 };
1878 1849
1879 i2c0: i2c@1f000 { 1850 i2c0: i2c@1f000 {
1880 compatible = 1851 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1852 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1853 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1854 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1855 #address-cells = <1>;
1885 #size-cells = 1856 #size-cells = <0>;
1886 status = "dis 1857 status = "disabled";
1887 }; 1858 };
1888 1859
1889 uart_B: serial@23000 1860 uart_B: serial@23000 {
1890 compatible = 1861 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1862 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1863 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1864 status = "disabled";
1894 clocks = <&xt 1865 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1866 clock-names = "xtal", "pclk", "baud";
1896 }; 1867 };
1897 1868
1898 uart_A: serial@24000 1869 uart_A: serial@24000 {
1899 compatible = 1870 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1871 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1872 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1873 status = "disabled";
1903 clocks = <&xt 1874 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1875 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < 1876 fifo-size = <128>;
1906 }; 1877 };
1907 }; 1878 };
1908 1879
1909 apb: bus@ffe00000 { 1880 apb: bus@ffe00000 {
1910 compatible = "simple- 1881 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1882 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1883 #address-cells = <2>;
1913 #size-cells = <2>; 1884 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1885 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1886
1916 sd_emmc_b: mmc@5000 { 1887 sd_emmc_b: mmc@5000 {
1917 compatible = 1888 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1889 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1890 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1891 status = "disabled";
1921 clocks = <&cl 1892 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1893 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1894 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1895 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1896 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1897 };
1927 1898
1928 sd_emmc_c: mmc@7000 { 1899 sd_emmc_c: mmc@7000 {
1929 compatible = 1900 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1901 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1902 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1903 status = "disabled";
1933 clocks = <&cl 1904 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1905 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1906 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1907 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1908 resets = <&reset RESET_SD_EMMC_C>;
1938 }; <<
1939 <<
1940 nfc: nand-controller@ <<
1941 compatible = <<
1942 reg = <0x0 0x <<
1943 <0x0 0x <<
1944 reg-names = " <<
1945 pinctrl-0 = < <<
1946 pinctrl-names <<
1947 #address-cell <<
1948 #size-cells = <<
1949 interrupts = <<
1950 clocks = <&cl <<
1951 <&cl <<
1952 clock-names = <<
1953 }; 1909 };
1954 1910
1955 usb2_phy1: phy@9020 { 1911 usb2_phy1: phy@9020 {
1956 compatible = 1912 compatible = "amlogic,meson-gxl-usb2-phy";
1957 #phy-cells = 1913 #phy-cells = <0>;
1958 reg = <0x0 0x 1914 reg = <0x0 0x9020 0x0 0x20>;
1959 clocks = <&cl 1915 clocks = <&clkc CLKID_USB>;
1960 clock-names = 1916 clock-names = "phy";
1961 resets = <&re 1917 resets = <&reset RESET_USB_OTG>;
1962 reset-names = 1918 reset-names = "phy";
1963 }; 1919 };
1964 }; 1920 };
1965 1921
1966 sram: sram@fffc0000 { 1922 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1923 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1924 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1925 #address-cells = <1>;
1970 #size-cells = <1>; 1926 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1927 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1928
1973 cpu_scp_lpri: scp-sra 1929 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1930 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1931 reg = <0x13000 0x400>;
1976 }; 1932 };
1977 1933
1978 cpu_scp_hpri: scp-sra 1934 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1935 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1936 reg = <0x13400 0x400>;
1981 }; 1937 };
1982 }; 1938 };
1983 }; 1939 };
1984 1940
1985 timer { 1941 timer {
1986 compatible = "arm,armv8-timer 1942 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1943 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1944 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1945 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1946 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1947 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1948 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1949 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1950 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1951 };
1996 1952
1997 xtal: xtal-clk { 1953 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1954 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1955 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 1956 clock-output-names = "xtal";
2001 #clock-cells = <0>; 1957 #clock-cells = <0>;
2002 }; 1958 };
2003 }; 1959 };
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