1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2017 Amlogic, Inc. All rights 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/axg-aoclkc.h> 6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h> 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h> 8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h> 10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg- 13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg- 14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 #include <dt-bindings/power/meson-axg-power.h> 15 #include <dt-bindings/power/meson-axg-power.h>
16 16
17 / { 17 / {
18 compatible = "amlogic,meson-axg"; 18 compatible = "amlogic,meson-axg";
19 19
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 tdmif_a: audio-controller-0 { 24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm- 25 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>; 26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A"; 27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKI 28 clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29 <&clkc_audio AUD_CLKI 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>,
30 <&clkc_audio AUD_CLKI 30 <&clkc_audio AUD_CLKID_MST_A_MCLK>;
31 clock-names = "sclk", "lrclk", 31 clock-names = "sclk", "lrclk", "mclk";
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 tdmif_b: audio-controller-1 { 35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm- 36 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>; 37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B"; 38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKI 39 clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40 <&clkc_audio AUD_CLKI 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>,
41 <&clkc_audio AUD_CLKI 41 <&clkc_audio AUD_CLKID_MST_B_MCLK>;
42 clock-names = "sclk", "lrclk", 42 clock-names = "sclk", "lrclk", "mclk";
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 tdmif_c: audio-controller-2 { 46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm- 47 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>; 48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C"; 49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKI 50 clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51 <&clkc_audio AUD_CLKI 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>,
52 <&clkc_audio AUD_CLKI 52 <&clkc_audio AUD_CLKID_MST_C_MCLK>;
53 clock-names = "sclk", "lrclk", 53 clock-names = "sclk", "lrclk", "mclk";
54 status = "disabled"; 54 status = "disabled";
55 }; 55 };
56 56
57 arm-pmu { 57 arm-pmu {
58 compatible = "arm,cortex-a53-p 58 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_ 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_ 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_ 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_ 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 }; 64 };
65 65
66 cpus { 66 cpus {
67 #address-cells = <0x2>; 67 #address-cells = <0x2>;
68 #size-cells = <0x0>; 68 #size-cells = <0x0>;
69 69
70 cpu0: cpu@0 { 70 cpu0: cpu@0 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>; 73 reg = <0x0 0x0>;
74 enable-method = "psci" 74 enable-method = "psci";
75 next-level-cache = <&l 75 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0 76 clocks = <&scpi_dvfs 0>;
77 dynamic-power-coeffici 77 dynamic-power-coefficient = <140>;
78 #cooling-cells = <2>; 78 #cooling-cells = <2>;
79 }; 79 };
80 80
81 cpu1: cpu@1 { 81 cpu1: cpu@1 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>; 84 reg = <0x0 0x1>;
85 enable-method = "psci" 85 enable-method = "psci";
86 next-level-cache = <&l 86 next-level-cache = <&l2>;
87 clocks = <&scpi_dvfs 0 87 clocks = <&scpi_dvfs 0>;
88 dynamic-power-coeffici 88 dynamic-power-coefficient = <140>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 }; 90 };
91 91
92 cpu2: cpu@2 { 92 cpu2: cpu@2 {
93 device_type = "cpu"; 93 device_type = "cpu";
94 compatible = "arm,cort 94 compatible = "arm,cortex-a53";
95 reg = <0x0 0x2>; 95 reg = <0x0 0x2>;
96 enable-method = "psci" 96 enable-method = "psci";
97 next-level-cache = <&l 97 next-level-cache = <&l2>;
98 clocks = <&scpi_dvfs 0 98 clocks = <&scpi_dvfs 0>;
99 dynamic-power-coeffici 99 dynamic-power-coefficient = <140>;
100 #cooling-cells = <2>; 100 #cooling-cells = <2>;
101 }; 101 };
102 102
103 cpu3: cpu@3 { 103 cpu3: cpu@3 {
104 device_type = "cpu"; 104 device_type = "cpu";
105 compatible = "arm,cort 105 compatible = "arm,cortex-a53";
106 reg = <0x0 0x3>; 106 reg = <0x0 0x3>;
107 enable-method = "psci" 107 enable-method = "psci";
108 next-level-cache = <&l 108 next-level-cache = <&l2>;
109 clocks = <&scpi_dvfs 0 109 clocks = <&scpi_dvfs 0>;
110 dynamic-power-coeffici 110 dynamic-power-coefficient = <140>;
111 #cooling-cells = <2>; 111 #cooling-cells = <2>;
112 }; 112 };
113 113
114 l2: l2-cache0 { 114 l2: l2-cache0 {
115 compatible = "cache"; 115 compatible = "cache";
116 cache-level = <2>; 116 cache-level = <2>;
117 cache-unified; 117 cache-unified;
118 }; 118 };
119 }; 119 };
120 120
121 sm: secure-monitor { 121 sm: secure-monitor {
122 compatible = "amlogic,meson-gx 122 compatible = "amlogic,meson-gxbb-sm";
123 }; 123 };
124 124
125 efuse: efuse { 125 efuse: efuse {
126 compatible = "amlogic,meson-gx 126 compatible = "amlogic,meson-gxbb-efuse";
127 clocks = <&clkc CLKID_EFUSE>; 127 clocks = <&clkc CLKID_EFUSE>;
128 #address-cells = <1>; 128 #address-cells = <1>;
129 #size-cells = <1>; 129 #size-cells = <1>;
130 read-only; 130 read-only;
131 secure-monitor = <&sm>; 131 secure-monitor = <&sm>;
132 }; 132 };
133 133
134 psci { 134 psci {
135 compatible = "arm,psci-1.0"; 135 compatible = "arm,psci-1.0";
136 method = "smc"; 136 method = "smc";
137 }; 137 };
138 138
139 reserved-memory { 139 reserved-memory {
140 #address-cells = <2>; 140 #address-cells = <2>;
141 #size-cells = <2>; 141 #size-cells = <2>;
142 ranges; 142 ranges;
143 143
144 /* 16 MiB reserved for Hardwar 144 /* 16 MiB reserved for Hardware ROM Firmware */
145 hwrom_reserved: hwrom@0 { 145 hwrom_reserved: hwrom@0 {
146 reg = <0x0 0x0 0x0 0x1 146 reg = <0x0 0x0 0x0 0x1000000>;
147 no-map; 147 no-map;
148 }; 148 };
149 149
150 /* Alternate 3 MiB reserved fo 150 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
151 secmon_reserved: secmon@500000 151 secmon_reserved: secmon@5000000 {
152 reg = <0x0 0x05000000 152 reg = <0x0 0x05000000 0x0 0x300000>;
153 no-map; 153 no-map;
154 }; 154 };
155 }; 155 };
156 156
157 scpi { 157 scpi {
158 compatible = "arm,scpi-pre-1.0 158 compatible = "arm,scpi-pre-1.0";
159 mboxes = <&mailbox 1 &mailbox 159 mboxes = <&mailbox 1 &mailbox 2>;
160 shmem = <&cpu_scp_lpri &cpu_sc 160 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 161
162 scpi_clocks: clocks { 162 scpi_clocks: clocks {
163 compatible = "arm,scpi 163 compatible = "arm,scpi-clocks";
164 164
165 scpi_dvfs: clocks-0 { 165 scpi_dvfs: clocks-0 {
166 compatible = " 166 compatible = "arm,scpi-dvfs-clocks";
167 #clock-cells = 167 #clock-cells = <1>;
168 clock-indices 168 clock-indices = <0>;
169 clock-output-n 169 clock-output-names = "vcpu";
170 }; 170 };
171 }; 171 };
172 172
173 scpi_sensors: sensors { 173 scpi_sensors: sensors {
174 compatible = "amlogic, 174 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
175 #thermal-sensor-cells 175 #thermal-sensor-cells = <1>;
176 }; 176 };
177 }; 177 };
178 178
179 soc { 179 soc {
180 compatible = "simple-bus"; 180 compatible = "simple-bus";
181 #address-cells = <2>; 181 #address-cells = <2>;
182 #size-cells = <2>; 182 #size-cells = <2>;
183 ranges; 183 ranges;
184 184
185 pcieA: pcie@f9800000 { 185 pcieA: pcie@f9800000 {
186 compatible = "amlogic, 186 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
187 reg = <0x0 0xf9800000 187 reg = <0x0 0xf9800000 0x0 0x400000>,
188 <0x0 0xff646000 188 <0x0 0xff646000 0x0 0x2000>,
189 <0x0 0xf9f00000 189 <0x0 0xf9f00000 0x0 0x100000>;
190 reg-names = "elbi", "c 190 reg-names = "elbi", "cfg", "config";
191 interrupts = <GIC_SPI 191 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
192 #interrupt-cells = <1> 192 #interrupt-cells = <1>;
193 interrupt-map-mask = < 193 interrupt-map-mask = <0 0 0 0>;
194 interrupt-map = <0 0 0 194 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
195 bus-range = <0x0 0xff> 195 bus-range = <0x0 0xff>;
196 #address-cells = <3>; 196 #address-cells = <3>;
197 #size-cells = <2>; 197 #size-cells = <2>;
198 device_type = "pci"; 198 device_type = "pci";
199 ranges = <0x82000000 0 199 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
200 200
201 clocks = <&clkc CLKID_ 201 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
202 clock-names = "general 202 clock-names = "general", "pclk", "port";
203 resets = <&reset RESET 203 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
204 reset-names = "port", 204 reset-names = "port", "apb";
205 num-lanes = <1>; 205 num-lanes = <1>;
206 phys = <&pcie_phy>; 206 phys = <&pcie_phy>;
207 phy-names = "pcie"; 207 phy-names = "pcie";
208 status = "disabled"; 208 status = "disabled";
209 }; 209 };
210 210
211 pcieB: pcie@fa000000 { 211 pcieB: pcie@fa000000 {
212 compatible = "amlogic, 212 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
213 reg = <0x0 0xfa000000 213 reg = <0x0 0xfa000000 0x0 0x400000>,
214 <0x0 0xff648000 214 <0x0 0xff648000 0x0 0x2000>,
215 <0x0 0xfa400000 215 <0x0 0xfa400000 0x0 0x100000>;
216 reg-names = "elbi", "c 216 reg-names = "elbi", "cfg", "config";
217 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
218 #interrupt-cells = <1> 218 #interrupt-cells = <1>;
219 interrupt-map-mask = < 219 interrupt-map-mask = <0 0 0 0>;
220 interrupt-map = <0 0 0 220 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
221 bus-range = <0x0 0xff> 221 bus-range = <0x0 0xff>;
222 #address-cells = <3>; 222 #address-cells = <3>;
223 #size-cells = <2>; 223 #size-cells = <2>;
224 device_type = "pci"; 224 device_type = "pci";
225 ranges = <0x82000000 0 225 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
226 226
227 clocks = <&clkc CLKID_ 227 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
228 clock-names = "general 228 clock-names = "general", "pclk", "port";
229 resets = <&reset RESET 229 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
230 reset-names = "port", 230 reset-names = "port", "apb";
231 num-lanes = <1>; 231 num-lanes = <1>;
232 phys = <&pcie_phy>; 232 phys = <&pcie_phy>;
233 phy-names = "pcie"; 233 phy-names = "pcie";
234 status = "disabled"; 234 status = "disabled";
235 }; 235 };
236 236
237 usb: usb@ffe09080 { 237 usb: usb@ffe09080 {
238 compatible = "amlogic, 238 compatible = "amlogic,meson-axg-usb-ctrl";
239 reg = <0x0 0xffe09080 239 reg = <0x0 0xffe09080 0x0 0x20>;
240 interrupts = <GIC_SPI 240 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <2>; 241 #address-cells = <2>;
242 #size-cells = <2>; 242 #size-cells = <2>;
243 ranges; 243 ranges;
244 244
245 clocks = <&clkc CLKID_ 245 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
246 clock-names = "usb_ctr 246 clock-names = "usb_ctrl", "ddr";
247 resets = <&reset RESET 247 resets = <&reset RESET_USB_OTG>;
248 248
249 dr_mode = "otg"; 249 dr_mode = "otg";
250 250
251 phys = <&usb2_phy1>; 251 phys = <&usb2_phy1>;
252 phy-names = "usb2-phy1 252 phy-names = "usb2-phy1";
253 253
254 dwc2: usb@ff400000 { 254 dwc2: usb@ff400000 {
255 compatible = " 255 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
256 reg = <0x0 0xf 256 reg = <0x0 0xff400000 0x0 0x40000>;
257 interrupts = < 257 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk 258 clocks = <&clkc CLKID_USB1>;
259 clock-names = 259 clock-names = "otg";
260 phys = <&usb2_ 260 phys = <&usb2_phy1>;
261 dr_mode = "per 261 dr_mode = "peripheral";
262 g-rx-fifo-size 262 g-rx-fifo-size = <192>;
263 g-np-tx-fifo-s 263 g-np-tx-fifo-size = <128>;
264 g-tx-fifo-size 264 g-tx-fifo-size = <128 128 16 16 16>;
265 }; 265 };
266 266
267 dwc3: usb@ff500000 { 267 dwc3: usb@ff500000 {
268 compatible = " 268 compatible = "snps,dwc3";
269 reg = <0x0 0xf 269 reg = <0x0 0xff500000 0x0 0x100000>;
270 interrupts = < 270 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
271 dr_mode = "hos 271 dr_mode = "host";
272 maximum-speed 272 maximum-speed = "high-speed";
273 snps,dis_u2_su 273 snps,dis_u2_susphy_quirk;
274 }; 274 };
275 }; 275 };
276 276
277 ethmac: ethernet@ff3f0000 { 277 ethmac: ethernet@ff3f0000 {
278 compatible = "amlogic, 278 compatible = "amlogic,meson-axg-dwmac",
279 "snps,dwm 279 "snps,dwmac-3.70a",
280 "snps,dwm 280 "snps,dwmac";
281 reg = <0x0 0xff3f0000 281 reg = <0x0 0xff3f0000 0x0 0x10000>,
282 <0x0 0xff634540 282 <0x0 0xff634540 0x0 0x8>;
283 interrupts = <GIC_SPI 283 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mac 284 interrupt-names = "macirq";
285 clocks = <&clkc CLKID_ 285 clocks = <&clkc CLKID_ETH>,
286 <&clkc CLKID_ 286 <&clkc CLKID_FCLK_DIV2>,
287 <&clkc CLKID_ 287 <&clkc CLKID_MPLL2>,
288 <&clkc CLKID_ 288 <&clkc CLKID_FCLK_DIV2>;
289 clock-names = "stmmace 289 clock-names = "stmmaceth", "clkin0", "clkin1",
290 "timing- 290 "timing-adjustment";
291 rx-fifo-depth = <4096> 291 rx-fifo-depth = <4096>;
292 tx-fifo-depth = <2048> 292 tx-fifo-depth = <2048>;
293 power-domains = <&pwrc 293 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
294 status = "disabled"; 294 status = "disabled";
295 }; 295 };
296 296
297 pcie_phy: phy@ff644000 { 297 pcie_phy: phy@ff644000 {
298 compatible = "amlogic, 298 compatible = "amlogic,axg-pcie-phy";
299 reg = <0x0 0xff644000 299 reg = <0x0 0xff644000 0x0 0x1c>;
300 resets = <&reset RESET 300 resets = <&reset RESET_PCIE_PHY>;
301 phys = <&mipi_pcie_ana 301 phys = <&mipi_pcie_analog_dphy>;
302 phy-names = "analog"; 302 phy-names = "analog";
303 #phy-cells = <0>; 303 #phy-cells = <0>;
304 }; 304 };
305 305
306 pdm: audio-controller@ff632000 306 pdm: audio-controller@ff632000 {
307 compatible = "amlogic, 307 compatible = "amlogic,axg-pdm";
308 reg = <0x0 0xff632000 308 reg = <0x0 0xff632000 0x0 0x34>;
309 #sound-dai-cells = <0> 309 #sound-dai-cells = <0>;
310 sound-name-prefix = "P 310 sound-name-prefix = "PDM";
311 clocks = <&clkc_audio 311 clocks = <&clkc_audio AUD_CLKID_PDM>,
312 <&clkc_audio 312 <&clkc_audio AUD_CLKID_PDM_DCLK>,
313 <&clkc_audio 313 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
314 clock-names = "pclk", 314 clock-names = "pclk", "dclk", "sysclk";
315 status = "disabled"; 315 status = "disabled";
316 }; 316 };
317 317
318 periphs: bus@ff634000 { 318 periphs: bus@ff634000 {
319 compatible = "simple-b 319 compatible = "simple-bus";
320 reg = <0x0 0xff634000 320 reg = <0x0 0xff634000 0x0 0x2000>;
321 #address-cells = <2>; 321 #address-cells = <2>;
322 #size-cells = <2>; 322 #size-cells = <2>;
323 ranges = <0x0 0x0 0x0 323 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
324 324
325 hwrng: rng@18 { 325 hwrng: rng@18 {
326 compatible = " 326 compatible = "amlogic,meson-rng";
327 reg = <0x0 0x1 327 reg = <0x0 0x18 0x0 0x4>;
328 clocks = <&clk 328 clocks = <&clkc CLKID_RNG0>;
329 clock-names = 329 clock-names = "core";
330 }; 330 };
331 331
332 pinctrl_periphs: pinct 332 pinctrl_periphs: pinctrl@480 {
333 compatible = " 333 compatible = "amlogic,meson-axg-periphs-pinctrl";
334 #address-cells 334 #address-cells = <2>;
335 #size-cells = 335 #size-cells = <2>;
336 ranges; 336 ranges;
337 337
338 gpio: bank@480 338 gpio: bank@480 {
339 reg = 339 reg = <0x0 0x00480 0x0 0x40>,
340 340 <0x0 0x004e8 0x0 0x14>,
341 341 <0x0 0x00520 0x0 0x14>,
342 342 <0x0 0x00430 0x0 0x3c>;
343 reg-na 343 reg-names = "mux", "pull", "pull-enable", "gpio";
344 gpio-c 344 gpio-controller;
345 #gpio- 345 #gpio-cells = <2>;
346 gpio-r 346 gpio-ranges = <&pinctrl_periphs 0 0 86>;
347 }; 347 };
348 348
349 i2c0_pins: i2c 349 i2c0_pins: i2c0 {
350 mux { 350 mux {
351 351 groups = "i2c0_sck",
352 352 "i2c0_sda";
353 353 function = "i2c0";
354 354 bias-disable;
355 }; 355 };
356 }; 356 };
357 357
358 i2c1_x_pins: i 358 i2c1_x_pins: i2c1_x {
359 mux { 359 mux {
360 360 groups = "i2c1_sck_x",
361 361 "i2c1_sda_x";
362 362 function = "i2c1";
363 363 bias-disable;
364 }; 364 };
365 }; 365 };
366 366
367 i2c1_z_pins: i 367 i2c1_z_pins: i2c1_z {
368 mux { 368 mux {
369 369 groups = "i2c1_sck_z",
370 370 "i2c1_sda_z";
371 371 function = "i2c1";
372 372 bias-disable;
373 }; 373 };
374 }; 374 };
375 375
376 i2c2_a_pins: i 376 i2c2_a_pins: i2c2_a {
377 mux { 377 mux {
378 378 groups = "i2c2_sck_a",
379 379 "i2c2_sda_a";
380 380 function = "i2c2";
381 381 bias-disable;
382 }; 382 };
383 }; 383 };
384 384
385 i2c2_x_pins: i 385 i2c2_x_pins: i2c2_x {
386 mux { 386 mux {
387 387 groups = "i2c2_sck_x",
388 388 "i2c2_sda_x";
389 389 function = "i2c2";
390 390 bias-disable;
391 }; 391 };
392 }; 392 };
393 393
394 i2c3_a6_pins: 394 i2c3_a6_pins: i2c3_a6 {
395 mux { 395 mux {
396 396 groups = "i2c3_sda_a6",
397 397 "i2c3_sck_a7";
398 398 function = "i2c3";
399 399 bias-disable;
400 }; 400 };
401 }; 401 };
402 402
403 i2c3_a12_pins: 403 i2c3_a12_pins: i2c3_a12 {
404 mux { 404 mux {
405 405 groups = "i2c3_sda_a12",
406 406 "i2c3_sck_a13";
407 407 function = "i2c3";
408 408 bias-disable;
409 }; 409 };
410 }; 410 };
411 411
412 i2c3_a19_pins: 412 i2c3_a19_pins: i2c3_a19 {
413 mux { 413 mux {
414 414 groups = "i2c3_sda_a19",
415 415 "i2c3_sck_a20";
416 416 function = "i2c3";
417 417 bias-disable;
418 }; 418 };
419 }; 419 };
420 420
421 emmc_pins: emm 421 emmc_pins: emmc {
422 mux-0 422 mux-0 {
423 423 groups = "emmc_nand_d0",
424 424 "emmc_nand_d1",
425 425 "emmc_nand_d2",
426 426 "emmc_nand_d3",
427 427 "emmc_nand_d4",
428 428 "emmc_nand_d5",
429 429 "emmc_nand_d6",
430 430 "emmc_nand_d7",
431 431 "emmc_cmd";
432 432 function = "emmc";
433 433 bias-pull-up;
434 }; 434 };
435 435
436 mux-1 436 mux-1 {
437 437 groups = "emmc_clk";
438 438 function = "emmc";
439 439 bias-disable;
440 }; 440 };
441 }; 441 };
442 442
443 nand_all_pins: 443 nand_all_pins: nand-all-pins {
444 mux { 444 mux {
445 445 groups = "emmc_nand_d0",
446 446 "emmc_nand_d1",
447 447 "emmc_nand_d2",
448 448 "emmc_nand_d3",
449 449 "emmc_nand_d4",
450 450 "emmc_nand_d5",
451 451 "emmc_nand_d6",
452 452 "emmc_nand_d7",
453 453 "nand_ce0",
454 454 "nand_ale",
455 455 "nand_cle",
456 456 "nand_wen_clk",
457 457 "nand_ren_wr";
458 458 function = "nand";
459 459 input-enable;
460 460 bias-pull-up;
461 }; 461 };
462 }; 462 };
463 463
464 emmc_ds_pins: 464 emmc_ds_pins: emmc_ds {
465 mux { 465 mux {
466 466 groups = "emmc_ds";
467 467 function = "emmc";
468 468 bias-pull-down;
469 }; 469 };
470 }; 470 };
471 471
472 emmc_clk_gate_ 472 emmc_clk_gate_pins: emmc_clk_gate {
473 mux { 473 mux {
474 474 groups = "BOOT_8";
475 475 function = "gpio_periphs";
476 476 bias-pull-down;
477 }; 477 };
478 }; 478 };
479 479
480 eth_rgmii_x_pi 480 eth_rgmii_x_pins: eth-x-rgmii {
481 mux { 481 mux {
482 482 groups = "eth_mdio_x",
483 483 "eth_mdc_x",
484 484 "eth_rgmii_rx_clk_x",
485 485 "eth_rx_dv_x",
486 486 "eth_rxd0_x",
487 487 "eth_rxd1_x",
488 488 "eth_rxd2_rgmii",
489 489 "eth_rxd3_rgmii",
490 490 "eth_rgmii_tx_clk",
491 491 "eth_txen_x",
492 492 "eth_txd0_x",
493 493 "eth_txd1_x",
494 494 "eth_txd2_rgmii",
495 495 "eth_txd3_rgmii";
496 496 function = "eth";
497 497 bias-disable;
498 }; 498 };
499 }; 499 };
500 500
501 eth_rgmii_y_pi 501 eth_rgmii_y_pins: eth-y-rgmii {
502 mux { 502 mux {
503 503 groups = "eth_mdio_y",
504 504 "eth_mdc_y",
505 505 "eth_rgmii_rx_clk_y",
506 506 "eth_rx_dv_y",
507 507 "eth_rxd0_y",
508 508 "eth_rxd1_y",
509 509 "eth_rxd2_rgmii",
510 510 "eth_rxd3_rgmii",
511 511 "eth_rgmii_tx_clk",
512 512 "eth_txen_y",
513 513 "eth_txd0_y",
514 514 "eth_txd1_y",
515 515 "eth_txd2_rgmii",
516 516 "eth_txd3_rgmii";
517 517 function = "eth";
518 518 bias-disable;
519 }; 519 };
520 }; 520 };
521 521
522 eth_rmii_x_pin 522 eth_rmii_x_pins: eth-x-rmii {
523 mux { 523 mux {
524 524 groups = "eth_mdio_x",
525 525 "eth_mdc_x",
526 526 "eth_rgmii_rx_clk_x",
527 527 "eth_rx_dv_x",
528 528 "eth_rxd0_x",
529 529 "eth_rxd1_x",
530 530 "eth_txen_x",
531 531 "eth_txd0_x",
532 532 "eth_txd1_x";
533 533 function = "eth";
534 534 bias-disable;
535 }; 535 };
536 }; 536 };
537 537
538 eth_rmii_y_pin 538 eth_rmii_y_pins: eth-y-rmii {
539 mux { 539 mux {
540 540 groups = "eth_mdio_y",
541 541 "eth_mdc_y",
542 542 "eth_rgmii_rx_clk_y",
543 543 "eth_rx_dv_y",
544 544 "eth_rxd0_y",
545 545 "eth_rxd1_y",
546 546 "eth_txen_y",
547 547 "eth_txd0_y",
548 548 "eth_txd1_y";
549 549 function = "eth";
550 550 bias-disable;
551 }; 551 };
552 }; 552 };
553 553
554 mclk_b_pins: m 554 mclk_b_pins: mclk_b {
555 mux { 555 mux {
556 556 groups = "mclk_b";
557 557 function = "mclk_b";
558 558 bias-disable;
559 }; 559 };
560 }; 560 };
561 561
562 mclk_c_pins: m 562 mclk_c_pins: mclk_c {
563 mux { 563 mux {
564 564 groups = "mclk_c";
565 565 function = "mclk_c";
566 566 bias-disable;
567 }; 567 };
568 }; 568 };
569 569
570 pdm_dclk_a14_p 570 pdm_dclk_a14_pins: pdm_dclk_a14 {
571 mux { 571 mux {
572 572 groups = "pdm_dclk_a14";
573 573 function = "pdm";
574 574 bias-disable;
575 }; 575 };
576 }; 576 };
577 577
578 pdm_dclk_a19_p 578 pdm_dclk_a19_pins: pdm_dclk_a19 {
579 mux { 579 mux {
580 580 groups = "pdm_dclk_a19";
581 581 function = "pdm";
582 582 bias-disable;
583 }; 583 };
584 }; 584 };
585 585
586 pdm_din0_pins: 586 pdm_din0_pins: pdm_din0 {
587 mux { 587 mux {
588 588 groups = "pdm_din0";
589 589 function = "pdm";
590 590 bias-disable;
591 }; 591 };
592 }; 592 };
593 593
594 pdm_din1_pins: 594 pdm_din1_pins: pdm_din1 {
595 mux { 595 mux {
596 596 groups = "pdm_din1";
597 597 function = "pdm";
598 598 bias-disable;
599 }; 599 };
600 }; 600 };
601 601
602 pdm_din2_pins: 602 pdm_din2_pins: pdm_din2 {
603 mux { 603 mux {
604 604 groups = "pdm_din2";
605 605 function = "pdm";
606 606 bias-disable;
607 }; 607 };
608 }; 608 };
609 609
610 pdm_din3_pins: 610 pdm_din3_pins: pdm_din3 {
611 mux { 611 mux {
612 612 groups = "pdm_din3";
613 613 function = "pdm";
614 614 bias-disable;
615 }; 615 };
616 }; 616 };
617 617
618 pwm_a_a_pins: 618 pwm_a_a_pins: pwm_a_a {
619 mux { 619 mux {
620 620 groups = "pwm_a_a";
621 621 function = "pwm_a";
622 622 bias-disable;
623 }; 623 };
624 }; 624 };
625 625
626 pwm_a_x18_pins 626 pwm_a_x18_pins: pwm_a_x18 {
627 mux { 627 mux {
628 628 groups = "pwm_a_x18";
629 629 function = "pwm_a";
630 630 bias-disable;
631 }; 631 };
632 }; 632 };
633 633
634 pwm_a_x20_pins 634 pwm_a_x20_pins: pwm_a_x20 {
635 mux { 635 mux {
636 636 groups = "pwm_a_x20";
637 637 function = "pwm_a";
638 638 bias-disable;
639 }; 639 };
640 }; 640 };
641 641
642 pwm_a_z_pins: 642 pwm_a_z_pins: pwm_a_z {
643 mux { 643 mux {
644 644 groups = "pwm_a_z";
645 645 function = "pwm_a";
646 646 bias-disable;
647 }; 647 };
648 }; 648 };
649 649
650 pwm_b_a_pins: 650 pwm_b_a_pins: pwm_b_a {
651 mux { 651 mux {
652 652 groups = "pwm_b_a";
653 653 function = "pwm_b";
654 654 bias-disable;
655 }; 655 };
656 }; 656 };
657 657
658 pwm_b_x_pins: 658 pwm_b_x_pins: pwm_b_x {
659 mux { 659 mux {
660 660 groups = "pwm_b_x";
661 661 function = "pwm_b";
662 662 bias-disable;
663 }; 663 };
664 }; 664 };
665 665
666 pwm_b_z_pins: 666 pwm_b_z_pins: pwm_b_z {
667 mux { 667 mux {
668 668 groups = "pwm_b_z";
669 669 function = "pwm_b";
670 670 bias-disable;
671 }; 671 };
672 }; 672 };
673 673
674 pwm_c_a_pins: 674 pwm_c_a_pins: pwm_c_a {
675 mux { 675 mux {
676 676 groups = "pwm_c_a";
677 677 function = "pwm_c";
678 678 bias-disable;
679 }; 679 };
680 }; 680 };
681 681
682 pwm_c_x10_pins 682 pwm_c_x10_pins: pwm_c_x10 {
683 mux { 683 mux {
684 684 groups = "pwm_c_x10";
685 685 function = "pwm_c";
686 686 bias-disable;
687 }; 687 };
688 }; 688 };
689 689
690 pwm_c_x17_pins 690 pwm_c_x17_pins: pwm_c_x17 {
691 mux { 691 mux {
692 692 groups = "pwm_c_x17";
693 693 function = "pwm_c";
694 694 bias-disable;
695 }; 695 };
696 }; 696 };
697 697
698 pwm_d_x11_pins 698 pwm_d_x11_pins: pwm_d_x11 {
699 mux { 699 mux {
700 700 groups = "pwm_d_x11";
701 701 function = "pwm_d";
702 702 bias-disable;
703 }; 703 };
704 }; 704 };
705 705
706 pwm_d_x16_pins 706 pwm_d_x16_pins: pwm_d_x16 {
707 mux { 707 mux {
708 708 groups = "pwm_d_x16";
709 709 function = "pwm_d";
710 710 bias-disable;
711 }; 711 };
712 }; 712 };
713 713
714 sdio_pins: sdi 714 sdio_pins: sdio {
715 mux-0 715 mux-0 {
716 716 groups = "sdio_d0",
717 717 "sdio_d1",
718 718 "sdio_d2",
719 719 "sdio_d3",
720 720 "sdio_cmd";
721 721 function = "sdio";
722 722 bias-pull-up;
723 }; 723 };
724 724
725 mux-1 725 mux-1 {
726 726 groups = "sdio_clk";
727 727 function = "sdio";
728 728 bias-disable;
729 }; 729 };
730 }; 730 };
731 731
732 sdio_clk_gate_ 732 sdio_clk_gate_pins: sdio_clk_gate {
733 mux { 733 mux {
734 734 groups = "GPIOX_4";
735 735 function = "gpio_periphs";
736 736 bias-pull-down;
737 }; 737 };
738 }; 738 };
739 739
740 spdif_in_z_pin 740 spdif_in_z_pins: spdif_in_z {
741 mux { 741 mux {
742 742 groups = "spdif_in_z";
743 743 function = "spdif_in";
744 744 bias-disable;
745 }; 745 };
746 }; 746 };
747 747
748 spdif_in_a1_pi 748 spdif_in_a1_pins: spdif_in_a1 {
749 mux { 749 mux {
750 750 groups = "spdif_in_a1";
751 751 function = "spdif_in";
752 752 bias-disable;
753 }; 753 };
754 }; 754 };
755 755
756 spdif_in_a7_pi 756 spdif_in_a7_pins: spdif_in_a7 {
757 mux { 757 mux {
758 758 groups = "spdif_in_a7";
759 759 function = "spdif_in";
760 760 bias-disable;
761 }; 761 };
762 }; 762 };
763 763
764 spdif_in_a19_p 764 spdif_in_a19_pins: spdif_in_a19 {
765 mux { 765 mux {
766 766 groups = "spdif_in_a19";
767 767 function = "spdif_in";
768 768 bias-disable;
769 }; 769 };
770 }; 770 };
771 771
772 spdif_in_a20_p 772 spdif_in_a20_pins: spdif_in_a20 {
773 mux { 773 mux {
774 774 groups = "spdif_in_a20";
775 775 function = "spdif_in";
776 776 bias-disable;
777 }; 777 };
778 }; 778 };
779 779
780 spdif_out_a1_p 780 spdif_out_a1_pins: spdif_out_a1 {
781 mux { 781 mux {
782 782 groups = "spdif_out_a1";
783 783 function = "spdif_out";
784 784 bias-disable;
785 }; 785 };
786 }; 786 };
787 787
788 spdif_out_a11_ 788 spdif_out_a11_pins: spdif_out_a11 {
789 mux { 789 mux {
790 790 groups = "spdif_out_a11";
791 791 function = "spdif_out";
792 792 bias-disable;
793 }; 793 };
794 }; 794 };
795 795
796 spdif_out_a19_ 796 spdif_out_a19_pins: spdif_out_a19 {
797 mux { 797 mux {
798 798 groups = "spdif_out_a19";
799 799 function = "spdif_out";
800 800 bias-disable;
801 }; 801 };
802 }; 802 };
803 803
804 spdif_out_a20_ 804 spdif_out_a20_pins: spdif_out_a20 {
805 mux { 805 mux {
806 806 groups = "spdif_out_a20";
807 807 function = "spdif_out";
808 808 bias-disable;
809 }; 809 };
810 }; 810 };
811 811
812 spdif_out_z_pi 812 spdif_out_z_pins: spdif_out_z {
813 mux { 813 mux {
814 814 groups = "spdif_out_z";
815 815 function = "spdif_out";
816 816 bias-disable;
817 }; 817 };
818 }; 818 };
819 819
820 spi0_pins: spi 820 spi0_pins: spi0 {
821 mux { 821 mux {
822 822 groups = "spi0_miso",
823 823 "spi0_mosi",
824 824 "spi0_clk";
825 825 function = "spi0";
826 826 bias-disable;
827 }; 827 };
828 }; 828 };
829 829
830 spi0_ss0_pins: 830 spi0_ss0_pins: spi0_ss0 {
831 mux { 831 mux {
832 832 groups = "spi0_ss0";
833 833 function = "spi0";
834 834 bias-disable;
835 }; 835 };
836 }; 836 };
837 837
838 spi0_ss1_pins: 838 spi0_ss1_pins: spi0_ss1 {
839 mux { 839 mux {
840 840 groups = "spi0_ss1";
841 841 function = "spi0";
842 842 bias-disable;
843 }; 843 };
844 }; 844 };
845 845
846 spi0_ss2_pins: 846 spi0_ss2_pins: spi0_ss2 {
847 mux { 847 mux {
848 848 groups = "spi0_ss2";
849 849 function = "spi0";
850 850 bias-disable;
851 }; 851 };
852 }; 852 };
853 853
854 spi1_a_pins: s 854 spi1_a_pins: spi1_a {
855 mux { 855 mux {
856 856 groups = "spi1_miso_a",
857 857 "spi1_mosi_a",
858 858 "spi1_clk_a";
859 859 function = "spi1";
860 860 bias-disable;
861 }; 861 };
862 }; 862 };
863 863
864 spi1_ss0_a_pin 864 spi1_ss0_a_pins: spi1_ss0_a {
865 mux { 865 mux {
866 866 groups = "spi1_ss0_a";
867 867 function = "spi1";
868 868 bias-disable;
869 }; 869 };
870 }; 870 };
871 871
872 spi1_ss1_pins: 872 spi1_ss1_pins: spi1_ss1 {
873 mux { 873 mux {
874 874 groups = "spi1_ss1";
875 875 function = "spi1";
876 876 bias-disable;
877 }; 877 };
878 }; 878 };
879 879
880 spi1_x_pins: s 880 spi1_x_pins: spi1_x {
881 mux { 881 mux {
882 882 groups = "spi1_miso_x",
883 883 "spi1_mosi_x",
884 884 "spi1_clk_x";
885 885 function = "spi1";
886 886 bias-disable;
887 }; 887 };
888 }; 888 };
889 889
890 spi1_ss0_x_pin 890 spi1_ss0_x_pins: spi1_ss0_x {
891 mux { 891 mux {
892 892 groups = "spi1_ss0_x";
893 893 function = "spi1";
894 894 bias-disable;
895 }; 895 };
896 }; 896 };
897 897
898 tdma_din0_pins 898 tdma_din0_pins: tdma_din0 {
899 mux { 899 mux {
900 900 groups = "tdma_din0";
901 901 function = "tdma";
902 902 bias-disable;
903 }; 903 };
904 }; 904 };
905 905
906 tdma_dout0_x14 906 tdma_dout0_x14_pins: tdma_dout0_x14 {
907 mux { 907 mux {
908 908 groups = "tdma_dout0_x14";
909 909 function = "tdma";
910 910 bias-disable;
911 }; 911 };
912 }; 912 };
913 913
914 tdma_dout0_x15 914 tdma_dout0_x15_pins: tdma_dout0_x15 {
915 mux { 915 mux {
916 916 groups = "tdma_dout0_x15";
917 917 function = "tdma";
918 918 bias-disable;
919 }; 919 };
920 }; 920 };
921 921
922 tdma_dout1_pin 922 tdma_dout1_pins: tdma_dout1 {
923 mux { 923 mux {
924 924 groups = "tdma_dout1";
925 925 function = "tdma";
926 926 bias-disable;
927 }; 927 };
928 }; 928 };
929 929
930 tdma_din1_pins 930 tdma_din1_pins: tdma_din1 {
931 mux { 931 mux {
932 932 groups = "tdma_din1";
933 933 function = "tdma";
934 934 bias-disable;
935 }; 935 };
936 }; 936 };
937 937
938 tdma_fs_pins: 938 tdma_fs_pins: tdma_fs {
939 mux { 939 mux {
940 940 groups = "tdma_fs";
941 941 function = "tdma";
942 942 bias-disable;
943 }; 943 };
944 }; 944 };
945 945
946 tdma_fs_slv_pi 946 tdma_fs_slv_pins: tdma_fs_slv {
947 mux { 947 mux {
948 948 groups = "tdma_fs_slv";
949 949 function = "tdma";
950 950 bias-disable;
951 }; 951 };
952 }; 952 };
953 953
954 tdma_sclk_pins 954 tdma_sclk_pins: tdma_sclk {
955 mux { 955 mux {
956 956 groups = "tdma_sclk";
957 957 function = "tdma";
958 958 bias-disable;
959 }; 959 };
960 }; 960 };
961 961
962 tdma_sclk_slv_ 962 tdma_sclk_slv_pins: tdma_sclk_slv {
963 mux { 963 mux {
964 964 groups = "tdma_sclk_slv";
965 965 function = "tdma";
966 966 bias-disable;
967 }; 967 };
968 }; 968 };
969 969
970 tdmb_din0_pins 970 tdmb_din0_pins: tdmb_din0 {
971 mux { 971 mux {
972 972 groups = "tdmb_din0";
973 973 function = "tdmb";
974 974 bias-disable;
975 }; 975 };
976 }; 976 };
977 977
978 tdmb_din1_pins 978 tdmb_din1_pins: tdmb_din1 {
979 mux { 979 mux {
980 980 groups = "tdmb_din1";
981 981 function = "tdmb";
982 982 bias-disable;
983 }; 983 };
984 }; 984 };
985 985
986 tdmb_din2_pins 986 tdmb_din2_pins: tdmb_din2 {
987 mux { 987 mux {
988 988 groups = "tdmb_din2";
989 989 function = "tdmb";
990 990 bias-disable;
991 }; 991 };
992 }; 992 };
993 993
994 tdmb_din3_pins 994 tdmb_din3_pins: tdmb_din3 {
995 mux { 995 mux {
996 996 groups = "tdmb_din3";
997 997 function = "tdmb";
998 998 bias-disable;
999 }; 999 };
1000 }; 1000 };
1001 1001
1002 tdmb_dout0_pi 1002 tdmb_dout0_pins: tdmb_dout0 {
1003 mux { 1003 mux {
1004 1004 groups = "tdmb_dout0";
1005 1005 function = "tdmb";
1006 1006 bias-disable;
1007 }; 1007 };
1008 }; 1008 };
1009 1009
1010 tdmb_dout1_pi 1010 tdmb_dout1_pins: tdmb_dout1 {
1011 mux { 1011 mux {
1012 1012 groups = "tdmb_dout1";
1013 1013 function = "tdmb";
1014 1014 bias-disable;
1015 }; 1015 };
1016 }; 1016 };
1017 1017
1018 tdmb_dout2_pi 1018 tdmb_dout2_pins: tdmb_dout2 {
1019 mux { 1019 mux {
1020 1020 groups = "tdmb_dout2";
1021 1021 function = "tdmb";
1022 1022 bias-disable;
1023 }; 1023 };
1024 }; 1024 };
1025 1025
1026 tdmb_dout3_pi 1026 tdmb_dout3_pins: tdmb_dout3 {
1027 mux { 1027 mux {
1028 1028 groups = "tdmb_dout3";
1029 1029 function = "tdmb";
1030 1030 bias-disable;
1031 }; 1031 };
1032 }; 1032 };
1033 1033
1034 tdmb_fs_pins: 1034 tdmb_fs_pins: tdmb_fs {
1035 mux { 1035 mux {
1036 1036 groups = "tdmb_fs";
1037 1037 function = "tdmb";
1038 1038 bias-disable;
1039 }; 1039 };
1040 }; 1040 };
1041 1041
1042 tdmb_fs_slv_p 1042 tdmb_fs_slv_pins: tdmb_fs_slv {
1043 mux { 1043 mux {
1044 1044 groups = "tdmb_fs_slv";
1045 1045 function = "tdmb";
1046 1046 bias-disable;
1047 }; 1047 };
1048 }; 1048 };
1049 1049
1050 tdmb_sclk_pin 1050 tdmb_sclk_pins: tdmb_sclk {
1051 mux { 1051 mux {
1052 1052 groups = "tdmb_sclk";
1053 1053 function = "tdmb";
1054 1054 bias-disable;
1055 }; 1055 };
1056 }; 1056 };
1057 1057
1058 tdmb_sclk_slv 1058 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1059 mux { 1059 mux {
1060 1060 groups = "tdmb_sclk_slv";
1061 1061 function = "tdmb";
1062 1062 bias-disable;
1063 }; 1063 };
1064 }; 1064 };
1065 1065
1066 tdmc_fs_pins: 1066 tdmc_fs_pins: tdmc_fs {
1067 mux { 1067 mux {
1068 1068 groups = "tdmc_fs";
1069 1069 function = "tdmc";
1070 1070 bias-disable;
1071 }; 1071 };
1072 }; 1072 };
1073 1073
1074 tdmc_fs_slv_p 1074 tdmc_fs_slv_pins: tdmc_fs_slv {
1075 mux { 1075 mux {
1076 1076 groups = "tdmc_fs_slv";
1077 1077 function = "tdmc";
1078 1078 bias-disable;
1079 }; 1079 };
1080 }; 1080 };
1081 1081
1082 tdmc_sclk_pin 1082 tdmc_sclk_pins: tdmc_sclk {
1083 mux { 1083 mux {
1084 1084 groups = "tdmc_sclk";
1085 1085 function = "tdmc";
1086 1086 bias-disable;
1087 }; 1087 };
1088 }; 1088 };
1089 1089
1090 tdmc_sclk_slv 1090 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1091 mux { 1091 mux {
1092 1092 groups = "tdmc_sclk_slv";
1093 1093 function = "tdmc";
1094 1094 bias-disable;
1095 }; 1095 };
1096 }; 1096 };
1097 1097
1098 tdmc_din0_pin 1098 tdmc_din0_pins: tdmc_din0 {
1099 mux { 1099 mux {
1100 1100 groups = "tdmc_din0";
1101 1101 function = "tdmc";
1102 1102 bias-disable;
1103 }; 1103 };
1104 }; 1104 };
1105 1105
1106 tdmc_din1_pin 1106 tdmc_din1_pins: tdmc_din1 {
1107 mux { 1107 mux {
1108 1108 groups = "tdmc_din1";
1109 1109 function = "tdmc";
1110 1110 bias-disable;
1111 }; 1111 };
1112 }; 1112 };
1113 1113
1114 tdmc_din2_pin 1114 tdmc_din2_pins: tdmc_din2 {
1115 mux { 1115 mux {
1116 1116 groups = "tdmc_din2";
1117 1117 function = "tdmc";
1118 1118 bias-disable;
1119 }; 1119 };
1120 }; 1120 };
1121 1121
1122 tdmc_din3_pin 1122 tdmc_din3_pins: tdmc_din3 {
1123 mux { 1123 mux {
1124 1124 groups = "tdmc_din3";
1125 1125 function = "tdmc";
1126 1126 bias-disable;
1127 }; 1127 };
1128 }; 1128 };
1129 1129
1130 tdmc_dout0_pi 1130 tdmc_dout0_pins: tdmc_dout0 {
1131 mux { 1131 mux {
1132 1132 groups = "tdmc_dout0";
1133 1133 function = "tdmc";
1134 1134 bias-disable;
1135 }; 1135 };
1136 }; 1136 };
1137 1137
1138 tdmc_dout1_pi 1138 tdmc_dout1_pins: tdmc_dout1 {
1139 mux { 1139 mux {
1140 1140 groups = "tdmc_dout1";
1141 1141 function = "tdmc";
1142 1142 bias-disable;
1143 }; 1143 };
1144 }; 1144 };
1145 1145
1146 tdmc_dout2_pi 1146 tdmc_dout2_pins: tdmc_dout2 {
1147 mux { 1147 mux {
1148 1148 groups = "tdmc_dout2";
1149 1149 function = "tdmc";
1150 1150 bias-disable;
1151 }; 1151 };
1152 }; 1152 };
1153 1153
1154 tdmc_dout3_pi 1154 tdmc_dout3_pins: tdmc_dout3 {
1155 mux { 1155 mux {
1156 1156 groups = "tdmc_dout3";
1157 1157 function = "tdmc";
1158 1158 bias-disable;
1159 }; 1159 };
1160 }; 1160 };
1161 1161
1162 uart_a_pins: 1162 uart_a_pins: uart_a {
1163 mux { 1163 mux {
1164 1164 groups = "uart_tx_a",
1165 1165 "uart_rx_a";
1166 1166 function = "uart_a";
1167 1167 bias-disable;
1168 }; 1168 };
1169 }; 1169 };
1170 1170
1171 uart_a_cts_rt 1171 uart_a_cts_rts_pins: uart_a_cts_rts {
1172 mux { 1172 mux {
1173 1173 groups = "uart_cts_a",
1174 1174 "uart_rts_a";
1175 1175 function = "uart_a";
1176 1176 bias-disable;
1177 }; 1177 };
1178 }; 1178 };
1179 1179
1180 uart_b_x_pins 1180 uart_b_x_pins: uart_b_x {
1181 mux { 1181 mux {
1182 1182 groups = "uart_tx_b_x",
1183 1183 "uart_rx_b_x";
1184 1184 function = "uart_b";
1185 1185 bias-disable;
1186 }; 1186 };
1187 }; 1187 };
1188 1188
1189 uart_b_x_cts_ 1189 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1190 mux { 1190 mux {
1191 1191 groups = "uart_cts_b_x",
1192 1192 "uart_rts_b_x";
1193 1193 function = "uart_b";
1194 1194 bias-disable;
1195 }; 1195 };
1196 }; 1196 };
1197 1197
1198 uart_b_z_pins 1198 uart_b_z_pins: uart_b_z {
1199 mux { 1199 mux {
1200 1200 groups = "uart_tx_b_z",
1201 1201 "uart_rx_b_z";
1202 1202 function = "uart_b";
1203 1203 bias-disable;
1204 }; 1204 };
1205 }; 1205 };
1206 1206
1207 uart_b_z_cts_ 1207 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1208 mux { 1208 mux {
1209 1209 groups = "uart_cts_b_z",
1210 1210 "uart_rts_b_z";
1211 1211 function = "uart_b";
1212 1212 bias-disable;
1213 }; 1213 };
1214 }; 1214 };
1215 1215
1216 uart_ao_b_z_p 1216 uart_ao_b_z_pins: uart_ao_b_z {
1217 mux { 1217 mux {
1218 1218 groups = "uart_ao_tx_b_z",
1219 1219 "uart_ao_rx_b_z";
1220 1220 function = "uart_ao_b_z";
1221 1221 bias-disable;
1222 }; 1222 };
1223 }; 1223 };
1224 1224
1225 uart_ao_b_z_c 1225 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1226 mux { 1226 mux {
1227 1227 groups = "uart_ao_cts_b_z",
1228 1228 "uart_ao_rts_b_z";
1229 1229 function = "uart_ao_b_z";
1230 1230 bias-disable;
1231 }; 1231 };
1232 }; 1232 };
1233 }; 1233 };
1234 }; 1234 };
1235 1235
1236 hiubus: bus@ff63c000 { 1236 hiubus: bus@ff63c000 {
1237 compatible = "simple- 1237 compatible = "simple-bus";
1238 reg = <0x0 0xff63c000 1238 reg = <0x0 0xff63c000 0x0 0x1c00>;
1239 #address-cells = <2>; 1239 #address-cells = <2>;
1240 #size-cells = <2>; 1240 #size-cells = <2>;
1241 ranges = <0x0 0x0 0x0 1241 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1242 1242
1243 sysctrl: system-contr 1243 sysctrl: system-controller@0 {
1244 compatible = 1244 compatible = "amlogic,meson-axg-hhi-sysctrl",
1245 1245 "simple-mfd", "syscon";
1246 reg = <0 0 0 1246 reg = <0 0 0 0x400>;
1247 1247
1248 clkc: clock-c 1248 clkc: clock-controller {
1249 compa 1249 compatible = "amlogic,axg-clkc";
1250 #cloc 1250 #clock-cells = <1>;
1251 clock 1251 clocks = <&xtal>;
1252 clock 1252 clock-names = "xtal";
1253 }; 1253 };
1254 1254
1255 pwrc: power-c 1255 pwrc: power-controller {
1256 compa 1256 compatible = "amlogic,meson-axg-pwrc";
1257 #powe 1257 #power-domain-cells = <1>;
1258 amlog 1258 amlogic,ao-sysctrl = <&sysctrl_AO>;
1259 reset 1259 resets = <&reset RESET_VIU>,
1260 1260 <&reset RESET_VENC>,
1261 1261 <&reset RESET_VCBUS>,
1262 1262 <&reset RESET_VENCL>,
1263 1263 <&reset RESET_VID_LOCK>;
1264 reset 1264 reset-names = "viu", "venc", "vcbus",
1265 1265 "vencl", "vid_lock";
1266 clock 1266 clocks = <&clkc CLKID_VPU>,
1267 1267 <&clkc CLKID_VAPB>;
1268 clock 1268 clock-names = "vpu", "vapb";
1269 /* 1269 /*
1270 * VP 1270 * VPU clocking is provided by two identical clock paths
1271 * VP 1271 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1272 * fr 1272 * free mux to safely change frequency while running.
1273 * Sa 1273 * Same for VAPB but with a final gate after the glitch free mux.
1274 */ 1274 */
1275 assig 1275 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1276 1276 <&clkc CLKID_VPU_0>,
1277 1277 <&clkc CLKID_VPU>, /* Glitch free mux */
1278 1278 <&clkc CLKID_VAPB_0_SEL>,
1279 1279 <&clkc CLKID_VAPB_0>,
1280 1280 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1281 assig 1281 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1282 1282 <0>, /* Do Nothing */
1283 1283 <&clkc CLKID_VPU_0>,
1284 1284 <&clkc CLKID_FCLK_DIV4>,
1285 1285 <0>, /* Do Nothing */
1286 1286 <&clkc CLKID_VAPB_0>;
1287 assig 1287 assigned-clock-rates = <0>, /* Do Nothing */
1288 1288 <250000000>,
1289 1289 <0>, /* Do Nothing */
1290 1290 <0>, /* Do Nothing */
1291 1291 <250000000>,
1292 1292 <0>; /* Do Nothing */
1293 }; 1293 };
1294 1294
1295 mipi_pcie_ana 1295 mipi_pcie_analog_dphy: phy {
1296 compa 1296 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1297 #phy- 1297 #phy-cells = <0>;
1298 statu 1298 status = "disabled";
1299 }; 1299 };
1300 }; 1300 };
1301 }; 1301 };
1302 1302
1303 mailbox: mailbox@ff63c404 { 1303 mailbox: mailbox@ff63c404 {
1304 compatible = "amlogic 1304 compatible = "amlogic,meson-gxbb-mhu";
1305 reg = <0 0xff63c404 0 1305 reg = <0 0xff63c404 0 0x4c>;
1306 interrupts = <GIC_SPI 1306 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1307 <GIC_SPI 1307 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1308 <GIC_SPI 1308 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1309 #mbox-cells = <1>; 1309 #mbox-cells = <1>;
1310 }; 1310 };
1311 1311
1312 mipi_dphy: phy@ff640000 { 1312 mipi_dphy: phy@ff640000 {
1313 compatible = "amlogic 1313 compatible = "amlogic,axg-mipi-dphy";
1314 reg = <0x0 0xff640000 1314 reg = <0x0 0xff640000 0x0 0x100>;
1315 clocks = <&clkc CLKID 1315 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1316 clock-names = "pclk"; 1316 clock-names = "pclk";
1317 resets = <&reset RESE 1317 resets = <&reset RESET_MIPI_PHY>;
1318 reset-names = "phy"; 1318 reset-names = "phy";
1319 phys = <&mipi_pcie_an 1319 phys = <&mipi_pcie_analog_dphy>;
1320 phy-names = "analog"; 1320 phy-names = "analog";
1321 #phy-cells = <0>; 1321 #phy-cells = <0>;
1322 status = "disabled"; 1322 status = "disabled";
1323 }; 1323 };
1324 1324
1325 audio: bus@ff642000 { 1325 audio: bus@ff642000 {
1326 compatible = "simple- 1326 compatible = "simple-bus";
1327 reg = <0x0 0xff642000 1327 reg = <0x0 0xff642000 0x0 0x2000>;
1328 #address-cells = <2>; 1328 #address-cells = <2>;
1329 #size-cells = <2>; 1329 #size-cells = <2>;
1330 ranges = <0x0 0x0 0x0 1330 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1331 1331
1332 clkc_audio: clock-con 1332 clkc_audio: clock-controller@0 {
1333 compatible = 1333 compatible = "amlogic,axg-audio-clkc";
1334 reg = <0x0 0x 1334 reg = <0x0 0x0 0x0 0xb4>;
1335 #clock-cells 1335 #clock-cells = <1>;
1336 1336
1337 clocks = <&cl 1337 clocks = <&clkc CLKID_AUDIO>,
1338 <&cl 1338 <&clkc CLKID_MPLL0>,
1339 <&cl 1339 <&clkc CLKID_MPLL1>,
1340 <&cl 1340 <&clkc CLKID_MPLL2>,
1341 <&cl 1341 <&clkc CLKID_MPLL3>,
1342 <&cl 1342 <&clkc CLKID_HIFI_PLL>,
1343 <&cl 1343 <&clkc CLKID_FCLK_DIV3>,
1344 <&cl 1344 <&clkc CLKID_FCLK_DIV4>,
1345 <&cl 1345 <&clkc CLKID_GP0_PLL>;
1346 clock-names = 1346 clock-names = "pclk",
1347 1347 "mst_in0",
1348 1348 "mst_in1",
1349 1349 "mst_in2",
1350 1350 "mst_in3",
1351 1351 "mst_in4",
1352 1352 "mst_in5",
1353 1353 "mst_in6",
1354 1354 "mst_in7";
1355 1355
1356 resets = <&re 1356 resets = <&reset RESET_AUDIO>;
1357 }; 1357 };
1358 1358
1359 toddr_a: audio-contro 1359 toddr_a: audio-controller@100 {
1360 compatible = 1360 compatible = "amlogic,axg-toddr";
1361 reg = <0x0 0x 1361 reg = <0x0 0x100 0x0 0x2c>;
1362 #sound-dai-ce 1362 #sound-dai-cells = <0>;
1363 sound-name-pr 1363 sound-name-prefix = "TODDR_A";
1364 interrupts = 1364 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1365 clocks = <&cl 1365 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1366 resets = <&ar 1366 resets = <&arb AXG_ARB_TODDR_A>;
1367 amlogic,fifo- 1367 amlogic,fifo-depth = <512>;
1368 status = "dis 1368 status = "disabled";
1369 }; 1369 };
1370 1370
1371 toddr_b: audio-contro 1371 toddr_b: audio-controller@140 {
1372 compatible = 1372 compatible = "amlogic,axg-toddr";
1373 reg = <0x0 0x 1373 reg = <0x0 0x140 0x0 0x2c>;
1374 #sound-dai-ce 1374 #sound-dai-cells = <0>;
1375 sound-name-pr 1375 sound-name-prefix = "TODDR_B";
1376 interrupts = 1376 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1377 clocks = <&cl 1377 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1378 resets = <&ar 1378 resets = <&arb AXG_ARB_TODDR_B>;
1379 amlogic,fifo- 1379 amlogic,fifo-depth = <256>;
1380 status = "dis 1380 status = "disabled";
1381 }; 1381 };
1382 1382
1383 toddr_c: audio-contro 1383 toddr_c: audio-controller@180 {
1384 compatible = 1384 compatible = "amlogic,axg-toddr";
1385 reg = <0x0 0x 1385 reg = <0x0 0x180 0x0 0x2c>;
1386 #sound-dai-ce 1386 #sound-dai-cells = <0>;
1387 sound-name-pr 1387 sound-name-prefix = "TODDR_C";
1388 interrupts = 1388 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1389 clocks = <&cl 1389 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1390 resets = <&ar 1390 resets = <&arb AXG_ARB_TODDR_C>;
1391 amlogic,fifo- 1391 amlogic,fifo-depth = <256>;
1392 status = "dis 1392 status = "disabled";
1393 }; 1393 };
1394 1394
1395 frddr_a: audio-contro 1395 frddr_a: audio-controller@1c0 {
1396 compatible = 1396 compatible = "amlogic,axg-frddr";
1397 reg = <0x0 0x 1397 reg = <0x0 0x1c0 0x0 0x2c>;
1398 #sound-dai-ce 1398 #sound-dai-cells = <0>;
1399 sound-name-pr 1399 sound-name-prefix = "FRDDR_A";
1400 interrupts = 1400 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1401 clocks = <&cl 1401 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1402 resets = <&ar 1402 resets = <&arb AXG_ARB_FRDDR_A>;
1403 amlogic,fifo- 1403 amlogic,fifo-depth = <512>;
1404 status = "dis 1404 status = "disabled";
1405 }; 1405 };
1406 1406
1407 frddr_b: audio-contro 1407 frddr_b: audio-controller@200 {
1408 compatible = 1408 compatible = "amlogic,axg-frddr";
1409 reg = <0x0 0x 1409 reg = <0x0 0x200 0x0 0x2c>;
1410 #sound-dai-ce 1410 #sound-dai-cells = <0>;
1411 sound-name-pr 1411 sound-name-prefix = "FRDDR_B";
1412 interrupts = 1412 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1413 clocks = <&cl 1413 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1414 resets = <&ar 1414 resets = <&arb AXG_ARB_FRDDR_B>;
1415 amlogic,fifo- 1415 amlogic,fifo-depth = <256>;
1416 status = "dis 1416 status = "disabled";
1417 }; 1417 };
1418 1418
1419 frddr_c: audio-contro 1419 frddr_c: audio-controller@240 {
1420 compatible = 1420 compatible = "amlogic,axg-frddr";
1421 reg = <0x0 0x 1421 reg = <0x0 0x240 0x0 0x2c>;
1422 #sound-dai-ce 1422 #sound-dai-cells = <0>;
1423 sound-name-pr 1423 sound-name-prefix = "FRDDR_C";
1424 interrupts = 1424 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1425 clocks = <&cl 1425 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1426 resets = <&ar 1426 resets = <&arb AXG_ARB_FRDDR_C>;
1427 amlogic,fifo- 1427 amlogic,fifo-depth = <256>;
1428 status = "dis 1428 status = "disabled";
1429 }; 1429 };
1430 1430
1431 arb: reset-controller 1431 arb: reset-controller@280 {
1432 compatible = 1432 compatible = "amlogic,meson-axg-audio-arb";
1433 reg = <0x0 0x 1433 reg = <0x0 0x280 0x0 0x4>;
1434 #reset-cells 1434 #reset-cells = <1>;
1435 clocks = <&cl 1435 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1436 }; 1436 };
1437 1437
1438 tdmin_a: audio-contro 1438 tdmin_a: audio-controller@300 {
1439 compatible = 1439 compatible = "amlogic,axg-tdmin";
1440 reg = <0x0 0x 1440 reg = <0x0 0x300 0x0 0x40>;
1441 sound-name-pr 1441 sound-name-prefix = "TDMIN_A";
1442 clocks = <&cl 1442 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1443 <&cl 1443 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1444 <&cl 1444 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1445 <&cl 1445 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1446 <&cl 1446 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1447 clock-names = 1447 clock-names = "pclk", "sclk", "sclk_sel",
1448 1448 "lrclk", "lrclk_sel";
1449 status = "dis 1449 status = "disabled";
1450 }; 1450 };
1451 1451
1452 tdmin_b: audio-contro 1452 tdmin_b: audio-controller@340 {
1453 compatible = 1453 compatible = "amlogic,axg-tdmin";
1454 reg = <0x0 0x 1454 reg = <0x0 0x340 0x0 0x40>;
1455 sound-name-pr 1455 sound-name-prefix = "TDMIN_B";
1456 clocks = <&cl 1456 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1457 <&cl 1457 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1458 <&cl 1458 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1459 <&cl 1459 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1460 <&cl 1460 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1461 clock-names = 1461 clock-names = "pclk", "sclk", "sclk_sel",
1462 1462 "lrclk", "lrclk_sel";
1463 status = "dis 1463 status = "disabled";
1464 }; 1464 };
1465 1465
1466 tdmin_c: audio-contro 1466 tdmin_c: audio-controller@380 {
1467 compatible = 1467 compatible = "amlogic,axg-tdmin";
1468 reg = <0x0 0x 1468 reg = <0x0 0x380 0x0 0x40>;
1469 sound-name-pr 1469 sound-name-prefix = "TDMIN_C";
1470 clocks = <&cl 1470 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1471 <&cl 1471 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1472 <&cl 1472 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1473 <&cl 1473 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1474 <&cl 1474 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1475 clock-names = 1475 clock-names = "pclk", "sclk", "sclk_sel",
1476 1476 "lrclk", "lrclk_sel";
1477 status = "dis 1477 status = "disabled";
1478 }; 1478 };
1479 1479
1480 tdmin_lb: audio-contr 1480 tdmin_lb: audio-controller@3c0 {
1481 compatible = 1481 compatible = "amlogic,axg-tdmin";
1482 reg = <0x0 0x 1482 reg = <0x0 0x3c0 0x0 0x40>;
1483 sound-name-pr 1483 sound-name-prefix = "TDMIN_LB";
1484 clocks = <&cl 1484 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1485 <&cl 1485 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1486 <&cl 1486 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1487 <&cl 1487 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1488 <&cl 1488 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1489 clock-names = 1489 clock-names = "pclk", "sclk", "sclk_sel",
1490 1490 "lrclk", "lrclk_sel";
1491 status = "dis 1491 status = "disabled";
1492 }; 1492 };
1493 1493
1494 spdifin: audio-contro 1494 spdifin: audio-controller@400 {
1495 compatible = 1495 compatible = "amlogic,axg-spdifin";
1496 reg = <0x0 0x 1496 reg = <0x0 0x400 0x0 0x30>;
1497 #sound-dai-ce 1497 #sound-dai-cells = <0>;
1498 sound-name-pr 1498 sound-name-prefix = "SPDIFIN";
1499 interrupts = 1499 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1500 clocks = <&cl 1500 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1501 <&cl 1501 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1502 clock-names = 1502 clock-names = "pclk", "refclk";
1503 status = "dis 1503 status = "disabled";
1504 }; 1504 };
1505 1505
1506 spdifout: audio-contr 1506 spdifout: audio-controller@480 {
1507 compatible = 1507 compatible = "amlogic,axg-spdifout";
1508 reg = <0x0 0x 1508 reg = <0x0 0x480 0x0 0x50>;
1509 #sound-dai-ce 1509 #sound-dai-cells = <0>;
1510 sound-name-pr 1510 sound-name-prefix = "SPDIFOUT";
1511 clocks = <&cl 1511 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1512 <&cl 1512 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1513 clock-names = 1513 clock-names = "pclk", "mclk";
1514 status = "dis 1514 status = "disabled";
1515 }; 1515 };
1516 1516
1517 tdmout_a: audio-contr 1517 tdmout_a: audio-controller@500 {
1518 compatible = 1518 compatible = "amlogic,axg-tdmout";
1519 reg = <0x0 0x 1519 reg = <0x0 0x500 0x0 0x40>;
1520 sound-name-pr 1520 sound-name-prefix = "TDMOUT_A";
1521 clocks = <&cl 1521 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1522 <&cl 1522 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1523 <&cl 1523 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1524 <&cl 1524 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1525 <&cl 1525 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1526 clock-names = 1526 clock-names = "pclk", "sclk", "sclk_sel",
1527 1527 "lrclk", "lrclk_sel";
1528 status = "dis 1528 status = "disabled";
1529 }; 1529 };
1530 1530
1531 tdmout_b: audio-contr 1531 tdmout_b: audio-controller@540 {
1532 compatible = 1532 compatible = "amlogic,axg-tdmout";
1533 reg = <0x0 0x 1533 reg = <0x0 0x540 0x0 0x40>;
1534 sound-name-pr 1534 sound-name-prefix = "TDMOUT_B";
1535 clocks = <&cl 1535 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1536 <&cl 1536 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1537 <&cl 1537 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1538 <&cl 1538 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1539 <&cl 1539 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1540 clock-names = 1540 clock-names = "pclk", "sclk", "sclk_sel",
1541 1541 "lrclk", "lrclk_sel";
1542 status = "dis 1542 status = "disabled";
1543 }; 1543 };
1544 1544
1545 tdmout_c: audio-contr 1545 tdmout_c: audio-controller@580 {
1546 compatible = 1546 compatible = "amlogic,axg-tdmout";
1547 reg = <0x0 0x 1547 reg = <0x0 0x580 0x0 0x40>;
1548 sound-name-pr 1548 sound-name-prefix = "TDMOUT_C";
1549 clocks = <&cl 1549 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1550 <&cl 1550 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1551 <&cl 1551 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1552 <&cl 1552 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1553 <&cl 1553 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1554 clock-names = 1554 clock-names = "pclk", "sclk", "sclk_sel",
1555 1555 "lrclk", "lrclk_sel";
1556 status = "dis 1556 status = "disabled";
1557 }; 1557 };
1558 }; 1558 };
1559 1559
1560 aobus: bus@ff800000 { 1560 aobus: bus@ff800000 {
1561 compatible = "simple- 1561 compatible = "simple-bus";
1562 reg = <0x0 0xff800000 1562 reg = <0x0 0xff800000 0x0 0x100000>;
1563 #address-cells = <2>; 1563 #address-cells = <2>;
1564 #size-cells = <2>; 1564 #size-cells = <2>;
1565 ranges = <0x0 0x0 0x0 1565 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1566 1566
1567 sysctrl_AO: sys-ctrl@ 1567 sysctrl_AO: sys-ctrl@0 {
1568 compatible = 1568 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1569 reg = <0x0 0x 1569 reg = <0x0 0x0 0x0 0x100>;
1570 1570
1571 clkc_AO: cloc 1571 clkc_AO: clock-controller {
1572 compa 1572 compatible = "amlogic,meson-axg-aoclkc";
1573 #cloc 1573 #clock-cells = <1>;
1574 #rese 1574 #reset-cells = <1>;
1575 clock 1575 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock 1576 clock-names = "xtal", "mpeg-clk";
1577 }; 1577 };
1578 }; 1578 };
1579 1579
1580 pinctrl_aobus: pinctr 1580 pinctrl_aobus: pinctrl@14 {
1581 compatible = 1581 compatible = "amlogic,meson-axg-aobus-pinctrl";
1582 #address-cell 1582 #address-cells = <2>;
1583 #size-cells = 1583 #size-cells = <2>;
1584 ranges; 1584 ranges;
1585 1585
1586 gpio_ao: bank 1586 gpio_ao: bank@14 {
1587 reg = 1587 reg = <0x0 0x00014 0x0 0x8>,
1588 1588 <0x0 0x0002c 0x0 0x4>,
1589 1589 <0x0 0x00024 0x0 0x8>;
1590 reg-n 1590 reg-names = "mux", "pull", "gpio";
1591 gpio- 1591 gpio-controller;
1592 #gpio 1592 #gpio-cells = <2>;
1593 gpio- 1593 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1594 }; 1594 };
1595 1595
1596 i2c_ao_sck_4_ 1596 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1597 mux { 1597 mux {
1598 1598 groups = "i2c_ao_sck_4";
1599 1599 function = "i2c_ao";
1600 1600 bias-disable;
1601 }; 1601 };
1602 }; 1602 };
1603 1603
1604 i2c_ao_sck_8_ 1604 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1605 mux { 1605 mux {
1606 1606 groups = "i2c_ao_sck_8";
1607 1607 function = "i2c_ao";
1608 1608 bias-disable;
1609 }; 1609 };
1610 }; 1610 };
1611 1611
1612 i2c_ao_sck_10 1612 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1613 mux { 1613 mux {
1614 1614 groups = "i2c_ao_sck_10";
1615 1615 function = "i2c_ao";
1616 1616 bias-disable;
1617 }; 1617 };
1618 }; 1618 };
1619 1619
1620 i2c_ao_sda_5_ 1620 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1621 mux { 1621 mux {
1622 1622 groups = "i2c_ao_sda_5";
1623 1623 function = "i2c_ao";
1624 1624 bias-disable;
1625 }; 1625 };
1626 }; 1626 };
1627 1627
1628 i2c_ao_sda_9_ 1628 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1629 mux { 1629 mux {
1630 1630 groups = "i2c_ao_sda_9";
1631 1631 function = "i2c_ao";
1632 1632 bias-disable;
1633 }; 1633 };
1634 }; 1634 };
1635 1635
1636 i2c_ao_sda_11 1636 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1637 mux { 1637 mux {
1638 1638 groups = "i2c_ao_sda_11";
1639 1639 function = "i2c_ao";
1640 1640 bias-disable;
1641 }; 1641 };
1642 }; 1642 };
1643 1643
1644 remote_input_ 1644 remote_input_ao_pins: remote_input_ao {
1645 mux { 1645 mux {
1646 1646 groups = "remote_input_ao";
1647 1647 function = "remote_input_ao";
1648 1648 bias-disable;
1649 }; 1649 };
1650 }; 1650 };
1651 1651
1652 uart_ao_a_pin 1652 uart_ao_a_pins: uart_ao_a {
1653 mux { 1653 mux {
1654 1654 groups = "uart_ao_tx_a",
1655 1655 "uart_ao_rx_a";
1656 1656 function = "uart_ao_a";
1657 1657 bias-disable;
1658 }; 1658 };
1659 }; 1659 };
1660 1660
1661 uart_ao_a_cts 1661 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1662 mux { 1662 mux {
1663 1663 groups = "uart_ao_cts_a",
1664 1664 "uart_ao_rts_a";
1665 1665 function = "uart_ao_a";
1666 1666 bias-disable;
1667 }; 1667 };
1668 }; 1668 };
1669 1669
1670 uart_ao_b_pin 1670 uart_ao_b_pins: uart_ao_b {
1671 mux { 1671 mux {
1672 1672 groups = "uart_ao_tx_b",
1673 1673 "uart_ao_rx_b";
1674 1674 function = "uart_ao_b";
1675 1675 bias-disable;
1676 }; 1676 };
1677 }; 1677 };
1678 1678
1679 uart_ao_b_cts 1679 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1680 mux { 1680 mux {
1681 1681 groups = "uart_ao_cts_b",
1682 1682 "uart_ao_rts_b";
1683 1683 function = "uart_ao_b";
1684 1684 bias-disable;
1685 }; 1685 };
1686 }; 1686 };
1687 }; 1687 };
1688 1688
1689 sec_AO: ao-secure@140 1689 sec_AO: ao-secure@140 {
1690 compatible = 1690 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1691 reg = <0x0 0x 1691 reg = <0x0 0x140 0x0 0x140>;
1692 amlogic,has-c 1692 amlogic,has-chip-id;
1693 }; 1693 };
1694 1694
1695 pwm_AO_cd: pwm@2000 { 1695 pwm_AO_cd: pwm@2000 {
1696 compatible = 1696 compatible = "amlogic,meson-axg-ao-pwm";
1697 reg = <0x0 0x 1697 reg = <0x0 0x02000 0x0 0x20>;
1698 #pwm-cells = 1698 #pwm-cells = <3>;
1699 status = "dis 1699 status = "disabled";
1700 }; 1700 };
1701 1701
1702 uart_AO: serial@3000 1702 uart_AO: serial@3000 {
1703 compatible = 1703 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1704 reg = <0x0 0x 1704 reg = <0x0 0x3000 0x0 0x18>;
1705 interrupts = 1705 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1706 clocks = <&xt 1706 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = 1707 clock-names = "xtal", "pclk", "baud";
1708 status = "dis 1708 status = "disabled";
1709 }; 1709 };
1710 1710
1711 uart_AO_B: serial@400 1711 uart_AO_B: serial@4000 {
1712 compatible = 1712 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1713 reg = <0x0 0x 1713 reg = <0x0 0x4000 0x0 0x18>;
1714 interrupts = 1714 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1715 clocks = <&xt 1715 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = 1716 clock-names = "xtal", "pclk", "baud";
1717 status = "dis 1717 status = "disabled";
1718 }; 1718 };
1719 1719
1720 i2c_AO: i2c@5000 { 1720 i2c_AO: i2c@5000 {
1721 compatible = 1721 compatible = "amlogic,meson-axg-i2c";
1722 reg = <0x0 0x 1722 reg = <0x0 0x05000 0x0 0x20>;
1723 interrupts = 1723 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1724 clocks = <&cl 1724 clocks = <&clkc CLKID_AO_I2C>;
1725 #address-cell 1725 #address-cells = <1>;
1726 #size-cells = 1726 #size-cells = <0>;
1727 status = "dis 1727 status = "disabled";
1728 }; 1728 };
1729 1729
1730 pwm_AO_ab: pwm@7000 { 1730 pwm_AO_ab: pwm@7000 {
1731 compatible = 1731 compatible = "amlogic,meson-axg-ao-pwm";
1732 reg = <0x0 0x 1732 reg = <0x0 0x07000 0x0 0x20>;
1733 #pwm-cells = 1733 #pwm-cells = <3>;
1734 status = "dis 1734 status = "disabled";
1735 }; 1735 };
1736 1736
1737 ir: ir@8000 { 1737 ir: ir@8000 {
1738 compatible = 1738 compatible = "amlogic,meson-gxbb-ir";
1739 reg = <0x0 0x 1739 reg = <0x0 0x8000 0x0 0x20>;
1740 interrupts = 1740 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1741 status = "dis 1741 status = "disabled";
1742 }; 1742 };
1743 1743
1744 saradc: adc@9000 { 1744 saradc: adc@9000 {
1745 compatible = 1745 compatible = "amlogic,meson-axg-saradc",
1746 "amlo 1746 "amlogic,meson-saradc";
1747 reg = <0x0 0x 1747 reg = <0x0 0x9000 0x0 0x38>;
1748 #io-channel-c 1748 #io-channel-cells = <1>;
1749 interrupts = 1749 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1750 clocks = <&xt 1750 clocks = <&xtal>,
1751 <&cl 1751 <&clkc_AO CLKID_AO_SAR_ADC>,
1752 <&cl 1752 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1753 <&cl 1753 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1754 clock-names = 1754 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1755 status = "dis 1755 status = "disabled";
1756 }; 1756 };
1757 }; 1757 };
1758 1758
1759 ge2d: ge2d@ff940000 { 1759 ge2d: ge2d@ff940000 {
1760 compatible = "amlogic 1760 compatible = "amlogic,axg-ge2d";
1761 reg = <0x0 0xff940000 1761 reg = <0x0 0xff940000 0x0 0x10000>;
1762 interrupts = <GIC_SPI 1762 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1763 clocks = <&clkc CLKID 1763 clocks = <&clkc CLKID_VAPB>;
1764 resets = <&reset RESE 1764 resets = <&reset RESET_GE2D>;
1765 }; 1765 };
1766 1766
1767 gic: interrupt-controller@ffc 1767 gic: interrupt-controller@ffc01000 {
1768 compatible = "arm,gic 1768 compatible = "arm,gic-400";
1769 reg = <0x0 0xffc01000 1769 reg = <0x0 0xffc01000 0 0x1000>,
1770 <0x0 0xffc02000 1770 <0x0 0xffc02000 0 0x2000>,
1771 <0x0 0xffc04000 1771 <0x0 0xffc04000 0 0x2000>,
1772 <0x0 0xffc06000 1772 <0x0 0xffc06000 0 0x2000>;
1773 interrupt-controller; 1773 interrupt-controller;
1774 interrupts = <GIC_PPI 1774 interrupts = <GIC_PPI 9
1775 (GIC_CPU_MASK 1775 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1776 #interrupt-cells = <3 1776 #interrupt-cells = <3>;
1777 #address-cells = <0>; 1777 #address-cells = <0>;
1778 }; 1778 };
1779 1779
1780 cbus: bus@ffd00000 { 1780 cbus: bus@ffd00000 {
1781 compatible = "simple- 1781 compatible = "simple-bus";
1782 reg = <0x0 0xffd00000 1782 reg = <0x0 0xffd00000 0x0 0x25000>;
1783 #address-cells = <2>; 1783 #address-cells = <2>;
1784 #size-cells = <2>; 1784 #size-cells = <2>;
1785 ranges = <0x0 0x0 0x0 1785 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1786 1786
1787 reset: reset-controll 1787 reset: reset-controller@1004 {
1788 compatible = 1788 compatible = "amlogic,meson-axg-reset";
1789 reg = <0x0 0x 1789 reg = <0x0 0x01004 0x0 0x9c>;
1790 #reset-cells 1790 #reset-cells = <1>;
1791 }; 1791 };
1792 1792
1793 gpio_intc: interrupt- 1793 gpio_intc: interrupt-controller@f080 {
1794 compatible = 1794 compatible = "amlogic,meson-axg-gpio-intc",
1795 1795 "amlogic,meson-gpio-intc";
1796 reg = <0x0 0x 1796 reg = <0x0 0xf080 0x0 0x10>;
1797 interrupt-con 1797 interrupt-controller;
1798 #interrupt-ce 1798 #interrupt-cells = <2>;
1799 amlogic,chann 1799 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1800 }; 1800 };
1801 1801
1802 watchdog@f0d0 { 1802 watchdog@f0d0 {
1803 compatible = 1803 compatible = "amlogic,meson-gxbb-wdt";
1804 reg = <0x0 0x 1804 reg = <0x0 0xf0d0 0x0 0x10>;
1805 clocks = <&xt 1805 clocks = <&xtal>;
1806 }; 1806 };
1807 1807
1808 pwm_ab: pwm@1b000 { 1808 pwm_ab: pwm@1b000 {
1809 compatible = 1809 compatible = "amlogic,meson-axg-ee-pwm";
1810 reg = <0x0 0x 1810 reg = <0x0 0x1b000 0x0 0x20>;
1811 #pwm-cells = 1811 #pwm-cells = <3>;
1812 status = "dis 1812 status = "disabled";
1813 }; 1813 };
1814 1814
1815 pwm_cd: pwm@1a000 { 1815 pwm_cd: pwm@1a000 {
1816 compatible = 1816 compatible = "amlogic,meson-axg-ee-pwm";
1817 reg = <0x0 0x 1817 reg = <0x0 0x1a000 0x0 0x20>;
1818 #pwm-cells = 1818 #pwm-cells = <3>;
1819 status = "dis 1819 status = "disabled";
1820 }; 1820 };
1821 1821
1822 spicc0: spi@13000 { 1822 spicc0: spi@13000 {
1823 compatible = 1823 compatible = "amlogic,meson-axg-spicc";
1824 reg = <0x0 0x 1824 reg = <0x0 0x13000 0x0 0x3c>;
1825 interrupts = 1825 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cl 1826 clocks = <&clkc CLKID_SPICC0>;
1827 clock-names = 1827 clock-names = "core";
1828 #address-cell 1828 #address-cells = <1>;
1829 #size-cells = 1829 #size-cells = <0>;
1830 status = "dis 1830 status = "disabled";
1831 }; 1831 };
1832 1832
1833 spicc1: spi@15000 { 1833 spicc1: spi@15000 {
1834 compatible = 1834 compatible = "amlogic,meson-axg-spicc";
1835 reg = <0x0 0x 1835 reg = <0x0 0x15000 0x0 0x3c>;
1836 interrupts = 1836 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&cl 1837 clocks = <&clkc CLKID_SPICC1>;
1838 clock-names = 1838 clock-names = "core";
1839 #address-cell 1839 #address-cells = <1>;
1840 #size-cells = 1840 #size-cells = <0>;
1841 status = "dis 1841 status = "disabled";
1842 }; 1842 };
1843 1843
1844 clk_msr: clock-measur 1844 clk_msr: clock-measure@18000 {
1845 compatible = 1845 compatible = "amlogic,meson-axg-clk-measure";
1846 reg = <0x0 0x 1846 reg = <0x0 0x18000 0x0 0x10>;
1847 }; 1847 };
1848 1848
1849 i2c3: i2c@1c000 { 1849 i2c3: i2c@1c000 {
1850 compatible = 1850 compatible = "amlogic,meson-axg-i2c";
1851 reg = <0x0 0x 1851 reg = <0x0 0x1c000 0x0 0x20>;
1852 interrupts = 1852 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1853 clocks = <&cl 1853 clocks = <&clkc CLKID_I2C>;
1854 #address-cell 1854 #address-cells = <1>;
1855 #size-cells = 1855 #size-cells = <0>;
1856 status = "dis 1856 status = "disabled";
1857 }; 1857 };
1858 1858
1859 i2c2: i2c@1d000 { 1859 i2c2: i2c@1d000 {
1860 compatible = 1860 compatible = "amlogic,meson-axg-i2c";
1861 reg = <0x0 0x 1861 reg = <0x0 0x1d000 0x0 0x20>;
1862 interrupts = 1862 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1863 clocks = <&cl 1863 clocks = <&clkc CLKID_I2C>;
1864 #address-cell 1864 #address-cells = <1>;
1865 #size-cells = 1865 #size-cells = <0>;
1866 status = "dis 1866 status = "disabled";
1867 }; 1867 };
1868 1868
1869 i2c1: i2c@1e000 { 1869 i2c1: i2c@1e000 {
1870 compatible = 1870 compatible = "amlogic,meson-axg-i2c";
1871 reg = <0x0 0x 1871 reg = <0x0 0x1e000 0x0 0x20>;
1872 interrupts = 1872 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1873 clocks = <&cl 1873 clocks = <&clkc CLKID_I2C>;
1874 #address-cell 1874 #address-cells = <1>;
1875 #size-cells = 1875 #size-cells = <0>;
1876 status = "dis 1876 status = "disabled";
1877 }; 1877 };
1878 1878
1879 i2c0: i2c@1f000 { 1879 i2c0: i2c@1f000 {
1880 compatible = 1880 compatible = "amlogic,meson-axg-i2c";
1881 reg = <0x0 0x 1881 reg = <0x0 0x1f000 0x0 0x20>;
1882 interrupts = 1882 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1883 clocks = <&cl 1883 clocks = <&clkc CLKID_I2C>;
1884 #address-cell 1884 #address-cells = <1>;
1885 #size-cells = 1885 #size-cells = <0>;
1886 status = "dis 1886 status = "disabled";
1887 }; 1887 };
1888 1888
1889 uart_B: serial@23000 1889 uart_B: serial@23000 {
1890 compatible = 1890 compatible = "amlogic,meson-gx-uart";
1891 reg = <0x0 0x 1891 reg = <0x0 0x23000 0x0 0x18>;
1892 interrupts = 1892 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1893 status = "dis 1893 status = "disabled";
1894 clocks = <&xt 1894 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1895 clock-names = 1895 clock-names = "xtal", "pclk", "baud";
1896 }; 1896 };
1897 1897
1898 uart_A: serial@24000 1898 uart_A: serial@24000 {
1899 compatible = 1899 compatible = "amlogic,meson-gx-uart";
1900 reg = <0x0 0x 1900 reg = <0x0 0x24000 0x0 0x18>;
1901 interrupts = 1901 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1902 status = "dis 1902 status = "disabled";
1903 clocks = <&xt 1903 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1904 clock-names = 1904 clock-names = "xtal", "pclk", "baud";
1905 fifo-size = < 1905 fifo-size = <128>;
1906 }; 1906 };
1907 }; 1907 };
1908 1908
1909 apb: bus@ffe00000 { 1909 apb: bus@ffe00000 {
1910 compatible = "simple- 1910 compatible = "simple-bus";
1911 reg = <0x0 0xffe00000 1911 reg = <0x0 0xffe00000 0x0 0x200000>;
1912 #address-cells = <2>; 1912 #address-cells = <2>;
1913 #size-cells = <2>; 1913 #size-cells = <2>;
1914 ranges = <0x0 0x0 0x0 1914 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1915 1915
1916 sd_emmc_b: mmc@5000 { 1916 sd_emmc_b: mmc@5000 {
1917 compatible = 1917 compatible = "amlogic,meson-axg-mmc";
1918 reg = <0x0 0x 1918 reg = <0x0 0x5000 0x0 0x800>;
1919 interrupts = 1919 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1920 status = "dis 1920 status = "disabled";
1921 clocks = <&cl 1921 clocks = <&clkc CLKID_SD_EMMC_B>,
1922 <&clk 1922 <&clkc CLKID_SD_EMMC_B_CLK0>,
1923 <&clk 1923 <&clkc CLKID_FCLK_DIV2>;
1924 clock-names = 1924 clock-names = "core", "clkin0", "clkin1";
1925 resets = <&re 1925 resets = <&reset RESET_SD_EMMC_B>;
1926 }; 1926 };
1927 1927
1928 sd_emmc_c: mmc@7000 { 1928 sd_emmc_c: mmc@7000 {
1929 compatible = 1929 compatible = "amlogic,meson-axg-mmc";
1930 reg = <0x0 0x 1930 reg = <0x0 0x7000 0x0 0x800>;
1931 interrupts = 1931 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1932 status = "dis 1932 status = "disabled";
1933 clocks = <&cl 1933 clocks = <&clkc CLKID_SD_EMMC_C>,
1934 <&clk 1934 <&clkc CLKID_SD_EMMC_C_CLK0>,
1935 <&clk 1935 <&clkc CLKID_FCLK_DIV2>;
1936 clock-names = 1936 clock-names = "core", "clkin0", "clkin1";
1937 resets = <&re 1937 resets = <&reset RESET_SD_EMMC_C>;
1938 }; 1938 };
1939 1939
1940 nfc: nand-controller@ 1940 nfc: nand-controller@7800 {
1941 compatible = 1941 compatible = "amlogic,meson-axg-nfc";
1942 reg = <0x0 0x 1942 reg = <0x0 0x7800 0x0 0x100>,
1943 <0x0 0x 1943 <0x0 0x7000 0x0 0x800>;
1944 reg-names = " 1944 reg-names = "nfc", "emmc";
1945 pinctrl-0 = < 1945 pinctrl-0 = <&nand_all_pins>;
1946 pinctrl-names 1946 pinctrl-names = "default";
1947 #address-cell 1947 #address-cells = <1>;
1948 #size-cells = 1948 #size-cells = <0>;
1949 interrupts = 1949 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
1950 clocks = <&cl 1950 clocks = <&clkc CLKID_SD_EMMC_C>,
1951 <&cl 1951 <&clkc CLKID_FCLK_DIV2>;
1952 clock-names = 1952 clock-names = "core", "device";
1953 }; 1953 };
1954 1954
1955 usb2_phy1: phy@9020 { 1955 usb2_phy1: phy@9020 {
1956 compatible = 1956 compatible = "amlogic,meson-gxl-usb2-phy";
1957 #phy-cells = 1957 #phy-cells = <0>;
1958 reg = <0x0 0x 1958 reg = <0x0 0x9020 0x0 0x20>;
1959 clocks = <&cl 1959 clocks = <&clkc CLKID_USB>;
1960 clock-names = 1960 clock-names = "phy";
1961 resets = <&re 1961 resets = <&reset RESET_USB_OTG>;
1962 reset-names = 1962 reset-names = "phy";
1963 }; 1963 };
1964 }; 1964 };
1965 1965
1966 sram: sram@fffc0000 { 1966 sram: sram@fffc0000 {
1967 compatible = "mmio-sr 1967 compatible = "mmio-sram";
1968 reg = <0x0 0xfffc0000 1968 reg = <0x0 0xfffc0000 0x0 0x20000>;
1969 #address-cells = <1>; 1969 #address-cells = <1>;
1970 #size-cells = <1>; 1970 #size-cells = <1>;
1971 ranges = <0 0x0 0xfff 1971 ranges = <0 0x0 0xfffc0000 0x20000>;
1972 1972
1973 cpu_scp_lpri: scp-sra 1973 cpu_scp_lpri: scp-sram@13000 {
1974 compatible = 1974 compatible = "amlogic,meson-axg-scp-shmem";
1975 reg = <0x1300 1975 reg = <0x13000 0x400>;
1976 }; 1976 };
1977 1977
1978 cpu_scp_hpri: scp-sra 1978 cpu_scp_hpri: scp-sram@13400 {
1979 compatible = 1979 compatible = "amlogic,meson-axg-scp-shmem";
1980 reg = <0x1340 1980 reg = <0x13400 0x400>;
1981 }; 1981 };
1982 }; 1982 };
1983 }; 1983 };
1984 1984
1985 timer { 1985 timer {
1986 compatible = "arm,armv8-timer 1986 compatible = "arm,armv8-timer";
1987 interrupts = <GIC_PPI 13 1987 interrupts = <GIC_PPI 13
1988 (GIC_CPU_MASK_RAW(0xf 1988 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1989 <GIC_PPI 14 1989 <GIC_PPI 14
1990 (GIC_CPU_MASK_RAW(0xf 1990 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1991 <GIC_PPI 11 1991 <GIC_PPI 11
1992 (GIC_CPU_MASK_RAW(0xf 1992 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 10 1993 <GIC_PPI 10
1994 (GIC_CPU_MASK_RAW(0xf 1994 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1995 }; 1995 };
1996 1996
1997 xtal: xtal-clk { 1997 xtal: xtal-clk {
1998 compatible = "fixed-clock"; 1998 compatible = "fixed-clock";
1999 clock-frequency = <24000000>; 1999 clock-frequency = <24000000>;
2000 clock-output-names = "xtal"; 2000 clock-output-names = "xtal";
2001 #clock-cells = <0>; 2001 #clock-cells = <0>;
2002 }; 2002 };
2003 }; 2003 };
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