1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy.h> 6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h> 8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h> 9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/aml <<
13 #include <dt-bindings/reset/amlogic,meson-g12a 12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { 20 aliases {
22 mmc0 = &sd_emmc_b; /* SD card 21 mmc0 = &sd_emmc_b; /* SD card */
23 mmc1 = &sd_emmc_c; /* eMMC */ 22 mmc1 = &sd_emmc_c; /* eMMC */
24 mmc2 = &sd_emmc_a; /* SDIO */ 23 mmc2 = &sd_emmc_a; /* SDIO */
25 }; 24 };
26 25
27 chosen { 26 chosen {
28 #address-cells = <2>; 27 #address-cells = <2>;
29 #size-cells = <2>; 28 #size-cells = <2>;
30 ranges; 29 ranges;
31 30
32 simplefb_cvbs: framebuffer-cvb 31 simplefb_cvbs: framebuffer-cvbs {
33 compatible = "amlogic, 32 compatible = "amlogic,simple-framebuffer",
34 "simple-f 33 "simple-framebuffer";
35 amlogic,pipeline = "vp 34 amlogic,pipeline = "vpu-cvbs";
36 clocks = <&clkc CLKID_ 35 clocks = <&clkc CLKID_HDMI>,
37 <&clkc CLKID_ 36 <&clkc CLKID_HTX_PCLK>,
38 <&clkc CLKID_ 37 <&clkc CLKID_VPU_INTR>;
39 status = "disabled"; 38 status = "disabled";
40 }; 39 };
41 40
42 simplefb_hdmi: framebuffer-hdm 41 simplefb_hdmi: framebuffer-hdmi {
43 compatible = "amlogic, 42 compatible = "amlogic,simple-framebuffer",
44 "simple-fr 43 "simple-framebuffer";
45 amlogic,pipeline = "vp 44 amlogic,pipeline = "vpu-hdmi";
46 clocks = <&clkc CLKID_ 45 clocks = <&clkc CLKID_HDMI>,
47 <&clkc CLKID_ 46 <&clkc CLKID_HTX_PCLK>,
48 <&clkc CLKID_ 47 <&clkc CLKID_VPU_INTR>;
49 status = "disabled"; 48 status = "disabled";
50 }; 49 };
51 }; 50 };
52 51
53 efuse: efuse { 52 efuse: efuse {
54 compatible = "amlogic,meson-gx 53 compatible = "amlogic,meson-gxbb-efuse";
55 clocks = <&clkc CLKID_EFUSE>; 54 clocks = <&clkc CLKID_EFUSE>;
56 #address-cells = <1>; 55 #address-cells = <1>;
57 #size-cells = <1>; 56 #size-cells = <1>;
58 read-only; 57 read-only;
59 secure-monitor = <&sm>; 58 secure-monitor = <&sm>;
60 }; 59 };
61 60
62 gpu_opp_table: opp-table-gpu { 61 gpu_opp_table: opp-table-gpu {
63 compatible = "operating-points 62 compatible = "operating-points-v2";
64 63
65 opp-124999998 { 64 opp-124999998 {
66 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <124999998>;
67 opp-microvolt = <80000 66 opp-microvolt = <800000>;
68 }; 67 };
69 opp-249999996 { 68 opp-249999996 {
70 opp-hz = /bits/ 64 <24 69 opp-hz = /bits/ 64 <249999996>;
71 opp-microvolt = <80000 70 opp-microvolt = <800000>;
72 }; 71 };
73 opp-285714281 { 72 opp-285714281 {
74 opp-hz = /bits/ 64 <28 73 opp-hz = /bits/ 64 <285714281>;
75 opp-microvolt = <80000 74 opp-microvolt = <800000>;
76 }; 75 };
77 opp-399999994 { 76 opp-399999994 {
78 opp-hz = /bits/ 64 <39 77 opp-hz = /bits/ 64 <399999994>;
79 opp-microvolt = <80000 78 opp-microvolt = <800000>;
80 }; 79 };
81 opp-499999992 { 80 opp-499999992 {
82 opp-hz = /bits/ 64 <49 81 opp-hz = /bits/ 64 <499999992>;
83 opp-microvolt = <80000 82 opp-microvolt = <800000>;
84 }; 83 };
85 opp-666666656 { 84 opp-666666656 {
86 opp-hz = /bits/ 64 <66 85 opp-hz = /bits/ 64 <666666656>;
87 opp-microvolt = <80000 86 opp-microvolt = <800000>;
88 }; 87 };
89 opp-799999987 { 88 opp-799999987 {
90 opp-hz = /bits/ 64 <79 89 opp-hz = /bits/ 64 <799999987>;
91 opp-microvolt = <80000 90 opp-microvolt = <800000>;
92 }; 91 };
93 }; 92 };
94 93
95 psci { 94 psci {
96 compatible = "arm,psci-1.0"; 95 compatible = "arm,psci-1.0";
97 method = "smc"; 96 method = "smc";
98 }; 97 };
99 98
100 reserved-memory { 99 reserved-memory {
101 #address-cells = <2>; 100 #address-cells = <2>;
102 #size-cells = <2>; 101 #size-cells = <2>;
103 ranges; 102 ranges;
104 103
105 /* 3 MiB reserved for ARM Trus 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
106 secmon_reserved: secmon@500000 105 secmon_reserved: secmon@5000000 {
107 reg = <0x0 0x05000000 106 reg = <0x0 0x05000000 0x0 0x300000>;
108 no-map; 107 no-map;
109 }; 108 };
110 109
111 /* 32 MiB reserved for ARM Tru 110 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
112 secmon_reserved_bl32: secmon@5 111 secmon_reserved_bl32: secmon@5300000 {
113 reg = <0x0 0x05300000 112 reg = <0x0 0x05300000 0x0 0x2000000>;
114 no-map; 113 no-map;
115 }; 114 };
116 115
117 linux,cma { 116 linux,cma {
118 compatible = "shared-d 117 compatible = "shared-dma-pool";
119 reusable; 118 reusable;
120 size = <0x0 0x10000000 119 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400 120 alignment = <0x0 0x400000>;
122 linux,cma-default; 121 linux,cma-default;
123 }; 122 };
124 }; 123 };
125 124
126 sm: secure-monitor { 125 sm: secure-monitor {
127 compatible = "amlogic,meson-gx 126 compatible = "amlogic,meson-gxbb-sm";
128 }; 127 };
129 128
130 soc { 129 soc {
131 compatible = "simple-bus"; 130 compatible = "simple-bus";
132 #address-cells = <2>; 131 #address-cells = <2>;
133 #size-cells = <2>; 132 #size-cells = <2>;
134 ranges; 133 ranges;
135 134
136 pcie: pcie@fc000000 { 135 pcie: pcie@fc000000 {
137 compatible = "amlogic, 136 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
138 reg = <0x0 0xfc000000 137 reg = <0x0 0xfc000000 0x0 0x400000>,
139 <0x0 0xff648000 138 <0x0 0xff648000 0x0 0x2000>,
140 <0x0 0xfc400000 139 <0x0 0xfc400000 0x0 0x200000>;
141 reg-names = "elbi", "c 140 reg-names = "elbi", "cfg", "config";
142 interrupts = <GIC_SPI 141 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
143 #interrupt-cells = <1> 142 #interrupt-cells = <1>;
144 interrupt-map-mask = < 143 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff> 145 bus-range = <0x0 0xff>;
147 #address-cells = <3>; 146 #address-cells = <3>;
148 #size-cells = <2>; 147 #size-cells = <2>;
149 device_type = "pci"; 148 device_type = "pci";
150 ranges = <0x81000000 0 149 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
151 <0x82000000 0 150 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
152 151
153 clocks = <&clkc CLKID_ 152 clocks = <&clkc CLKID_PCIE_PHY
154 &clkc CLKID_ 153 &clkc CLKID_PCIE_COMB
155 &clkc CLKID_ 154 &clkc CLKID_PCIE_PLL>;
156 clock-names = "general 155 clock-names = "general",
157 "pclk", 156 "pclk",
158 "port"; 157 "port";
159 resets = <&reset RESET 158 resets = <&reset RESET_PCIE_CTRL_A>,
160 <&reset RESET 159 <&reset RESET_PCIE_APB>;
161 reset-names = "port", 160 reset-names = "port",
162 "apb"; 161 "apb";
163 num-lanes = <1>; 162 num-lanes = <1>;
164 phys = <&usb3_pcie_phy 163 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
165 phy-names = "pcie"; 164 phy-names = "pcie";
166 status = "disabled"; 165 status = "disabled";
167 }; 166 };
168 167
>> 168 thermal-zones {
>> 169 cpu_thermal: cpu-thermal {
>> 170 polling-delay = <1000>;
>> 171 polling-delay-passive = <100>;
>> 172 thermal-sensors = <&cpu_temp>;
>> 173
>> 174 trips {
>> 175 cpu_passive: cpu-passive {
>> 176 temperature = <85000>; /* millicelsius */
>> 177 hysteresis = <2000>; /* millicelsius */
>> 178 type = "passive";
>> 179 };
>> 180
>> 181 cpu_hot: cpu-hot {
>> 182 temperature = <95000>; /* millicelsius */
>> 183 hysteresis = <2000>; /* millicelsius */
>> 184 type = "hot";
>> 185 };
>> 186
>> 187 cpu_critical: cpu-critical {
>> 188 temperature = <110000>; /* millicelsius */
>> 189 hysteresis = <2000>; /* millicelsius */
>> 190 type = "critical";
>> 191 };
>> 192 };
>> 193 };
>> 194
>> 195 ddr_thermal: ddr-thermal {
>> 196 polling-delay = <1000>;
>> 197 polling-delay-passive = <100>;
>> 198 thermal-sensors = <&ddr_temp>;
>> 199
>> 200 trips {
>> 201 ddr_passive: ddr-passive {
>> 202 temperature = <85000>; /* millicelsius */
>> 203 hysteresis = <2000>; /* millicelsius */
>> 204 type = "passive";
>> 205 };
>> 206
>> 207 ddr_critical: ddr-critical {
>> 208 temperature = <110000>; /* millicelsius */
>> 209 hysteresis = <2000>; /* millicelsius */
>> 210 type = "critical";
>> 211 };
>> 212 };
>> 213
>> 214 cooling-maps {
>> 215 map {
>> 216 trip = <&ddr_passive>;
>> 217 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 218 };
>> 219 };
>> 220 };
>> 221 };
>> 222
169 ethmac: ethernet@ff3f0000 { 223 ethmac: ethernet@ff3f0000 {
170 compatible = "amlogic, 224 compatible = "amlogic,meson-g12a-dwmac",
171 "snps,dwm 225 "snps,dwmac-3.70a",
172 "snps,dwm 226 "snps,dwmac";
173 reg = <0x0 0xff3f0000 227 reg = <0x0 0xff3f0000 0x0 0x10000>,
174 <0x0 0xff634540 228 <0x0 0xff634540 0x0 0x8>;
175 interrupts = <GIC_SPI 229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "mac 230 interrupt-names = "macirq";
177 clocks = <&clkc CLKID_ 231 clocks = <&clkc CLKID_ETH>,
178 <&clkc CLKID_ 232 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_ 233 <&clkc CLKID_MPLL2>,
180 <&clkc CLKID_ 234 <&clkc CLKID_FCLK_DIV2>;
181 clock-names = "stmmace 235 clock-names = "stmmaceth", "clkin0", "clkin1",
182 "timing- 236 "timing-adjustment";
183 rx-fifo-depth = <4096> 237 rx-fifo-depth = <4096>;
184 tx-fifo-depth = <2048> 238 tx-fifo-depth = <2048>;
185 status = "disabled"; 239 status = "disabled";
186 240
187 mdio0: mdio { 241 mdio0: mdio {
188 #address-cells 242 #address-cells = <1>;
189 #size-cells = 243 #size-cells = <0>;
190 compatible = " 244 compatible = "snps,dwmac-mdio";
191 }; 245 };
192 }; 246 };
193 247
194 apb: bus@ff600000 { 248 apb: bus@ff600000 {
195 compatible = "simple-b 249 compatible = "simple-bus";
196 reg = <0x0 0xff600000 250 reg = <0x0 0xff600000 0x0 0x200000>;
197 #address-cells = <2>; 251 #address-cells = <2>;
198 #size-cells = <2>; 252 #size-cells = <2>;
199 ranges = <0x0 0x0 0x0 253 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
200 254
201 hdmi_tx: hdmi-tx@0 { 255 hdmi_tx: hdmi-tx@0 {
202 compatible = " 256 compatible = "amlogic,meson-g12a-dw-hdmi";
203 reg = <0x0 0x0 257 reg = <0x0 0x0 0x0 0x10000>;
204 interrupts = < 258 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
205 resets = <&res 259 resets = <&reset RESET_HDMITX_CAPB3>,
206 <&res 260 <&reset RESET_HDMITX_PHY>,
207 <&res 261 <&reset RESET_HDMITX>;
208 reset-names = 262 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
209 clocks = <&clk 263 clocks = <&clkc CLKID_HDMI>,
210 <&clk 264 <&clkc CLKID_HTX_PCLK>,
211 <&clk 265 <&clkc CLKID_VPU_INTR>;
212 clock-names = 266 clock-names = "isfr", "iahb", "venci";
213 #address-cells 267 #address-cells = <1>;
214 #size-cells = 268 #size-cells = <0>;
215 #sound-dai-cel 269 #sound-dai-cells = <0>;
216 status = "disa 270 status = "disabled";
217 271
218 assigned-clock <<
219 <<
220 assigned-clock <<
221 assigned-clock <<
222 <<
223 /* VPU VENC In 272 /* VPU VENC Input */
224 hdmi_tx_venc_p 273 hdmi_tx_venc_port: port@0 {
225 reg = 274 reg = <0>;
226 275
227 hdmi_t 276 hdmi_tx_in: endpoint {
228 277 remote-endpoint = <&hdmi_tx_out>;
229 }; 278 };
230 }; 279 };
231 280
232 /* TMDS Output 281 /* TMDS Output */
233 hdmi_tx_tmds_p 282 hdmi_tx_tmds_port: port@1 {
234 reg = 283 reg = <1>;
235 }; 284 };
236 }; 285 };
237 286
238 apb_efuse: bus@30000 { 287 apb_efuse: bus@30000 {
239 compatible = " 288 compatible = "simple-bus";
240 reg = <0x0 0x3 289 reg = <0x0 0x30000 0x0 0x2000>;
241 #address-cells 290 #address-cells = <2>;
242 #size-cells = 291 #size-cells = <2>;
243 ranges = <0x0 292 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
244 293
245 hwrng: rng@218 294 hwrng: rng@218 {
246 compat 295 compatible = "amlogic,meson-rng";
247 reg = 296 reg = <0x0 0x218 0x0 0x4>;
248 clocks 297 clocks = <&clkc CLKID_RNG0>;
249 clock- 298 clock-names = "core";
250 }; 299 };
251 }; 300 };
252 301
253 acodec: audio-controll 302 acodec: audio-controller@32000 {
254 compatible = " 303 compatible = "amlogic,t9015";
255 reg = <0x0 0x3 304 reg = <0x0 0x32000 0x0 0x14>;
256 #sound-dai-cel 305 #sound-dai-cells = <0>;
257 sound-name-pre 306 sound-name-prefix = "ACODEC";
258 clocks = <&clk 307 clocks = <&clkc CLKID_AUDIO_CODEC>;
259 clock-names = 308 clock-names = "pclk";
260 resets = <&res 309 resets = <&reset RESET_AUDIO_CODEC>;
261 status = "disa 310 status = "disabled";
262 }; 311 };
263 312
264 periphs: bus@34400 { 313 periphs: bus@34400 {
265 compatible = " 314 compatible = "simple-bus";
266 reg = <0x0 0x3 315 reg = <0x0 0x34400 0x0 0x400>;
267 #address-cells 316 #address-cells = <2>;
268 #size-cells = 317 #size-cells = <2>;
269 ranges = <0x0 318 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
270 319
271 periphs_pinctr 320 periphs_pinctrl: pinctrl@40 {
272 compat 321 compatible = "amlogic,meson-g12a-periphs-pinctrl";
273 #addre 322 #address-cells = <2>;
274 #size- 323 #size-cells = <2>;
275 ranges 324 ranges;
276 325
277 gpio: 326 gpio: bank@40 {
278 327 reg = <0x0 0x40 0x0 0x4c>,
279 328 <0x0 0xe8 0x0 0x18>,
280 329 <0x0 0x120 0x0 0x18>,
281 330 <0x0 0x2c0 0x0 0x40>,
282 331 <0x0 0x340 0x0 0x1c>;
283 332 reg-names = "gpio",
284 333 "pull",
285 334 "pull-enable",
286 335 "mux",
287 336 "ds";
288 337 gpio-controller;
289 338 #gpio-cells = <2>;
290 339 gpio-ranges = <&periphs_pinctrl 0 0 86>;
291 }; 340 };
292 341
293 cec_ao 342 cec_ao_a_h_pins: cec_ao_a_h {
294 343 mux {
295 344 groups = "cec_ao_a_h";
296 345 function = "cec_ao_a_h";
297 346 bias-disable;
298 347 };
299 }; 348 };
300 349
301 cec_ao 350 cec_ao_b_h_pins: cec_ao_b_h {
302 351 mux {
303 352 groups = "cec_ao_b_h";
304 353 function = "cec_ao_b_h";
305 354 bias-disable;
306 355 };
307 }; 356 };
308 357
309 emmc_c 358 emmc_ctrl_pins: emmc-ctrl {
310 359 mux-0 {
311 360 groups = "emmc_cmd";
312 361 function = "emmc";
313 362 bias-pull-up;
314 363 drive-strength-microamp = <4000>;
315 364 };
316 365
317 366 mux-1 {
318 367 groups = "emmc_clk";
319 368 function = "emmc";
320 369 bias-disable;
321 370 drive-strength-microamp = <4000>;
322 371 };
323 }; 372 };
324 373
325 emmc_d 374 emmc_data_4b_pins: emmc-data-4b {
326 375 mux-0 {
327 376 groups = "emmc_nand_d0",
328 377 "emmc_nand_d1",
329 378 "emmc_nand_d2",
330 379 "emmc_nand_d3";
331 380 function = "emmc";
332 381 bias-pull-up;
333 382 drive-strength-microamp = <4000>;
334 383 };
335 }; 384 };
336 385
337 emmc_d 386 emmc_data_8b_pins: emmc-data-8b {
338 387 mux-0 {
339 388 groups = "emmc_nand_d0",
340 389 "emmc_nand_d1",
341 390 "emmc_nand_d2",
342 391 "emmc_nand_d3",
343 392 "emmc_nand_d4",
344 393 "emmc_nand_d5",
345 394 "emmc_nand_d6",
346 395 "emmc_nand_d7";
347 396 function = "emmc";
348 397 bias-pull-up;
349 398 drive-strength-microamp = <4000>;
350 399 };
351 }; 400 };
352 401
353 emmc_d 402 emmc_ds_pins: emmc-ds {
354 403 mux {
355 404 groups = "emmc_nand_ds";
356 405 function = "emmc";
357 406 bias-pull-down;
358 407 drive-strength-microamp = <4000>;
359 408 };
360 }; 409 };
361 410
362 emmc_c 411 emmc_clk_gate_pins: emmc_clk_gate {
363 412 mux {
364 413 groups = "BOOT_8";
365 414 function = "gpio_periphs";
366 415 bias-pull-down;
367 416 drive-strength-microamp = <4000>;
368 417 };
369 }; 418 };
370 419
371 hdmitx 420 hdmitx_ddc_pins: hdmitx_ddc {
372 421 mux {
373 422 groups = "hdmitx_sda",
374 423 "hdmitx_sck";
375 424 function = "hdmitx";
376 425 bias-disable;
377 426 drive-strength-microamp = <4000>;
378 427 };
379 }; 428 };
380 429
381 hdmitx 430 hdmitx_hpd_pins: hdmitx_hpd {
382 431 mux {
383 432 groups = "hdmitx_hpd_in";
384 433 function = "hdmitx";
385 434 bias-disable;
386 435 };
387 }; 436 };
388 437
389 438
390 i2c0_s 439 i2c0_sda_c_pins: i2c0-sda-c {
391 440 mux {
392 441 groups = "i2c0_sda_c";
393 442 function = "i2c0";
394 443 bias-disable;
395 444 drive-strength-microamp = <3000>;
396 445
397 446 };
398 }; 447 };
399 448
400 i2c0_s 449 i2c0_sck_c_pins: i2c0-sck-c {
401 450 mux {
402 451 groups = "i2c0_sck_c";
403 452 function = "i2c0";
404 453 bias-disable;
405 454 drive-strength-microamp = <3000>;
406 455 };
407 }; 456 };
408 457
409 i2c0_s 458 i2c0_sda_z0_pins: i2c0-sda-z0 {
410 459 mux {
411 460 groups = "i2c0_sda_z0";
412 461 function = "i2c0";
413 462 bias-disable;
414 463 drive-strength-microamp = <3000>;
415 464 };
416 }; 465 };
417 466
418 i2c0_s 467 i2c0_sck_z1_pins: i2c0-sck-z1 {
419 468 mux {
420 469 groups = "i2c0_sck_z1";
421 470 function = "i2c0";
422 471 bias-disable;
423 472 drive-strength-microamp = <3000>;
424 473 };
425 }; 474 };
426 475
427 i2c0_s 476 i2c0_sda_z7_pins: i2c0-sda-z7 {
428 477 mux {
429 478 groups = "i2c0_sda_z7";
430 479 function = "i2c0";
431 480 bias-disable;
432 481 drive-strength-microamp = <3000>;
433 482 };
434 }; 483 };
435 484
436 i2c0_s 485 i2c0_sda_z8_pins: i2c0-sda-z8 {
437 486 mux {
438 487 groups = "i2c0_sda_z8";
439 488 function = "i2c0";
440 489 bias-disable;
441 490 drive-strength-microamp = <3000>;
442 491 };
443 }; 492 };
444 493
445 i2c1_s 494 i2c1_sda_x_pins: i2c1-sda-x {
446 495 mux {
447 496 groups = "i2c1_sda_x";
448 497 function = "i2c1";
449 498 bias-disable;
450 499 drive-strength-microamp = <3000>;
451 500 };
452 }; 501 };
453 502
454 i2c1_s 503 i2c1_sck_x_pins: i2c1-sck-x {
455 504 mux {
456 505 groups = "i2c1_sck_x";
457 506 function = "i2c1";
458 507 bias-disable;
459 508 drive-strength-microamp = <3000>;
460 509 };
461 }; 510 };
462 511
463 i2c1_s 512 i2c1_sda_h2_pins: i2c1-sda-h2 {
464 513 mux {
465 514 groups = "i2c1_sda_h2";
466 515 function = "i2c1";
467 516 bias-disable;
468 517 drive-strength-microamp = <3000>;
469 518 };
470 }; 519 };
471 520
472 i2c1_s 521 i2c1_sck_h3_pins: i2c1-sck-h3 {
473 522 mux {
474 523 groups = "i2c1_sck_h3";
475 524 function = "i2c1";
476 525 bias-disable;
477 526 drive-strength-microamp = <3000>;
478 527 };
479 }; 528 };
480 529
481 i2c1_s 530 i2c1_sda_h6_pins: i2c1-sda-h6 {
482 531 mux {
483 532 groups = "i2c1_sda_h6";
484 533 function = "i2c1";
485 534 bias-disable;
486 535 drive-strength-microamp = <3000>;
487 536 };
488 }; 537 };
489 538
490 i2c1_s 539 i2c1_sck_h7_pins: i2c1-sck-h7 {
491 540 mux {
492 541 groups = "i2c1_sck_h7";
493 542 function = "i2c1";
494 543 bias-disable;
495 544 drive-strength-microamp = <3000>;
496 545 };
497 }; 546 };
498 547
499 i2c2_s 548 i2c2_sda_x_pins: i2c2-sda-x {
500 549 mux {
501 550 groups = "i2c2_sda_x";
502 551 function = "i2c2";
503 552 bias-disable;
504 553 drive-strength-microamp = <3000>;
505 554 };
506 }; 555 };
507 556
508 i2c2_s 557 i2c2_sck_x_pins: i2c2-sck-x {
509 558 mux {
510 559 groups = "i2c2_sck_x";
511 560 function = "i2c2";
512 561 bias-disable;
513 562 drive-strength-microamp = <3000>;
514 563 };
515 }; 564 };
516 565
517 i2c2_s 566 i2c2_sda_z_pins: i2c2-sda-z {
518 567 mux {
519 568 groups = "i2c2_sda_z";
520 569 function = "i2c2";
521 570 bias-disable;
522 571 drive-strength-microamp = <3000>;
523 572 };
524 }; 573 };
525 574
526 i2c2_s 575 i2c2_sck_z_pins: i2c2-sck-z {
527 576 mux {
528 577 groups = "i2c2_sck_z";
529 578 function = "i2c2";
530 579 bias-disable;
531 580 drive-strength-microamp = <3000>;
532 581 };
533 }; 582 };
534 583
535 i2c3_s 584 i2c3_sda_h_pins: i2c3-sda-h {
536 585 mux {
537 586 groups = "i2c3_sda_h";
538 587 function = "i2c3";
539 588 bias-disable;
540 589 drive-strength-microamp = <3000>;
541 590 };
542 }; 591 };
543 592
544 i2c3_s 593 i2c3_sck_h_pins: i2c3-sck-h {
545 594 mux {
546 595 groups = "i2c3_sck_h";
547 596 function = "i2c3";
548 597 bias-disable;
549 598 drive-strength-microamp = <3000>;
550 599 };
551 }; 600 };
552 601
553 i2c3_s 602 i2c3_sda_a_pins: i2c3-sda-a {
554 603 mux {
555 604 groups = "i2c3_sda_a";
556 605 function = "i2c3";
557 606 bias-disable;
558 607 drive-strength-microamp = <3000>;
559 608 };
560 }; 609 };
561 610
562 i2c3_s 611 i2c3_sck_a_pins: i2c3-sck-a {
563 612 mux {
564 613 groups = "i2c3_sck_a";
565 614 function = "i2c3";
566 615 bias-disable;
567 616 drive-strength-microamp = <3000>;
568 617 };
569 }; 618 };
570 619
571 mclk0_ 620 mclk0_a_pins: mclk0-a {
572 621 mux {
573 622 groups = "mclk0_a";
574 623 function = "mclk0";
575 624 bias-disable;
576 625 drive-strength-microamp = <3000>;
577 626 };
578 }; 627 };
579 628
580 mclk1_ 629 mclk1_a_pins: mclk1-a {
581 630 mux {
582 631 groups = "mclk1_a";
583 632 function = "mclk1";
584 633 bias-disable;
585 634 drive-strength-microamp = <3000>;
586 635 };
587 }; 636 };
588 637
589 mclk1_ 638 mclk1_x_pins: mclk1-x {
590 639 mux {
591 640 groups = "mclk1_x";
592 641 function = "mclk1";
593 642 bias-disable;
594 643 drive-strength-microamp = <3000>;
595 644 };
596 }; 645 };
597 646
598 mclk1_ 647 mclk1_z_pins: mclk1-z {
599 648 mux {
600 649 groups = "mclk1_z";
601 650 function = "mclk1";
602 651 bias-disable;
603 652 drive-strength-microamp = <3000>;
604 653 };
605 }; 654 };
606 655
607 nor_pi 656 nor_pins: nor {
608 657 mux {
609 658 groups = "nor_d",
610 659 "nor_q",
611 660 "nor_c",
612 661 "nor_cs";
613 662 function = "nor";
614 663 bias-disable;
615 664 };
616 }; 665 };
617 666
618 pdm_di 667 pdm_din0_a_pins: pdm-din0-a {
619 668 mux {
620 669 groups = "pdm_din0_a";
621 670 function = "pdm";
622 671 bias-disable;
623 672 };
624 }; 673 };
625 674
626 pdm_di 675 pdm_din0_c_pins: pdm-din0-c {
627 676 mux {
628 677 groups = "pdm_din0_c";
629 678 function = "pdm";
630 679 bias-disable;
631 680 };
632 }; 681 };
633 682
634 pdm_di 683 pdm_din0_x_pins: pdm-din0-x {
635 684 mux {
636 685 groups = "pdm_din0_x";
637 686 function = "pdm";
638 687 bias-disable;
639 688 };
640 }; 689 };
641 690
642 pdm_di 691 pdm_din0_z_pins: pdm-din0-z {
643 692 mux {
644 693 groups = "pdm_din0_z";
645 694 function = "pdm";
646 695 bias-disable;
647 696 };
648 }; 697 };
649 698
650 pdm_di 699 pdm_din1_a_pins: pdm-din1-a {
651 700 mux {
652 701 groups = "pdm_din1_a";
653 702 function = "pdm";
654 703 bias-disable;
655 704 };
656 }; 705 };
657 706
658 pdm_di 707 pdm_din1_c_pins: pdm-din1-c {
659 708 mux {
660 709 groups = "pdm_din1_c";
661 710 function = "pdm";
662 711 bias-disable;
663 712 };
664 }; 713 };
665 714
666 pdm_di 715 pdm_din1_x_pins: pdm-din1-x {
667 716 mux {
668 717 groups = "pdm_din1_x";
669 718 function = "pdm";
670 719 bias-disable;
671 720 };
672 }; 721 };
673 722
674 pdm_di 723 pdm_din1_z_pins: pdm-din1-z {
675 724 mux {
676 725 groups = "pdm_din1_z";
677 726 function = "pdm";
678 727 bias-disable;
679 728 };
680 }; 729 };
681 730
682 pdm_di 731 pdm_din2_a_pins: pdm-din2-a {
683 732 mux {
684 733 groups = "pdm_din2_a";
685 734 function = "pdm";
686 735 bias-disable;
687 736 };
688 }; 737 };
689 738
690 pdm_di 739 pdm_din2_c_pins: pdm-din2-c {
691 740 mux {
692 741 groups = "pdm_din2_c";
693 742 function = "pdm";
694 743 bias-disable;
695 744 };
696 }; 745 };
697 746
698 pdm_di 747 pdm_din2_x_pins: pdm-din2-x {
699 748 mux {
700 749 groups = "pdm_din2_x";
701 750 function = "pdm";
702 751 bias-disable;
703 752 };
704 }; 753 };
705 754
706 pdm_di 755 pdm_din2_z_pins: pdm-din2-z {
707 756 mux {
708 757 groups = "pdm_din2_z";
709 758 function = "pdm";
710 759 bias-disable;
711 760 };
712 }; 761 };
713 762
714 pdm_di 763 pdm_din3_a_pins: pdm-din3-a {
715 764 mux {
716 765 groups = "pdm_din3_a";
717 766 function = "pdm";
718 767 bias-disable;
719 768 };
720 }; 769 };
721 770
722 pdm_di 771 pdm_din3_c_pins: pdm-din3-c {
723 772 mux {
724 773 groups = "pdm_din3_c";
725 774 function = "pdm";
726 775 bias-disable;
727 776 };
728 }; 777 };
729 778
730 pdm_di 779 pdm_din3_x_pins: pdm-din3-x {
731 780 mux {
732 781 groups = "pdm_din3_x";
733 782 function = "pdm";
734 783 bias-disable;
735 784 };
736 }; 785 };
737 786
738 pdm_di 787 pdm_din3_z_pins: pdm-din3-z {
739 788 mux {
740 789 groups = "pdm_din3_z";
741 790 function = "pdm";
742 791 bias-disable;
743 792 };
744 }; 793 };
745 794
746 pdm_dc 795 pdm_dclk_a_pins: pdm-dclk-a {
747 796 mux {
748 797 groups = "pdm_dclk_a";
749 798 function = "pdm";
750 799 bias-disable;
751 800 drive-strength-microamp = <500>;
752 801 };
753 }; 802 };
754 803
755 pdm_dc 804 pdm_dclk_c_pins: pdm-dclk-c {
756 805 mux {
757 806 groups = "pdm_dclk_c";
758 807 function = "pdm";
759 808 bias-disable;
760 809 drive-strength-microamp = <500>;
761 810 };
762 }; 811 };
763 812
764 pdm_dc 813 pdm_dclk_x_pins: pdm-dclk-x {
765 814 mux {
766 815 groups = "pdm_dclk_x";
767 816 function = "pdm";
768 817 bias-disable;
769 818 drive-strength-microamp = <500>;
770 819 };
771 }; 820 };
772 821
773 pdm_dc 822 pdm_dclk_z_pins: pdm-dclk-z {
774 823 mux {
775 824 groups = "pdm_dclk_z";
776 825 function = "pdm";
777 826 bias-disable;
778 827 drive-strength-microamp = <500>;
779 828 };
780 }; 829 };
781 830
782 pwm_a_ 831 pwm_a_pins: pwm-a {
783 832 mux {
784 833 groups = "pwm_a";
785 834 function = "pwm_a";
786 835 bias-disable;
787 836 };
788 }; 837 };
789 838
790 pwm_b_ 839 pwm_b_x7_pins: pwm-b-x7 {
791 840 mux {
792 841 groups = "pwm_b_x7";
793 842 function = "pwm_b";
794 843 bias-disable;
795 844 };
796 }; 845 };
797 846
798 pwm_b_ 847 pwm_b_x19_pins: pwm-b-x19 {
799 848 mux {
800 849 groups = "pwm_b_x19";
801 850 function = "pwm_b";
802 851 bias-disable;
803 852 };
804 }; 853 };
805 854
806 pwm_c_ 855 pwm_c_c_pins: pwm-c-c {
807 856 mux {
808 857 groups = "pwm_c_c";
809 858 function = "pwm_c";
810 859 bias-disable;
811 860 };
812 }; 861 };
813 862
814 pwm_c_ 863 pwm_c_x5_pins: pwm-c-x5 {
815 864 mux {
816 865 groups = "pwm_c_x5";
817 866 function = "pwm_c";
818 867 bias-disable;
819 868 };
820 }; 869 };
821 870
822 pwm_c_ 871 pwm_c_x8_pins: pwm-c-x8 {
823 872 mux {
824 873 groups = "pwm_c_x8";
825 874 function = "pwm_c";
826 875 bias-disable;
827 876 };
828 }; 877 };
829 878
830 pwm_d_ 879 pwm_d_x3_pins: pwm-d-x3 {
831 880 mux {
832 881 groups = "pwm_d_x3";
833 882 function = "pwm_d";
834 883 bias-disable;
835 884 };
836 }; 885 };
837 886
838 pwm_d_ 887 pwm_d_x6_pins: pwm-d-x6 {
839 888 mux {
840 889 groups = "pwm_d_x6";
841 890 function = "pwm_d";
842 891 bias-disable;
843 892 };
844 }; 893 };
845 894
846 pwm_e_ 895 pwm_e_pins: pwm-e {
847 896 mux {
848 897 groups = "pwm_e";
849 898 function = "pwm_e";
850 899 bias-disable;
851 900 };
852 }; 901 };
853 902
854 pwm_f_ <<
855 <<
856 <<
857 <<
858 <<
859 <<
860 }; <<
861 <<
862 pwm_f_ <<
863 <<
864 <<
865 <<
866 <<
867 <<
868 }; <<
869 <<
870 pwm_f_ 903 pwm_f_x_pins: pwm-f-x {
871 904 mux {
872 905 groups = "pwm_f_x";
873 906 function = "pwm_f";
874 907 bias-disable;
875 908 };
876 }; 909 };
877 910
878 pwm_f_ 911 pwm_f_h_pins: pwm-f-h {
879 912 mux {
880 913 groups = "pwm_f_h";
881 914 function = "pwm_f";
882 915 bias-disable;
883 916 };
884 }; 917 };
885 918
886 sdcard 919 sdcard_c_pins: sdcard_c {
887 920 mux-0 {
888 921 groups = "sdcard_d0_c",
889 922 "sdcard_d1_c",
890 923 "sdcard_d2_c",
891 924 "sdcard_d3_c",
892 925 "sdcard_cmd_c";
893 926 function = "sdcard";
894 927 bias-pull-up;
895 928 drive-strength-microamp = <4000>;
896 929 };
897 930
898 931 mux-1 {
899 932 groups = "sdcard_clk_c";
900 933 function = "sdcard";
901 934 bias-disable;
902 935 drive-strength-microamp = <4000>;
903 936 };
904 }; 937 };
905 938
906 sdcard 939 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
907 940 mux {
908 941 groups = "GPIOC_4";
909 942 function = "gpio_periphs";
910 943 bias-pull-down;
911 944 drive-strength-microamp = <4000>;
912 945 };
913 }; 946 };
914 947
915 sdcard 948 sdcard_z_pins: sdcard_z {
916 949 mux-0 {
917 950 groups = "sdcard_d0_z",
918 951 "sdcard_d1_z",
919 952 "sdcard_d2_z",
920 953 "sdcard_d3_z",
921 954 "sdcard_cmd_z";
922 955 function = "sdcard";
923 956 bias-pull-up;
924 957 drive-strength-microamp = <4000>;
925 958 };
926 959
927 960 mux-1 {
928 961 groups = "sdcard_clk_z";
929 962 function = "sdcard";
930 963 bias-disable;
931 964 drive-strength-microamp = <4000>;
932 965 };
933 }; 966 };
934 967
935 sdcard 968 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
936 969 mux {
937 970 groups = "GPIOZ_6";
938 971 function = "gpio_periphs";
939 972 bias-pull-down;
940 973 drive-strength-microamp = <4000>;
941 974 };
942 }; 975 };
943 976
944 sdio_p 977 sdio_pins: sdio {
945 978 mux {
946 979 groups = "sdio_d0",
947 980 "sdio_d1",
948 981 "sdio_d2",
949 982 "sdio_d3",
950 983 "sdio_clk",
951 984 "sdio_cmd";
952 985 function = "sdio";
953 986 bias-disable;
954 987 drive-strength-microamp = <4000>;
955 988 };
956 }; 989 };
957 990
958 sdio_c 991 sdio_clk_gate_pins: sdio_clk_gate {
959 992 mux {
960 993 groups = "GPIOX_4";
961 994 function = "gpio_periphs";
962 995 bias-pull-down;
963 996 drive-strength-microamp = <4000>;
964 997 };
965 }; 998 };
966 999
967 spdif_ 1000 spdif_in_a10_pins: spdif-in-a10 {
968 1001 mux {
969 1002 groups = "spdif_in_a10";
970 1003 function = "spdif_in";
971 1004 bias-disable;
972 1005 };
973 }; 1006 };
974 1007
975 spdif_ 1008 spdif_in_a12_pins: spdif-in-a12 {
976 1009 mux {
977 1010 groups = "spdif_in_a12";
978 1011 function = "spdif_in";
979 1012 bias-disable;
980 1013 };
981 }; 1014 };
982 1015
983 spdif_ 1016 spdif_in_h_pins: spdif-in-h {
984 1017 mux {
985 1018 groups = "spdif_in_h";
986 1019 function = "spdif_in";
987 1020 bias-disable;
988 1021 };
989 }; 1022 };
990 1023
991 spdif_ 1024 spdif_out_h_pins: spdif-out-h {
992 1025 mux {
993 1026 groups = "spdif_out_h";
994 1027 function = "spdif_out";
995 !! 1028 drive-strength-microamp = <500>;
996 1029 bias-disable;
997 1030 };
998 }; 1031 };
999 1032
1000 spdif 1033 spdif_out_a11_pins: spdif-out-a11 {
1001 1034 mux {
1002 1035 groups = "spdif_out_a11";
1003 1036 function = "spdif_out";
1004 !! 1037 drive-strength-microamp = <500>;
1005 1038 bias-disable;
1006 1039 };
1007 }; 1040 };
1008 1041
1009 spdif 1042 spdif_out_a13_pins: spdif-out-a13 {
1010 1043 mux {
1011 1044 groups = "spdif_out_a13";
1012 1045 function = "spdif_out";
1013 !! 1046 drive-strength-microamp = <500>;
1014 1047 bias-disable;
1015 1048 };
1016 }; 1049 };
1017 1050
1018 spicc 1051 spicc0_x_pins: spicc0-x {
1019 1052 mux {
1020 1053 groups = "spi0_mosi_x",
1021 1054 "spi0_miso_x",
1022 1055 "spi0_clk_x";
1023 1056 function = "spi0";
1024 1057 drive-strength-microamp = <4000>;
1025 1058 bias-disable;
1026 1059 };
1027 }; 1060 };
1028 1061
1029 spicc 1062 spicc0_ss0_x_pins: spicc0-ss0-x {
1030 1063 mux {
1031 1064 groups = "spi0_ss0_x";
1032 1065 function = "spi0";
1033 1066 drive-strength-microamp = <4000>;
1034 1067 bias-disable;
1035 1068 };
1036 }; 1069 };
1037 1070
1038 spicc 1071 spicc0_c_pins: spicc0-c {
1039 1072 mux {
1040 1073 groups = "spi0_mosi_c",
1041 1074 "spi0_miso_c",
1042 1075 "spi0_ss0_c",
1043 1076 "spi0_clk_c";
1044 1077 function = "spi0";
1045 1078 drive-strength-microamp = <4000>;
1046 1079 bias-disable;
1047 1080 };
1048 }; 1081 };
1049 1082
1050 spicc 1083 spicc1_pins: spicc1 {
1051 1084 mux {
1052 1085 groups = "spi1_mosi",
1053 1086 "spi1_miso",
1054 1087 "spi1_clk";
1055 1088 function = "spi1";
1056 1089 drive-strength-microamp = <4000>;
1057 1090 };
1058 }; 1091 };
1059 1092
1060 spicc 1093 spicc1_ss0_pins: spicc1-ss0 {
1061 1094 mux {
1062 1095 groups = "spi1_ss0";
1063 1096 function = "spi1";
1064 1097 drive-strength-microamp = <4000>;
1065 1098 bias-disable;
1066 1099 };
1067 }; 1100 };
1068 1101
1069 tdm_a 1102 tdm_a_din0_pins: tdm-a-din0 {
1070 1103 mux {
1071 1104 groups = "tdm_a_din0";
1072 1105 function = "tdm_a";
1073 1106 bias-disable;
1074 1107 };
1075 }; 1108 };
1076 1109
1077 1110
1078 tdm_a 1111 tdm_a_din1_pins: tdm-a-din1 {
1079 1112 mux {
1080 1113 groups = "tdm_a_din1";
1081 1114 function = "tdm_a";
1082 1115 bias-disable;
1083 1116 };
1084 }; 1117 };
1085 1118
1086 tdm_a 1119 tdm_a_dout0_pins: tdm-a-dout0 {
1087 1120 mux {
1088 1121 groups = "tdm_a_dout0";
1089 1122 function = "tdm_a";
1090 1123 bias-disable;
1091 1124 drive-strength-microamp = <3000>;
1092 1125 };
1093 }; 1126 };
1094 1127
1095 tdm_a 1128 tdm_a_dout1_pins: tdm-a-dout1 {
1096 1129 mux {
1097 1130 groups = "tdm_a_dout1";
1098 1131 function = "tdm_a";
1099 1132 bias-disable;
1100 1133 drive-strength-microamp = <3000>;
1101 1134 };
1102 }; 1135 };
1103 1136
1104 tdm_a 1137 tdm_a_fs_pins: tdm-a-fs {
1105 1138 mux {
1106 1139 groups = "tdm_a_fs";
1107 1140 function = "tdm_a";
1108 1141 bias-disable;
1109 1142 drive-strength-microamp = <3000>;
1110 1143 };
1111 }; 1144 };
1112 1145
1113 tdm_a 1146 tdm_a_sclk_pins: tdm-a-sclk {
1114 1147 mux {
1115 1148 groups = "tdm_a_sclk";
1116 1149 function = "tdm_a";
1117 1150 bias-disable;
1118 1151 drive-strength-microamp = <3000>;
1119 1152 };
1120 }; 1153 };
1121 1154
1122 tdm_a 1155 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1123 1156 mux {
1124 1157 groups = "tdm_a_slv_fs";
1125 1158 function = "tdm_a";
1126 1159 bias-disable;
1127 1160 };
1128 }; 1161 };
1129 1162
1130 1163
1131 tdm_a 1164 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1132 1165 mux {
1133 1166 groups = "tdm_a_slv_sclk";
1134 1167 function = "tdm_a";
1135 1168 bias-disable;
1136 1169 };
1137 }; 1170 };
1138 1171
1139 tdm_b 1172 tdm_b_din0_pins: tdm-b-din0 {
1140 1173 mux {
1141 1174 groups = "tdm_b_din0";
1142 1175 function = "tdm_b";
1143 1176 bias-disable;
1144 1177 };
1145 }; 1178 };
1146 1179
1147 tdm_b 1180 tdm_b_din1_pins: tdm-b-din1 {
1148 1181 mux {
1149 1182 groups = "tdm_b_din1";
1150 1183 function = "tdm_b";
1151 1184 bias-disable;
1152 1185 };
1153 }; 1186 };
1154 1187
1155 tdm_b 1188 tdm_b_din2_pins: tdm-b-din2 {
1156 1189 mux {
1157 1190 groups = "tdm_b_din2";
1158 1191 function = "tdm_b";
1159 1192 bias-disable;
1160 1193 };
1161 }; 1194 };
1162 1195
1163 tdm_b 1196 tdm_b_din3_a_pins: tdm-b-din3-a {
1164 1197 mux {
1165 1198 groups = "tdm_b_din3_a";
1166 1199 function = "tdm_b";
1167 1200 bias-disable;
1168 1201 };
1169 }; 1202 };
1170 1203
1171 tdm_b 1204 tdm_b_din3_h_pins: tdm-b-din3-h {
1172 1205 mux {
1173 1206 groups = "tdm_b_din3_h";
1174 1207 function = "tdm_b";
1175 1208 bias-disable;
1176 1209 };
1177 }; 1210 };
1178 1211
1179 tdm_b 1212 tdm_b_dout0_pins: tdm-b-dout0 {
1180 1213 mux {
1181 1214 groups = "tdm_b_dout0";
1182 1215 function = "tdm_b";
1183 1216 bias-disable;
1184 1217 drive-strength-microamp = <3000>;
1185 1218 };
1186 }; 1219 };
1187 1220
1188 tdm_b 1221 tdm_b_dout1_pins: tdm-b-dout1 {
1189 1222 mux {
1190 1223 groups = "tdm_b_dout1";
1191 1224 function = "tdm_b";
1192 1225 bias-disable;
1193 1226 drive-strength-microamp = <3000>;
1194 1227 };
1195 }; 1228 };
1196 1229
1197 tdm_b 1230 tdm_b_dout2_pins: tdm-b-dout2 {
1198 1231 mux {
1199 1232 groups = "tdm_b_dout2";
1200 1233 function = "tdm_b";
1201 1234 bias-disable;
1202 1235 drive-strength-microamp = <3000>;
1203 1236 };
1204 }; 1237 };
1205 1238
1206 tdm_b 1239 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1207 1240 mux {
1208 1241 groups = "tdm_b_dout3_a";
1209 1242 function = "tdm_b";
1210 1243 bias-disable;
1211 1244 drive-strength-microamp = <3000>;
1212 1245 };
1213 }; 1246 };
1214 1247
1215 tdm_b 1248 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1216 1249 mux {
1217 1250 groups = "tdm_b_dout3_h";
1218 1251 function = "tdm_b";
1219 1252 bias-disable;
1220 1253 drive-strength-microamp = <3000>;
1221 1254 };
1222 }; 1255 };
1223 1256
1224 tdm_b 1257 tdm_b_fs_pins: tdm-b-fs {
1225 1258 mux {
1226 1259 groups = "tdm_b_fs";
1227 1260 function = "tdm_b";
1228 1261 bias-disable;
1229 1262 drive-strength-microamp = <3000>;
1230 1263 };
1231 }; 1264 };
1232 1265
1233 tdm_b 1266 tdm_b_sclk_pins: tdm-b-sclk {
1234 1267 mux {
1235 1268 groups = "tdm_b_sclk";
1236 1269 function = "tdm_b";
1237 1270 bias-disable;
1238 1271 drive-strength-microamp = <3000>;
1239 1272 };
1240 }; 1273 };
1241 1274
1242 tdm_b 1275 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1243 1276 mux {
1244 1277 groups = "tdm_b_slv_fs";
1245 1278 function = "tdm_b";
1246 1279 bias-disable;
1247 1280 };
1248 }; 1281 };
1249 1282
1250 tdm_b 1283 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1251 1284 mux {
1252 1285 groups = "tdm_b_slv_sclk";
1253 1286 function = "tdm_b";
1254 1287 bias-disable;
1255 1288 };
1256 }; 1289 };
1257 1290
1258 tdm_c 1291 tdm_c_din0_a_pins: tdm-c-din0-a {
1259 1292 mux {
1260 1293 groups = "tdm_c_din0_a";
1261 1294 function = "tdm_c";
1262 1295 bias-disable;
1263 1296 };
1264 }; 1297 };
1265 1298
1266 tdm_c 1299 tdm_c_din0_z_pins: tdm-c-din0-z {
1267 1300 mux {
1268 1301 groups = "tdm_c_din0_z";
1269 1302 function = "tdm_c";
1270 1303 bias-disable;
1271 1304 };
1272 }; 1305 };
1273 1306
1274 tdm_c 1307 tdm_c_din1_a_pins: tdm-c-din1-a {
1275 1308 mux {
1276 1309 groups = "tdm_c_din1_a";
1277 1310 function = "tdm_c";
1278 1311 bias-disable;
1279 1312 };
1280 }; 1313 };
1281 1314
1282 tdm_c 1315 tdm_c_din1_z_pins: tdm-c-din1-z {
1283 1316 mux {
1284 1317 groups = "tdm_c_din1_z";
1285 1318 function = "tdm_c";
1286 1319 bias-disable;
1287 1320 };
1288 }; 1321 };
1289 1322
1290 tdm_c 1323 tdm_c_din2_a_pins: tdm-c-din2-a {
1291 1324 mux {
1292 1325 groups = "tdm_c_din2_a";
1293 1326 function = "tdm_c";
1294 1327 bias-disable;
1295 1328 };
1296 }; 1329 };
1297 1330
1298 eth_l 1331 eth_leds_pins: eth-leds {
1299 1332 mux {
1300 1333 groups = "eth_link_led",
1301 1334 "eth_act_led";
1302 1335 function = "eth";
1303 1336 bias-disable;
1304 1337 };
1305 }; 1338 };
1306 1339
1307 eth_p 1340 eth_pins: eth {
1308 1341 mux {
1309 1342 groups = "eth_mdio",
1310 1343 "eth_mdc",
1311 1344 "eth_rgmii_rx_clk",
1312 1345 "eth_rx_dv",
1313 1346 "eth_rxd0",
1314 1347 "eth_rxd1",
1315 1348 "eth_txen",
1316 1349 "eth_txd0",
1317 1350 "eth_txd1";
1318 1351 function = "eth";
1319 1352 drive-strength-microamp = <4000>;
1320 1353 bias-disable;
1321 1354 };
1322 }; 1355 };
1323 1356
1324 eth_r 1357 eth_rgmii_pins: eth-rgmii {
1325 1358 mux {
1326 1359 groups = "eth_rxd2_rgmii",
1327 1360 "eth_rxd3_rgmii",
1328 1361 "eth_rgmii_tx_clk",
1329 1362 "eth_txd2_rgmii",
1330 1363 "eth_txd3_rgmii";
1331 1364 function = "eth";
1332 1365 drive-strength-microamp = <4000>;
1333 1366 bias-disable;
1334 1367 };
1335 }; 1368 };
1336 1369
1337 tdm_c 1370 tdm_c_din2_z_pins: tdm-c-din2-z {
1338 1371 mux {
1339 1372 groups = "tdm_c_din2_z";
1340 1373 function = "tdm_c";
1341 1374 bias-disable;
1342 1375 };
1343 }; 1376 };
1344 1377
1345 tdm_c 1378 tdm_c_din3_a_pins: tdm-c-din3-a {
1346 1379 mux {
1347 1380 groups = "tdm_c_din3_a";
1348 1381 function = "tdm_c";
1349 1382 bias-disable;
1350 1383 };
1351 }; 1384 };
1352 1385
1353 tdm_c 1386 tdm_c_din3_z_pins: tdm-c-din3-z {
1354 1387 mux {
1355 1388 groups = "tdm_c_din3_z";
1356 1389 function = "tdm_c";
1357 1390 bias-disable;
1358 1391 };
1359 }; 1392 };
1360 1393
1361 tdm_c 1394 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1362 1395 mux {
1363 1396 groups = "tdm_c_dout0_a";
1364 1397 function = "tdm_c";
1365 1398 bias-disable;
1366 1399 drive-strength-microamp = <3000>;
1367 1400 };
1368 }; 1401 };
1369 1402
1370 tdm_c 1403 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1371 1404 mux {
1372 1405 groups = "tdm_c_dout0_z";
1373 1406 function = "tdm_c";
1374 1407 bias-disable;
1375 1408 drive-strength-microamp = <3000>;
1376 1409 };
1377 }; 1410 };
1378 1411
1379 tdm_c 1412 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1380 1413 mux {
1381 1414 groups = "tdm_c_dout1_a";
1382 1415 function = "tdm_c";
1383 1416 bias-disable;
1384 1417 drive-strength-microamp = <3000>;
1385 1418 };
1386 }; 1419 };
1387 1420
1388 tdm_c 1421 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1389 1422 mux {
1390 1423 groups = "tdm_c_dout1_z";
1391 1424 function = "tdm_c";
1392 1425 bias-disable;
1393 1426 drive-strength-microamp = <3000>;
1394 1427 };
1395 }; 1428 };
1396 1429
1397 tdm_c 1430 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1398 1431 mux {
1399 1432 groups = "tdm_c_dout2_a";
1400 1433 function = "tdm_c";
1401 1434 bias-disable;
1402 1435 drive-strength-microamp = <3000>;
1403 1436 };
1404 }; 1437 };
1405 1438
1406 tdm_c 1439 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1407 1440 mux {
1408 1441 groups = "tdm_c_dout2_z";
1409 1442 function = "tdm_c";
1410 1443 bias-disable;
1411 1444 drive-strength-microamp = <3000>;
1412 1445 };
1413 }; 1446 };
1414 1447
1415 tdm_c 1448 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1416 1449 mux {
1417 1450 groups = "tdm_c_dout3_a";
1418 1451 function = "tdm_c";
1419 1452 bias-disable;
1420 1453 drive-strength-microamp = <3000>;
1421 1454 };
1422 }; 1455 };
1423 1456
1424 tdm_c 1457 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1425 1458 mux {
1426 1459 groups = "tdm_c_dout3_z";
1427 1460 function = "tdm_c";
1428 1461 bias-disable;
1429 1462 drive-strength-microamp = <3000>;
1430 1463 };
1431 }; 1464 };
1432 1465
1433 tdm_c 1466 tdm_c_fs_a_pins: tdm-c-fs-a {
1434 1467 mux {
1435 1468 groups = "tdm_c_fs_a";
1436 1469 function = "tdm_c";
1437 1470 bias-disable;
1438 1471 drive-strength-microamp = <3000>;
1439 1472 };
1440 }; 1473 };
1441 1474
1442 tdm_c 1475 tdm_c_fs_z_pins: tdm-c-fs-z {
1443 1476 mux {
1444 1477 groups = "tdm_c_fs_z";
1445 1478 function = "tdm_c";
1446 1479 bias-disable;
1447 1480 drive-strength-microamp = <3000>;
1448 1481 };
1449 }; 1482 };
1450 1483
1451 tdm_c 1484 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1452 1485 mux {
1453 1486 groups = "tdm_c_sclk_a";
1454 1487 function = "tdm_c";
1455 1488 bias-disable;
1456 1489 drive-strength-microamp = <3000>;
1457 1490 };
1458 }; 1491 };
1459 1492
1460 tdm_c 1493 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1461 1494 mux {
1462 1495 groups = "tdm_c_sclk_z";
1463 1496 function = "tdm_c";
1464 1497 bias-disable;
1465 1498 drive-strength-microamp = <3000>;
1466 1499 };
1467 }; 1500 };
1468 1501
1469 tdm_c 1502 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1470 1503 mux {
1471 1504 groups = "tdm_c_slv_fs_a";
1472 1505 function = "tdm_c";
1473 1506 bias-disable;
1474 1507 };
1475 }; 1508 };
1476 1509
1477 tdm_c 1510 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1478 1511 mux {
1479 1512 groups = "tdm_c_slv_fs_z";
1480 1513 function = "tdm_c";
1481 1514 bias-disable;
1482 1515 };
1483 }; 1516 };
1484 1517
1485 tdm_c 1518 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1486 1519 mux {
1487 1520 groups = "tdm_c_slv_sclk_a";
1488 1521 function = "tdm_c";
1489 1522 bias-disable;
1490 1523 };
1491 }; 1524 };
1492 1525
1493 tdm_c 1526 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1494 1527 mux {
1495 1528 groups = "tdm_c_slv_sclk_z";
1496 1529 function = "tdm_c";
1497 1530 bias-disable;
1498 1531 };
1499 }; 1532 };
1500 1533
1501 uart_ 1534 uart_a_pins: uart-a {
1502 1535 mux {
1503 1536 groups = "uart_a_tx",
1504 1537 "uart_a_rx";
1505 1538 function = "uart_a";
1506 1539 bias-disable;
1507 1540 };
1508 }; 1541 };
1509 1542
1510 uart_ 1543 uart_a_cts_rts_pins: uart-a-cts-rts {
1511 1544 mux {
1512 1545 groups = "uart_a_cts",
1513 1546 "uart_a_rts";
1514 1547 function = "uart_a";
1515 1548 bias-disable;
1516 1549 };
1517 }; 1550 };
1518 1551
1519 uart_ 1552 uart_b_pins: uart-b {
1520 1553 mux {
1521 1554 groups = "uart_b_tx",
1522 1555 "uart_b_rx";
1523 1556 function = "uart_b";
1524 1557 bias-disable;
1525 1558 };
1526 }; 1559 };
1527 1560
1528 uart_ 1561 uart_c_pins: uart-c {
1529 1562 mux {
1530 1563 groups = "uart_c_tx",
1531 1564 "uart_c_rx";
1532 1565 function = "uart_c";
1533 1566 bias-disable;
1534 1567 };
1535 }; 1568 };
1536 1569
1537 uart_ 1570 uart_c_cts_rts_pins: uart-c-cts-rts {
1538 1571 mux {
1539 1572 groups = "uart_c_cts",
1540 1573 "uart_c_rts";
1541 1574 function = "uart_c";
1542 1575 bias-disable;
1543 1576 };
1544 }; 1577 };
1545 }; 1578 };
1546 }; 1579 };
1547 1580
1548 cpu_temp: temperature 1581 cpu_temp: temperature-sensor@34800 {
1549 compatible = 1582 compatible = "amlogic,g12a-cpu-thermal",
1550 1583 "amlogic,g12a-thermal";
1551 reg = <0x0 0x 1584 reg = <0x0 0x34800 0x0 0x50>;
1552 interrupts = 1585 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1553 clocks = <&cl 1586 clocks = <&clkc CLKID_TS>;
1554 #thermal-sens 1587 #thermal-sensor-cells = <0>;
1555 amlogic,ao-se 1588 amlogic,ao-secure = <&sec_AO>;
1556 }; 1589 };
1557 1590
1558 ddr_temp: temperature 1591 ddr_temp: temperature-sensor@34c00 {
1559 compatible = 1592 compatible = "amlogic,g12a-ddr-thermal",
1560 1593 "amlogic,g12a-thermal";
1561 reg = <0x0 0x 1594 reg = <0x0 0x34c00 0x0 0x50>;
1562 interrupts = 1595 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1563 clocks = <&cl 1596 clocks = <&clkc CLKID_TS>;
1564 #thermal-sens 1597 #thermal-sensor-cells = <0>;
1565 amlogic,ao-se 1598 amlogic,ao-secure = <&sec_AO>;
1566 }; 1599 };
1567 1600
1568 usb2_phy0: phy@36000 1601 usb2_phy0: phy@36000 {
1569 compatible = 1602 compatible = "amlogic,g12a-usb2-phy";
1570 reg = <0x0 0x 1603 reg = <0x0 0x36000 0x0 0x2000>;
1571 clocks = <&xt 1604 clocks = <&xtal>;
1572 clock-names = 1605 clock-names = "xtal";
1573 resets = <&re 1606 resets = <&reset RESET_USB_PHY20>;
1574 reset-names = 1607 reset-names = "phy";
1575 #phy-cells = 1608 #phy-cells = <0>;
1576 }; 1609 };
1577 1610
1578 dmc: bus@38000 { 1611 dmc: bus@38000 {
1579 compatible = 1612 compatible = "simple-bus";
1580 #address-cell 1613 #address-cells = <2>;
1581 #size-cells = 1614 #size-cells = <2>;
1582 ranges = <0x0 1615 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>;
1583 1616
1584 canvas: video 1617 canvas: video-lut@48 {
1585 compa 1618 compatible = "amlogic,canvas";
1586 reg = 1619 reg = <0x0 0x48 0x0 0x14>;
1587 }; 1620 };
1588 <<
1589 pmu: pmu@80 { <<
1590 reg = <<
1591 <<
1592 inter <<
1593 }; <<
1594 }; 1621 };
1595 1622
1596 usb2_phy1: phy@3a000 1623 usb2_phy1: phy@3a000 {
1597 compatible = 1624 compatible = "amlogic,g12a-usb2-phy";
1598 reg = <0x0 0x 1625 reg = <0x0 0x3a000 0x0 0x2000>;
1599 clocks = <&xt 1626 clocks = <&xtal>;
1600 clock-names = 1627 clock-names = "xtal";
1601 resets = <&re 1628 resets = <&reset RESET_USB_PHY21>;
1602 reset-names = 1629 reset-names = "phy";
1603 #phy-cells = 1630 #phy-cells = <0>;
1604 }; 1631 };
1605 1632
1606 hiu: bus@3c000 { 1633 hiu: bus@3c000 {
1607 compatible = 1634 compatible = "simple-bus";
1608 reg = <0x0 0x 1635 reg = <0x0 0x3c000 0x0 0x1400>;
1609 #address-cell 1636 #address-cells = <2>;
1610 #size-cells = 1637 #size-cells = <2>;
1611 ranges = <0x0 1638 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1612 1639
1613 hhi: system-c 1640 hhi: system-controller@0 {
1614 compa 1641 compatible = "amlogic,meson-gx-hhi-sysctrl",
1615 1642 "simple-mfd", "syscon";
1616 reg = 1643 reg = <0 0 0 0x400>;
1617 1644
1618 clkc: 1645 clkc: clock-controller {
1619 1646 compatible = "amlogic,g12a-clkc";
1620 1647 #clock-cells = <1>;
1621 1648 clocks = <&xtal>;
1622 1649 clock-names = "xtal";
1623 }; 1650 };
1624 1651
1625 pwrc: 1652 pwrc: power-controller {
1626 1653 compatible = "amlogic,meson-g12a-pwrc";
1627 1654 #power-domain-cells = <1>;
1628 1655 amlogic,ao-sysctrl = <&rti>;
1629 1656 resets = <&reset RESET_VIU>,
1630 1657 <&reset RESET_VENC>,
1631 1658 <&reset RESET_VCBUS>,
1632 1659 <&reset RESET_BT656>,
1633 1660 <&reset RESET_RDMA>,
1634 1661 <&reset RESET_VENCI>,
1635 1662 <&reset RESET_VENCP>,
1636 1663 <&reset RESET_VDAC>,
1637 1664 <&reset RESET_VDI6>,
1638 1665 <&reset RESET_VENCL>,
1639 1666 <&reset RESET_VID_LOCK>;
1640 1667 reset-names = "viu", "venc", "vcbus", "bt656",
1641 1668 "rdma", "venci", "vencp", "vdac",
1642 1669 "vdi6", "vencl", "vid_lock";
1643 1670 clocks = <&clkc CLKID_VPU>,
1644 1671 <&clkc CLKID_VAPB>;
1645 1672 clock-names = "vpu", "vapb";
1646 1673 /*
1647 1674 * VPU clocking is provided by two identical clock paths
1648 1675 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1649 1676 * free mux to safely change frequency while running.
1650 1677 * Same for VAPB but with a final gate after the glitch free mux.
1651 1678 */
1652 1679 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1653 1680 <&clkc CLKID_VPU_0>,
1654 1681 <&clkc CLKID_VPU>, /* Glitch free mux */
1655 1682 <&clkc CLKID_VAPB_0_SEL>,
1656 1683 <&clkc CLKID_VAPB_0>,
1657 1684 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1658 1685 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1659 1686 <0>, /* Do Nothing */
1660 1687 <&clkc CLKID_VPU_0>,
1661 1688 <&clkc CLKID_FCLK_DIV4>,
1662 1689 <0>, /* Do Nothing */
1663 1690 <&clkc CLKID_VAPB_0>;
1664 1691 assigned-clock-rates = <0>, /* Do Nothing */
1665 1692 <666666666>,
1666 1693 <0>, /* Do Nothing */
1667 1694 <0>, /* Do Nothing */
1668 1695 <250000000>,
1669 1696 <0>; /* Do Nothing */
1670 }; 1697 };
1671 <<
1672 mipi_ <<
1673 <<
1674 <<
1675 <<
1676 }; <<
1677 }; 1698 };
1678 }; 1699 };
1679 1700
1680 mipi_dphy: phy@44000 <<
1681 compatible = <<
1682 reg = <0x0 0x <<
1683 clocks = <&cl <<
1684 clock-names = <<
1685 resets = <&re <<
1686 reset-names = <<
1687 phys = <&mipi <<
1688 phy-names = " <<
1689 #phy-cells = <<
1690 status = "dis <<
1691 }; <<
1692 <<
1693 usb3_pcie_phy: phy@46 1701 usb3_pcie_phy: phy@46000 {
1694 compatible = 1702 compatible = "amlogic,g12a-usb3-pcie-phy";
1695 reg = <0x0 0x 1703 reg = <0x0 0x46000 0x0 0x2000>;
1696 clocks = <&cl 1704 clocks = <&clkc CLKID_PCIE_PLL>;
1697 clock-names = 1705 clock-names = "ref_clk";
1698 resets = <&re 1706 resets = <&reset RESET_PCIE_PHY>;
1699 reset-names = 1707 reset-names = "phy";
1700 assigned-cloc 1708 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1701 assigned-cloc 1709 assigned-clock-rates = <100000000>;
1702 #phy-cells = 1710 #phy-cells = <1>;
1703 }; 1711 };
1704 1712
1705 eth_phy: mdio-multipl 1713 eth_phy: mdio-multiplexer@4c000 {
1706 compatible = 1714 compatible = "amlogic,g12a-mdio-mux";
1707 reg = <0x0 0x 1715 reg = <0x0 0x4c000 0x0 0xa4>;
1708 clocks = <&cl 1716 clocks = <&clkc CLKID_ETH_PHY>,
1709 <&xt 1717 <&xtal>,
1710 <&cl 1718 <&clkc CLKID_MPLL_50M>;
1711 clock-names = 1719 clock-names = "pclk", "clkin0", "clkin1";
1712 mdio-parent-b 1720 mdio-parent-bus = <&mdio0>;
1713 #address-cell 1721 #address-cells = <1>;
1714 #size-cells = 1722 #size-cells = <0>;
1715 1723
1716 ext_mdio: mdi 1724 ext_mdio: mdio@0 {
1717 reg = 1725 reg = <0>;
1718 #addr 1726 #address-cells = <1>;
1719 #size 1727 #size-cells = <0>;
1720 }; 1728 };
1721 1729
1722 int_mdio: mdi 1730 int_mdio: mdio@1 {
1723 reg = 1731 reg = <1>;
1724 #addr 1732 #address-cells = <1>;
1725 #size 1733 #size-cells = <0>;
1726 1734
1727 inter 1735 internal_ephy: ethernet-phy@8 {
1728 1736 compatible = "ethernet-phy-id0180.3301",
1729 1737 "ethernet-phy-ieee802.3-c22";
1730 1738 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1731 1739 reg = <8>;
1732 1740 max-speed = <100>;
1733 }; 1741 };
1734 }; 1742 };
1735 }; 1743 };
1736 }; 1744 };
1737 1745
1738 aobus: bus@ff800000 { 1746 aobus: bus@ff800000 {
1739 compatible = "simple- 1747 compatible = "simple-bus";
1740 reg = <0x0 0xff800000 1748 reg = <0x0 0xff800000 0x0 0x100000>;
1741 #address-cells = <2>; 1749 #address-cells = <2>;
1742 #size-cells = <2>; 1750 #size-cells = <2>;
1743 ranges = <0x0 0x0 0x0 1751 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1744 1752
1745 rti: sys-ctrl@0 { 1753 rti: sys-ctrl@0 {
1746 compatible = 1754 compatible = "amlogic,meson-gx-ao-sysctrl",
1747 1755 "simple-mfd", "syscon";
1748 reg = <0x0 0x 1756 reg = <0x0 0x0 0x0 0x100>;
>> 1757 #address-cells = <2>;
>> 1758 #size-cells = <2>;
>> 1759 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1749 1760
1750 clkc_AO: cloc 1761 clkc_AO: clock-controller {
1751 compa 1762 compatible = "amlogic,meson-g12a-aoclkc";
1752 #cloc 1763 #clock-cells = <1>;
1753 #rese 1764 #reset-cells = <1>;
1754 clock 1765 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1755 clock 1766 clock-names = "xtal", "mpeg-clk";
1756 }; 1767 };
1757 }; <<
1758 <<
1759 ao_pinctrl: pinctrl@1 <<
1760 compatible = <<
1761 #address-cell <<
1762 #size-cells = <<
1763 ranges; <<
1764 <<
1765 gpio_ao: bank <<
1766 reg = <<
1767 <<
1768 <<
1769 reg-n <<
1770 <<
1771 <<
1772 gpio- <<
1773 #gpio <<
1774 gpio- <<
1775 }; <<
1776 <<
1777 i2c_ao_sck_pi <<
1778 mux { <<
1779 <<
1780 <<
1781 <<
1782 <<
1783 }; <<
1784 }; <<
1785 1768
1786 i2c_ao_sda_pi !! 1769 ao_pinctrl: pinctrl@14 {
1787 mux { !! 1770 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1788 !! 1771 #address-cells = <2>;
1789 !! 1772 #size-cells = <2>;
1790 !! 1773 ranges;
1791 <<
1792 }; <<
1793 }; <<
1794 1774
1795 i2c_ao_sck_e_ !! 1775 gpio_ao: bank@14 {
1796 mux { !! 1776 reg = <0x0 0x14 0x0 0x8>,
1797 !! 1777 <0x0 0x1c 0x0 0x8>,
1798 !! 1778 <0x0 0x24 0x0 0x14>;
1799 !! 1779 reg-names = "mux",
1800 !! 1780 "ds",
>> 1781 "gpio";
>> 1782 gpio-controller;
>> 1783 #gpio-cells = <2>;
>> 1784 gpio-ranges = <&ao_pinctrl 0 0 15>;
1801 }; 1785 };
1802 }; <<
1803 1786
1804 i2c_ao_sda_e_ !! 1787 i2c_ao_sck_pins: i2c_ao_sck_pins {
1805 mux { !! 1788 mux {
1806 !! 1789 groups = "i2c_ao_sck";
1807 !! 1790 function = "i2c_ao";
1808 !! 1791 bias-disable;
1809 !! 1792 drive-strength-microamp = <3000>;
>> 1793 };
1810 }; 1794 };
1811 }; <<
1812 1795
1813 mclk0_ao_pins !! 1796 i2c_ao_sda_pins: i2c_ao_sda {
1814 mux { !! 1797 mux {
1815 !! 1798 groups = "i2c_ao_sda";
1816 !! 1799 function = "i2c_ao";
1817 !! 1800 bias-disable;
1818 !! 1801 drive-strength-microamp = <3000>;
>> 1802 };
1819 }; 1803 };
1820 }; <<
1821 1804
1822 tdm_ao_b_din0 !! 1805 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1823 mux { !! 1806 mux {
1824 !! 1807 groups = "i2c_ao_sck_e";
1825 !! 1808 function = "i2c_ao";
1826 !! 1809 bias-disable;
>> 1810 drive-strength-microamp = <3000>;
>> 1811 };
1827 }; 1812 };
1828 }; <<
1829 1813
1830 spdif_ao_out_ !! 1814 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1831 mux { !! 1815 mux {
1832 !! 1816 groups = "i2c_ao_sda_e";
1833 !! 1817 function = "i2c_ao";
1834 !! 1818 bias-disable;
1835 !! 1819 drive-strength-microamp = <3000>;
>> 1820 };
1836 }; 1821 };
1837 }; <<
1838 1822
1839 tdm_ao_b_din1 !! 1823 mclk0_ao_pins: mclk0-ao {
1840 mux { !! 1824 mux {
1841 !! 1825 groups = "mclk0_ao";
1842 !! 1826 function = "mclk0_ao";
1843 !! 1827 bias-disable;
>> 1828 drive-strength-microamp = <3000>;
>> 1829 };
1844 }; 1830 };
1845 }; <<
1846 1831
1847 tdm_ao_b_din2 !! 1832 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1848 mux { !! 1833 mux {
1849 !! 1834 groups = "tdm_ao_b_din0";
1850 !! 1835 function = "tdm_ao_b";
1851 !! 1836 bias-disable;
>> 1837 };
1852 }; 1838 };
1853 }; <<
1854 1839
1855 tdm_ao_b_dout !! 1840 spdif_ao_out_pins: spdif-ao-out {
1856 mux { !! 1841 mux {
1857 !! 1842 groups = "spdif_ao_out";
1858 !! 1843 function = "spdif_ao_out";
1859 !! 1844 drive-strength-microamp = <500>;
1860 !! 1845 bias-disable;
>> 1846 };
1861 }; 1847 };
1862 }; <<
1863 1848
1864 tdm_ao_b_dout !! 1849 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1865 mux { !! 1850 mux {
1866 !! 1851 groups = "tdm_ao_b_din1";
1867 !! 1852 function = "tdm_ao_b";
1868 !! 1853 bias-disable;
1869 !! 1854 };
1870 }; 1855 };
1871 }; <<
1872 1856
1873 tdm_ao_b_dout !! 1857 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1874 mux { !! 1858 mux {
1875 !! 1859 groups = "tdm_ao_b_din2";
1876 !! 1860 function = "tdm_ao_b";
1877 !! 1861 bias-disable;
1878 !! 1862 };
1879 }; 1863 };
1880 }; <<
1881 1864
1882 tdm_ao_b_fs_p !! 1865 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1883 mux { !! 1866 mux {
1884 !! 1867 groups = "tdm_ao_b_dout0";
1885 !! 1868 function = "tdm_ao_b";
1886 !! 1869 bias-disable;
1887 !! 1870 drive-strength-microamp = <3000>;
>> 1871 };
1888 }; 1872 };
1889 }; <<
1890 1873
1891 tdm_ao_b_sclk !! 1874 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1892 mux { !! 1875 mux {
1893 !! 1876 groups = "tdm_ao_b_dout1";
1894 !! 1877 function = "tdm_ao_b";
1895 !! 1878 bias-disable;
1896 !! 1879 drive-strength-microamp = <3000>;
>> 1880 };
1897 }; 1881 };
1898 }; <<
1899 1882
1900 tdm_ao_b_slv_ !! 1883 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1901 mux { !! 1884 mux {
1902 !! 1885 groups = "tdm_ao_b_dout2";
1903 !! 1886 function = "tdm_ao_b";
1904 !! 1887 bias-disable;
>> 1888 drive-strength-microamp = <3000>;
>> 1889 };
1905 }; 1890 };
1906 }; <<
1907 1891
1908 tdm_ao_b_slv_ !! 1892 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1909 mux { !! 1893 mux {
1910 !! 1894 groups = "tdm_ao_b_fs";
1911 !! 1895 function = "tdm_ao_b";
1912 !! 1896 bias-disable;
>> 1897 drive-strength-microamp = <3000>;
>> 1898 };
1913 }; 1899 };
1914 }; <<
1915 1900
1916 uart_ao_a_pin !! 1901 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1917 mux { !! 1902 mux {
1918 !! 1903 groups = "tdm_ao_b_sclk";
1919 !! 1904 function = "tdm_ao_b";
1920 !! 1905 bias-disable;
1921 !! 1906 drive-strength-microamp = <3000>;
>> 1907 };
1922 }; 1908 };
1923 }; <<
1924 1909
1925 uart_ao_a_cts !! 1910 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1926 mux { !! 1911 mux {
1927 !! 1912 groups = "tdm_ao_b_slv_fs";
1928 !! 1913 function = "tdm_ao_b";
1929 !! 1914 bias-disable;
1930 !! 1915 };
1931 }; 1916 };
1932 }; <<
1933 1917
1934 uart_ao_b_2_3 !! 1918 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1935 mux { !! 1919 mux {
1936 !! 1920 groups = "tdm_ao_b_slv_sclk";
1937 !! 1921 function = "tdm_ao_b";
1938 !! 1922 bias-disable;
1939 !! 1923 };
1940 }; 1924 };
1941 }; <<
1942 1925
1943 uart_ao_b_8_9 !! 1926 uart_ao_a_pins: uart-a-ao {
1944 mux { !! 1927 mux {
1945 !! 1928 groups = "uart_ao_a_tx",
1946 !! 1929 "uart_ao_a_rx";
1947 !! 1930 function = "uart_ao_a";
1948 !! 1931 bias-disable;
>> 1932 };
1949 }; 1933 };
1950 }; <<
1951 1934
1952 uart_ao_b_cts !! 1935 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1953 mux { !! 1936 mux {
1954 !! 1937 groups = "uart_ao_a_cts",
1955 !! 1938 "uart_ao_a_rts";
1956 !! 1939 function = "uart_ao_a";
1957 !! 1940 bias-disable;
>> 1941 };
1958 }; 1942 };
1959 }; <<
1960 1943
1961 pwm_a_e_pins: !! 1944 pwm_a_e_pins: pwm-a-e {
1962 mux { !! 1945 mux {
1963 !! 1946 groups = "pwm_a_e";
1964 !! 1947 function = "pwm_a_e";
1965 !! 1948 bias-disable;
>> 1949 };
1966 }; 1950 };
1967 }; <<
1968 1951
1969 pwm_ao_a_pins !! 1952 pwm_ao_a_pins: pwm-ao-a {
1970 mux { !! 1953 mux {
1971 !! 1954 groups = "pwm_ao_a";
1972 !! 1955 function = "pwm_ao_a";
1973 !! 1956 bias-disable;
>> 1957 };
1974 }; 1958 };
1975 }; <<
1976 1959
1977 pwm_ao_b_pins !! 1960 pwm_ao_b_pins: pwm-ao-b {
1978 mux { !! 1961 mux {
1979 !! 1962 groups = "pwm_ao_b";
1980 !! 1963 function = "pwm_ao_b";
1981 !! 1964 bias-disable;
>> 1965 };
1982 }; 1966 };
1983 }; <<
1984 1967
1985 pwm_ao_c_4_pi !! 1968 pwm_ao_c_4_pins: pwm-ao-c-4 {
1986 mux { !! 1969 mux {
1987 !! 1970 groups = "pwm_ao_c_4";
1988 !! 1971 function = "pwm_ao_c";
1989 !! 1972 bias-disable;
>> 1973 };
1990 }; 1974 };
1991 }; <<
1992 1975
1993 pwm_ao_c_6_pi !! 1976 pwm_ao_c_6_pins: pwm-ao-c-6 {
1994 mux { !! 1977 mux {
1995 !! 1978 groups = "pwm_ao_c_6";
1996 !! 1979 function = "pwm_ao_c";
1997 !! 1980 bias-disable;
>> 1981 };
1998 }; 1982 };
1999 }; <<
2000 1983
2001 pwm_ao_d_5_pi !! 1984 pwm_ao_d_5_pins: pwm-ao-d-5 {
2002 mux { !! 1985 mux {
2003 !! 1986 groups = "pwm_ao_d_5";
2004 !! 1987 function = "pwm_ao_d";
2005 !! 1988 bias-disable;
>> 1989 };
2006 }; 1990 };
2007 }; <<
2008 1991
2009 pwm_ao_d_10_p !! 1992 pwm_ao_d_10_pins: pwm-ao-d-10 {
2010 mux { !! 1993 mux {
2011 !! 1994 groups = "pwm_ao_d_10";
2012 !! 1995 function = "pwm_ao_d";
2013 !! 1996 bias-disable;
>> 1997 };
2014 }; 1998 };
2015 }; <<
2016 1999
2017 pwm_ao_d_e_pi !! 2000 pwm_ao_d_e_pins: pwm-ao-d-e {
2018 mux { !! 2001 mux {
2019 !! 2002 groups = "pwm_ao_d_e";
2020 !! 2003 function = "pwm_ao_d";
>> 2004 };
2021 }; 2005 };
2022 }; <<
2023 2006
2024 remote_input_ !! 2007 remote_input_ao_pins: remote-input-ao {
2025 mux { !! 2008 mux {
2026 !! 2009 groups = "remote_ao_input";
2027 !! 2010 function = "remote_ao_input";
2028 !! 2011 bias-disable;
>> 2012 };
2029 }; 2013 };
2030 }; 2014 };
2031 }; 2015 };
2032 2016
2033 vrtc: rtc@a8 { 2017 vrtc: rtc@a8 {
2034 compatible = 2018 compatible = "amlogic,meson-vrtc";
2035 reg = <0x0 0x 2019 reg = <0x0 0x000a8 0x0 0x4>;
2036 }; 2020 };
2037 2021
2038 cec_AO: cec@100 { 2022 cec_AO: cec@100 {
2039 compatible = 2023 compatible = "amlogic,meson-gx-ao-cec";
2040 reg = <0x0 0x 2024 reg = <0x0 0x00100 0x0 0x14>;
2041 interrupts = 2025 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2042 clocks = <&cl 2026 clocks = <&clkc_AO CLKID_AO_CEC>;
2043 clock-names = 2027 clock-names = "core";
2044 status = "dis 2028 status = "disabled";
2045 }; 2029 };
2046 2030
2047 sec_AO: ao-secure@140 2031 sec_AO: ao-secure@140 {
2048 compatible = 2032 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2049 reg = <0x0 0x 2033 reg = <0x0 0x140 0x0 0x140>;
2050 amlogic,has-c 2034 amlogic,has-chip-id;
2051 }; 2035 };
2052 2036
2053 cecb_AO: cec@280 { 2037 cecb_AO: cec@280 {
2054 compatible = 2038 compatible = "amlogic,meson-g12a-ao-cec";
2055 reg = <0x0 0x 2039 reg = <0x0 0x00280 0x0 0x1c>;
2056 interrupts = 2040 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2057 clocks = <&cl 2041 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2058 clock-names = 2042 clock-names = "oscin";
2059 status = "dis 2043 status = "disabled";
2060 }; 2044 };
2061 2045
2062 pwm_AO_cd: pwm@2000 { 2046 pwm_AO_cd: pwm@2000 {
2063 compatible = 2047 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2064 reg = <0x0 0x 2048 reg = <0x0 0x2000 0x0 0x20>;
2065 #pwm-cells = 2049 #pwm-cells = <3>;
2066 status = "dis 2050 status = "disabled";
2067 }; 2051 };
2068 2052
2069 uart_AO: serial@3000 2053 uart_AO: serial@3000 {
2070 compatible = !! 2054 compatible = "amlogic,meson-gx-uart",
2071 <<
2072 2055 "amlogic,meson-ao-uart";
2073 reg = <0x0 0x 2056 reg = <0x0 0x3000 0x0 0x18>;
2074 interrupts = 2057 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2075 clocks = <&xt 2058 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2076 clock-names = 2059 clock-names = "xtal", "pclk", "baud";
2077 status = "dis 2060 status = "disabled";
2078 }; 2061 };
2079 2062
2080 uart_AO_B: serial@400 2063 uart_AO_B: serial@4000 {
2081 compatible = !! 2064 compatible = "amlogic,meson-gx-uart",
2082 <<
2083 2065 "amlogic,meson-ao-uart";
2084 reg = <0x0 0x 2066 reg = <0x0 0x4000 0x0 0x18>;
2085 interrupts = 2067 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2086 clocks = <&xt 2068 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2087 clock-names = 2069 clock-names = "xtal", "pclk", "baud";
2088 status = "dis 2070 status = "disabled";
2089 }; 2071 };
2090 2072
2091 i2c_AO: i2c@5000 { 2073 i2c_AO: i2c@5000 {
2092 compatible = 2074 compatible = "amlogic,meson-axg-i2c";
2093 status = "dis 2075 status = "disabled";
2094 reg = <0x0 0x 2076 reg = <0x0 0x05000 0x0 0x20>;
2095 interrupts = 2077 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2096 #address-cell 2078 #address-cells = <1>;
2097 #size-cells = 2079 #size-cells = <0>;
2098 clocks = <&cl 2080 clocks = <&clkc CLKID_I2C>;
2099 }; 2081 };
2100 2082
2101 pwm_AO_ab: pwm@7000 { 2083 pwm_AO_ab: pwm@7000 {
2102 compatible = 2084 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2103 reg = <0x0 0x 2085 reg = <0x0 0x7000 0x0 0x20>;
2104 #pwm-cells = 2086 #pwm-cells = <3>;
2105 status = "dis 2087 status = "disabled";
2106 }; 2088 };
2107 2089
2108 ir: ir@8000 { 2090 ir: ir@8000 {
2109 compatible = 2091 compatible = "amlogic,meson-gxbb-ir";
2110 reg = <0x0 0x 2092 reg = <0x0 0x8000 0x0 0x20>;
2111 interrupts = 2093 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2112 status = "dis 2094 status = "disabled";
2113 }; 2095 };
2114 2096
2115 saradc: adc@9000 { 2097 saradc: adc@9000 {
2116 compatible = 2098 compatible = "amlogic,meson-g12a-saradc",
2117 2099 "amlogic,meson-saradc";
2118 reg = <0x0 0x 2100 reg = <0x0 0x9000 0x0 0x48>;
2119 #io-channel-c 2101 #io-channel-cells = <1>;
2120 interrupts = 2102 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2121 clocks = <&xt 2103 clocks = <&xtal>,
2122 <&cl 2104 <&clkc_AO CLKID_AO_SAR_ADC>,
2123 <&cl 2105 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2124 <&cl 2106 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2125 clock-names = 2107 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2126 status = "dis 2108 status = "disabled";
2127 }; 2109 };
2128 }; 2110 };
2129 2111
2130 vdec: video-decoder@ff620000 2112 vdec: video-decoder@ff620000 {
2131 compatible = "amlogic 2113 compatible = "amlogic,g12a-vdec";
2132 reg = <0x0 0xff620000 2114 reg = <0x0 0xff620000 0x0 0x10000>,
2133 <0x0 0xffd0e180 2115 <0x0 0xffd0e180 0x0 0xe4>;
2134 reg-names = "dos", "e 2116 reg-names = "dos", "esparser";
2135 interrupts = <GIC_SPI 2117 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2136 <GIC_SPI 2118 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2137 interrupt-names = "vd 2119 interrupt-names = "vdec", "esparser";
2138 2120
2139 amlogic,ao-sysctrl = 2121 amlogic,ao-sysctrl = <&rti>;
2140 amlogic,canvas = <&ca 2122 amlogic,canvas = <&canvas>;
2141 2123
2142 clocks = <&clkc CLKID 2124 clocks = <&clkc CLKID_PARSER>,
2143 <&clkc CLKID 2125 <&clkc CLKID_DOS>,
2144 <&clkc CLKID 2126 <&clkc CLKID_VDEC_1>,
2145 <&clkc CLKID 2127 <&clkc CLKID_VDEC_HEVC>,
2146 <&clkc CLKID 2128 <&clkc CLKID_VDEC_HEVCF>;
2147 clock-names = "dos_pa 2129 clock-names = "dos_parser", "dos", "vdec_1",
2148 "vdec_h 2130 "vdec_hevc", "vdec_hevcf";
2149 resets = <&reset RESE 2131 resets = <&reset RESET_PARSER>;
2150 reset-names = "espars 2132 reset-names = "esparser";
2151 }; 2133 };
2152 2134
2153 vpu: vpu@ff900000 { 2135 vpu: vpu@ff900000 {
2154 compatible = "amlogic 2136 compatible = "amlogic,meson-g12a-vpu";
2155 reg = <0x0 0xff900000 2137 reg = <0x0 0xff900000 0x0 0x100000>,
2156 <0x0 0xff63c000 2138 <0x0 0xff63c000 0x0 0x1000>;
2157 reg-names = "vpu", "h 2139 reg-names = "vpu", "hhi";
2158 interrupts = <GIC_SPI 2140 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2159 #address-cells = <1>; 2141 #address-cells = <1>;
2160 #size-cells = <0>; 2142 #size-cells = <0>;
2161 amlogic,canvas = <&ca 2143 amlogic,canvas = <&canvas>;
2162 2144
2163 /* CVBS VDAC output p 2145 /* CVBS VDAC output port */
2164 cvbs_vdac_port: port@ 2146 cvbs_vdac_port: port@0 {
2165 reg = <0>; 2147 reg = <0>;
2166 }; 2148 };
2167 2149
2168 /* HDMI-TX output por 2150 /* HDMI-TX output port */
2169 hdmi_tx_port: port@1 2151 hdmi_tx_port: port@1 {
2170 reg = <1>; 2152 reg = <1>;
2171 2153
2172 hdmi_tx_out: 2154 hdmi_tx_out: endpoint {
2173 remot 2155 remote-endpoint = <&hdmi_tx_in>;
2174 }; 2156 };
2175 }; 2157 };
2176 <<
2177 /* DPI output port */ <<
2178 dpi_port: port@2 { <<
2179 reg = <2>; <<
2180 <<
2181 dpi_out: endp <<
2182 remot <<
2183 }; <<
2184 }; <<
2185 }; 2158 };
2186 2159
2187 gic: interrupt-controller@ffc 2160 gic: interrupt-controller@ffc01000 {
2188 compatible = "arm,gic 2161 compatible = "arm,gic-400";
2189 reg = <0x0 0xffc01000 2162 reg = <0x0 0xffc01000 0 0x1000>,
2190 <0x0 0xffc02000 2163 <0x0 0xffc02000 0 0x2000>,
2191 <0x0 0xffc04000 2164 <0x0 0xffc04000 0 0x2000>,
2192 <0x0 0xffc06000 2165 <0x0 0xffc06000 0 0x2000>;
2193 interrupt-controller; 2166 interrupt-controller;
2194 interrupts = <GIC_PPI 2167 interrupts = <GIC_PPI 9
2195 (GIC_CPU_MASK 2168 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2196 #interrupt-cells = <3 2169 #interrupt-cells = <3>;
2197 #address-cells = <0>; 2170 #address-cells = <0>;
2198 }; 2171 };
2199 2172
2200 cbus: bus@ffd00000 { 2173 cbus: bus@ffd00000 {
2201 compatible = "simple- 2174 compatible = "simple-bus";
2202 reg = <0x0 0xffd00000 2175 reg = <0x0 0xffd00000 0x0 0x100000>;
2203 #address-cells = <2>; 2176 #address-cells = <2>;
2204 #size-cells = <2>; 2177 #size-cells = <2>;
2205 ranges = <0x0 0x0 0x0 2178 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2206 2179
2207 reset: reset-controll 2180 reset: reset-controller@1004 {
2208 compatible = 2181 compatible = "amlogic,meson-axg-reset";
2209 reg = <0x0 0x 2182 reg = <0x0 0x1004 0x0 0x9c>;
2210 #reset-cells 2183 #reset-cells = <1>;
2211 }; 2184 };
2212 2185
2213 gpio_intc: interrupt- 2186 gpio_intc: interrupt-controller@f080 {
2214 compatible = 2187 compatible = "amlogic,meson-g12a-gpio-intc",
2215 2188 "amlogic,meson-gpio-intc";
2216 reg = <0x0 0x 2189 reg = <0x0 0xf080 0x0 0x10>;
2217 interrupt-con 2190 interrupt-controller;
2218 #interrupt-ce 2191 #interrupt-cells = <2>;
2219 amlogic,chann 2192 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2220 }; 2193 };
2221 2194
2222 mipi_dsi: dsi@7000 { <<
2223 compatible = <<
2224 reg = <0x0 0x <<
2225 resets = <&re <<
2226 reset-names = <<
2227 clocks = <&cl <<
2228 <&cl <<
2229 <&cl <<
2230 clock-names = <<
2231 phys = <&mipi <<
2232 phy-names = " <<
2233 #address-cell <<
2234 #size-cells = <<
2235 status = "dis <<
2236 <<
2237 assigned-cloc <<
2238 <&cl <<
2239 <&cl <<
2240 assigned-cloc <<
2241 <&cl <<
2242 <&cl <<
2243 <<
2244 ports { <<
2245 #addr <<
2246 #size <<
2247 <<
2248 /* VP <<
2249 mipi_ <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 <<
2257 /* DS <<
2258 mipi_ <<
2259 <<
2260 }; <<
2261 }; <<
2262 }; <<
2263 <<
2264 watchdog: watchdog@f0 2195 watchdog: watchdog@f0d0 {
2265 compatible = 2196 compatible = "amlogic,meson-gxbb-wdt";
2266 reg = <0x0 0x 2197 reg = <0x0 0xf0d0 0x0 0x10>;
2267 clocks = <&xt 2198 clocks = <&xtal>;
2268 }; 2199 };
2269 2200
2270 spicc0: spi@13000 { 2201 spicc0: spi@13000 {
2271 compatible = 2202 compatible = "amlogic,meson-g12a-spicc";
2272 reg = <0x0 0x 2203 reg = <0x0 0x13000 0x0 0x44>;
2273 interrupts = 2204 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2274 clocks = <&cl 2205 clocks = <&clkc CLKID_SPICC0>,
2275 <&cl 2206 <&clkc CLKID_SPICC0_SCLK>;
2276 clock-names = 2207 clock-names = "core", "pclk";
2277 #address-cell 2208 #address-cells = <1>;
2278 #size-cells = 2209 #size-cells = <0>;
2279 status = "dis 2210 status = "disabled";
2280 }; 2211 };
2281 2212
2282 spicc1: spi@15000 { 2213 spicc1: spi@15000 {
2283 compatible = 2214 compatible = "amlogic,meson-g12a-spicc";
2284 reg = <0x0 0x 2215 reg = <0x0 0x15000 0x0 0x44>;
2285 interrupts = 2216 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2286 clocks = <&cl 2217 clocks = <&clkc CLKID_SPICC1>,
2287 <&cl 2218 <&clkc CLKID_SPICC1_SCLK>;
2288 clock-names = 2219 clock-names = "core", "pclk";
2289 #address-cell 2220 #address-cells = <1>;
2290 #size-cells = 2221 #size-cells = <0>;
2291 status = "dis 2222 status = "disabled";
2292 }; 2223 };
2293 2224
2294 spifc: spi@14000 { 2225 spifc: spi@14000 {
2295 compatible = 2226 compatible = "amlogic,meson-gxbb-spifc";
2296 status = "dis 2227 status = "disabled";
2297 reg = <0x0 0x 2228 reg = <0x0 0x14000 0x0 0x80>;
2298 #address-cell 2229 #address-cells = <1>;
2299 #size-cells = 2230 #size-cells = <0>;
2300 clocks = <&cl 2231 clocks = <&clkc CLKID_CLK81>;
2301 }; 2232 };
2302 2233
2303 pwm_ef: pwm@19000 { 2234 pwm_ef: pwm@19000 {
2304 compatible = 2235 compatible = "amlogic,meson-g12a-ee-pwm";
2305 reg = <0x0 0x 2236 reg = <0x0 0x19000 0x0 0x20>;
2306 #pwm-cells = 2237 #pwm-cells = <3>;
2307 status = "dis 2238 status = "disabled";
2308 }; 2239 };
2309 2240
2310 pwm_cd: pwm@1a000 { 2241 pwm_cd: pwm@1a000 {
2311 compatible = 2242 compatible = "amlogic,meson-g12a-ee-pwm";
2312 reg = <0x0 0x 2243 reg = <0x0 0x1a000 0x0 0x20>;
2313 #pwm-cells = 2244 #pwm-cells = <3>;
2314 status = "dis 2245 status = "disabled";
2315 }; 2246 };
2316 2247
2317 pwm_ab: pwm@1b000 { 2248 pwm_ab: pwm@1b000 {
2318 compatible = 2249 compatible = "amlogic,meson-g12a-ee-pwm";
2319 reg = <0x0 0x 2250 reg = <0x0 0x1b000 0x0 0x20>;
2320 #pwm-cells = 2251 #pwm-cells = <3>;
2321 status = "dis 2252 status = "disabled";
2322 }; 2253 };
2323 2254
2324 i2c3: i2c@1c000 { 2255 i2c3: i2c@1c000 {
2325 compatible = 2256 compatible = "amlogic,meson-axg-i2c";
2326 status = "dis 2257 status = "disabled";
2327 reg = <0x0 0x 2258 reg = <0x0 0x1c000 0x0 0x20>;
2328 interrupts = 2259 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2329 #address-cell 2260 #address-cells = <1>;
2330 #size-cells = 2261 #size-cells = <0>;
2331 clocks = <&cl 2262 clocks = <&clkc CLKID_I2C>;
2332 }; 2263 };
2333 2264
2334 i2c2: i2c@1d000 { 2265 i2c2: i2c@1d000 {
2335 compatible = 2266 compatible = "amlogic,meson-axg-i2c";
2336 status = "dis 2267 status = "disabled";
2337 reg = <0x0 0x 2268 reg = <0x0 0x1d000 0x0 0x20>;
2338 interrupts = 2269 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2339 #address-cell 2270 #address-cells = <1>;
2340 #size-cells = 2271 #size-cells = <0>;
2341 clocks = <&cl 2272 clocks = <&clkc CLKID_I2C>;
2342 }; 2273 };
2343 2274
2344 i2c1: i2c@1e000 { 2275 i2c1: i2c@1e000 {
2345 compatible = 2276 compatible = "amlogic,meson-axg-i2c";
2346 status = "dis 2277 status = "disabled";
2347 reg = <0x0 0x 2278 reg = <0x0 0x1e000 0x0 0x20>;
2348 interrupts = 2279 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2349 #address-cell 2280 #address-cells = <1>;
2350 #size-cells = 2281 #size-cells = <0>;
2351 clocks = <&cl 2282 clocks = <&clkc CLKID_I2C>;
2352 }; 2283 };
2353 2284
2354 i2c0: i2c@1f000 { 2285 i2c0: i2c@1f000 {
2355 compatible = 2286 compatible = "amlogic,meson-axg-i2c";
2356 status = "dis 2287 status = "disabled";
2357 reg = <0x0 0x 2288 reg = <0x0 0x1f000 0x0 0x20>;
2358 interrupts = 2289 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2359 #address-cell 2290 #address-cells = <1>;
2360 #size-cells = 2291 #size-cells = <0>;
2361 clocks = <&cl 2292 clocks = <&clkc CLKID_I2C>;
2362 }; 2293 };
2363 2294
2364 clk_msr: clock-measur 2295 clk_msr: clock-measure@18000 {
2365 compatible = 2296 compatible = "amlogic,meson-g12a-clk-measure";
2366 reg = <0x0 0x 2297 reg = <0x0 0x18000 0x0 0x10>;
2367 }; 2298 };
2368 2299
2369 uart_C: serial@22000 2300 uart_C: serial@22000 {
2370 compatible = !! 2301 compatible = "amlogic,meson-gx-uart";
2371 <<
2372 reg = <0x0 0x 2302 reg = <0x0 0x22000 0x0 0x18>;
2373 interrupts = 2303 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2374 clocks = <&xt 2304 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2375 clock-names = 2305 clock-names = "xtal", "pclk", "baud";
2376 status = "dis 2306 status = "disabled";
2377 }; 2307 };
2378 2308
2379 uart_B: serial@23000 2309 uart_B: serial@23000 {
2380 compatible = !! 2310 compatible = "amlogic,meson-gx-uart";
2381 <<
2382 reg = <0x0 0x 2311 reg = <0x0 0x23000 0x0 0x18>;
2383 interrupts = 2312 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2384 clocks = <&xt 2313 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2385 clock-names = 2314 clock-names = "xtal", "pclk", "baud";
2386 status = "dis 2315 status = "disabled";
2387 }; 2316 };
2388 2317
2389 uart_A: serial@24000 2318 uart_A: serial@24000 {
2390 compatible = !! 2319 compatible = "amlogic,meson-gx-uart";
2391 <<
2392 reg = <0x0 0x 2320 reg = <0x0 0x24000 0x0 0x18>;
2393 interrupts = 2321 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2394 clocks = <&xt 2322 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2395 clock-names = 2323 clock-names = "xtal", "pclk", "baud";
2396 status = "dis 2324 status = "disabled";
2397 fifo-size = < 2325 fifo-size = <128>;
2398 }; 2326 };
2399 }; 2327 };
2400 2328
2401 sd_emmc_a: mmc@ffe03000 { !! 2329 sd_emmc_a: sd@ffe03000 {
2402 compatible = "amlogic 2330 compatible = "amlogic,meson-axg-mmc";
2403 reg = <0x0 0xffe03000 2331 reg = <0x0 0xffe03000 0x0 0x800>;
2404 interrupts = <GIC_SPI 2332 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2405 status = "disabled"; 2333 status = "disabled";
2406 clocks = <&clkc CLKID 2334 clocks = <&clkc CLKID_SD_EMMC_A>,
2407 <&clkc CLKID 2335 <&clkc CLKID_SD_EMMC_A_CLK0>,
2408 <&clkc CLKID 2336 <&clkc CLKID_FCLK_DIV2>;
2409 clock-names = "core", 2337 clock-names = "core", "clkin0", "clkin1";
2410 resets = <&reset RESE 2338 resets = <&reset RESET_SD_EMMC_A>;
2411 }; 2339 };
2412 2340
2413 sd_emmc_b: mmc@ffe05000 { !! 2341 sd_emmc_b: sd@ffe05000 {
2414 compatible = "amlogic 2342 compatible = "amlogic,meson-axg-mmc";
2415 reg = <0x0 0xffe05000 2343 reg = <0x0 0xffe05000 0x0 0x800>;
2416 interrupts = <GIC_SPI 2344 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2417 status = "disabled"; 2345 status = "disabled";
2418 clocks = <&clkc CLKID 2346 clocks = <&clkc CLKID_SD_EMMC_B>,
2419 <&clkc CLKID 2347 <&clkc CLKID_SD_EMMC_B_CLK0>,
2420 <&clkc CLKID 2348 <&clkc CLKID_FCLK_DIV2>;
2421 clock-names = "core", 2349 clock-names = "core", "clkin0", "clkin1";
2422 resets = <&reset RESE 2350 resets = <&reset RESET_SD_EMMC_B>;
2423 }; 2351 };
2424 2352
2425 sd_emmc_c: mmc@ffe07000 { 2353 sd_emmc_c: mmc@ffe07000 {
2426 compatible = "amlogic 2354 compatible = "amlogic,meson-axg-mmc";
2427 reg = <0x0 0xffe07000 2355 reg = <0x0 0xffe07000 0x0 0x800>;
2428 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2429 status = "disabled"; 2357 status = "disabled";
2430 clocks = <&clkc CLKID 2358 clocks = <&clkc CLKID_SD_EMMC_C>,
2431 <&clkc CLKID 2359 <&clkc CLKID_SD_EMMC_C_CLK0>,
2432 <&clkc CLKID 2360 <&clkc CLKID_FCLK_DIV2>;
2433 clock-names = "core", 2361 clock-names = "core", "clkin0", "clkin1";
2434 resets = <&reset RESE 2362 resets = <&reset RESET_SD_EMMC_C>;
2435 }; 2363 };
2436 2364
2437 usb: usb@ffe09000 { 2365 usb: usb@ffe09000 {
2438 status = "disabled"; 2366 status = "disabled";
2439 compatible = "amlogic 2367 compatible = "amlogic,meson-g12a-usb-ctrl";
2440 reg = <0x0 0xffe09000 2368 reg = <0x0 0xffe09000 0x0 0xa0>;
2441 interrupts = <GIC_SPI 2369 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2442 #address-cells = <2>; 2370 #address-cells = <2>;
2443 #size-cells = <2>; 2371 #size-cells = <2>;
2444 ranges; 2372 ranges;
2445 2373
2446 clocks = <&clkc CLKID 2374 clocks = <&clkc CLKID_USB>;
2447 resets = <&reset RESE 2375 resets = <&reset RESET_USB>;
2448 2376
2449 dr_mode = "otg"; 2377 dr_mode = "otg";
2450 2378
2451 phys = <&usb2_phy0>, 2379 phys = <&usb2_phy0>, <&usb2_phy1>,
2452 <&usb3_pcie_ph 2380 <&usb3_pcie_phy PHY_TYPE_USB3>;
2453 phy-names = "usb2-phy 2381 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2454 2382
2455 dwc2: usb@ff400000 { 2383 dwc2: usb@ff400000 {
2456 compatible = 2384 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2457 reg = <0x0 0x 2385 reg = <0x0 0xff400000 0x0 0x40000>;
2458 interrupts = 2386 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2459 clocks = <&cl 2387 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2460 clock-names = 2388 clock-names = "otg";
2461 phys = <&usb2 2389 phys = <&usb2_phy1>;
2462 phy-names = " 2390 phy-names = "usb2-phy";
2463 dr_mode = "pe 2391 dr_mode = "peripheral";
2464 g-rx-fifo-siz 2392 g-rx-fifo-size = <192>;
2465 g-np-tx-fifo- 2393 g-np-tx-fifo-size = <128>;
2466 g-tx-fifo-siz 2394 g-tx-fifo-size = <128 128 16 16 16>;
2467 }; 2395 };
2468 2396
2469 dwc3: usb@ff500000 { 2397 dwc3: usb@ff500000 {
2470 compatible = 2398 compatible = "snps,dwc3";
2471 reg = <0x0 0x 2399 reg = <0x0 0xff500000 0x0 0x100000>;
2472 interrupts = 2400 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2473 dr_mode = "ho 2401 dr_mode = "host";
2474 snps,dis_u2_s 2402 snps,dis_u2_susphy_quirk;
2475 snps,quirk-fr 2403 snps,quirk-frame-length-adjustment = <0x20>;
2476 snps,parkmode 2404 snps,parkmode-disable-ss-quirk;
2477 }; 2405 };
2478 }; 2406 };
2479 2407
2480 mali: gpu@ffe40000 { 2408 mali: gpu@ffe40000 {
2481 compatible = "amlogic 2409 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2482 reg = <0x0 0xffe40000 2410 reg = <0x0 0xffe40000 0x0 0x40000>;
2483 interrupt-parent = <& 2411 interrupt-parent = <&gic>;
2484 interrupts = <GIC_SPI 2412 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 2413 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 2414 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2487 interrupt-names = "jo 2415 interrupt-names = "job", "mmu", "gpu";
2488 clocks = <&clkc CLKID 2416 clocks = <&clkc CLKID_MALI>;
2489 resets = <&reset RESE 2417 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2490 operating-points-v2 = 2418 operating-points-v2 = <&gpu_opp_table>;
2491 #cooling-cells = <2>; 2419 #cooling-cells = <2>;
2492 }; 2420 };
2493 }; 2421 };
2494 2422
2495 thermal-zones { <<
2496 cpu_thermal: cpu-thermal { <<
2497 polling-delay = <1000 <<
2498 polling-delay-passive <<
2499 thermal-sensors = <&c <<
2500 <<
2501 trips { <<
2502 cpu_passive: <<
2503 tempe <<
2504 hyste <<
2505 type <<
2506 }; <<
2507 <<
2508 cpu_hot: cpu- <<
2509 tempe <<
2510 hyste <<
2511 type <<
2512 }; <<
2513 <<
2514 cpu_critical: <<
2515 tempe <<
2516 hyste <<
2517 type <<
2518 }; <<
2519 }; <<
2520 }; <<
2521 <<
2522 ddr_thermal: ddr-thermal { <<
2523 polling-delay = <1000 <<
2524 polling-delay-passive <<
2525 thermal-sensors = <&d <<
2526 <<
2527 trips { <<
2528 ddr_passive: <<
2529 tempe <<
2530 hyste <<
2531 type <<
2532 }; <<
2533 <<
2534 ddr_critical: <<
2535 tempe <<
2536 hyste <<
2537 type <<
2538 }; <<
2539 }; <<
2540 <<
2541 cooling-maps { <<
2542 map { <<
2543 trip <<
2544 cooli <<
2545 }; <<
2546 }; <<
2547 }; <<
2548 }; <<
2549 <<
2550 timer { 2423 timer {
2551 compatible = "arm,armv8-timer 2424 compatible = "arm,armv8-timer";
2552 interrupts = <GIC_PPI 13 2425 interrupts = <GIC_PPI 13
2553 (GIC_CPU_MASK_RAW(0xf 2426 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2554 <GIC_PPI 14 2427 <GIC_PPI 14
2555 (GIC_CPU_MASK_RAW(0xf 2428 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2556 <GIC_PPI 11 2429 <GIC_PPI 11
2557 (GIC_CPU_MASK_RAW(0xf 2430 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2558 <GIC_PPI 10 2431 <GIC_PPI 10
2559 (GIC_CPU_MASK_RAW(0xf 2432 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2560 arm,no-tick-in-suspend; 2433 arm,no-tick-in-suspend;
2561 }; 2434 };
2562 2435
2563 xtal: xtal-clk { 2436 xtal: xtal-clk {
2564 compatible = "fixed-clock"; 2437 compatible = "fixed-clock";
2565 clock-frequency = <24000000>; 2438 clock-frequency = <24000000>;
2566 clock-output-names = "xtal"; 2439 clock-output-names = "xtal";
2567 #clock-cells = <0>; 2440 #clock-cells = <0>;
2568 }; 2441 };
2569 2442
2570 npu: npu@ff100000 { <<
2571 compatible = "vivante,gc"; <<
2572 reg = <0x0 0xff100000 0x0 0x2 <<
2573 interrupts = <0 147 4>; <<
2574 clocks = <&clkc CLKID_NNA_COR <<
2575 <&clkc CLKID_NNA_AXI <<
2576 clock-names = "core", "bus"; <<
2577 assigned-clocks = <&clkc CLKI <<
2578 <&clkc CLKI <<
2579 assigned-clock-rates = <80000 <<
2580 resets = <&reset RESET_NNA>; <<
2581 status = "disabled"; <<
2582 }; <<
2583 }; 2443 };
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