1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy.h> 6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h> 8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h> 9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/aml <<
13 #include <dt-bindings/reset/amlogic,meson-g12a 12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { <<
22 mmc0 = &sd_emmc_b; /* SD card <<
23 mmc1 = &sd_emmc_c; /* eMMC */ <<
24 mmc2 = &sd_emmc_a; /* SDIO */ <<
25 }; <<
26 <<
27 chosen { 20 chosen {
28 #address-cells = <2>; 21 #address-cells = <2>;
29 #size-cells = <2>; 22 #size-cells = <2>;
30 ranges; 23 ranges;
31 24
32 simplefb_cvbs: framebuffer-cvb 25 simplefb_cvbs: framebuffer-cvbs {
33 compatible = "amlogic, 26 compatible = "amlogic,simple-framebuffer",
34 "simple-f 27 "simple-framebuffer";
35 amlogic,pipeline = "vp 28 amlogic,pipeline = "vpu-cvbs";
36 clocks = <&clkc CLKID_ 29 clocks = <&clkc CLKID_HDMI>,
37 <&clkc CLKID_ 30 <&clkc CLKID_HTX_PCLK>,
38 <&clkc CLKID_ 31 <&clkc CLKID_VPU_INTR>;
39 status = "disabled"; 32 status = "disabled";
40 }; 33 };
41 34
42 simplefb_hdmi: framebuffer-hdm 35 simplefb_hdmi: framebuffer-hdmi {
43 compatible = "amlogic, 36 compatible = "amlogic,simple-framebuffer",
44 "simple-fr 37 "simple-framebuffer";
45 amlogic,pipeline = "vp 38 amlogic,pipeline = "vpu-hdmi";
46 clocks = <&clkc CLKID_ 39 clocks = <&clkc CLKID_HDMI>,
47 <&clkc CLKID_ 40 <&clkc CLKID_HTX_PCLK>,
48 <&clkc CLKID_ 41 <&clkc CLKID_VPU_INTR>;
49 status = "disabled"; 42 status = "disabled";
50 }; 43 };
51 }; 44 };
52 45
53 efuse: efuse { 46 efuse: efuse {
54 compatible = "amlogic,meson-gx 47 compatible = "amlogic,meson-gxbb-efuse";
55 clocks = <&clkc CLKID_EFUSE>; 48 clocks = <&clkc CLKID_EFUSE>;
56 #address-cells = <1>; 49 #address-cells = <1>;
57 #size-cells = <1>; 50 #size-cells = <1>;
58 read-only; 51 read-only;
59 secure-monitor = <&sm>; 52 secure-monitor = <&sm>;
60 }; 53 };
61 54
62 gpu_opp_table: opp-table-gpu { <<
63 compatible = "operating-points <<
64 <<
65 opp-124999998 { <<
66 opp-hz = /bits/ 64 <12 <<
67 opp-microvolt = <80000 <<
68 }; <<
69 opp-249999996 { <<
70 opp-hz = /bits/ 64 <24 <<
71 opp-microvolt = <80000 <<
72 }; <<
73 opp-285714281 { <<
74 opp-hz = /bits/ 64 <28 <<
75 opp-microvolt = <80000 <<
76 }; <<
77 opp-399999994 { <<
78 opp-hz = /bits/ 64 <39 <<
79 opp-microvolt = <80000 <<
80 }; <<
81 opp-499999992 { <<
82 opp-hz = /bits/ 64 <49 <<
83 opp-microvolt = <80000 <<
84 }; <<
85 opp-666666656 { <<
86 opp-hz = /bits/ 64 <66 <<
87 opp-microvolt = <80000 <<
88 }; <<
89 opp-799999987 { <<
90 opp-hz = /bits/ 64 <79 <<
91 opp-microvolt = <80000 <<
92 }; <<
93 }; <<
94 <<
95 psci { 55 psci {
96 compatible = "arm,psci-1.0"; 56 compatible = "arm,psci-1.0";
97 method = "smc"; 57 method = "smc";
98 }; 58 };
99 59
100 reserved-memory { 60 reserved-memory {
101 #address-cells = <2>; 61 #address-cells = <2>;
102 #size-cells = <2>; 62 #size-cells = <2>;
103 ranges; 63 ranges;
104 64
105 /* 3 MiB reserved for ARM Trus 65 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
106 secmon_reserved: secmon@500000 66 secmon_reserved: secmon@5000000 {
107 reg = <0x0 0x05000000 67 reg = <0x0 0x05000000 0x0 0x300000>;
108 no-map; 68 no-map;
109 }; 69 };
110 70
111 /* 32 MiB reserved for ARM Tru <<
112 secmon_reserved_bl32: secmon@5 <<
113 reg = <0x0 0x05300000 <<
114 no-map; <<
115 }; <<
116 <<
117 linux,cma { 71 linux,cma {
118 compatible = "shared-d 72 compatible = "shared-dma-pool";
119 reusable; 73 reusable;
120 size = <0x0 0x10000000 74 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400 75 alignment = <0x0 0x400000>;
122 linux,cma-default; 76 linux,cma-default;
123 }; 77 };
124 }; 78 };
125 79
126 sm: secure-monitor { 80 sm: secure-monitor {
127 compatible = "amlogic,meson-gx 81 compatible = "amlogic,meson-gxbb-sm";
128 }; 82 };
129 83
130 soc { 84 soc {
131 compatible = "simple-bus"; 85 compatible = "simple-bus";
132 #address-cells = <2>; 86 #address-cells = <2>;
133 #size-cells = <2>; 87 #size-cells = <2>;
134 ranges; 88 ranges;
135 89
136 pcie: pcie@fc000000 { 90 pcie: pcie@fc000000 {
137 compatible = "amlogic, 91 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
138 reg = <0x0 0xfc000000 !! 92 reg = <0x0 0xfc000000 0x0 0x400000
139 <0x0 0xff648000 !! 93 0x0 0xff648000 0x0 0x2000
140 <0x0 0xfc400000 !! 94 0x0 0xfc400000 0x0 0x200000>;
141 reg-names = "elbi", "c 95 reg-names = "elbi", "cfg", "config";
142 interrupts = <GIC_SPI 96 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
143 #interrupt-cells = <1> 97 #interrupt-cells = <1>;
144 interrupt-map-mask = < 98 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 99 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff> 100 bus-range = <0x0 0xff>;
147 #address-cells = <3>; 101 #address-cells = <3>;
148 #size-cells = <2>; 102 #size-cells = <2>;
149 device_type = "pci"; 103 device_type = "pci";
150 ranges = <0x81000000 0 !! 104 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
151 <0x82000000 0 !! 105 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
152 106
153 clocks = <&clkc CLKID_ 107 clocks = <&clkc CLKID_PCIE_PHY
154 &clkc CLKID_ 108 &clkc CLKID_PCIE_COMB
155 &clkc CLKID_ 109 &clkc CLKID_PCIE_PLL>;
156 clock-names = "general 110 clock-names = "general",
157 "pclk", 111 "pclk",
158 "port"; 112 "port";
159 resets = <&reset RESET 113 resets = <&reset RESET_PCIE_CTRL_A>,
160 <&reset RESET 114 <&reset RESET_PCIE_APB>;
161 reset-names = "port", 115 reset-names = "port",
162 "apb"; 116 "apb";
163 num-lanes = <1>; 117 num-lanes = <1>;
164 phys = <&usb3_pcie_phy 118 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
165 phy-names = "pcie"; 119 phy-names = "pcie";
166 status = "disabled"; 120 status = "disabled";
167 }; 121 };
168 122
>> 123 thermal-zones {
>> 124 cpu_thermal: cpu-thermal {
>> 125 polling-delay = <1000>;
>> 126 polling-delay-passive = <100>;
>> 127 thermal-sensors = <&cpu_temp>;
>> 128
>> 129 trips {
>> 130 cpu_passive: cpu-passive {
>> 131 temperature = <85000>; /* millicelsius */
>> 132 hysteresis = <2000>; /* millicelsius */
>> 133 type = "passive";
>> 134 };
>> 135
>> 136 cpu_hot: cpu-hot {
>> 137 temperature = <95000>; /* millicelsius */
>> 138 hysteresis = <2000>; /* millicelsius */
>> 139 type = "hot";
>> 140 };
>> 141
>> 142 cpu_critical: cpu-critical {
>> 143 temperature = <110000>; /* millicelsius */
>> 144 hysteresis = <2000>; /* millicelsius */
>> 145 type = "critical";
>> 146 };
>> 147 };
>> 148 };
>> 149
>> 150 ddr_thermal: ddr-thermal {
>> 151 polling-delay = <1000>;
>> 152 polling-delay-passive = <100>;
>> 153 thermal-sensors = <&ddr_temp>;
>> 154
>> 155 trips {
>> 156 ddr_passive: ddr-passive {
>> 157 temperature = <85000>; /* millicelsius */
>> 158 hysteresis = <2000>; /* millicelsius */
>> 159 type = "passive";
>> 160 };
>> 161
>> 162 ddr_critical: ddr-critical {
>> 163 temperature = <110000>; /* millicelsius */
>> 164 hysteresis = <2000>; /* millicelsius */
>> 165 type = "critical";
>> 166 };
>> 167 };
>> 168
>> 169 cooling-maps {
>> 170 map {
>> 171 trip = <&ddr_passive>;
>> 172 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 173 };
>> 174 };
>> 175 };
>> 176 };
>> 177
169 ethmac: ethernet@ff3f0000 { 178 ethmac: ethernet@ff3f0000 {
170 compatible = "amlogic, !! 179 compatible = "amlogic,meson-axg-dwmac",
171 "snps,dwm 180 "snps,dwmac-3.70a",
172 "snps,dwm 181 "snps,dwmac";
173 reg = <0x0 0xff3f0000 182 reg = <0x0 0xff3f0000 0x0 0x10000>,
174 <0x0 0xff634540 183 <0x0 0xff634540 0x0 0x8>;
175 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "mac 185 interrupt-names = "macirq";
177 clocks = <&clkc CLKID_ 186 clocks = <&clkc CLKID_ETH>,
178 <&clkc CLKID_ 187 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_ !! 188 <&clkc CLKID_MPLL2>;
180 <&clkc CLKID_ !! 189 clock-names = "stmmaceth", "clkin0", "clkin1";
181 clock-names = "stmmace <<
182 "timing- <<
183 rx-fifo-depth = <4096> 190 rx-fifo-depth = <4096>;
184 tx-fifo-depth = <2048> 191 tx-fifo-depth = <2048>;
185 status = "disabled"; 192 status = "disabled";
186 193
187 mdio0: mdio { 194 mdio0: mdio {
188 #address-cells 195 #address-cells = <1>;
189 #size-cells = 196 #size-cells = <0>;
190 compatible = " 197 compatible = "snps,dwmac-mdio";
191 }; 198 };
192 }; 199 };
193 200
194 apb: bus@ff600000 { 201 apb: bus@ff600000 {
195 compatible = "simple-b 202 compatible = "simple-bus";
196 reg = <0x0 0xff600000 203 reg = <0x0 0xff600000 0x0 0x200000>;
197 #address-cells = <2>; 204 #address-cells = <2>;
198 #size-cells = <2>; 205 #size-cells = <2>;
199 ranges = <0x0 0x0 0x0 206 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
200 207
201 hdmi_tx: hdmi-tx@0 { 208 hdmi_tx: hdmi-tx@0 {
202 compatible = " 209 compatible = "amlogic,meson-g12a-dw-hdmi";
203 reg = <0x0 0x0 210 reg = <0x0 0x0 0x0 0x10000>;
204 interrupts = < 211 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
205 resets = <&res 212 resets = <&reset RESET_HDMITX_CAPB3>,
206 <&res 213 <&reset RESET_HDMITX_PHY>,
207 <&res 214 <&reset RESET_HDMITX>;
208 reset-names = 215 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
209 clocks = <&clk 216 clocks = <&clkc CLKID_HDMI>,
210 <&clk 217 <&clkc CLKID_HTX_PCLK>,
211 <&clk 218 <&clkc CLKID_VPU_INTR>;
212 clock-names = 219 clock-names = "isfr", "iahb", "venci";
213 #address-cells 220 #address-cells = <1>;
214 #size-cells = 221 #size-cells = <0>;
215 #sound-dai-cel 222 #sound-dai-cells = <0>;
216 status = "disa 223 status = "disabled";
217 224
218 assigned-clock <<
219 <<
220 assigned-clock <<
221 assigned-clock <<
222 <<
223 /* VPU VENC In 225 /* VPU VENC Input */
224 hdmi_tx_venc_p 226 hdmi_tx_venc_port: port@0 {
225 reg = 227 reg = <0>;
226 228
227 hdmi_t 229 hdmi_tx_in: endpoint {
228 230 remote-endpoint = <&hdmi_tx_out>;
229 }; 231 };
230 }; 232 };
231 233
232 /* TMDS Output 234 /* TMDS Output */
233 hdmi_tx_tmds_p 235 hdmi_tx_tmds_port: port@1 {
234 reg = 236 reg = <1>;
235 }; 237 };
236 }; 238 };
237 239
238 apb_efuse: bus@30000 { 240 apb_efuse: bus@30000 {
239 compatible = " 241 compatible = "simple-bus";
240 reg = <0x0 0x3 242 reg = <0x0 0x30000 0x0 0x2000>;
241 #address-cells 243 #address-cells = <2>;
242 #size-cells = 244 #size-cells = <2>;
243 ranges = <0x0 245 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
244 246
245 hwrng: rng@218 247 hwrng: rng@218 {
246 compat 248 compatible = "amlogic,meson-rng";
247 reg = 249 reg = <0x0 0x218 0x0 0x4>;
248 clocks <<
249 clock- <<
250 }; 250 };
251 }; 251 };
252 252
253 acodec: audio-controll <<
254 compatible = " <<
255 reg = <0x0 0x3 <<
256 #sound-dai-cel <<
257 sound-name-pre <<
258 clocks = <&clk <<
259 clock-names = <<
260 resets = <&res <<
261 status = "disa <<
262 }; <<
263 <<
264 periphs: bus@34400 { 253 periphs: bus@34400 {
265 compatible = " 254 compatible = "simple-bus";
266 reg = <0x0 0x3 255 reg = <0x0 0x34400 0x0 0x400>;
267 #address-cells 256 #address-cells = <2>;
268 #size-cells = 257 #size-cells = <2>;
269 ranges = <0x0 258 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
270 259
271 periphs_pinctr 260 periphs_pinctrl: pinctrl@40 {
272 compat 261 compatible = "amlogic,meson-g12a-periphs-pinctrl";
273 #addre 262 #address-cells = <2>;
274 #size- 263 #size-cells = <2>;
275 ranges 264 ranges;
276 265
277 gpio: 266 gpio: bank@40 {
278 267 reg = <0x0 0x40 0x0 0x4c>,
279 268 <0x0 0xe8 0x0 0x18>,
280 269 <0x0 0x120 0x0 0x18>,
281 270 <0x0 0x2c0 0x0 0x40>,
282 271 <0x0 0x340 0x0 0x1c>;
283 272 reg-names = "gpio",
284 273 "pull",
285 274 "pull-enable",
286 275 "mux",
287 276 "ds";
288 277 gpio-controller;
289 278 #gpio-cells = <2>;
290 279 gpio-ranges = <&periphs_pinctrl 0 0 86>;
291 }; 280 };
292 281
293 cec_ao 282 cec_ao_a_h_pins: cec_ao_a_h {
294 283 mux {
295 284 groups = "cec_ao_a_h";
296 285 function = "cec_ao_a_h";
297 286 bias-disable;
298 287 };
299 }; 288 };
300 289
301 cec_ao 290 cec_ao_b_h_pins: cec_ao_b_h {
302 291 mux {
303 292 groups = "cec_ao_b_h";
304 293 function = "cec_ao_b_h";
305 294 bias-disable;
306 295 };
307 }; 296 };
308 297
309 emmc_c !! 298 emmc_pins: emmc {
310 <<
311 <<
312 <<
313 <<
314 <<
315 <<
316 <<
317 <<
318 <<
319 <<
320 <<
321 <<
322 <<
323 }; <<
324 <<
325 emmc_d <<
326 <<
327 <<
328 <<
329 <<
330 <<
331 <<
332 <<
333 <<
334 <<
335 }; <<
336 <<
337 emmc_d <<
338 299 mux-0 {
339 300 groups = "emmc_nand_d0",
340 301 "emmc_nand_d1",
341 302 "emmc_nand_d2",
342 303 "emmc_nand_d3",
343 304 "emmc_nand_d4",
344 305 "emmc_nand_d5",
345 306 "emmc_nand_d6",
346 !! 307 "emmc_nand_d7",
>> 308 "emmc_cmd";
347 309 function = "emmc";
348 310 bias-pull-up;
349 311 drive-strength-microamp = <4000>;
350 312 };
>> 313
>> 314 mux-1 {
>> 315 groups = "emmc_clk";
>> 316 function = "emmc";
>> 317 bias-disable;
>> 318 drive-strength-microamp = <4000>;
>> 319 };
351 }; 320 };
352 321
353 emmc_d 322 emmc_ds_pins: emmc-ds {
354 323 mux {
355 324 groups = "emmc_nand_ds";
356 325 function = "emmc";
357 326 bias-pull-down;
358 327 drive-strength-microamp = <4000>;
359 328 };
360 }; 329 };
361 330
362 emmc_c 331 emmc_clk_gate_pins: emmc_clk_gate {
363 332 mux {
364 333 groups = "BOOT_8";
365 334 function = "gpio_periphs";
366 335 bias-pull-down;
367 336 drive-strength-microamp = <4000>;
368 337 };
369 }; 338 };
370 339
371 hdmitx 340 hdmitx_ddc_pins: hdmitx_ddc {
372 341 mux {
373 342 groups = "hdmitx_sda",
374 343 "hdmitx_sck";
375 344 function = "hdmitx";
376 345 bias-disable;
377 346 drive-strength-microamp = <4000>;
378 347 };
379 }; 348 };
380 349
381 hdmitx 350 hdmitx_hpd_pins: hdmitx_hpd {
382 351 mux {
383 352 groups = "hdmitx_hpd_in";
384 353 function = "hdmitx";
385 354 bias-disable;
386 355 };
387 }; 356 };
388 357
389 358
390 i2c0_s 359 i2c0_sda_c_pins: i2c0-sda-c {
391 360 mux {
392 361 groups = "i2c0_sda_c";
393 362 function = "i2c0";
394 363 bias-disable;
395 364 drive-strength-microamp = <3000>;
396 365
397 366 };
398 }; 367 };
399 368
400 i2c0_s 369 i2c0_sck_c_pins: i2c0-sck-c {
401 370 mux {
402 371 groups = "i2c0_sck_c";
403 372 function = "i2c0";
404 373 bias-disable;
405 374 drive-strength-microamp = <3000>;
406 375 };
407 }; 376 };
408 377
409 i2c0_s 378 i2c0_sda_z0_pins: i2c0-sda-z0 {
410 379 mux {
411 380 groups = "i2c0_sda_z0";
412 381 function = "i2c0";
413 382 bias-disable;
414 383 drive-strength-microamp = <3000>;
415 384 };
416 }; 385 };
417 386
418 i2c0_s 387 i2c0_sck_z1_pins: i2c0-sck-z1 {
419 388 mux {
420 389 groups = "i2c0_sck_z1";
421 390 function = "i2c0";
422 391 bias-disable;
423 392 drive-strength-microamp = <3000>;
424 393 };
425 }; 394 };
426 395
427 i2c0_s 396 i2c0_sda_z7_pins: i2c0-sda-z7 {
428 397 mux {
429 398 groups = "i2c0_sda_z7";
430 399 function = "i2c0";
431 400 bias-disable;
432 401 drive-strength-microamp = <3000>;
433 402 };
434 }; 403 };
435 404
436 i2c0_s 405 i2c0_sda_z8_pins: i2c0-sda-z8 {
437 406 mux {
438 407 groups = "i2c0_sda_z8";
439 408 function = "i2c0";
440 409 bias-disable;
441 410 drive-strength-microamp = <3000>;
442 411 };
443 }; 412 };
444 413
445 i2c1_s 414 i2c1_sda_x_pins: i2c1-sda-x {
446 415 mux {
447 416 groups = "i2c1_sda_x";
448 417 function = "i2c1";
449 418 bias-disable;
450 419 drive-strength-microamp = <3000>;
451 420 };
452 }; 421 };
453 422
454 i2c1_s 423 i2c1_sck_x_pins: i2c1-sck-x {
455 424 mux {
456 425 groups = "i2c1_sck_x";
457 426 function = "i2c1";
458 427 bias-disable;
459 428 drive-strength-microamp = <3000>;
460 429 };
461 }; 430 };
462 431
463 i2c1_s 432 i2c1_sda_h2_pins: i2c1-sda-h2 {
464 433 mux {
465 434 groups = "i2c1_sda_h2";
466 435 function = "i2c1";
467 436 bias-disable;
468 437 drive-strength-microamp = <3000>;
469 438 };
470 }; 439 };
471 440
472 i2c1_s 441 i2c1_sck_h3_pins: i2c1-sck-h3 {
473 442 mux {
474 443 groups = "i2c1_sck_h3";
475 444 function = "i2c1";
476 445 bias-disable;
477 446 drive-strength-microamp = <3000>;
478 447 };
479 }; 448 };
480 449
481 i2c1_s 450 i2c1_sda_h6_pins: i2c1-sda-h6 {
482 451 mux {
483 452 groups = "i2c1_sda_h6";
484 453 function = "i2c1";
485 454 bias-disable;
486 455 drive-strength-microamp = <3000>;
487 456 };
488 }; 457 };
489 458
490 i2c1_s 459 i2c1_sck_h7_pins: i2c1-sck-h7 {
491 460 mux {
492 461 groups = "i2c1_sck_h7";
493 462 function = "i2c1";
494 463 bias-disable;
495 464 drive-strength-microamp = <3000>;
496 465 };
497 }; 466 };
498 467
499 i2c2_s 468 i2c2_sda_x_pins: i2c2-sda-x {
500 469 mux {
501 470 groups = "i2c2_sda_x";
502 471 function = "i2c2";
503 472 bias-disable;
504 473 drive-strength-microamp = <3000>;
505 474 };
506 }; 475 };
507 476
508 i2c2_s 477 i2c2_sck_x_pins: i2c2-sck-x {
509 478 mux {
510 479 groups = "i2c2_sck_x";
511 480 function = "i2c2";
512 481 bias-disable;
513 482 drive-strength-microamp = <3000>;
514 483 };
515 }; 484 };
516 485
517 i2c2_s 486 i2c2_sda_z_pins: i2c2-sda-z {
518 487 mux {
519 488 groups = "i2c2_sda_z";
520 489 function = "i2c2";
521 490 bias-disable;
522 491 drive-strength-microamp = <3000>;
523 492 };
524 }; 493 };
525 494
526 i2c2_s 495 i2c2_sck_z_pins: i2c2-sck-z {
527 496 mux {
528 497 groups = "i2c2_sck_z";
529 498 function = "i2c2";
530 499 bias-disable;
531 500 drive-strength-microamp = <3000>;
532 501 };
533 }; 502 };
534 503
535 i2c3_s 504 i2c3_sda_h_pins: i2c3-sda-h {
536 505 mux {
537 506 groups = "i2c3_sda_h";
538 507 function = "i2c3";
539 508 bias-disable;
540 509 drive-strength-microamp = <3000>;
541 510 };
542 }; 511 };
543 512
544 i2c3_s 513 i2c3_sck_h_pins: i2c3-sck-h {
545 514 mux {
546 515 groups = "i2c3_sck_h";
547 516 function = "i2c3";
548 517 bias-disable;
549 518 drive-strength-microamp = <3000>;
550 519 };
551 }; 520 };
552 521
553 i2c3_s 522 i2c3_sda_a_pins: i2c3-sda-a {
554 523 mux {
555 524 groups = "i2c3_sda_a";
556 525 function = "i2c3";
557 526 bias-disable;
558 527 drive-strength-microamp = <3000>;
559 528 };
560 }; 529 };
561 530
562 i2c3_s 531 i2c3_sck_a_pins: i2c3-sck-a {
563 532 mux {
564 533 groups = "i2c3_sck_a";
565 534 function = "i2c3";
566 535 bias-disable;
567 536 drive-strength-microamp = <3000>;
568 537 };
569 }; 538 };
570 539
571 mclk0_ 540 mclk0_a_pins: mclk0-a {
572 541 mux {
573 542 groups = "mclk0_a";
574 543 function = "mclk0";
575 544 bias-disable;
576 545 drive-strength-microamp = <3000>;
577 546 };
578 }; 547 };
579 548
580 mclk1_ 549 mclk1_a_pins: mclk1-a {
581 550 mux {
582 551 groups = "mclk1_a";
583 552 function = "mclk1";
584 553 bias-disable;
585 554 drive-strength-microamp = <3000>;
586 555 };
587 }; 556 };
588 557
589 mclk1_ 558 mclk1_x_pins: mclk1-x {
590 559 mux {
591 560 groups = "mclk1_x";
592 561 function = "mclk1";
593 562 bias-disable;
594 563 drive-strength-microamp = <3000>;
595 564 };
596 }; 565 };
597 566
598 mclk1_ 567 mclk1_z_pins: mclk1-z {
599 568 mux {
600 569 groups = "mclk1_z";
601 570 function = "mclk1";
602 571 bias-disable;
603 572 drive-strength-microamp = <3000>;
604 573 };
605 }; 574 };
606 575
607 nor_pi <<
608 <<
609 <<
610 <<
611 <<
612 <<
613 <<
614 <<
615 <<
616 }; <<
617 <<
618 pdm_di 576 pdm_din0_a_pins: pdm-din0-a {
619 577 mux {
620 578 groups = "pdm_din0_a";
621 579 function = "pdm";
622 580 bias-disable;
623 581 };
624 }; 582 };
625 583
626 pdm_di 584 pdm_din0_c_pins: pdm-din0-c {
627 585 mux {
628 586 groups = "pdm_din0_c";
629 587 function = "pdm";
630 588 bias-disable;
631 589 };
632 }; 590 };
633 591
634 pdm_di 592 pdm_din0_x_pins: pdm-din0-x {
635 593 mux {
636 594 groups = "pdm_din0_x";
637 595 function = "pdm";
638 596 bias-disable;
639 597 };
640 }; 598 };
641 599
642 pdm_di 600 pdm_din0_z_pins: pdm-din0-z {
643 601 mux {
644 602 groups = "pdm_din0_z";
645 603 function = "pdm";
646 604 bias-disable;
647 605 };
648 }; 606 };
649 607
650 pdm_di 608 pdm_din1_a_pins: pdm-din1-a {
651 609 mux {
652 610 groups = "pdm_din1_a";
653 611 function = "pdm";
654 612 bias-disable;
655 613 };
656 }; 614 };
657 615
658 pdm_di 616 pdm_din1_c_pins: pdm-din1-c {
659 617 mux {
660 618 groups = "pdm_din1_c";
661 619 function = "pdm";
662 620 bias-disable;
663 621 };
664 }; 622 };
665 623
666 pdm_di 624 pdm_din1_x_pins: pdm-din1-x {
667 625 mux {
668 626 groups = "pdm_din1_x";
669 627 function = "pdm";
670 628 bias-disable;
671 629 };
672 }; 630 };
673 631
674 pdm_di 632 pdm_din1_z_pins: pdm-din1-z {
675 633 mux {
676 634 groups = "pdm_din1_z";
677 635 function = "pdm";
678 636 bias-disable;
679 637 };
680 }; 638 };
681 639
682 pdm_di 640 pdm_din2_a_pins: pdm-din2-a {
683 641 mux {
684 642 groups = "pdm_din2_a";
685 643 function = "pdm";
686 644 bias-disable;
687 645 };
688 }; 646 };
689 647
690 pdm_di 648 pdm_din2_c_pins: pdm-din2-c {
691 649 mux {
692 650 groups = "pdm_din2_c";
693 651 function = "pdm";
694 652 bias-disable;
695 653 };
696 }; 654 };
697 655
698 pdm_di 656 pdm_din2_x_pins: pdm-din2-x {
699 657 mux {
700 658 groups = "pdm_din2_x";
701 659 function = "pdm";
702 660 bias-disable;
703 661 };
704 }; 662 };
705 663
706 pdm_di 664 pdm_din2_z_pins: pdm-din2-z {
707 665 mux {
708 666 groups = "pdm_din2_z";
709 667 function = "pdm";
710 668 bias-disable;
711 669 };
712 }; 670 };
713 671
714 pdm_di 672 pdm_din3_a_pins: pdm-din3-a {
715 673 mux {
716 674 groups = "pdm_din3_a";
717 675 function = "pdm";
718 676 bias-disable;
719 677 };
720 }; 678 };
721 679
722 pdm_di 680 pdm_din3_c_pins: pdm-din3-c {
723 681 mux {
724 682 groups = "pdm_din3_c";
725 683 function = "pdm";
726 684 bias-disable;
727 685 };
728 }; 686 };
729 687
730 pdm_di 688 pdm_din3_x_pins: pdm-din3-x {
731 689 mux {
732 690 groups = "pdm_din3_x";
733 691 function = "pdm";
734 692 bias-disable;
735 693 };
736 }; 694 };
737 695
738 pdm_di 696 pdm_din3_z_pins: pdm-din3-z {
739 697 mux {
740 698 groups = "pdm_din3_z";
741 699 function = "pdm";
742 700 bias-disable;
743 701 };
744 }; 702 };
745 703
746 pdm_dc 704 pdm_dclk_a_pins: pdm-dclk-a {
747 705 mux {
748 706 groups = "pdm_dclk_a";
749 707 function = "pdm";
750 708 bias-disable;
751 709 drive-strength-microamp = <500>;
752 710 };
753 }; 711 };
754 712
755 pdm_dc 713 pdm_dclk_c_pins: pdm-dclk-c {
756 714 mux {
757 715 groups = "pdm_dclk_c";
758 716 function = "pdm";
759 717 bias-disable;
760 718 drive-strength-microamp = <500>;
761 719 };
762 }; 720 };
763 721
764 pdm_dc 722 pdm_dclk_x_pins: pdm-dclk-x {
765 723 mux {
766 724 groups = "pdm_dclk_x";
767 725 function = "pdm";
768 726 bias-disable;
769 727 drive-strength-microamp = <500>;
770 728 };
771 }; 729 };
772 730
773 pdm_dc 731 pdm_dclk_z_pins: pdm-dclk-z {
774 732 mux {
775 733 groups = "pdm_dclk_z";
776 734 function = "pdm";
777 735 bias-disable;
778 736 drive-strength-microamp = <500>;
779 737 };
780 }; 738 };
781 739
782 pwm_a_ 740 pwm_a_pins: pwm-a {
783 741 mux {
784 742 groups = "pwm_a";
785 743 function = "pwm_a";
786 744 bias-disable;
787 745 };
788 }; 746 };
789 747
790 pwm_b_ 748 pwm_b_x7_pins: pwm-b-x7 {
791 749 mux {
792 750 groups = "pwm_b_x7";
793 751 function = "pwm_b";
794 752 bias-disable;
795 753 };
796 }; 754 };
797 755
798 pwm_b_ 756 pwm_b_x19_pins: pwm-b-x19 {
799 757 mux {
800 758 groups = "pwm_b_x19";
801 759 function = "pwm_b";
802 760 bias-disable;
803 761 };
804 }; 762 };
805 763
806 pwm_c_ 764 pwm_c_c_pins: pwm-c-c {
807 765 mux {
808 766 groups = "pwm_c_c";
809 767 function = "pwm_c";
810 768 bias-disable;
811 769 };
812 }; 770 };
813 771
814 pwm_c_ 772 pwm_c_x5_pins: pwm-c-x5 {
815 773 mux {
816 774 groups = "pwm_c_x5";
817 775 function = "pwm_c";
818 776 bias-disable;
819 777 };
820 }; 778 };
821 779
822 pwm_c_ 780 pwm_c_x8_pins: pwm-c-x8 {
823 781 mux {
824 782 groups = "pwm_c_x8";
825 783 function = "pwm_c";
826 784 bias-disable;
827 785 };
828 }; 786 };
829 787
830 pwm_d_ 788 pwm_d_x3_pins: pwm-d-x3 {
831 789 mux {
832 790 groups = "pwm_d_x3";
833 791 function = "pwm_d";
834 792 bias-disable;
835 793 };
836 }; 794 };
837 795
838 pwm_d_ 796 pwm_d_x6_pins: pwm-d-x6 {
839 797 mux {
840 798 groups = "pwm_d_x6";
841 799 function = "pwm_d";
842 800 bias-disable;
843 801 };
844 }; 802 };
845 803
846 pwm_e_ 804 pwm_e_pins: pwm-e {
847 805 mux {
848 806 groups = "pwm_e";
849 807 function = "pwm_e";
850 808 bias-disable;
851 809 };
852 }; 810 };
853 811
854 pwm_f_ <<
855 <<
856 <<
857 <<
858 <<
859 <<
860 }; <<
861 <<
862 pwm_f_ <<
863 <<
864 <<
865 <<
866 <<
867 <<
868 }; <<
869 <<
870 pwm_f_ 812 pwm_f_x_pins: pwm-f-x {
871 813 mux {
872 814 groups = "pwm_f_x";
873 815 function = "pwm_f";
874 816 bias-disable;
875 817 };
876 }; 818 };
877 819
878 pwm_f_ 820 pwm_f_h_pins: pwm-f-h {
879 821 mux {
880 822 groups = "pwm_f_h";
881 823 function = "pwm_f";
882 824 bias-disable;
883 825 };
884 }; 826 };
885 827
886 sdcard 828 sdcard_c_pins: sdcard_c {
887 829 mux-0 {
888 830 groups = "sdcard_d0_c",
889 831 "sdcard_d1_c",
890 832 "sdcard_d2_c",
891 833 "sdcard_d3_c",
892 834 "sdcard_cmd_c";
893 835 function = "sdcard";
894 836 bias-pull-up;
895 837 drive-strength-microamp = <4000>;
896 838 };
897 839
898 840 mux-1 {
899 841 groups = "sdcard_clk_c";
900 842 function = "sdcard";
901 843 bias-disable;
902 844 drive-strength-microamp = <4000>;
903 845 };
904 }; 846 };
905 847
906 sdcard 848 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
907 849 mux {
908 850 groups = "GPIOC_4";
909 851 function = "gpio_periphs";
910 852 bias-pull-down;
911 853 drive-strength-microamp = <4000>;
912 854 };
913 }; 855 };
914 856
915 sdcard 857 sdcard_z_pins: sdcard_z {
916 858 mux-0 {
917 859 groups = "sdcard_d0_z",
918 860 "sdcard_d1_z",
919 861 "sdcard_d2_z",
920 862 "sdcard_d3_z",
921 863 "sdcard_cmd_z";
922 864 function = "sdcard";
923 865 bias-pull-up;
924 866 drive-strength-microamp = <4000>;
925 867 };
926 868
927 869 mux-1 {
928 870 groups = "sdcard_clk_z";
929 871 function = "sdcard";
930 872 bias-disable;
931 873 drive-strength-microamp = <4000>;
932 874 };
933 }; 875 };
934 876
935 sdcard 877 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
936 878 mux {
937 879 groups = "GPIOZ_6";
938 880 function = "gpio_periphs";
939 881 bias-pull-down;
940 882 drive-strength-microamp = <4000>;
941 883 };
942 }; 884 };
943 885
944 sdio_p 886 sdio_pins: sdio {
945 887 mux {
946 888 groups = "sdio_d0",
947 889 "sdio_d1",
948 890 "sdio_d2",
949 891 "sdio_d3",
950 892 "sdio_clk",
951 893 "sdio_cmd";
952 894 function = "sdio";
953 895 bias-disable;
954 896 drive-strength-microamp = <4000>;
955 897 };
956 }; 898 };
957 899
958 sdio_c 900 sdio_clk_gate_pins: sdio_clk_gate {
959 901 mux {
960 902 groups = "GPIOX_4";
961 903 function = "gpio_periphs";
962 904 bias-pull-down;
963 905 drive-strength-microamp = <4000>;
964 906 };
965 }; 907 };
966 908
967 spdif_ 909 spdif_in_a10_pins: spdif-in-a10 {
968 910 mux {
969 911 groups = "spdif_in_a10";
970 912 function = "spdif_in";
971 913 bias-disable;
972 914 };
973 }; 915 };
974 916
975 spdif_ 917 spdif_in_a12_pins: spdif-in-a12 {
976 918 mux {
977 919 groups = "spdif_in_a12";
978 920 function = "spdif_in";
979 921 bias-disable;
980 922 };
981 }; 923 };
982 924
983 spdif_ 925 spdif_in_h_pins: spdif-in-h {
984 926 mux {
985 927 groups = "spdif_in_h";
986 928 function = "spdif_in";
987 929 bias-disable;
988 930 };
989 }; 931 };
990 932
991 spdif_ 933 spdif_out_h_pins: spdif-out-h {
992 934 mux {
993 935 groups = "spdif_out_h";
994 936 function = "spdif_out";
995 !! 937 drive-strength-microamp = <500>;
996 938 bias-disable;
997 939 };
998 }; 940 };
999 941
1000 spdif 942 spdif_out_a11_pins: spdif-out-a11 {
1001 943 mux {
1002 944 groups = "spdif_out_a11";
1003 945 function = "spdif_out";
1004 !! 946 drive-strength-microamp = <500>;
1005 947 bias-disable;
1006 948 };
1007 }; 949 };
1008 950
1009 spdif 951 spdif_out_a13_pins: spdif-out-a13 {
1010 952 mux {
1011 953 groups = "spdif_out_a13";
1012 954 function = "spdif_out";
1013 !! 955 drive-strength-microamp = <500>;
1014 <<
1015 <<
1016 }; <<
1017 <<
1018 spicc <<
1019 <<
1020 <<
1021 <<
1022 <<
1023 <<
1024 <<
1025 <<
1026 <<
1027 }; <<
1028 <<
1029 spicc <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 <<
1035 <<
1036 }; <<
1037 <<
1038 spicc <<
1039 <<
1040 <<
1041 <<
1042 <<
1043 <<
1044 <<
1045 <<
1046 <<
1047 <<
1048 }; <<
1049 <<
1050 spicc <<
1051 <<
1052 <<
1053 <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 }; <<
1059 <<
1060 spicc <<
1061 <<
1062 <<
1063 <<
1064 <<
1065 956 bias-disable;
1066 957 };
1067 }; 958 };
1068 959
1069 tdm_a 960 tdm_a_din0_pins: tdm-a-din0 {
1070 961 mux {
1071 962 groups = "tdm_a_din0";
1072 963 function = "tdm_a";
1073 964 bias-disable;
1074 965 };
1075 }; 966 };
1076 967
1077 968
1078 tdm_a 969 tdm_a_din1_pins: tdm-a-din1 {
1079 970 mux {
1080 971 groups = "tdm_a_din1";
1081 972 function = "tdm_a";
1082 973 bias-disable;
1083 974 };
1084 }; 975 };
1085 976
1086 tdm_a 977 tdm_a_dout0_pins: tdm-a-dout0 {
1087 978 mux {
1088 979 groups = "tdm_a_dout0";
1089 980 function = "tdm_a";
1090 981 bias-disable;
1091 982 drive-strength-microamp = <3000>;
1092 983 };
1093 }; 984 };
1094 985
1095 tdm_a 986 tdm_a_dout1_pins: tdm-a-dout1 {
1096 987 mux {
1097 988 groups = "tdm_a_dout1";
1098 989 function = "tdm_a";
1099 990 bias-disable;
1100 991 drive-strength-microamp = <3000>;
1101 992 };
1102 }; 993 };
1103 994
1104 tdm_a 995 tdm_a_fs_pins: tdm-a-fs {
1105 996 mux {
1106 997 groups = "tdm_a_fs";
1107 998 function = "tdm_a";
1108 999 bias-disable;
1109 1000 drive-strength-microamp = <3000>;
1110 1001 };
1111 }; 1002 };
1112 1003
1113 tdm_a 1004 tdm_a_sclk_pins: tdm-a-sclk {
1114 1005 mux {
1115 1006 groups = "tdm_a_sclk";
1116 1007 function = "tdm_a";
1117 1008 bias-disable;
1118 1009 drive-strength-microamp = <3000>;
1119 1010 };
1120 }; 1011 };
1121 1012
1122 tdm_a 1013 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1123 1014 mux {
1124 1015 groups = "tdm_a_slv_fs";
1125 1016 function = "tdm_a";
1126 1017 bias-disable;
1127 1018 };
1128 }; 1019 };
1129 1020
1130 1021
1131 tdm_a 1022 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1132 1023 mux {
1133 1024 groups = "tdm_a_slv_sclk";
1134 1025 function = "tdm_a";
1135 1026 bias-disable;
1136 1027 };
1137 }; 1028 };
1138 1029
1139 tdm_b 1030 tdm_b_din0_pins: tdm-b-din0 {
1140 1031 mux {
1141 1032 groups = "tdm_b_din0";
1142 1033 function = "tdm_b";
1143 1034 bias-disable;
1144 1035 };
1145 }; 1036 };
1146 1037
1147 tdm_b 1038 tdm_b_din1_pins: tdm-b-din1 {
1148 1039 mux {
1149 1040 groups = "tdm_b_din1";
1150 1041 function = "tdm_b";
1151 1042 bias-disable;
1152 1043 };
1153 }; 1044 };
1154 1045
1155 tdm_b 1046 tdm_b_din2_pins: tdm-b-din2 {
1156 1047 mux {
1157 1048 groups = "tdm_b_din2";
1158 1049 function = "tdm_b";
1159 1050 bias-disable;
1160 1051 };
1161 }; 1052 };
1162 1053
1163 tdm_b 1054 tdm_b_din3_a_pins: tdm-b-din3-a {
1164 1055 mux {
1165 1056 groups = "tdm_b_din3_a";
1166 1057 function = "tdm_b";
1167 1058 bias-disable;
1168 1059 };
1169 }; 1060 };
1170 1061
1171 tdm_b 1062 tdm_b_din3_h_pins: tdm-b-din3-h {
1172 1063 mux {
1173 1064 groups = "tdm_b_din3_h";
1174 1065 function = "tdm_b";
1175 1066 bias-disable;
1176 1067 };
1177 }; 1068 };
1178 1069
1179 tdm_b 1070 tdm_b_dout0_pins: tdm-b-dout0 {
1180 1071 mux {
1181 1072 groups = "tdm_b_dout0";
1182 1073 function = "tdm_b";
1183 1074 bias-disable;
1184 1075 drive-strength-microamp = <3000>;
1185 1076 };
1186 }; 1077 };
1187 1078
1188 tdm_b 1079 tdm_b_dout1_pins: tdm-b-dout1 {
1189 1080 mux {
1190 1081 groups = "tdm_b_dout1";
1191 1082 function = "tdm_b";
1192 1083 bias-disable;
1193 1084 drive-strength-microamp = <3000>;
1194 1085 };
1195 }; 1086 };
1196 1087
1197 tdm_b 1088 tdm_b_dout2_pins: tdm-b-dout2 {
1198 1089 mux {
1199 1090 groups = "tdm_b_dout2";
1200 1091 function = "tdm_b";
1201 1092 bias-disable;
1202 1093 drive-strength-microamp = <3000>;
1203 1094 };
1204 }; 1095 };
1205 1096
1206 tdm_b 1097 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1207 1098 mux {
1208 1099 groups = "tdm_b_dout3_a";
1209 1100 function = "tdm_b";
1210 1101 bias-disable;
1211 1102 drive-strength-microamp = <3000>;
1212 1103 };
1213 }; 1104 };
1214 1105
1215 tdm_b 1106 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1216 1107 mux {
1217 1108 groups = "tdm_b_dout3_h";
1218 1109 function = "tdm_b";
1219 1110 bias-disable;
1220 1111 drive-strength-microamp = <3000>;
1221 1112 };
1222 }; 1113 };
1223 1114
1224 tdm_b 1115 tdm_b_fs_pins: tdm-b-fs {
1225 1116 mux {
1226 1117 groups = "tdm_b_fs";
1227 1118 function = "tdm_b";
1228 1119 bias-disable;
1229 1120 drive-strength-microamp = <3000>;
1230 1121 };
1231 }; 1122 };
1232 1123
1233 tdm_b 1124 tdm_b_sclk_pins: tdm-b-sclk {
1234 1125 mux {
1235 1126 groups = "tdm_b_sclk";
1236 1127 function = "tdm_b";
1237 1128 bias-disable;
1238 1129 drive-strength-microamp = <3000>;
1239 1130 };
1240 }; 1131 };
1241 1132
1242 tdm_b 1133 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1243 1134 mux {
1244 1135 groups = "tdm_b_slv_fs";
1245 1136 function = "tdm_b";
1246 1137 bias-disable;
1247 1138 };
1248 }; 1139 };
1249 1140
1250 tdm_b 1141 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1251 1142 mux {
1252 1143 groups = "tdm_b_slv_sclk";
1253 1144 function = "tdm_b";
1254 1145 bias-disable;
1255 1146 };
1256 }; 1147 };
1257 1148
1258 tdm_c 1149 tdm_c_din0_a_pins: tdm-c-din0-a {
1259 1150 mux {
1260 1151 groups = "tdm_c_din0_a";
1261 1152 function = "tdm_c";
1262 1153 bias-disable;
1263 1154 };
1264 }; 1155 };
1265 1156
1266 tdm_c 1157 tdm_c_din0_z_pins: tdm-c-din0-z {
1267 1158 mux {
1268 1159 groups = "tdm_c_din0_z";
1269 1160 function = "tdm_c";
1270 1161 bias-disable;
1271 1162 };
1272 }; 1163 };
1273 1164
1274 tdm_c 1165 tdm_c_din1_a_pins: tdm-c-din1-a {
1275 1166 mux {
1276 1167 groups = "tdm_c_din1_a";
1277 1168 function = "tdm_c";
1278 1169 bias-disable;
1279 1170 };
1280 }; 1171 };
1281 1172
1282 tdm_c 1173 tdm_c_din1_z_pins: tdm-c-din1-z {
1283 1174 mux {
1284 1175 groups = "tdm_c_din1_z";
1285 1176 function = "tdm_c";
1286 1177 bias-disable;
1287 1178 };
1288 }; 1179 };
1289 1180
1290 tdm_c 1181 tdm_c_din2_a_pins: tdm-c-din2-a {
1291 1182 mux {
1292 1183 groups = "tdm_c_din2_a";
1293 1184 function = "tdm_c";
1294 1185 bias-disable;
1295 1186 };
1296 }; 1187 };
1297 1188
1298 eth_l 1189 eth_leds_pins: eth-leds {
1299 1190 mux {
1300 1191 groups = "eth_link_led",
1301 1192 "eth_act_led";
1302 1193 function = "eth";
1303 1194 bias-disable;
1304 1195 };
1305 }; 1196 };
1306 1197
1307 eth_p 1198 eth_pins: eth {
1308 1199 mux {
1309 1200 groups = "eth_mdio",
1310 1201 "eth_mdc",
1311 1202 "eth_rgmii_rx_clk",
1312 1203 "eth_rx_dv",
1313 1204 "eth_rxd0",
1314 1205 "eth_rxd1",
1315 1206 "eth_txen",
1316 1207 "eth_txd0",
1317 1208 "eth_txd1";
1318 1209 function = "eth";
1319 1210 drive-strength-microamp = <4000>;
1320 1211 bias-disable;
1321 1212 };
1322 }; 1213 };
1323 1214
1324 eth_r 1215 eth_rgmii_pins: eth-rgmii {
1325 1216 mux {
1326 1217 groups = "eth_rxd2_rgmii",
1327 1218 "eth_rxd3_rgmii",
1328 1219 "eth_rgmii_tx_clk",
1329 1220 "eth_txd2_rgmii",
1330 1221 "eth_txd3_rgmii";
1331 1222 function = "eth";
1332 1223 drive-strength-microamp = <4000>;
1333 1224 bias-disable;
1334 1225 };
1335 }; 1226 };
1336 1227
1337 tdm_c 1228 tdm_c_din2_z_pins: tdm-c-din2-z {
1338 1229 mux {
1339 1230 groups = "tdm_c_din2_z";
1340 1231 function = "tdm_c";
1341 1232 bias-disable;
1342 1233 };
1343 }; 1234 };
1344 1235
1345 tdm_c 1236 tdm_c_din3_a_pins: tdm-c-din3-a {
1346 1237 mux {
1347 1238 groups = "tdm_c_din3_a";
1348 1239 function = "tdm_c";
1349 1240 bias-disable;
1350 1241 };
1351 }; 1242 };
1352 1243
1353 tdm_c 1244 tdm_c_din3_z_pins: tdm-c-din3-z {
1354 1245 mux {
1355 1246 groups = "tdm_c_din3_z";
1356 1247 function = "tdm_c";
1357 1248 bias-disable;
1358 1249 };
1359 }; 1250 };
1360 1251
1361 tdm_c 1252 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1362 1253 mux {
1363 1254 groups = "tdm_c_dout0_a";
1364 1255 function = "tdm_c";
1365 1256 bias-disable;
1366 1257 drive-strength-microamp = <3000>;
1367 1258 };
1368 }; 1259 };
1369 1260
1370 tdm_c 1261 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1371 1262 mux {
1372 1263 groups = "tdm_c_dout0_z";
1373 1264 function = "tdm_c";
1374 1265 bias-disable;
1375 1266 drive-strength-microamp = <3000>;
1376 1267 };
1377 }; 1268 };
1378 1269
1379 tdm_c 1270 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1380 1271 mux {
1381 1272 groups = "tdm_c_dout1_a";
1382 1273 function = "tdm_c";
1383 1274 bias-disable;
1384 1275 drive-strength-microamp = <3000>;
1385 1276 };
1386 }; 1277 };
1387 1278
1388 tdm_c 1279 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1389 1280 mux {
1390 1281 groups = "tdm_c_dout1_z";
1391 1282 function = "tdm_c";
1392 1283 bias-disable;
1393 1284 drive-strength-microamp = <3000>;
1394 1285 };
1395 }; 1286 };
1396 1287
1397 tdm_c 1288 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1398 1289 mux {
1399 1290 groups = "tdm_c_dout2_a";
1400 1291 function = "tdm_c";
1401 1292 bias-disable;
1402 1293 drive-strength-microamp = <3000>;
1403 1294 };
1404 }; 1295 };
1405 1296
1406 tdm_c 1297 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1407 1298 mux {
1408 1299 groups = "tdm_c_dout2_z";
1409 1300 function = "tdm_c";
1410 1301 bias-disable;
1411 1302 drive-strength-microamp = <3000>;
1412 1303 };
1413 }; 1304 };
1414 1305
1415 tdm_c 1306 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1416 1307 mux {
1417 1308 groups = "tdm_c_dout3_a";
1418 1309 function = "tdm_c";
1419 1310 bias-disable;
1420 1311 drive-strength-microamp = <3000>;
1421 1312 };
1422 }; 1313 };
1423 1314
1424 tdm_c 1315 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1425 1316 mux {
1426 1317 groups = "tdm_c_dout3_z";
1427 1318 function = "tdm_c";
1428 1319 bias-disable;
1429 1320 drive-strength-microamp = <3000>;
1430 1321 };
1431 }; 1322 };
1432 1323
1433 tdm_c 1324 tdm_c_fs_a_pins: tdm-c-fs-a {
1434 1325 mux {
1435 1326 groups = "tdm_c_fs_a";
1436 1327 function = "tdm_c";
1437 1328 bias-disable;
1438 1329 drive-strength-microamp = <3000>;
1439 1330 };
1440 }; 1331 };
1441 1332
1442 tdm_c 1333 tdm_c_fs_z_pins: tdm-c-fs-z {
1443 1334 mux {
1444 1335 groups = "tdm_c_fs_z";
1445 1336 function = "tdm_c";
1446 1337 bias-disable;
1447 1338 drive-strength-microamp = <3000>;
1448 1339 };
1449 }; 1340 };
1450 1341
1451 tdm_c 1342 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1452 1343 mux {
1453 1344 groups = "tdm_c_sclk_a";
1454 1345 function = "tdm_c";
1455 1346 bias-disable;
1456 1347 drive-strength-microamp = <3000>;
1457 1348 };
1458 }; 1349 };
1459 1350
1460 tdm_c 1351 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1461 1352 mux {
1462 1353 groups = "tdm_c_sclk_z";
1463 1354 function = "tdm_c";
1464 1355 bias-disable;
1465 1356 drive-strength-microamp = <3000>;
1466 1357 };
1467 }; 1358 };
1468 1359
1469 tdm_c 1360 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1470 1361 mux {
1471 1362 groups = "tdm_c_slv_fs_a";
1472 1363 function = "tdm_c";
1473 1364 bias-disable;
1474 1365 };
1475 }; 1366 };
1476 1367
1477 tdm_c 1368 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1478 1369 mux {
1479 1370 groups = "tdm_c_slv_fs_z";
1480 1371 function = "tdm_c";
1481 1372 bias-disable;
1482 1373 };
1483 }; 1374 };
1484 1375
1485 tdm_c 1376 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1486 1377 mux {
1487 1378 groups = "tdm_c_slv_sclk_a";
1488 1379 function = "tdm_c";
1489 1380 bias-disable;
1490 1381 };
1491 }; 1382 };
1492 1383
1493 tdm_c 1384 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1494 1385 mux {
1495 1386 groups = "tdm_c_slv_sclk_z";
1496 1387 function = "tdm_c";
1497 1388 bias-disable;
1498 1389 };
1499 }; 1390 };
1500 1391
1501 uart_ 1392 uart_a_pins: uart-a {
1502 1393 mux {
1503 1394 groups = "uart_a_tx",
1504 1395 "uart_a_rx";
1505 1396 function = "uart_a";
1506 1397 bias-disable;
1507 1398 };
1508 }; 1399 };
1509 1400
1510 uart_ 1401 uart_a_cts_rts_pins: uart-a-cts-rts {
1511 1402 mux {
1512 1403 groups = "uart_a_cts",
1513 1404 "uart_a_rts";
1514 1405 function = "uart_a";
1515 1406 bias-disable;
1516 1407 };
1517 }; 1408 };
1518 1409
1519 uart_ 1410 uart_b_pins: uart-b {
1520 1411 mux {
1521 1412 groups = "uart_b_tx",
1522 1413 "uart_b_rx";
1523 1414 function = "uart_b";
1524 1415 bias-disable;
1525 1416 };
1526 }; 1417 };
1527 1418
1528 uart_ 1419 uart_c_pins: uart-c {
1529 1420 mux {
1530 1421 groups = "uart_c_tx",
1531 1422 "uart_c_rx";
1532 1423 function = "uart_c";
1533 1424 bias-disable;
1534 1425 };
1535 }; 1426 };
1536 1427
1537 uart_ 1428 uart_c_cts_rts_pins: uart-c-cts-rts {
1538 1429 mux {
1539 1430 groups = "uart_c_cts",
1540 1431 "uart_c_rts";
1541 1432 function = "uart_c";
1542 1433 bias-disable;
1543 1434 };
1544 }; 1435 };
1545 }; 1436 };
1546 }; 1437 };
1547 1438
1548 cpu_temp: temperature 1439 cpu_temp: temperature-sensor@34800 {
1549 compatible = 1440 compatible = "amlogic,g12a-cpu-thermal",
1550 1441 "amlogic,g12a-thermal";
1551 reg = <0x0 0x 1442 reg = <0x0 0x34800 0x0 0x50>;
1552 interrupts = 1443 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1553 clocks = <&cl 1444 clocks = <&clkc CLKID_TS>;
1554 #thermal-sens 1445 #thermal-sensor-cells = <0>;
1555 amlogic,ao-se 1446 amlogic,ao-secure = <&sec_AO>;
1556 }; 1447 };
1557 1448
1558 ddr_temp: temperature 1449 ddr_temp: temperature-sensor@34c00 {
1559 compatible = 1450 compatible = "amlogic,g12a-ddr-thermal",
1560 1451 "amlogic,g12a-thermal";
1561 reg = <0x0 0x 1452 reg = <0x0 0x34c00 0x0 0x50>;
1562 interrupts = 1453 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1563 clocks = <&cl 1454 clocks = <&clkc CLKID_TS>;
1564 #thermal-sens 1455 #thermal-sensor-cells = <0>;
1565 amlogic,ao-se 1456 amlogic,ao-secure = <&sec_AO>;
1566 }; 1457 };
1567 1458
1568 usb2_phy0: phy@36000 1459 usb2_phy0: phy@36000 {
1569 compatible = 1460 compatible = "amlogic,g12a-usb2-phy";
1570 reg = <0x0 0x 1461 reg = <0x0 0x36000 0x0 0x2000>;
1571 clocks = <&xt 1462 clocks = <&xtal>;
1572 clock-names = 1463 clock-names = "xtal";
1573 resets = <&re 1464 resets = <&reset RESET_USB_PHY20>;
1574 reset-names = 1465 reset-names = "phy";
1575 #phy-cells = 1466 #phy-cells = <0>;
1576 }; 1467 };
1577 1468
1578 dmc: bus@38000 { 1469 dmc: bus@38000 {
1579 compatible = 1470 compatible = "simple-bus";
>> 1471 reg = <0x0 0x38000 0x0 0x400>;
1580 #address-cell 1472 #address-cells = <2>;
1581 #size-cells = 1473 #size-cells = <2>;
1582 ranges = <0x0 !! 1474 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1583 1475
1584 canvas: video 1476 canvas: video-lut@48 {
1585 compa 1477 compatible = "amlogic,canvas";
1586 reg = 1478 reg = <0x0 0x48 0x0 0x14>;
1587 }; 1479 };
1588 <<
1589 pmu: pmu@80 { <<
1590 reg = <<
1591 <<
1592 inter <<
1593 }; <<
1594 }; 1480 };
1595 1481
1596 usb2_phy1: phy@3a000 1482 usb2_phy1: phy@3a000 {
1597 compatible = 1483 compatible = "amlogic,g12a-usb2-phy";
1598 reg = <0x0 0x 1484 reg = <0x0 0x3a000 0x0 0x2000>;
1599 clocks = <&xt 1485 clocks = <&xtal>;
1600 clock-names = 1486 clock-names = "xtal";
1601 resets = <&re 1487 resets = <&reset RESET_USB_PHY21>;
1602 reset-names = 1488 reset-names = "phy";
1603 #phy-cells = 1489 #phy-cells = <0>;
1604 }; 1490 };
1605 1491
1606 hiu: bus@3c000 { 1492 hiu: bus@3c000 {
1607 compatible = 1493 compatible = "simple-bus";
1608 reg = <0x0 0x 1494 reg = <0x0 0x3c000 0x0 0x1400>;
1609 #address-cell 1495 #address-cells = <2>;
1610 #size-cells = 1496 #size-cells = <2>;
1611 ranges = <0x0 1497 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1612 1498
1613 hhi: system-c 1499 hhi: system-controller@0 {
1614 compa 1500 compatible = "amlogic,meson-gx-hhi-sysctrl",
1615 1501 "simple-mfd", "syscon";
1616 reg = 1502 reg = <0 0 0 0x400>;
1617 1503
1618 clkc: 1504 clkc: clock-controller {
1619 1505 compatible = "amlogic,g12a-clkc";
1620 1506 #clock-cells = <1>;
1621 1507 clocks = <&xtal>;
1622 1508 clock-names = "xtal";
1623 }; 1509 };
1624 1510
1625 pwrc: 1511 pwrc: power-controller {
1626 1512 compatible = "amlogic,meson-g12a-pwrc";
1627 1513 #power-domain-cells = <1>;
1628 1514 amlogic,ao-sysctrl = <&rti>;
1629 1515 resets = <&reset RESET_VIU>,
1630 1516 <&reset RESET_VENC>,
1631 1517 <&reset RESET_VCBUS>,
1632 1518 <&reset RESET_BT656>,
1633 1519 <&reset RESET_RDMA>,
1634 1520 <&reset RESET_VENCI>,
1635 1521 <&reset RESET_VENCP>,
1636 1522 <&reset RESET_VDAC>,
1637 1523 <&reset RESET_VDI6>,
1638 1524 <&reset RESET_VENCL>,
1639 1525 <&reset RESET_VID_LOCK>;
1640 1526 reset-names = "viu", "venc", "vcbus", "bt656",
1641 1527 "rdma", "venci", "vencp", "vdac",
1642 1528 "vdi6", "vencl", "vid_lock";
1643 1529 clocks = <&clkc CLKID_VPU>,
1644 1530 <&clkc CLKID_VAPB>;
1645 1531 clock-names = "vpu", "vapb";
1646 1532 /*
1647 1533 * VPU clocking is provided by two identical clock paths
1648 1534 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1649 1535 * free mux to safely change frequency while running.
1650 1536 * Same for VAPB but with a final gate after the glitch free mux.
1651 1537 */
1652 1538 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1653 1539 <&clkc CLKID_VPU_0>,
1654 1540 <&clkc CLKID_VPU>, /* Glitch free mux */
1655 1541 <&clkc CLKID_VAPB_0_SEL>,
1656 1542 <&clkc CLKID_VAPB_0>,
1657 1543 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1658 1544 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1659 1545 <0>, /* Do Nothing */
1660 1546 <&clkc CLKID_VPU_0>,
1661 1547 <&clkc CLKID_FCLK_DIV4>,
1662 1548 <0>, /* Do Nothing */
1663 1549 <&clkc CLKID_VAPB_0>;
1664 1550 assigned-clock-rates = <0>, /* Do Nothing */
1665 1551 <666666666>,
1666 1552 <0>, /* Do Nothing */
1667 1553 <0>, /* Do Nothing */
1668 1554 <250000000>,
1669 1555 <0>; /* Do Nothing */
1670 }; 1556 };
1671 <<
1672 mipi_ <<
1673 <<
1674 <<
1675 <<
1676 }; <<
1677 }; 1557 };
1678 }; 1558 };
1679 1559
1680 mipi_dphy: phy@44000 <<
1681 compatible = <<
1682 reg = <0x0 0x <<
1683 clocks = <&cl <<
1684 clock-names = <<
1685 resets = <&re <<
1686 reset-names = <<
1687 phys = <&mipi <<
1688 phy-names = " <<
1689 #phy-cells = <<
1690 status = "dis <<
1691 }; <<
1692 <<
1693 usb3_pcie_phy: phy@46 1560 usb3_pcie_phy: phy@46000 {
1694 compatible = 1561 compatible = "amlogic,g12a-usb3-pcie-phy";
1695 reg = <0x0 0x 1562 reg = <0x0 0x46000 0x0 0x2000>;
1696 clocks = <&cl 1563 clocks = <&clkc CLKID_PCIE_PLL>;
1697 clock-names = 1564 clock-names = "ref_clk";
1698 resets = <&re 1565 resets = <&reset RESET_PCIE_PHY>;
1699 reset-names = 1566 reset-names = "phy";
1700 assigned-cloc 1567 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1701 assigned-cloc 1568 assigned-clock-rates = <100000000>;
1702 #phy-cells = 1569 #phy-cells = <1>;
1703 }; 1570 };
1704 1571
1705 eth_phy: mdio-multipl 1572 eth_phy: mdio-multiplexer@4c000 {
1706 compatible = 1573 compatible = "amlogic,g12a-mdio-mux";
1707 reg = <0x0 0x 1574 reg = <0x0 0x4c000 0x0 0xa4>;
1708 clocks = <&cl 1575 clocks = <&clkc CLKID_ETH_PHY>,
1709 <&xt 1576 <&xtal>,
1710 <&cl 1577 <&clkc CLKID_MPLL_50M>;
1711 clock-names = 1578 clock-names = "pclk", "clkin0", "clkin1";
1712 mdio-parent-b 1579 mdio-parent-bus = <&mdio0>;
1713 #address-cell 1580 #address-cells = <1>;
1714 #size-cells = 1581 #size-cells = <0>;
1715 1582
1716 ext_mdio: mdi 1583 ext_mdio: mdio@0 {
1717 reg = 1584 reg = <0>;
1718 #addr 1585 #address-cells = <1>;
1719 #size 1586 #size-cells = <0>;
1720 }; 1587 };
1721 1588
1722 int_mdio: mdi 1589 int_mdio: mdio@1 {
1723 reg = 1590 reg = <1>;
1724 #addr 1591 #address-cells = <1>;
1725 #size 1592 #size-cells = <0>;
1726 1593
1727 inter !! 1594 internal_ephy: ethernet_phy@8 {
1728 1595 compatible = "ethernet-phy-id0180.3301",
1729 1596 "ethernet-phy-ieee802.3-c22";
1730 1597 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1731 1598 reg = <8>;
1732 1599 max-speed = <100>;
1733 }; 1600 };
1734 }; 1601 };
1735 }; 1602 };
1736 }; 1603 };
1737 1604
1738 aobus: bus@ff800000 { 1605 aobus: bus@ff800000 {
1739 compatible = "simple- 1606 compatible = "simple-bus";
1740 reg = <0x0 0xff800000 1607 reg = <0x0 0xff800000 0x0 0x100000>;
1741 #address-cells = <2>; 1608 #address-cells = <2>;
1742 #size-cells = <2>; 1609 #size-cells = <2>;
1743 ranges = <0x0 0x0 0x0 1610 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1744 1611
1745 rti: sys-ctrl@0 { 1612 rti: sys-ctrl@0 {
1746 compatible = 1613 compatible = "amlogic,meson-gx-ao-sysctrl",
1747 1614 "simple-mfd", "syscon";
1748 reg = <0x0 0x 1615 reg = <0x0 0x0 0x0 0x100>;
>> 1616 #address-cells = <2>;
>> 1617 #size-cells = <2>;
>> 1618 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1749 1619
1750 clkc_AO: cloc 1620 clkc_AO: clock-controller {
1751 compa 1621 compatible = "amlogic,meson-g12a-aoclkc";
1752 #cloc 1622 #clock-cells = <1>;
1753 #rese 1623 #reset-cells = <1>;
1754 clock 1624 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1755 clock 1625 clock-names = "xtal", "mpeg-clk";
1756 }; 1626 };
1757 }; <<
1758 <<
1759 ao_pinctrl: pinctrl@1 <<
1760 compatible = <<
1761 #address-cell <<
1762 #size-cells = <<
1763 ranges; <<
1764 <<
1765 gpio_ao: bank <<
1766 reg = <<
1767 <<
1768 <<
1769 reg-n <<
1770 <<
1771 <<
1772 gpio- <<
1773 #gpio <<
1774 gpio- <<
1775 }; <<
1776 <<
1777 i2c_ao_sck_pi <<
1778 mux { <<
1779 <<
1780 <<
1781 <<
1782 <<
1783 }; <<
1784 }; <<
1785 1627
1786 i2c_ao_sda_pi !! 1628 ao_pinctrl: pinctrl@14 {
1787 mux { !! 1629 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1788 !! 1630 #address-cells = <2>;
1789 !! 1631 #size-cells = <2>;
1790 !! 1632 ranges;
1791 <<
1792 }; <<
1793 }; <<
1794 1633
1795 i2c_ao_sck_e_ !! 1634 gpio_ao: bank@14 {
1796 mux { !! 1635 reg = <0x0 0x14 0x0 0x8>,
1797 !! 1636 <0x0 0x1c 0x0 0x8>,
1798 !! 1637 <0x0 0x24 0x0 0x14>;
1799 !! 1638 reg-names = "mux",
1800 !! 1639 "ds",
>> 1640 "gpio";
>> 1641 gpio-controller;
>> 1642 #gpio-cells = <2>;
>> 1643 gpio-ranges = <&ao_pinctrl 0 0 15>;
1801 }; 1644 };
1802 }; <<
1803 1645
1804 i2c_ao_sda_e_ !! 1646 i2c_ao_sck_pins: i2c_ao_sck_pins {
1805 mux { !! 1647 mux {
1806 !! 1648 groups = "i2c_ao_sck";
1807 !! 1649 function = "i2c_ao";
1808 !! 1650 bias-disable;
1809 !! 1651 drive-strength-microamp = <3000>;
>> 1652 };
1810 }; 1653 };
1811 }; <<
1812 1654
1813 mclk0_ao_pins !! 1655 i2c_ao_sda_pins: i2c_ao_sda {
1814 mux { !! 1656 mux {
1815 !! 1657 groups = "i2c_ao_sda";
1816 !! 1658 function = "i2c_ao";
1817 !! 1659 bias-disable;
1818 !! 1660 drive-strength-microamp = <3000>;
>> 1661 };
1819 }; 1662 };
1820 }; <<
1821 1663
1822 tdm_ao_b_din0 !! 1664 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1823 mux { !! 1665 mux {
1824 !! 1666 groups = "i2c_ao_sck_e";
1825 !! 1667 function = "i2c_ao";
1826 !! 1668 bias-disable;
>> 1669 drive-strength-microamp = <3000>;
>> 1670 };
1827 }; 1671 };
1828 }; <<
1829 1672
1830 spdif_ao_out_ !! 1673 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1831 mux { !! 1674 mux {
1832 !! 1675 groups = "i2c_ao_sda_e";
1833 !! 1676 function = "i2c_ao";
1834 !! 1677 bias-disable;
1835 !! 1678 drive-strength-microamp = <3000>;
>> 1679 };
1836 }; 1680 };
1837 }; <<
1838 1681
1839 tdm_ao_b_din1 !! 1682 mclk0_ao_pins: mclk0-ao {
1840 mux { !! 1683 mux {
1841 !! 1684 groups = "mclk0_ao";
1842 !! 1685 function = "mclk0_ao";
1843 !! 1686 bias-disable;
>> 1687 drive-strength-microamp = <3000>;
>> 1688 };
1844 }; 1689 };
1845 }; <<
1846 1690
1847 tdm_ao_b_din2 !! 1691 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1848 mux { !! 1692 mux {
1849 !! 1693 groups = "tdm_ao_b_din0";
1850 !! 1694 function = "tdm_ao_b";
1851 !! 1695 bias-disable;
>> 1696 };
1852 }; 1697 };
1853 }; <<
1854 1698
1855 tdm_ao_b_dout !! 1699 spdif_ao_out_pins: spdif-ao-out {
1856 mux { !! 1700 mux {
1857 !! 1701 groups = "spdif_ao_out";
1858 !! 1702 function = "spdif_ao_out";
1859 !! 1703 drive-strength-microamp = <500>;
1860 !! 1704 bias-disable;
>> 1705 };
1861 }; 1706 };
1862 }; <<
1863 1707
1864 tdm_ao_b_dout !! 1708 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1865 mux { !! 1709 mux {
1866 !! 1710 groups = "tdm_ao_b_din1";
1867 !! 1711 function = "tdm_ao_b";
1868 !! 1712 bias-disable;
1869 !! 1713 };
1870 }; 1714 };
1871 }; <<
1872 1715
1873 tdm_ao_b_dout !! 1716 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1874 mux { !! 1717 mux {
1875 !! 1718 groups = "tdm_ao_b_din2";
1876 !! 1719 function = "tdm_ao_b";
1877 !! 1720 bias-disable;
1878 !! 1721 };
1879 }; 1722 };
1880 }; <<
1881 1723
1882 tdm_ao_b_fs_p !! 1724 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1883 mux { !! 1725 mux {
1884 !! 1726 groups = "tdm_ao_b_dout0";
1885 !! 1727 function = "tdm_ao_b";
1886 !! 1728 bias-disable;
1887 !! 1729 drive-strength-microamp = <3000>;
>> 1730 };
1888 }; 1731 };
1889 }; <<
1890 1732
1891 tdm_ao_b_sclk !! 1733 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1892 mux { !! 1734 mux {
1893 !! 1735 groups = "tdm_ao_b_dout1";
1894 !! 1736 function = "tdm_ao_b";
1895 !! 1737 bias-disable;
1896 !! 1738 drive-strength-microamp = <3000>;
>> 1739 };
1897 }; 1740 };
1898 }; <<
1899 1741
1900 tdm_ao_b_slv_ !! 1742 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1901 mux { !! 1743 mux {
1902 !! 1744 groups = "tdm_ao_b_dout2";
1903 !! 1745 function = "tdm_ao_b";
1904 !! 1746 bias-disable;
>> 1747 drive-strength-microamp = <3000>;
>> 1748 };
1905 }; 1749 };
1906 }; <<
1907 1750
1908 tdm_ao_b_slv_ !! 1751 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1909 mux { !! 1752 mux {
1910 !! 1753 groups = "tdm_ao_b_fs";
1911 !! 1754 function = "tdm_ao_b";
1912 !! 1755 bias-disable;
>> 1756 drive-strength-microamp = <3000>;
>> 1757 };
1913 }; 1758 };
1914 }; <<
1915 1759
1916 uart_ao_a_pin !! 1760 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1917 mux { !! 1761 mux {
1918 !! 1762 groups = "tdm_ao_b_sclk";
1919 !! 1763 function = "tdm_ao_b";
1920 !! 1764 bias-disable;
1921 !! 1765 drive-strength-microamp = <3000>;
>> 1766 };
1922 }; 1767 };
1923 }; <<
1924 1768
1925 uart_ao_a_cts !! 1769 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1926 mux { !! 1770 mux {
1927 !! 1771 groups = "tdm_ao_b_slv_fs";
1928 !! 1772 function = "tdm_ao_b";
1929 !! 1773 bias-disable;
1930 !! 1774 };
1931 }; 1775 };
1932 }; <<
1933 1776
1934 uart_ao_b_2_3 !! 1777 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1935 mux { !! 1778 mux {
1936 !! 1779 groups = "tdm_ao_b_slv_sclk";
1937 !! 1780 function = "tdm_ao_b";
1938 !! 1781 bias-disable;
1939 !! 1782 };
1940 }; 1783 };
1941 }; <<
1942 1784
1943 uart_ao_b_8_9 !! 1785 uart_ao_a_pins: uart-a-ao {
1944 mux { !! 1786 mux {
1945 !! 1787 groups = "uart_ao_a_tx",
1946 !! 1788 "uart_ao_a_rx";
1947 !! 1789 function = "uart_ao_a";
1948 !! 1790 bias-disable;
>> 1791 };
1949 }; 1792 };
1950 }; <<
1951 1793
1952 uart_ao_b_cts !! 1794 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1953 mux { !! 1795 mux {
1954 !! 1796 groups = "uart_ao_a_cts",
1955 !! 1797 "uart_ao_a_rts";
1956 !! 1798 function = "uart_ao_a";
1957 !! 1799 bias-disable;
>> 1800 };
1958 }; 1801 };
1959 }; <<
1960 1802
1961 pwm_a_e_pins: !! 1803 pwm_a_e_pins: pwm-a-e {
1962 mux { !! 1804 mux {
1963 !! 1805 groups = "pwm_a_e";
1964 !! 1806 function = "pwm_a_e";
1965 !! 1807 bias-disable;
>> 1808 };
1966 }; 1809 };
1967 }; <<
1968 1810
1969 pwm_ao_a_pins !! 1811 pwm_ao_a_pins: pwm-ao-a {
1970 mux { !! 1812 mux {
1971 !! 1813 groups = "pwm_ao_a";
1972 !! 1814 function = "pwm_ao_a";
1973 !! 1815 bias-disable;
>> 1816 };
1974 }; 1817 };
1975 }; <<
1976 1818
1977 pwm_ao_b_pins !! 1819 pwm_ao_b_pins: pwm-ao-b {
1978 mux { !! 1820 mux {
1979 !! 1821 groups = "pwm_ao_b";
1980 !! 1822 function = "pwm_ao_b";
1981 !! 1823 bias-disable;
>> 1824 };
1982 }; 1825 };
1983 }; <<
1984 1826
1985 pwm_ao_c_4_pi !! 1827 pwm_ao_c_4_pins: pwm-ao-c-4 {
1986 mux { !! 1828 mux {
1987 !! 1829 groups = "pwm_ao_c_4";
1988 !! 1830 function = "pwm_ao_c";
1989 !! 1831 bias-disable;
>> 1832 };
1990 }; 1833 };
1991 }; <<
1992 1834
1993 pwm_ao_c_6_pi !! 1835 pwm_ao_c_6_pins: pwm-ao-c-6 {
1994 mux { !! 1836 mux {
1995 !! 1837 groups = "pwm_ao_c_6";
1996 !! 1838 function = "pwm_ao_c";
1997 !! 1839 bias-disable;
>> 1840 };
1998 }; 1841 };
1999 }; <<
2000 1842
2001 pwm_ao_d_5_pi !! 1843 pwm_ao_d_5_pins: pwm-ao-d-5 {
2002 mux { !! 1844 mux {
2003 !! 1845 groups = "pwm_ao_d_5";
2004 !! 1846 function = "pwm_ao_d";
2005 !! 1847 bias-disable;
>> 1848 };
2006 }; 1849 };
2007 }; <<
2008 1850
2009 pwm_ao_d_10_p !! 1851 pwm_ao_d_10_pins: pwm-ao-d-10 {
2010 mux { !! 1852 mux {
2011 !! 1853 groups = "pwm_ao_d_10";
2012 !! 1854 function = "pwm_ao_d";
2013 !! 1855 bias-disable;
>> 1856 };
2014 }; 1857 };
2015 }; <<
2016 1858
2017 pwm_ao_d_e_pi !! 1859 pwm_ao_d_e_pins: pwm-ao-d-e {
2018 mux { !! 1860 mux {
2019 !! 1861 groups = "pwm_ao_d_e";
2020 !! 1862 function = "pwm_ao_d";
>> 1863 };
2021 }; 1864 };
2022 }; <<
2023 1865
2024 remote_input_ !! 1866 remote_input_ao_pins: remote-input-ao {
2025 mux { !! 1867 mux {
2026 !! 1868 groups = "remote_ao_input";
2027 !! 1869 function = "remote_ao_input";
2028 !! 1870 bias-disable;
>> 1871 };
2029 }; 1872 };
2030 }; 1873 };
2031 }; 1874 };
2032 1875
2033 vrtc: rtc@a8 { !! 1876 vrtc: rtc@0a8 {
2034 compatible = 1877 compatible = "amlogic,meson-vrtc";
2035 reg = <0x0 0x 1878 reg = <0x0 0x000a8 0x0 0x4>;
2036 }; 1879 };
2037 1880
2038 cec_AO: cec@100 { 1881 cec_AO: cec@100 {
2039 compatible = 1882 compatible = "amlogic,meson-gx-ao-cec";
2040 reg = <0x0 0x 1883 reg = <0x0 0x00100 0x0 0x14>;
2041 interrupts = 1884 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2042 clocks = <&cl 1885 clocks = <&clkc_AO CLKID_AO_CEC>;
2043 clock-names = 1886 clock-names = "core";
2044 status = "dis 1887 status = "disabled";
2045 }; 1888 };
2046 1889
2047 sec_AO: ao-secure@140 1890 sec_AO: ao-secure@140 {
2048 compatible = 1891 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2049 reg = <0x0 0x 1892 reg = <0x0 0x140 0x0 0x140>;
2050 amlogic,has-c 1893 amlogic,has-chip-id;
2051 }; 1894 };
2052 1895
2053 cecb_AO: cec@280 { 1896 cecb_AO: cec@280 {
2054 compatible = 1897 compatible = "amlogic,meson-g12a-ao-cec";
2055 reg = <0x0 0x 1898 reg = <0x0 0x00280 0x0 0x1c>;
2056 interrupts = 1899 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2057 clocks = <&cl 1900 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2058 clock-names = 1901 clock-names = "oscin";
2059 status = "dis 1902 status = "disabled";
2060 }; 1903 };
2061 1904
2062 pwm_AO_cd: pwm@2000 { 1905 pwm_AO_cd: pwm@2000 {
2063 compatible = 1906 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2064 reg = <0x0 0x 1907 reg = <0x0 0x2000 0x0 0x20>;
2065 #pwm-cells = 1908 #pwm-cells = <3>;
2066 status = "dis 1909 status = "disabled";
2067 }; 1910 };
2068 1911
2069 uart_AO: serial@3000 1912 uart_AO: serial@3000 {
2070 compatible = !! 1913 compatible = "amlogic,meson-gx-uart",
2071 <<
2072 1914 "amlogic,meson-ao-uart";
2073 reg = <0x0 0x 1915 reg = <0x0 0x3000 0x0 0x18>;
2074 interrupts = 1916 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2075 clocks = <&xt 1917 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2076 clock-names = 1918 clock-names = "xtal", "pclk", "baud";
2077 status = "dis 1919 status = "disabled";
2078 }; 1920 };
2079 1921
2080 uart_AO_B: serial@400 1922 uart_AO_B: serial@4000 {
2081 compatible = !! 1923 compatible = "amlogic,meson-gx-uart",
2082 <<
2083 1924 "amlogic,meson-ao-uart";
2084 reg = <0x0 0x 1925 reg = <0x0 0x4000 0x0 0x18>;
2085 interrupts = 1926 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2086 clocks = <&xt 1927 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2087 clock-names = 1928 clock-names = "xtal", "pclk", "baud";
2088 status = "dis 1929 status = "disabled";
2089 }; 1930 };
2090 1931
2091 i2c_AO: i2c@5000 { 1932 i2c_AO: i2c@5000 {
2092 compatible = 1933 compatible = "amlogic,meson-axg-i2c";
2093 status = "dis 1934 status = "disabled";
2094 reg = <0x0 0x 1935 reg = <0x0 0x05000 0x0 0x20>;
2095 interrupts = 1936 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2096 #address-cell 1937 #address-cells = <1>;
2097 #size-cells = 1938 #size-cells = <0>;
2098 clocks = <&cl 1939 clocks = <&clkc CLKID_I2C>;
2099 }; 1940 };
2100 1941
2101 pwm_AO_ab: pwm@7000 { 1942 pwm_AO_ab: pwm@7000 {
2102 compatible = 1943 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2103 reg = <0x0 0x 1944 reg = <0x0 0x7000 0x0 0x20>;
2104 #pwm-cells = 1945 #pwm-cells = <3>;
2105 status = "dis 1946 status = "disabled";
2106 }; 1947 };
2107 1948
2108 ir: ir@8000 { 1949 ir: ir@8000 {
2109 compatible = 1950 compatible = "amlogic,meson-gxbb-ir";
2110 reg = <0x0 0x 1951 reg = <0x0 0x8000 0x0 0x20>;
2111 interrupts = 1952 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2112 status = "dis 1953 status = "disabled";
2113 }; 1954 };
2114 1955
2115 saradc: adc@9000 { 1956 saradc: adc@9000 {
2116 compatible = 1957 compatible = "amlogic,meson-g12a-saradc",
2117 1958 "amlogic,meson-saradc";
2118 reg = <0x0 0x 1959 reg = <0x0 0x9000 0x0 0x48>;
2119 #io-channel-c 1960 #io-channel-cells = <1>;
2120 interrupts = 1961 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2121 clocks = <&xt 1962 clocks = <&xtal>,
2122 <&cl 1963 <&clkc_AO CLKID_AO_SAR_ADC>,
2123 <&cl 1964 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2124 <&cl 1965 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2125 clock-names = 1966 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2126 status = "dis 1967 status = "disabled";
2127 }; 1968 };
2128 }; 1969 };
2129 1970
2130 vdec: video-decoder@ff620000 1971 vdec: video-decoder@ff620000 {
2131 compatible = "amlogic 1972 compatible = "amlogic,g12a-vdec";
2132 reg = <0x0 0xff620000 1973 reg = <0x0 0xff620000 0x0 0x10000>,
2133 <0x0 0xffd0e180 1974 <0x0 0xffd0e180 0x0 0xe4>;
2134 reg-names = "dos", "e 1975 reg-names = "dos", "esparser";
2135 interrupts = <GIC_SPI 1976 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2136 <GIC_SPI 1977 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2137 interrupt-names = "vd 1978 interrupt-names = "vdec", "esparser";
2138 1979
2139 amlogic,ao-sysctrl = 1980 amlogic,ao-sysctrl = <&rti>;
2140 amlogic,canvas = <&ca 1981 amlogic,canvas = <&canvas>;
2141 1982
2142 clocks = <&clkc CLKID 1983 clocks = <&clkc CLKID_PARSER>,
2143 <&clkc CLKID 1984 <&clkc CLKID_DOS>,
2144 <&clkc CLKID 1985 <&clkc CLKID_VDEC_1>,
2145 <&clkc CLKID 1986 <&clkc CLKID_VDEC_HEVC>,
2146 <&clkc CLKID 1987 <&clkc CLKID_VDEC_HEVCF>;
2147 clock-names = "dos_pa 1988 clock-names = "dos_parser", "dos", "vdec_1",
2148 "vdec_h 1989 "vdec_hevc", "vdec_hevcf";
2149 resets = <&reset RESE 1990 resets = <&reset RESET_PARSER>;
2150 reset-names = "espars 1991 reset-names = "esparser";
2151 }; 1992 };
2152 1993
2153 vpu: vpu@ff900000 { 1994 vpu: vpu@ff900000 {
2154 compatible = "amlogic 1995 compatible = "amlogic,meson-g12a-vpu";
2155 reg = <0x0 0xff900000 1996 reg = <0x0 0xff900000 0x0 0x100000>,
2156 <0x0 0xff63c000 1997 <0x0 0xff63c000 0x0 0x1000>;
2157 reg-names = "vpu", "h 1998 reg-names = "vpu", "hhi";
2158 interrupts = <GIC_SPI 1999 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2159 #address-cells = <1>; 2000 #address-cells = <1>;
2160 #size-cells = <0>; 2001 #size-cells = <0>;
2161 amlogic,canvas = <&ca 2002 amlogic,canvas = <&canvas>;
2162 2003
2163 /* CVBS VDAC output p 2004 /* CVBS VDAC output port */
2164 cvbs_vdac_port: port@ 2005 cvbs_vdac_port: port@0 {
2165 reg = <0>; 2006 reg = <0>;
2166 }; 2007 };
2167 2008
2168 /* HDMI-TX output por 2009 /* HDMI-TX output port */
2169 hdmi_tx_port: port@1 2010 hdmi_tx_port: port@1 {
2170 reg = <1>; 2011 reg = <1>;
2171 2012
2172 hdmi_tx_out: 2013 hdmi_tx_out: endpoint {
2173 remot 2014 remote-endpoint = <&hdmi_tx_in>;
2174 }; 2015 };
2175 }; 2016 };
2176 <<
2177 /* DPI output port */ <<
2178 dpi_port: port@2 { <<
2179 reg = <2>; <<
2180 <<
2181 dpi_out: endp <<
2182 remot <<
2183 }; <<
2184 }; <<
2185 }; 2017 };
2186 2018
2187 gic: interrupt-controller@ffc 2019 gic: interrupt-controller@ffc01000 {
2188 compatible = "arm,gic 2020 compatible = "arm,gic-400";
2189 reg = <0x0 0xffc01000 2021 reg = <0x0 0xffc01000 0 0x1000>,
2190 <0x0 0xffc02000 2022 <0x0 0xffc02000 0 0x2000>,
2191 <0x0 0xffc04000 2023 <0x0 0xffc04000 0 0x2000>,
2192 <0x0 0xffc06000 2024 <0x0 0xffc06000 0 0x2000>;
2193 interrupt-controller; 2025 interrupt-controller;
2194 interrupts = <GIC_PPI 2026 interrupts = <GIC_PPI 9
2195 (GIC_CPU_MASK 2027 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2196 #interrupt-cells = <3 2028 #interrupt-cells = <3>;
2197 #address-cells = <0>; 2029 #address-cells = <0>;
2198 }; 2030 };
2199 2031
2200 cbus: bus@ffd00000 { 2032 cbus: bus@ffd00000 {
2201 compatible = "simple- 2033 compatible = "simple-bus";
2202 reg = <0x0 0xffd00000 2034 reg = <0x0 0xffd00000 0x0 0x100000>;
2203 #address-cells = <2>; 2035 #address-cells = <2>;
2204 #size-cells = <2>; 2036 #size-cells = <2>;
2205 ranges = <0x0 0x0 0x0 2037 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2206 2038
2207 reset: reset-controll 2039 reset: reset-controller@1004 {
2208 compatible = 2040 compatible = "amlogic,meson-axg-reset";
2209 reg = <0x0 0x 2041 reg = <0x0 0x1004 0x0 0x9c>;
2210 #reset-cells 2042 #reset-cells = <1>;
2211 }; 2043 };
2212 2044
2213 gpio_intc: interrupt- 2045 gpio_intc: interrupt-controller@f080 {
2214 compatible = 2046 compatible = "amlogic,meson-g12a-gpio-intc",
2215 2047 "amlogic,meson-gpio-intc";
2216 reg = <0x0 0x 2048 reg = <0x0 0xf080 0x0 0x10>;
2217 interrupt-con 2049 interrupt-controller;
2218 #interrupt-ce 2050 #interrupt-cells = <2>;
2219 amlogic,chann 2051 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2220 }; 2052 };
2221 2053
2222 mipi_dsi: dsi@7000 { <<
2223 compatible = <<
2224 reg = <0x0 0x <<
2225 resets = <&re <<
2226 reset-names = <<
2227 clocks = <&cl <<
2228 <&cl <<
2229 <&cl <<
2230 clock-names = <<
2231 phys = <&mipi <<
2232 phy-names = " <<
2233 #address-cell <<
2234 #size-cells = <<
2235 status = "dis <<
2236 <<
2237 assigned-cloc <<
2238 <&cl <<
2239 <&cl <<
2240 assigned-cloc <<
2241 <&cl <<
2242 <&cl <<
2243 <<
2244 ports { <<
2245 #addr <<
2246 #size <<
2247 <<
2248 /* VP <<
2249 mipi_ <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 <<
2257 /* DS <<
2258 mipi_ <<
2259 <<
2260 }; <<
2261 }; <<
2262 }; <<
2263 <<
2264 watchdog: watchdog@f0 <<
2265 compatible = <<
2266 reg = <0x0 0x <<
2267 clocks = <&xt <<
2268 }; <<
2269 <<
2270 spicc0: spi@13000 { <<
2271 compatible = <<
2272 reg = <0x0 0x <<
2273 interrupts = <<
2274 clocks = <&cl <<
2275 <&cl <<
2276 clock-names = <<
2277 #address-cell <<
2278 #size-cells = <<
2279 status = "dis <<
2280 }; <<
2281 <<
2282 spicc1: spi@15000 { <<
2283 compatible = <<
2284 reg = <0x0 0x <<
2285 interrupts = <<
2286 clocks = <&cl <<
2287 <&cl <<
2288 clock-names = <<
2289 #address-cell <<
2290 #size-cells = <<
2291 status = "dis <<
2292 }; <<
2293 <<
2294 spifc: spi@14000 { <<
2295 compatible = <<
2296 status = "dis <<
2297 reg = <0x0 0x <<
2298 #address-cell <<
2299 #size-cells = <<
2300 clocks = <&cl <<
2301 }; <<
2302 <<
2303 pwm_ef: pwm@19000 { 2054 pwm_ef: pwm@19000 {
2304 compatible = 2055 compatible = "amlogic,meson-g12a-ee-pwm";
2305 reg = <0x0 0x 2056 reg = <0x0 0x19000 0x0 0x20>;
2306 #pwm-cells = 2057 #pwm-cells = <3>;
2307 status = "dis 2058 status = "disabled";
2308 }; 2059 };
2309 2060
2310 pwm_cd: pwm@1a000 { 2061 pwm_cd: pwm@1a000 {
2311 compatible = 2062 compatible = "amlogic,meson-g12a-ee-pwm";
2312 reg = <0x0 0x 2063 reg = <0x0 0x1a000 0x0 0x20>;
2313 #pwm-cells = 2064 #pwm-cells = <3>;
2314 status = "dis 2065 status = "disabled";
2315 }; 2066 };
2316 2067
2317 pwm_ab: pwm@1b000 { 2068 pwm_ab: pwm@1b000 {
2318 compatible = 2069 compatible = "amlogic,meson-g12a-ee-pwm";
2319 reg = <0x0 0x 2070 reg = <0x0 0x1b000 0x0 0x20>;
2320 #pwm-cells = 2071 #pwm-cells = <3>;
2321 status = "dis 2072 status = "disabled";
2322 }; 2073 };
2323 2074
2324 i2c3: i2c@1c000 { 2075 i2c3: i2c@1c000 {
2325 compatible = 2076 compatible = "amlogic,meson-axg-i2c";
2326 status = "dis 2077 status = "disabled";
2327 reg = <0x0 0x 2078 reg = <0x0 0x1c000 0x0 0x20>;
2328 interrupts = 2079 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2329 #address-cell 2080 #address-cells = <1>;
2330 #size-cells = 2081 #size-cells = <0>;
2331 clocks = <&cl 2082 clocks = <&clkc CLKID_I2C>;
2332 }; 2083 };
2333 2084
2334 i2c2: i2c@1d000 { 2085 i2c2: i2c@1d000 {
2335 compatible = 2086 compatible = "amlogic,meson-axg-i2c";
2336 status = "dis 2087 status = "disabled";
2337 reg = <0x0 0x 2088 reg = <0x0 0x1d000 0x0 0x20>;
2338 interrupts = 2089 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2339 #address-cell 2090 #address-cells = <1>;
2340 #size-cells = 2091 #size-cells = <0>;
2341 clocks = <&cl 2092 clocks = <&clkc CLKID_I2C>;
2342 }; 2093 };
2343 2094
2344 i2c1: i2c@1e000 { 2095 i2c1: i2c@1e000 {
2345 compatible = 2096 compatible = "amlogic,meson-axg-i2c";
2346 status = "dis 2097 status = "disabled";
2347 reg = <0x0 0x 2098 reg = <0x0 0x1e000 0x0 0x20>;
2348 interrupts = 2099 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2349 #address-cell 2100 #address-cells = <1>;
2350 #size-cells = 2101 #size-cells = <0>;
2351 clocks = <&cl 2102 clocks = <&clkc CLKID_I2C>;
2352 }; 2103 };
2353 2104
2354 i2c0: i2c@1f000 { 2105 i2c0: i2c@1f000 {
2355 compatible = 2106 compatible = "amlogic,meson-axg-i2c";
2356 status = "dis 2107 status = "disabled";
2357 reg = <0x0 0x 2108 reg = <0x0 0x1f000 0x0 0x20>;
2358 interrupts = 2109 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2359 #address-cell 2110 #address-cells = <1>;
2360 #size-cells = 2111 #size-cells = <0>;
2361 clocks = <&cl 2112 clocks = <&clkc CLKID_I2C>;
2362 }; 2113 };
2363 2114
2364 clk_msr: clock-measur 2115 clk_msr: clock-measure@18000 {
2365 compatible = 2116 compatible = "amlogic,meson-g12a-clk-measure";
2366 reg = <0x0 0x 2117 reg = <0x0 0x18000 0x0 0x10>;
2367 }; 2118 };
2368 2119
2369 uart_C: serial@22000 2120 uart_C: serial@22000 {
2370 compatible = !! 2121 compatible = "amlogic,meson-gx-uart";
2371 <<
2372 reg = <0x0 0x 2122 reg = <0x0 0x22000 0x0 0x18>;
2373 interrupts = 2123 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2374 clocks = <&xt 2124 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2375 clock-names = 2125 clock-names = "xtal", "pclk", "baud";
2376 status = "dis 2126 status = "disabled";
2377 }; 2127 };
2378 2128
2379 uart_B: serial@23000 2129 uart_B: serial@23000 {
2380 compatible = !! 2130 compatible = "amlogic,meson-gx-uart";
2381 <<
2382 reg = <0x0 0x 2131 reg = <0x0 0x23000 0x0 0x18>;
2383 interrupts = 2132 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2384 clocks = <&xt 2133 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2385 clock-names = 2134 clock-names = "xtal", "pclk", "baud";
2386 status = "dis 2135 status = "disabled";
2387 }; 2136 };
2388 2137
2389 uart_A: serial@24000 2138 uart_A: serial@24000 {
2390 compatible = !! 2139 compatible = "amlogic,meson-gx-uart";
2391 <<
2392 reg = <0x0 0x 2140 reg = <0x0 0x24000 0x0 0x18>;
2393 interrupts = 2141 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2394 clocks = <&xt 2142 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2395 clock-names = 2143 clock-names = "xtal", "pclk", "baud";
2396 status = "dis 2144 status = "disabled";
2397 fifo-size = < <<
2398 }; 2145 };
2399 }; 2146 };
2400 2147
2401 sd_emmc_a: mmc@ffe03000 { !! 2148 sd_emmc_a: sd@ffe03000 {
2402 compatible = "amlogic 2149 compatible = "amlogic,meson-axg-mmc";
2403 reg = <0x0 0xffe03000 2150 reg = <0x0 0xffe03000 0x0 0x800>;
2404 interrupts = <GIC_SPI !! 2151 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2405 status = "disabled"; 2152 status = "disabled";
2406 clocks = <&clkc CLKID 2153 clocks = <&clkc CLKID_SD_EMMC_A>,
2407 <&clkc CLKID 2154 <&clkc CLKID_SD_EMMC_A_CLK0>,
2408 <&clkc CLKID 2155 <&clkc CLKID_FCLK_DIV2>;
2409 clock-names = "core", 2156 clock-names = "core", "clkin0", "clkin1";
2410 resets = <&reset RESE 2157 resets = <&reset RESET_SD_EMMC_A>;
2411 }; 2158 };
2412 2159
2413 sd_emmc_b: mmc@ffe05000 { !! 2160 sd_emmc_b: sd@ffe05000 {
2414 compatible = "amlogic 2161 compatible = "amlogic,meson-axg-mmc";
2415 reg = <0x0 0xffe05000 2162 reg = <0x0 0xffe05000 0x0 0x800>;
2416 interrupts = <GIC_SPI !! 2163 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2417 status = "disabled"; 2164 status = "disabled";
2418 clocks = <&clkc CLKID 2165 clocks = <&clkc CLKID_SD_EMMC_B>,
2419 <&clkc CLKID 2166 <&clkc CLKID_SD_EMMC_B_CLK0>,
2420 <&clkc CLKID 2167 <&clkc CLKID_FCLK_DIV2>;
2421 clock-names = "core", 2168 clock-names = "core", "clkin0", "clkin1";
2422 resets = <&reset RESE 2169 resets = <&reset RESET_SD_EMMC_B>;
2423 }; 2170 };
2424 2171
2425 sd_emmc_c: mmc@ffe07000 { 2172 sd_emmc_c: mmc@ffe07000 {
2426 compatible = "amlogic 2173 compatible = "amlogic,meson-axg-mmc";
2427 reg = <0x0 0xffe07000 2174 reg = <0x0 0xffe07000 0x0 0x800>;
2428 interrupts = <GIC_SPI !! 2175 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2429 status = "disabled"; 2176 status = "disabled";
2430 clocks = <&clkc CLKID 2177 clocks = <&clkc CLKID_SD_EMMC_C>,
2431 <&clkc CLKID 2178 <&clkc CLKID_SD_EMMC_C_CLK0>,
2432 <&clkc CLKID 2179 <&clkc CLKID_FCLK_DIV2>;
2433 clock-names = "core", 2180 clock-names = "core", "clkin0", "clkin1";
2434 resets = <&reset RESE 2181 resets = <&reset RESET_SD_EMMC_C>;
2435 }; 2182 };
2436 2183
2437 usb: usb@ffe09000 { 2184 usb: usb@ffe09000 {
2438 status = "disabled"; 2185 status = "disabled";
2439 compatible = "amlogic 2186 compatible = "amlogic,meson-g12a-usb-ctrl";
2440 reg = <0x0 0xffe09000 2187 reg = <0x0 0xffe09000 0x0 0xa0>;
2441 interrupts = <GIC_SPI 2188 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2442 #address-cells = <2>; 2189 #address-cells = <2>;
2443 #size-cells = <2>; 2190 #size-cells = <2>;
2444 ranges; 2191 ranges;
2445 2192
2446 clocks = <&clkc CLKID 2193 clocks = <&clkc CLKID_USB>;
2447 resets = <&reset RESE 2194 resets = <&reset RESET_USB>;
2448 2195
2449 dr_mode = "otg"; 2196 dr_mode = "otg";
2450 2197
2451 phys = <&usb2_phy0>, 2198 phys = <&usb2_phy0>, <&usb2_phy1>,
2452 <&usb3_pcie_ph 2199 <&usb3_pcie_phy PHY_TYPE_USB3>;
2453 phy-names = "usb2-phy 2200 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2454 2201
2455 dwc2: usb@ff400000 { 2202 dwc2: usb@ff400000 {
2456 compatible = 2203 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2457 reg = <0x0 0x 2204 reg = <0x0 0xff400000 0x0 0x40000>;
2458 interrupts = 2205 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2459 clocks = <&cl 2206 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2460 clock-names = 2207 clock-names = "otg";
2461 phys = <&usb2 2208 phys = <&usb2_phy1>;
2462 phy-names = " 2209 phy-names = "usb2-phy";
2463 dr_mode = "pe 2210 dr_mode = "peripheral";
2464 g-rx-fifo-siz 2211 g-rx-fifo-size = <192>;
2465 g-np-tx-fifo- 2212 g-np-tx-fifo-size = <128>;
2466 g-tx-fifo-siz 2213 g-tx-fifo-size = <128 128 16 16 16>;
2467 }; 2214 };
2468 2215
2469 dwc3: usb@ff500000 { 2216 dwc3: usb@ff500000 {
2470 compatible = 2217 compatible = "snps,dwc3";
2471 reg = <0x0 0x 2218 reg = <0x0 0xff500000 0x0 0x100000>;
2472 interrupts = 2219 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2473 dr_mode = "ho 2220 dr_mode = "host";
2474 snps,dis_u2_s 2221 snps,dis_u2_susphy_quirk;
2475 snps,quirk-fr !! 2222 snps,quirk-frame-length-adjustment;
2476 snps,parkmode <<
2477 }; 2223 };
2478 }; 2224 };
2479 2225
2480 mali: gpu@ffe40000 { 2226 mali: gpu@ffe40000 {
2481 compatible = "amlogic 2227 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2482 reg = <0x0 0xffe40000 2228 reg = <0x0 0xffe40000 0x0 0x40000>;
2483 interrupt-parent = <& 2229 interrupt-parent = <&gic>;
2484 interrupts = <GIC_SPI 2230 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 2231 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 2232 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2487 interrupt-names = "jo 2233 interrupt-names = "job", "mmu", "gpu";
2488 clocks = <&clkc CLKID 2234 clocks = <&clkc CLKID_MALI>;
2489 resets = <&reset RESE 2235 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2490 operating-points-v2 = <<
2491 #cooling-cells = <2>; <<
2492 }; <<
2493 }; <<
2494 <<
2495 thermal-zones { <<
2496 cpu_thermal: cpu-thermal { <<
2497 polling-delay = <1000 <<
2498 polling-delay-passive <<
2499 thermal-sensors = <&c <<
2500 <<
2501 trips { <<
2502 cpu_passive: <<
2503 tempe <<
2504 hyste <<
2505 type <<
2506 }; <<
2507 <<
2508 cpu_hot: cpu- <<
2509 tempe <<
2510 hyste <<
2511 type <<
2512 }; <<
2513 <<
2514 cpu_critical: <<
2515 tempe <<
2516 hyste <<
2517 type <<
2518 }; <<
2519 }; <<
2520 }; <<
2521 <<
2522 ddr_thermal: ddr-thermal { <<
2523 polling-delay = <1000 <<
2524 polling-delay-passive <<
2525 thermal-sensors = <&d <<
2526 <<
2527 trips { <<
2528 ddr_passive: <<
2529 tempe <<
2530 hyste <<
2531 type <<
2532 }; <<
2533 <<
2534 ddr_critical: <<
2535 tempe <<
2536 hyste <<
2537 type <<
2538 }; <<
2539 }; <<
2540 2236
2541 cooling-maps { !! 2237 /*
2542 map { !! 2238 * Mali clocking is provided by two identical clock paths
2543 trip !! 2239 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2544 cooli !! 2240 * free mux to safely change frequency while running.
2545 }; !! 2241 */
2546 }; !! 2242 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
>> 2243 <&clkc CLKID_MALI_0>,
>> 2244 <&clkc CLKID_MALI>; /* Glitch free mux */
>> 2245 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
>> 2246 <0>, /* Do Nothing */
>> 2247 <&clkc CLKID_MALI_0>;
>> 2248 assigned-clock-rates = <0>, /* Do Nothing */
>> 2249 <800000000>,
>> 2250 <0>; /* Do Nothing */
>> 2251 #cooling-cells = <2>;
2547 }; 2252 };
2548 }; 2253 };
2549 2254
2550 timer { 2255 timer {
2551 compatible = "arm,armv8-timer 2256 compatible = "arm,armv8-timer";
2552 interrupts = <GIC_PPI 13 2257 interrupts = <GIC_PPI 13
2553 (GIC_CPU_MASK_RAW(0xf 2258 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2554 <GIC_PPI 14 2259 <GIC_PPI 14
2555 (GIC_CPU_MASK_RAW(0xf 2260 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2556 <GIC_PPI 11 2261 <GIC_PPI 11
2557 (GIC_CPU_MASK_RAW(0xf 2262 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2558 <GIC_PPI 10 2263 <GIC_PPI 10
2559 (GIC_CPU_MASK_RAW(0xf 2264 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2560 arm,no-tick-in-suspend; 2265 arm,no-tick-in-suspend;
2561 }; 2266 };
2562 2267
2563 xtal: xtal-clk { 2268 xtal: xtal-clk {
2564 compatible = "fixed-clock"; 2269 compatible = "fixed-clock";
2565 clock-frequency = <24000000>; 2270 clock-frequency = <24000000>;
2566 clock-output-names = "xtal"; 2271 clock-output-names = "xtal";
2567 #clock-cells = <0>; 2272 #clock-cells = <0>;
2568 }; 2273 };
2569 2274
2570 npu: npu@ff100000 { <<
2571 compatible = "vivante,gc"; <<
2572 reg = <0x0 0xff100000 0x0 0x2 <<
2573 interrupts = <0 147 4>; <<
2574 clocks = <&clkc CLKID_NNA_COR <<
2575 <&clkc CLKID_NNA_AXI <<
2576 clock-names = "core", "bus"; <<
2577 assigned-clocks = <&clkc CLKI <<
2578 <&clkc CLKI <<
2579 assigned-clock-rates = <80000 <<
2580 resets = <&reset RESET_NNA>; <<
2581 status = "disabled"; <<
2582 }; <<
2583 }; 2275 };
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