1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy.h> 6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h> 8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h> 9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/aml <<
13 #include <dt-bindings/reset/amlogic,meson-g12a 12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { <<
22 mmc0 = &sd_emmc_b; /* SD card <<
23 mmc1 = &sd_emmc_c; /* eMMC */ <<
24 mmc2 = &sd_emmc_a; /* SDIO */ <<
25 }; <<
26 <<
27 chosen { 20 chosen {
28 #address-cells = <2>; 21 #address-cells = <2>;
29 #size-cells = <2>; 22 #size-cells = <2>;
30 ranges; 23 ranges;
31 24
32 simplefb_cvbs: framebuffer-cvb 25 simplefb_cvbs: framebuffer-cvbs {
33 compatible = "amlogic, 26 compatible = "amlogic,simple-framebuffer",
34 "simple-f 27 "simple-framebuffer";
35 amlogic,pipeline = "vp 28 amlogic,pipeline = "vpu-cvbs";
36 clocks = <&clkc CLKID_ 29 clocks = <&clkc CLKID_HDMI>,
37 <&clkc CLKID_ 30 <&clkc CLKID_HTX_PCLK>,
38 <&clkc CLKID_ 31 <&clkc CLKID_VPU_INTR>;
39 status = "disabled"; 32 status = "disabled";
40 }; 33 };
41 34
42 simplefb_hdmi: framebuffer-hdm 35 simplefb_hdmi: framebuffer-hdmi {
43 compatible = "amlogic, 36 compatible = "amlogic,simple-framebuffer",
44 "simple-fr 37 "simple-framebuffer";
45 amlogic,pipeline = "vp 38 amlogic,pipeline = "vpu-hdmi";
46 clocks = <&clkc CLKID_ 39 clocks = <&clkc CLKID_HDMI>,
47 <&clkc CLKID_ 40 <&clkc CLKID_HTX_PCLK>,
48 <&clkc CLKID_ 41 <&clkc CLKID_VPU_INTR>;
49 status = "disabled"; 42 status = "disabled";
50 }; 43 };
51 }; 44 };
52 45
53 efuse: efuse { 46 efuse: efuse {
54 compatible = "amlogic,meson-gx 47 compatible = "amlogic,meson-gxbb-efuse";
55 clocks = <&clkc CLKID_EFUSE>; 48 clocks = <&clkc CLKID_EFUSE>;
56 #address-cells = <1>; 49 #address-cells = <1>;
57 #size-cells = <1>; 50 #size-cells = <1>;
58 read-only; 51 read-only;
59 secure-monitor = <&sm>; 52 secure-monitor = <&sm>;
60 }; 53 };
61 54
62 gpu_opp_table: opp-table-gpu { !! 55 gpu_opp_table: gpu-opp-table {
63 compatible = "operating-points 56 compatible = "operating-points-v2";
64 57
65 opp-124999998 { 58 opp-124999998 {
66 opp-hz = /bits/ 64 <12 59 opp-hz = /bits/ 64 <124999998>;
67 opp-microvolt = <80000 60 opp-microvolt = <800000>;
68 }; 61 };
69 opp-249999996 { 62 opp-249999996 {
70 opp-hz = /bits/ 64 <24 63 opp-hz = /bits/ 64 <249999996>;
71 opp-microvolt = <80000 64 opp-microvolt = <800000>;
72 }; 65 };
73 opp-285714281 { 66 opp-285714281 {
74 opp-hz = /bits/ 64 <28 67 opp-hz = /bits/ 64 <285714281>;
75 opp-microvolt = <80000 68 opp-microvolt = <800000>;
76 }; 69 };
77 opp-399999994 { 70 opp-399999994 {
78 opp-hz = /bits/ 64 <39 71 opp-hz = /bits/ 64 <399999994>;
79 opp-microvolt = <80000 72 opp-microvolt = <800000>;
80 }; 73 };
81 opp-499999992 { 74 opp-499999992 {
82 opp-hz = /bits/ 64 <49 75 opp-hz = /bits/ 64 <499999992>;
83 opp-microvolt = <80000 76 opp-microvolt = <800000>;
84 }; 77 };
85 opp-666666656 { 78 opp-666666656 {
86 opp-hz = /bits/ 64 <66 79 opp-hz = /bits/ 64 <666666656>;
87 opp-microvolt = <80000 80 opp-microvolt = <800000>;
88 }; 81 };
89 opp-799999987 { 82 opp-799999987 {
90 opp-hz = /bits/ 64 <79 83 opp-hz = /bits/ 64 <799999987>;
91 opp-microvolt = <80000 84 opp-microvolt = <800000>;
92 }; 85 };
93 }; 86 };
94 87
95 psci { 88 psci {
96 compatible = "arm,psci-1.0"; 89 compatible = "arm,psci-1.0";
97 method = "smc"; 90 method = "smc";
98 }; 91 };
99 92
100 reserved-memory { 93 reserved-memory {
101 #address-cells = <2>; 94 #address-cells = <2>;
102 #size-cells = <2>; 95 #size-cells = <2>;
103 ranges; 96 ranges;
104 97
105 /* 3 MiB reserved for ARM Trus 98 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
106 secmon_reserved: secmon@500000 99 secmon_reserved: secmon@5000000 {
107 reg = <0x0 0x05000000 100 reg = <0x0 0x05000000 0x0 0x300000>;
108 no-map; 101 no-map;
109 }; 102 };
110 103
111 /* 32 MiB reserved for ARM Tru <<
112 secmon_reserved_bl32: secmon@5 <<
113 reg = <0x0 0x05300000 <<
114 no-map; <<
115 }; <<
116 <<
117 linux,cma { 104 linux,cma {
118 compatible = "shared-d 105 compatible = "shared-dma-pool";
119 reusable; 106 reusable;
120 size = <0x0 0x10000000 107 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400 108 alignment = <0x0 0x400000>;
122 linux,cma-default; 109 linux,cma-default;
123 }; 110 };
124 }; 111 };
125 112
126 sm: secure-monitor { 113 sm: secure-monitor {
127 compatible = "amlogic,meson-gx 114 compatible = "amlogic,meson-gxbb-sm";
128 }; 115 };
129 116
130 soc { 117 soc {
131 compatible = "simple-bus"; 118 compatible = "simple-bus";
132 #address-cells = <2>; 119 #address-cells = <2>;
133 #size-cells = <2>; 120 #size-cells = <2>;
134 ranges; 121 ranges;
135 122
136 pcie: pcie@fc000000 { 123 pcie: pcie@fc000000 {
137 compatible = "amlogic, 124 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
138 reg = <0x0 0xfc000000 !! 125 reg = <0x0 0xfc000000 0x0 0x400000
139 <0x0 0xff648000 !! 126 0x0 0xff648000 0x0 0x2000
140 <0x0 0xfc400000 !! 127 0x0 0xfc400000 0x0 0x200000>;
141 reg-names = "elbi", "c 128 reg-names = "elbi", "cfg", "config";
142 interrupts = <GIC_SPI 129 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
143 #interrupt-cells = <1> 130 #interrupt-cells = <1>;
144 interrupt-map-mask = < 131 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff> 133 bus-range = <0x0 0xff>;
147 #address-cells = <3>; 134 #address-cells = <3>;
148 #size-cells = <2>; 135 #size-cells = <2>;
149 device_type = "pci"; 136 device_type = "pci";
150 ranges = <0x81000000 0 !! 137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
151 <0x82000000 0 !! 138 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
152 139
153 clocks = <&clkc CLKID_ 140 clocks = <&clkc CLKID_PCIE_PHY
154 &clkc CLKID_ 141 &clkc CLKID_PCIE_COMB
155 &clkc CLKID_ 142 &clkc CLKID_PCIE_PLL>;
156 clock-names = "general 143 clock-names = "general",
157 "pclk", 144 "pclk",
158 "port"; 145 "port";
159 resets = <&reset RESET 146 resets = <&reset RESET_PCIE_CTRL_A>,
160 <&reset RESET 147 <&reset RESET_PCIE_APB>;
161 reset-names = "port", 148 reset-names = "port",
162 "apb"; 149 "apb";
163 num-lanes = <1>; 150 num-lanes = <1>;
164 phys = <&usb3_pcie_phy 151 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
165 phy-names = "pcie"; 152 phy-names = "pcie";
166 status = "disabled"; 153 status = "disabled";
167 }; 154 };
168 155
>> 156 thermal-zones {
>> 157 cpu_thermal: cpu-thermal {
>> 158 polling-delay = <1000>;
>> 159 polling-delay-passive = <100>;
>> 160 thermal-sensors = <&cpu_temp>;
>> 161
>> 162 trips {
>> 163 cpu_passive: cpu-passive {
>> 164 temperature = <85000>; /* millicelsius */
>> 165 hysteresis = <2000>; /* millicelsius */
>> 166 type = "passive";
>> 167 };
>> 168
>> 169 cpu_hot: cpu-hot {
>> 170 temperature = <95000>; /* millicelsius */
>> 171 hysteresis = <2000>; /* millicelsius */
>> 172 type = "hot";
>> 173 };
>> 174
>> 175 cpu_critical: cpu-critical {
>> 176 temperature = <110000>; /* millicelsius */
>> 177 hysteresis = <2000>; /* millicelsius */
>> 178 type = "critical";
>> 179 };
>> 180 };
>> 181 };
>> 182
>> 183 ddr_thermal: ddr-thermal {
>> 184 polling-delay = <1000>;
>> 185 polling-delay-passive = <100>;
>> 186 thermal-sensors = <&ddr_temp>;
>> 187
>> 188 trips {
>> 189 ddr_passive: ddr-passive {
>> 190 temperature = <85000>; /* millicelsius */
>> 191 hysteresis = <2000>; /* millicelsius */
>> 192 type = "passive";
>> 193 };
>> 194
>> 195 ddr_critical: ddr-critical {
>> 196 temperature = <110000>; /* millicelsius */
>> 197 hysteresis = <2000>; /* millicelsius */
>> 198 type = "critical";
>> 199 };
>> 200 };
>> 201
>> 202 cooling-maps {
>> 203 map {
>> 204 trip = <&ddr_passive>;
>> 205 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 206 };
>> 207 };
>> 208 };
>> 209 };
>> 210
169 ethmac: ethernet@ff3f0000 { 211 ethmac: ethernet@ff3f0000 {
170 compatible = "amlogic, 212 compatible = "amlogic,meson-g12a-dwmac",
171 "snps,dwm 213 "snps,dwmac-3.70a",
172 "snps,dwm 214 "snps,dwmac";
173 reg = <0x0 0xff3f0000 215 reg = <0x0 0xff3f0000 0x0 0x10000>,
174 <0x0 0xff634540 216 <0x0 0xff634540 0x0 0x8>;
175 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "mac 218 interrupt-names = "macirq";
177 clocks = <&clkc CLKID_ 219 clocks = <&clkc CLKID_ETH>,
178 <&clkc CLKID_ 220 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_ 221 <&clkc CLKID_MPLL2>,
180 <&clkc CLKID_ 222 <&clkc CLKID_FCLK_DIV2>;
181 clock-names = "stmmace 223 clock-names = "stmmaceth", "clkin0", "clkin1",
182 "timing- 224 "timing-adjustment";
183 rx-fifo-depth = <4096> 225 rx-fifo-depth = <4096>;
184 tx-fifo-depth = <2048> 226 tx-fifo-depth = <2048>;
>> 227 resets = <&reset RESET_ETHERNET>;
>> 228 reset-names = "stmmaceth";
185 status = "disabled"; 229 status = "disabled";
186 230
187 mdio0: mdio { 231 mdio0: mdio {
188 #address-cells 232 #address-cells = <1>;
189 #size-cells = 233 #size-cells = <0>;
190 compatible = " 234 compatible = "snps,dwmac-mdio";
191 }; 235 };
192 }; 236 };
193 237
194 apb: bus@ff600000 { 238 apb: bus@ff600000 {
195 compatible = "simple-b 239 compatible = "simple-bus";
196 reg = <0x0 0xff600000 240 reg = <0x0 0xff600000 0x0 0x200000>;
197 #address-cells = <2>; 241 #address-cells = <2>;
198 #size-cells = <2>; 242 #size-cells = <2>;
199 ranges = <0x0 0x0 0x0 243 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
200 244
201 hdmi_tx: hdmi-tx@0 { 245 hdmi_tx: hdmi-tx@0 {
202 compatible = " 246 compatible = "amlogic,meson-g12a-dw-hdmi";
203 reg = <0x0 0x0 247 reg = <0x0 0x0 0x0 0x10000>;
204 interrupts = < 248 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
205 resets = <&res 249 resets = <&reset RESET_HDMITX_CAPB3>,
206 <&res 250 <&reset RESET_HDMITX_PHY>,
207 <&res 251 <&reset RESET_HDMITX>;
208 reset-names = 252 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
209 clocks = <&clk 253 clocks = <&clkc CLKID_HDMI>,
210 <&clk 254 <&clkc CLKID_HTX_PCLK>,
211 <&clk 255 <&clkc CLKID_VPU_INTR>;
212 clock-names = 256 clock-names = "isfr", "iahb", "venci";
213 #address-cells 257 #address-cells = <1>;
214 #size-cells = 258 #size-cells = <0>;
215 #sound-dai-cel 259 #sound-dai-cells = <0>;
216 status = "disa 260 status = "disabled";
217 261
218 assigned-clock <<
219 <<
220 assigned-clock <<
221 assigned-clock <<
222 <<
223 /* VPU VENC In 262 /* VPU VENC Input */
224 hdmi_tx_venc_p 263 hdmi_tx_venc_port: port@0 {
225 reg = 264 reg = <0>;
226 265
227 hdmi_t 266 hdmi_tx_in: endpoint {
228 267 remote-endpoint = <&hdmi_tx_out>;
229 }; 268 };
230 }; 269 };
231 270
232 /* TMDS Output 271 /* TMDS Output */
233 hdmi_tx_tmds_p 272 hdmi_tx_tmds_port: port@1 {
234 reg = 273 reg = <1>;
235 }; 274 };
236 }; 275 };
237 276
238 apb_efuse: bus@30000 { 277 apb_efuse: bus@30000 {
239 compatible = " 278 compatible = "simple-bus";
240 reg = <0x0 0x3 279 reg = <0x0 0x30000 0x0 0x2000>;
241 #address-cells 280 #address-cells = <2>;
242 #size-cells = 281 #size-cells = <2>;
243 ranges = <0x0 282 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
244 283
245 hwrng: rng@218 284 hwrng: rng@218 {
246 compat 285 compatible = "amlogic,meson-rng";
247 reg = 286 reg = <0x0 0x218 0x0 0x4>;
248 clocks 287 clocks = <&clkc CLKID_RNG0>;
249 clock- 288 clock-names = "core";
250 }; 289 };
251 }; 290 };
252 291
253 acodec: audio-controll 292 acodec: audio-controller@32000 {
254 compatible = " 293 compatible = "amlogic,t9015";
255 reg = <0x0 0x3 294 reg = <0x0 0x32000 0x0 0x14>;
256 #sound-dai-cel 295 #sound-dai-cells = <0>;
257 sound-name-pre 296 sound-name-prefix = "ACODEC";
258 clocks = <&clk 297 clocks = <&clkc CLKID_AUDIO_CODEC>;
259 clock-names = 298 clock-names = "pclk";
260 resets = <&res 299 resets = <&reset RESET_AUDIO_CODEC>;
261 status = "disa 300 status = "disabled";
262 }; 301 };
263 302
264 periphs: bus@34400 { 303 periphs: bus@34400 {
265 compatible = " 304 compatible = "simple-bus";
266 reg = <0x0 0x3 305 reg = <0x0 0x34400 0x0 0x400>;
267 #address-cells 306 #address-cells = <2>;
268 #size-cells = 307 #size-cells = <2>;
269 ranges = <0x0 308 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
270 309
271 periphs_pinctr 310 periphs_pinctrl: pinctrl@40 {
272 compat 311 compatible = "amlogic,meson-g12a-periphs-pinctrl";
273 #addre 312 #address-cells = <2>;
274 #size- 313 #size-cells = <2>;
275 ranges 314 ranges;
276 315
277 gpio: 316 gpio: bank@40 {
278 317 reg = <0x0 0x40 0x0 0x4c>,
279 318 <0x0 0xe8 0x0 0x18>,
280 319 <0x0 0x120 0x0 0x18>,
281 320 <0x0 0x2c0 0x0 0x40>,
282 321 <0x0 0x340 0x0 0x1c>;
283 322 reg-names = "gpio",
284 323 "pull",
285 324 "pull-enable",
286 325 "mux",
287 326 "ds";
288 327 gpio-controller;
289 328 #gpio-cells = <2>;
290 329 gpio-ranges = <&periphs_pinctrl 0 0 86>;
291 }; 330 };
292 331
293 cec_ao 332 cec_ao_a_h_pins: cec_ao_a_h {
294 333 mux {
295 334 groups = "cec_ao_a_h";
296 335 function = "cec_ao_a_h";
297 336 bias-disable;
298 337 };
299 }; 338 };
300 339
301 cec_ao 340 cec_ao_b_h_pins: cec_ao_b_h {
302 341 mux {
303 342 groups = "cec_ao_b_h";
304 343 function = "cec_ao_b_h";
305 344 bias-disable;
306 345 };
307 }; 346 };
308 347
309 emmc_c 348 emmc_ctrl_pins: emmc-ctrl {
310 349 mux-0 {
311 350 groups = "emmc_cmd";
312 351 function = "emmc";
313 352 bias-pull-up;
314 353 drive-strength-microamp = <4000>;
315 354 };
316 355
317 356 mux-1 {
318 357 groups = "emmc_clk";
319 358 function = "emmc";
320 359 bias-disable;
321 360 drive-strength-microamp = <4000>;
322 361 };
323 }; 362 };
324 363
325 emmc_d 364 emmc_data_4b_pins: emmc-data-4b {
326 365 mux-0 {
327 366 groups = "emmc_nand_d0",
328 367 "emmc_nand_d1",
329 368 "emmc_nand_d2",
330 369 "emmc_nand_d3";
331 370 function = "emmc";
332 371 bias-pull-up;
333 372 drive-strength-microamp = <4000>;
334 373 };
335 }; 374 };
336 375
337 emmc_d 376 emmc_data_8b_pins: emmc-data-8b {
338 377 mux-0 {
339 378 groups = "emmc_nand_d0",
340 379 "emmc_nand_d1",
341 380 "emmc_nand_d2",
342 381 "emmc_nand_d3",
343 382 "emmc_nand_d4",
344 383 "emmc_nand_d5",
345 384 "emmc_nand_d6",
346 385 "emmc_nand_d7";
347 386 function = "emmc";
348 387 bias-pull-up;
349 388 drive-strength-microamp = <4000>;
350 389 };
351 }; 390 };
352 391
353 emmc_d 392 emmc_ds_pins: emmc-ds {
354 393 mux {
355 394 groups = "emmc_nand_ds";
356 395 function = "emmc";
357 396 bias-pull-down;
358 397 drive-strength-microamp = <4000>;
359 398 };
360 }; 399 };
361 400
362 emmc_c 401 emmc_clk_gate_pins: emmc_clk_gate {
363 402 mux {
364 403 groups = "BOOT_8";
365 404 function = "gpio_periphs";
366 405 bias-pull-down;
367 406 drive-strength-microamp = <4000>;
368 407 };
369 }; 408 };
370 409
371 hdmitx 410 hdmitx_ddc_pins: hdmitx_ddc {
372 411 mux {
373 412 groups = "hdmitx_sda",
374 413 "hdmitx_sck";
375 414 function = "hdmitx";
376 415 bias-disable;
377 416 drive-strength-microamp = <4000>;
378 417 };
379 }; 418 };
380 419
381 hdmitx 420 hdmitx_hpd_pins: hdmitx_hpd {
382 421 mux {
383 422 groups = "hdmitx_hpd_in";
384 423 function = "hdmitx";
385 424 bias-disable;
386 425 };
387 }; 426 };
388 427
389 428
390 i2c0_s 429 i2c0_sda_c_pins: i2c0-sda-c {
391 430 mux {
392 431 groups = "i2c0_sda_c";
393 432 function = "i2c0";
394 433 bias-disable;
395 434 drive-strength-microamp = <3000>;
396 435
397 436 };
398 }; 437 };
399 438
400 i2c0_s 439 i2c0_sck_c_pins: i2c0-sck-c {
401 440 mux {
402 441 groups = "i2c0_sck_c";
403 442 function = "i2c0";
404 443 bias-disable;
405 444 drive-strength-microamp = <3000>;
406 445 };
407 }; 446 };
408 447
409 i2c0_s 448 i2c0_sda_z0_pins: i2c0-sda-z0 {
410 449 mux {
411 450 groups = "i2c0_sda_z0";
412 451 function = "i2c0";
413 452 bias-disable;
414 453 drive-strength-microamp = <3000>;
415 454 };
416 }; 455 };
417 456
418 i2c0_s 457 i2c0_sck_z1_pins: i2c0-sck-z1 {
419 458 mux {
420 459 groups = "i2c0_sck_z1";
421 460 function = "i2c0";
422 461 bias-disable;
423 462 drive-strength-microamp = <3000>;
424 463 };
425 }; 464 };
426 465
427 i2c0_s 466 i2c0_sda_z7_pins: i2c0-sda-z7 {
428 467 mux {
429 468 groups = "i2c0_sda_z7";
430 469 function = "i2c0";
431 470 bias-disable;
432 471 drive-strength-microamp = <3000>;
433 472 };
434 }; 473 };
435 474
436 i2c0_s 475 i2c0_sda_z8_pins: i2c0-sda-z8 {
437 476 mux {
438 477 groups = "i2c0_sda_z8";
439 478 function = "i2c0";
440 479 bias-disable;
441 480 drive-strength-microamp = <3000>;
442 481 };
443 }; 482 };
444 483
445 i2c1_s 484 i2c1_sda_x_pins: i2c1-sda-x {
446 485 mux {
447 486 groups = "i2c1_sda_x";
448 487 function = "i2c1";
449 488 bias-disable;
450 489 drive-strength-microamp = <3000>;
451 490 };
452 }; 491 };
453 492
454 i2c1_s 493 i2c1_sck_x_pins: i2c1-sck-x {
455 494 mux {
456 495 groups = "i2c1_sck_x";
457 496 function = "i2c1";
458 497 bias-disable;
459 498 drive-strength-microamp = <3000>;
460 499 };
461 }; 500 };
462 501
463 i2c1_s 502 i2c1_sda_h2_pins: i2c1-sda-h2 {
464 503 mux {
465 504 groups = "i2c1_sda_h2";
466 505 function = "i2c1";
467 506 bias-disable;
468 507 drive-strength-microamp = <3000>;
469 508 };
470 }; 509 };
471 510
472 i2c1_s 511 i2c1_sck_h3_pins: i2c1-sck-h3 {
473 512 mux {
474 513 groups = "i2c1_sck_h3";
475 514 function = "i2c1";
476 515 bias-disable;
477 516 drive-strength-microamp = <3000>;
478 517 };
479 }; 518 };
480 519
481 i2c1_s 520 i2c1_sda_h6_pins: i2c1-sda-h6 {
482 521 mux {
483 522 groups = "i2c1_sda_h6";
484 523 function = "i2c1";
485 524 bias-disable;
486 525 drive-strength-microamp = <3000>;
487 526 };
488 }; 527 };
489 528
490 i2c1_s 529 i2c1_sck_h7_pins: i2c1-sck-h7 {
491 530 mux {
492 531 groups = "i2c1_sck_h7";
493 532 function = "i2c1";
494 533 bias-disable;
495 534 drive-strength-microamp = <3000>;
496 535 };
497 }; 536 };
498 537
499 i2c2_s 538 i2c2_sda_x_pins: i2c2-sda-x {
500 539 mux {
501 540 groups = "i2c2_sda_x";
502 541 function = "i2c2";
503 542 bias-disable;
504 543 drive-strength-microamp = <3000>;
505 544 };
506 }; 545 };
507 546
508 i2c2_s 547 i2c2_sck_x_pins: i2c2-sck-x {
509 548 mux {
510 549 groups = "i2c2_sck_x";
511 550 function = "i2c2";
512 551 bias-disable;
513 552 drive-strength-microamp = <3000>;
514 553 };
515 }; 554 };
516 555
517 i2c2_s 556 i2c2_sda_z_pins: i2c2-sda-z {
518 557 mux {
519 558 groups = "i2c2_sda_z";
520 559 function = "i2c2";
521 560 bias-disable;
522 561 drive-strength-microamp = <3000>;
523 562 };
524 }; 563 };
525 564
526 i2c2_s 565 i2c2_sck_z_pins: i2c2-sck-z {
527 566 mux {
528 567 groups = "i2c2_sck_z";
529 568 function = "i2c2";
530 569 bias-disable;
531 570 drive-strength-microamp = <3000>;
532 571 };
533 }; 572 };
534 573
535 i2c3_s 574 i2c3_sda_h_pins: i2c3-sda-h {
536 575 mux {
537 576 groups = "i2c3_sda_h";
538 577 function = "i2c3";
539 578 bias-disable;
540 579 drive-strength-microamp = <3000>;
541 580 };
542 }; 581 };
543 582
544 i2c3_s 583 i2c3_sck_h_pins: i2c3-sck-h {
545 584 mux {
546 585 groups = "i2c3_sck_h";
547 586 function = "i2c3";
548 587 bias-disable;
549 588 drive-strength-microamp = <3000>;
550 589 };
551 }; 590 };
552 591
553 i2c3_s 592 i2c3_sda_a_pins: i2c3-sda-a {
554 593 mux {
555 594 groups = "i2c3_sda_a";
556 595 function = "i2c3";
557 596 bias-disable;
558 597 drive-strength-microamp = <3000>;
559 598 };
560 }; 599 };
561 600
562 i2c3_s 601 i2c3_sck_a_pins: i2c3-sck-a {
563 602 mux {
564 603 groups = "i2c3_sck_a";
565 604 function = "i2c3";
566 605 bias-disable;
567 606 drive-strength-microamp = <3000>;
568 607 };
569 }; 608 };
570 609
571 mclk0_ 610 mclk0_a_pins: mclk0-a {
572 611 mux {
573 612 groups = "mclk0_a";
574 613 function = "mclk0";
575 614 bias-disable;
576 615 drive-strength-microamp = <3000>;
577 616 };
578 }; 617 };
579 618
580 mclk1_ 619 mclk1_a_pins: mclk1-a {
581 620 mux {
582 621 groups = "mclk1_a";
583 622 function = "mclk1";
584 623 bias-disable;
585 624 drive-strength-microamp = <3000>;
586 625 };
587 }; 626 };
588 627
589 mclk1_ 628 mclk1_x_pins: mclk1-x {
590 629 mux {
591 630 groups = "mclk1_x";
592 631 function = "mclk1";
593 632 bias-disable;
594 633 drive-strength-microamp = <3000>;
595 634 };
596 }; 635 };
597 636
598 mclk1_ 637 mclk1_z_pins: mclk1-z {
599 638 mux {
600 639 groups = "mclk1_z";
601 640 function = "mclk1";
602 641 bias-disable;
603 642 drive-strength-microamp = <3000>;
604 643 };
605 }; 644 };
606 645
607 nor_pi 646 nor_pins: nor {
608 647 mux {
609 648 groups = "nor_d",
610 649 "nor_q",
611 650 "nor_c",
612 651 "nor_cs";
613 652 function = "nor";
614 653 bias-disable;
615 654 };
616 }; 655 };
617 656
618 pdm_di 657 pdm_din0_a_pins: pdm-din0-a {
619 658 mux {
620 659 groups = "pdm_din0_a";
621 660 function = "pdm";
622 661 bias-disable;
623 662 };
624 }; 663 };
625 664
626 pdm_di 665 pdm_din0_c_pins: pdm-din0-c {
627 666 mux {
628 667 groups = "pdm_din0_c";
629 668 function = "pdm";
630 669 bias-disable;
631 670 };
632 }; 671 };
633 672
634 pdm_di 673 pdm_din0_x_pins: pdm-din0-x {
635 674 mux {
636 675 groups = "pdm_din0_x";
637 676 function = "pdm";
638 677 bias-disable;
639 678 };
640 }; 679 };
641 680
642 pdm_di 681 pdm_din0_z_pins: pdm-din0-z {
643 682 mux {
644 683 groups = "pdm_din0_z";
645 684 function = "pdm";
646 685 bias-disable;
647 686 };
648 }; 687 };
649 688
650 pdm_di 689 pdm_din1_a_pins: pdm-din1-a {
651 690 mux {
652 691 groups = "pdm_din1_a";
653 692 function = "pdm";
654 693 bias-disable;
655 694 };
656 }; 695 };
657 696
658 pdm_di 697 pdm_din1_c_pins: pdm-din1-c {
659 698 mux {
660 699 groups = "pdm_din1_c";
661 700 function = "pdm";
662 701 bias-disable;
663 702 };
664 }; 703 };
665 704
666 pdm_di 705 pdm_din1_x_pins: pdm-din1-x {
667 706 mux {
668 707 groups = "pdm_din1_x";
669 708 function = "pdm";
670 709 bias-disable;
671 710 };
672 }; 711 };
673 712
674 pdm_di 713 pdm_din1_z_pins: pdm-din1-z {
675 714 mux {
676 715 groups = "pdm_din1_z";
677 716 function = "pdm";
678 717 bias-disable;
679 718 };
680 }; 719 };
681 720
682 pdm_di 721 pdm_din2_a_pins: pdm-din2-a {
683 722 mux {
684 723 groups = "pdm_din2_a";
685 724 function = "pdm";
686 725 bias-disable;
687 726 };
688 }; 727 };
689 728
690 pdm_di 729 pdm_din2_c_pins: pdm-din2-c {
691 730 mux {
692 731 groups = "pdm_din2_c";
693 732 function = "pdm";
694 733 bias-disable;
695 734 };
696 }; 735 };
697 736
698 pdm_di 737 pdm_din2_x_pins: pdm-din2-x {
699 738 mux {
700 739 groups = "pdm_din2_x";
701 740 function = "pdm";
702 741 bias-disable;
703 742 };
704 }; 743 };
705 744
706 pdm_di 745 pdm_din2_z_pins: pdm-din2-z {
707 746 mux {
708 747 groups = "pdm_din2_z";
709 748 function = "pdm";
710 749 bias-disable;
711 750 };
712 }; 751 };
713 752
714 pdm_di 753 pdm_din3_a_pins: pdm-din3-a {
715 754 mux {
716 755 groups = "pdm_din3_a";
717 756 function = "pdm";
718 757 bias-disable;
719 758 };
720 }; 759 };
721 760
722 pdm_di 761 pdm_din3_c_pins: pdm-din3-c {
723 762 mux {
724 763 groups = "pdm_din3_c";
725 764 function = "pdm";
726 765 bias-disable;
727 766 };
728 }; 767 };
729 768
730 pdm_di 769 pdm_din3_x_pins: pdm-din3-x {
731 770 mux {
732 771 groups = "pdm_din3_x";
733 772 function = "pdm";
734 773 bias-disable;
735 774 };
736 }; 775 };
737 776
738 pdm_di 777 pdm_din3_z_pins: pdm-din3-z {
739 778 mux {
740 779 groups = "pdm_din3_z";
741 780 function = "pdm";
742 781 bias-disable;
743 782 };
744 }; 783 };
745 784
746 pdm_dc 785 pdm_dclk_a_pins: pdm-dclk-a {
747 786 mux {
748 787 groups = "pdm_dclk_a";
749 788 function = "pdm";
750 789 bias-disable;
751 790 drive-strength-microamp = <500>;
752 791 };
753 }; 792 };
754 793
755 pdm_dc 794 pdm_dclk_c_pins: pdm-dclk-c {
756 795 mux {
757 796 groups = "pdm_dclk_c";
758 797 function = "pdm";
759 798 bias-disable;
760 799 drive-strength-microamp = <500>;
761 800 };
762 }; 801 };
763 802
764 pdm_dc 803 pdm_dclk_x_pins: pdm-dclk-x {
765 804 mux {
766 805 groups = "pdm_dclk_x";
767 806 function = "pdm";
768 807 bias-disable;
769 808 drive-strength-microamp = <500>;
770 809 };
771 }; 810 };
772 811
773 pdm_dc 812 pdm_dclk_z_pins: pdm-dclk-z {
774 813 mux {
775 814 groups = "pdm_dclk_z";
776 815 function = "pdm";
777 816 bias-disable;
778 817 drive-strength-microamp = <500>;
779 818 };
780 }; 819 };
781 820
782 pwm_a_ 821 pwm_a_pins: pwm-a {
783 822 mux {
784 823 groups = "pwm_a";
785 824 function = "pwm_a";
786 825 bias-disable;
787 826 };
788 }; 827 };
789 828
790 pwm_b_ 829 pwm_b_x7_pins: pwm-b-x7 {
791 830 mux {
792 831 groups = "pwm_b_x7";
793 832 function = "pwm_b";
794 833 bias-disable;
795 834 };
796 }; 835 };
797 836
798 pwm_b_ 837 pwm_b_x19_pins: pwm-b-x19 {
799 838 mux {
800 839 groups = "pwm_b_x19";
801 840 function = "pwm_b";
802 841 bias-disable;
803 842 };
804 }; 843 };
805 844
806 pwm_c_ 845 pwm_c_c_pins: pwm-c-c {
807 846 mux {
808 847 groups = "pwm_c_c";
809 848 function = "pwm_c";
810 849 bias-disable;
811 850 };
812 }; 851 };
813 852
814 pwm_c_ 853 pwm_c_x5_pins: pwm-c-x5 {
815 854 mux {
816 855 groups = "pwm_c_x5";
817 856 function = "pwm_c";
818 857 bias-disable;
819 858 };
820 }; 859 };
821 860
822 pwm_c_ 861 pwm_c_x8_pins: pwm-c-x8 {
823 862 mux {
824 863 groups = "pwm_c_x8";
825 864 function = "pwm_c";
826 865 bias-disable;
827 866 };
828 }; 867 };
829 868
830 pwm_d_ 869 pwm_d_x3_pins: pwm-d-x3 {
831 870 mux {
832 871 groups = "pwm_d_x3";
833 872 function = "pwm_d";
834 873 bias-disable;
835 874 };
836 }; 875 };
837 876
838 pwm_d_ 877 pwm_d_x6_pins: pwm-d-x6 {
839 878 mux {
840 879 groups = "pwm_d_x6";
841 880 function = "pwm_d";
842 881 bias-disable;
843 882 };
844 }; 883 };
845 884
846 pwm_e_ 885 pwm_e_pins: pwm-e {
847 886 mux {
848 887 groups = "pwm_e";
849 888 function = "pwm_e";
850 889 bias-disable;
851 890 };
852 }; 891 };
853 892
854 pwm_f_ <<
855 <<
856 <<
857 <<
858 <<
859 <<
860 }; <<
861 <<
862 pwm_f_ <<
863 <<
864 <<
865 <<
866 <<
867 <<
868 }; <<
869 <<
870 pwm_f_ 893 pwm_f_x_pins: pwm-f-x {
871 894 mux {
872 895 groups = "pwm_f_x";
873 896 function = "pwm_f";
874 897 bias-disable;
875 898 };
876 }; 899 };
877 900
878 pwm_f_ 901 pwm_f_h_pins: pwm-f-h {
879 902 mux {
880 903 groups = "pwm_f_h";
881 904 function = "pwm_f";
882 905 bias-disable;
883 906 };
884 }; 907 };
885 908
886 sdcard 909 sdcard_c_pins: sdcard_c {
887 910 mux-0 {
888 911 groups = "sdcard_d0_c",
889 912 "sdcard_d1_c",
890 913 "sdcard_d2_c",
891 914 "sdcard_d3_c",
892 915 "sdcard_cmd_c";
893 916 function = "sdcard";
894 917 bias-pull-up;
895 918 drive-strength-microamp = <4000>;
896 919 };
897 920
898 921 mux-1 {
899 922 groups = "sdcard_clk_c";
900 923 function = "sdcard";
901 924 bias-disable;
902 925 drive-strength-microamp = <4000>;
903 926 };
904 }; 927 };
905 928
906 sdcard 929 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
907 930 mux {
908 931 groups = "GPIOC_4";
909 932 function = "gpio_periphs";
910 933 bias-pull-down;
911 934 drive-strength-microamp = <4000>;
912 935 };
913 }; 936 };
914 937
915 sdcard 938 sdcard_z_pins: sdcard_z {
916 939 mux-0 {
917 940 groups = "sdcard_d0_z",
918 941 "sdcard_d1_z",
919 942 "sdcard_d2_z",
920 943 "sdcard_d3_z",
921 944 "sdcard_cmd_z";
922 945 function = "sdcard";
923 946 bias-pull-up;
924 947 drive-strength-microamp = <4000>;
925 948 };
926 949
927 950 mux-1 {
928 951 groups = "sdcard_clk_z";
929 952 function = "sdcard";
930 953 bias-disable;
931 954 drive-strength-microamp = <4000>;
932 955 };
933 }; 956 };
934 957
935 sdcard 958 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
936 959 mux {
937 960 groups = "GPIOZ_6";
938 961 function = "gpio_periphs";
939 962 bias-pull-down;
940 963 drive-strength-microamp = <4000>;
941 964 };
942 }; 965 };
943 966
944 sdio_p 967 sdio_pins: sdio {
945 968 mux {
946 969 groups = "sdio_d0",
947 970 "sdio_d1",
948 971 "sdio_d2",
949 972 "sdio_d3",
950 973 "sdio_clk",
951 974 "sdio_cmd";
952 975 function = "sdio";
953 976 bias-disable;
954 977 drive-strength-microamp = <4000>;
955 978 };
956 }; 979 };
957 980
958 sdio_c 981 sdio_clk_gate_pins: sdio_clk_gate {
959 982 mux {
960 983 groups = "GPIOX_4";
961 984 function = "gpio_periphs";
962 985 bias-pull-down;
963 986 drive-strength-microamp = <4000>;
964 987 };
965 }; 988 };
966 989
967 spdif_ 990 spdif_in_a10_pins: spdif-in-a10 {
968 991 mux {
969 992 groups = "spdif_in_a10";
970 993 function = "spdif_in";
971 994 bias-disable;
972 995 };
973 }; 996 };
974 997
975 spdif_ 998 spdif_in_a12_pins: spdif-in-a12 {
976 999 mux {
977 1000 groups = "spdif_in_a12";
978 1001 function = "spdif_in";
979 1002 bias-disable;
980 1003 };
981 }; 1004 };
982 1005
983 spdif_ 1006 spdif_in_h_pins: spdif-in-h {
984 1007 mux {
985 1008 groups = "spdif_in_h";
986 1009 function = "spdif_in";
987 1010 bias-disable;
988 1011 };
989 }; 1012 };
990 1013
991 spdif_ 1014 spdif_out_h_pins: spdif-out-h {
992 1015 mux {
993 1016 groups = "spdif_out_h";
994 1017 function = "spdif_out";
995 !! 1018 drive-strength-microamp = <500>;
996 1019 bias-disable;
997 1020 };
998 }; 1021 };
999 1022
1000 spdif 1023 spdif_out_a11_pins: spdif-out-a11 {
1001 1024 mux {
1002 1025 groups = "spdif_out_a11";
1003 1026 function = "spdif_out";
1004 !! 1027 drive-strength-microamp = <500>;
1005 1028 bias-disable;
1006 1029 };
1007 }; 1030 };
1008 1031
1009 spdif 1032 spdif_out_a13_pins: spdif-out-a13 {
1010 1033 mux {
1011 1034 groups = "spdif_out_a13";
1012 1035 function = "spdif_out";
1013 !! 1036 drive-strength-microamp = <500>;
1014 1037 bias-disable;
1015 1038 };
1016 }; 1039 };
1017 1040
1018 spicc 1041 spicc0_x_pins: spicc0-x {
1019 1042 mux {
1020 1043 groups = "spi0_mosi_x",
1021 1044 "spi0_miso_x",
1022 1045 "spi0_clk_x";
1023 1046 function = "spi0";
1024 1047 drive-strength-microamp = <4000>;
1025 1048 bias-disable;
1026 1049 };
1027 }; 1050 };
1028 1051
1029 spicc 1052 spicc0_ss0_x_pins: spicc0-ss0-x {
1030 1053 mux {
1031 1054 groups = "spi0_ss0_x";
1032 1055 function = "spi0";
1033 1056 drive-strength-microamp = <4000>;
1034 1057 bias-disable;
1035 1058 };
1036 }; 1059 };
1037 1060
1038 spicc 1061 spicc0_c_pins: spicc0-c {
1039 1062 mux {
1040 1063 groups = "spi0_mosi_c",
1041 1064 "spi0_miso_c",
1042 1065 "spi0_ss0_c",
1043 1066 "spi0_clk_c";
1044 1067 function = "spi0";
1045 1068 drive-strength-microamp = <4000>;
1046 1069 bias-disable;
1047 1070 };
1048 }; 1071 };
1049 1072
1050 spicc 1073 spicc1_pins: spicc1 {
1051 1074 mux {
1052 1075 groups = "spi1_mosi",
1053 1076 "spi1_miso",
1054 1077 "spi1_clk";
1055 1078 function = "spi1";
1056 1079 drive-strength-microamp = <4000>;
1057 1080 };
1058 }; 1081 };
1059 1082
1060 spicc 1083 spicc1_ss0_pins: spicc1-ss0 {
1061 1084 mux {
1062 1085 groups = "spi1_ss0";
1063 1086 function = "spi1";
1064 1087 drive-strength-microamp = <4000>;
1065 1088 bias-disable;
1066 1089 };
1067 }; 1090 };
1068 1091
1069 tdm_a 1092 tdm_a_din0_pins: tdm-a-din0 {
1070 1093 mux {
1071 1094 groups = "tdm_a_din0";
1072 1095 function = "tdm_a";
1073 1096 bias-disable;
1074 1097 };
1075 }; 1098 };
1076 1099
1077 1100
1078 tdm_a 1101 tdm_a_din1_pins: tdm-a-din1 {
1079 1102 mux {
1080 1103 groups = "tdm_a_din1";
1081 1104 function = "tdm_a";
1082 1105 bias-disable;
1083 1106 };
1084 }; 1107 };
1085 1108
1086 tdm_a 1109 tdm_a_dout0_pins: tdm-a-dout0 {
1087 1110 mux {
1088 1111 groups = "tdm_a_dout0";
1089 1112 function = "tdm_a";
1090 1113 bias-disable;
1091 1114 drive-strength-microamp = <3000>;
1092 1115 };
1093 }; 1116 };
1094 1117
1095 tdm_a 1118 tdm_a_dout1_pins: tdm-a-dout1 {
1096 1119 mux {
1097 1120 groups = "tdm_a_dout1";
1098 1121 function = "tdm_a";
1099 1122 bias-disable;
1100 1123 drive-strength-microamp = <3000>;
1101 1124 };
1102 }; 1125 };
1103 1126
1104 tdm_a 1127 tdm_a_fs_pins: tdm-a-fs {
1105 1128 mux {
1106 1129 groups = "tdm_a_fs";
1107 1130 function = "tdm_a";
1108 1131 bias-disable;
1109 1132 drive-strength-microamp = <3000>;
1110 1133 };
1111 }; 1134 };
1112 1135
1113 tdm_a 1136 tdm_a_sclk_pins: tdm-a-sclk {
1114 1137 mux {
1115 1138 groups = "tdm_a_sclk";
1116 1139 function = "tdm_a";
1117 1140 bias-disable;
1118 1141 drive-strength-microamp = <3000>;
1119 1142 };
1120 }; 1143 };
1121 1144
1122 tdm_a 1145 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1123 1146 mux {
1124 1147 groups = "tdm_a_slv_fs";
1125 1148 function = "tdm_a";
1126 1149 bias-disable;
1127 1150 };
1128 }; 1151 };
1129 1152
1130 1153
1131 tdm_a 1154 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1132 1155 mux {
1133 1156 groups = "tdm_a_slv_sclk";
1134 1157 function = "tdm_a";
1135 1158 bias-disable;
1136 1159 };
1137 }; 1160 };
1138 1161
1139 tdm_b 1162 tdm_b_din0_pins: tdm-b-din0 {
1140 1163 mux {
1141 1164 groups = "tdm_b_din0";
1142 1165 function = "tdm_b";
1143 1166 bias-disable;
1144 1167 };
1145 }; 1168 };
1146 1169
1147 tdm_b 1170 tdm_b_din1_pins: tdm-b-din1 {
1148 1171 mux {
1149 1172 groups = "tdm_b_din1";
1150 1173 function = "tdm_b";
1151 1174 bias-disable;
1152 1175 };
1153 }; 1176 };
1154 1177
1155 tdm_b 1178 tdm_b_din2_pins: tdm-b-din2 {
1156 1179 mux {
1157 1180 groups = "tdm_b_din2";
1158 1181 function = "tdm_b";
1159 1182 bias-disable;
1160 1183 };
1161 }; 1184 };
1162 1185
1163 tdm_b 1186 tdm_b_din3_a_pins: tdm-b-din3-a {
1164 1187 mux {
1165 1188 groups = "tdm_b_din3_a";
1166 1189 function = "tdm_b";
1167 1190 bias-disable;
1168 1191 };
1169 }; 1192 };
1170 1193
1171 tdm_b 1194 tdm_b_din3_h_pins: tdm-b-din3-h {
1172 1195 mux {
1173 1196 groups = "tdm_b_din3_h";
1174 1197 function = "tdm_b";
1175 1198 bias-disable;
1176 1199 };
1177 }; 1200 };
1178 1201
1179 tdm_b 1202 tdm_b_dout0_pins: tdm-b-dout0 {
1180 1203 mux {
1181 1204 groups = "tdm_b_dout0";
1182 1205 function = "tdm_b";
1183 1206 bias-disable;
1184 1207 drive-strength-microamp = <3000>;
1185 1208 };
1186 }; 1209 };
1187 1210
1188 tdm_b 1211 tdm_b_dout1_pins: tdm-b-dout1 {
1189 1212 mux {
1190 1213 groups = "tdm_b_dout1";
1191 1214 function = "tdm_b";
1192 1215 bias-disable;
1193 1216 drive-strength-microamp = <3000>;
1194 1217 };
1195 }; 1218 };
1196 1219
1197 tdm_b 1220 tdm_b_dout2_pins: tdm-b-dout2 {
1198 1221 mux {
1199 1222 groups = "tdm_b_dout2";
1200 1223 function = "tdm_b";
1201 1224 bias-disable;
1202 1225 drive-strength-microamp = <3000>;
1203 1226 };
1204 }; 1227 };
1205 1228
1206 tdm_b 1229 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1207 1230 mux {
1208 1231 groups = "tdm_b_dout3_a";
1209 1232 function = "tdm_b";
1210 1233 bias-disable;
1211 1234 drive-strength-microamp = <3000>;
1212 1235 };
1213 }; 1236 };
1214 1237
1215 tdm_b 1238 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1216 1239 mux {
1217 1240 groups = "tdm_b_dout3_h";
1218 1241 function = "tdm_b";
1219 1242 bias-disable;
1220 1243 drive-strength-microamp = <3000>;
1221 1244 };
1222 }; 1245 };
1223 1246
1224 tdm_b 1247 tdm_b_fs_pins: tdm-b-fs {
1225 1248 mux {
1226 1249 groups = "tdm_b_fs";
1227 1250 function = "tdm_b";
1228 1251 bias-disable;
1229 1252 drive-strength-microamp = <3000>;
1230 1253 };
1231 }; 1254 };
1232 1255
1233 tdm_b 1256 tdm_b_sclk_pins: tdm-b-sclk {
1234 1257 mux {
1235 1258 groups = "tdm_b_sclk";
1236 1259 function = "tdm_b";
1237 1260 bias-disable;
1238 1261 drive-strength-microamp = <3000>;
1239 1262 };
1240 }; 1263 };
1241 1264
1242 tdm_b 1265 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1243 1266 mux {
1244 1267 groups = "tdm_b_slv_fs";
1245 1268 function = "tdm_b";
1246 1269 bias-disable;
1247 1270 };
1248 }; 1271 };
1249 1272
1250 tdm_b 1273 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1251 1274 mux {
1252 1275 groups = "tdm_b_slv_sclk";
1253 1276 function = "tdm_b";
1254 1277 bias-disable;
1255 1278 };
1256 }; 1279 };
1257 1280
1258 tdm_c 1281 tdm_c_din0_a_pins: tdm-c-din0-a {
1259 1282 mux {
1260 1283 groups = "tdm_c_din0_a";
1261 1284 function = "tdm_c";
1262 1285 bias-disable;
1263 1286 };
1264 }; 1287 };
1265 1288
1266 tdm_c 1289 tdm_c_din0_z_pins: tdm-c-din0-z {
1267 1290 mux {
1268 1291 groups = "tdm_c_din0_z";
1269 1292 function = "tdm_c";
1270 1293 bias-disable;
1271 1294 };
1272 }; 1295 };
1273 1296
1274 tdm_c 1297 tdm_c_din1_a_pins: tdm-c-din1-a {
1275 1298 mux {
1276 1299 groups = "tdm_c_din1_a";
1277 1300 function = "tdm_c";
1278 1301 bias-disable;
1279 1302 };
1280 }; 1303 };
1281 1304
1282 tdm_c 1305 tdm_c_din1_z_pins: tdm-c-din1-z {
1283 1306 mux {
1284 1307 groups = "tdm_c_din1_z";
1285 1308 function = "tdm_c";
1286 1309 bias-disable;
1287 1310 };
1288 }; 1311 };
1289 1312
1290 tdm_c 1313 tdm_c_din2_a_pins: tdm-c-din2-a {
1291 1314 mux {
1292 1315 groups = "tdm_c_din2_a";
1293 1316 function = "tdm_c";
1294 1317 bias-disable;
1295 1318 };
1296 }; 1319 };
1297 1320
1298 eth_l 1321 eth_leds_pins: eth-leds {
1299 1322 mux {
1300 1323 groups = "eth_link_led",
1301 1324 "eth_act_led";
1302 1325 function = "eth";
1303 1326 bias-disable;
1304 1327 };
1305 }; 1328 };
1306 1329
1307 eth_p 1330 eth_pins: eth {
1308 1331 mux {
1309 1332 groups = "eth_mdio",
1310 1333 "eth_mdc",
1311 1334 "eth_rgmii_rx_clk",
1312 1335 "eth_rx_dv",
1313 1336 "eth_rxd0",
1314 1337 "eth_rxd1",
1315 1338 "eth_txen",
1316 1339 "eth_txd0",
1317 1340 "eth_txd1";
1318 1341 function = "eth";
1319 1342 drive-strength-microamp = <4000>;
1320 1343 bias-disable;
1321 1344 };
1322 }; 1345 };
1323 1346
1324 eth_r 1347 eth_rgmii_pins: eth-rgmii {
1325 1348 mux {
1326 1349 groups = "eth_rxd2_rgmii",
1327 1350 "eth_rxd3_rgmii",
1328 1351 "eth_rgmii_tx_clk",
1329 1352 "eth_txd2_rgmii",
1330 1353 "eth_txd3_rgmii";
1331 1354 function = "eth";
1332 1355 drive-strength-microamp = <4000>;
1333 1356 bias-disable;
1334 1357 };
1335 }; 1358 };
1336 1359
1337 tdm_c 1360 tdm_c_din2_z_pins: tdm-c-din2-z {
1338 1361 mux {
1339 1362 groups = "tdm_c_din2_z";
1340 1363 function = "tdm_c";
1341 1364 bias-disable;
1342 1365 };
1343 }; 1366 };
1344 1367
1345 tdm_c 1368 tdm_c_din3_a_pins: tdm-c-din3-a {
1346 1369 mux {
1347 1370 groups = "tdm_c_din3_a";
1348 1371 function = "tdm_c";
1349 1372 bias-disable;
1350 1373 };
1351 }; 1374 };
1352 1375
1353 tdm_c 1376 tdm_c_din3_z_pins: tdm-c-din3-z {
1354 1377 mux {
1355 1378 groups = "tdm_c_din3_z";
1356 1379 function = "tdm_c";
1357 1380 bias-disable;
1358 1381 };
1359 }; 1382 };
1360 1383
1361 tdm_c 1384 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1362 1385 mux {
1363 1386 groups = "tdm_c_dout0_a";
1364 1387 function = "tdm_c";
1365 1388 bias-disable;
1366 1389 drive-strength-microamp = <3000>;
1367 1390 };
1368 }; 1391 };
1369 1392
1370 tdm_c 1393 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1371 1394 mux {
1372 1395 groups = "tdm_c_dout0_z";
1373 1396 function = "tdm_c";
1374 1397 bias-disable;
1375 1398 drive-strength-microamp = <3000>;
1376 1399 };
1377 }; 1400 };
1378 1401
1379 tdm_c 1402 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1380 1403 mux {
1381 1404 groups = "tdm_c_dout1_a";
1382 1405 function = "tdm_c";
1383 1406 bias-disable;
1384 1407 drive-strength-microamp = <3000>;
1385 1408 };
1386 }; 1409 };
1387 1410
1388 tdm_c 1411 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1389 1412 mux {
1390 1413 groups = "tdm_c_dout1_z";
1391 1414 function = "tdm_c";
1392 1415 bias-disable;
1393 1416 drive-strength-microamp = <3000>;
1394 1417 };
1395 }; 1418 };
1396 1419
1397 tdm_c 1420 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1398 1421 mux {
1399 1422 groups = "tdm_c_dout2_a";
1400 1423 function = "tdm_c";
1401 1424 bias-disable;
1402 1425 drive-strength-microamp = <3000>;
1403 1426 };
1404 }; 1427 };
1405 1428
1406 tdm_c 1429 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1407 1430 mux {
1408 1431 groups = "tdm_c_dout2_z";
1409 1432 function = "tdm_c";
1410 1433 bias-disable;
1411 1434 drive-strength-microamp = <3000>;
1412 1435 };
1413 }; 1436 };
1414 1437
1415 tdm_c 1438 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1416 1439 mux {
1417 1440 groups = "tdm_c_dout3_a";
1418 1441 function = "tdm_c";
1419 1442 bias-disable;
1420 1443 drive-strength-microamp = <3000>;
1421 1444 };
1422 }; 1445 };
1423 1446
1424 tdm_c 1447 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1425 1448 mux {
1426 1449 groups = "tdm_c_dout3_z";
1427 1450 function = "tdm_c";
1428 1451 bias-disable;
1429 1452 drive-strength-microamp = <3000>;
1430 1453 };
1431 }; 1454 };
1432 1455
1433 tdm_c 1456 tdm_c_fs_a_pins: tdm-c-fs-a {
1434 1457 mux {
1435 1458 groups = "tdm_c_fs_a";
1436 1459 function = "tdm_c";
1437 1460 bias-disable;
1438 1461 drive-strength-microamp = <3000>;
1439 1462 };
1440 }; 1463 };
1441 1464
1442 tdm_c 1465 tdm_c_fs_z_pins: tdm-c-fs-z {
1443 1466 mux {
1444 1467 groups = "tdm_c_fs_z";
1445 1468 function = "tdm_c";
1446 1469 bias-disable;
1447 1470 drive-strength-microamp = <3000>;
1448 1471 };
1449 }; 1472 };
1450 1473
1451 tdm_c 1474 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1452 1475 mux {
1453 1476 groups = "tdm_c_sclk_a";
1454 1477 function = "tdm_c";
1455 1478 bias-disable;
1456 1479 drive-strength-microamp = <3000>;
1457 1480 };
1458 }; 1481 };
1459 1482
1460 tdm_c 1483 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1461 1484 mux {
1462 1485 groups = "tdm_c_sclk_z";
1463 1486 function = "tdm_c";
1464 1487 bias-disable;
1465 1488 drive-strength-microamp = <3000>;
1466 1489 };
1467 }; 1490 };
1468 1491
1469 tdm_c 1492 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1470 1493 mux {
1471 1494 groups = "tdm_c_slv_fs_a";
1472 1495 function = "tdm_c";
1473 1496 bias-disable;
1474 1497 };
1475 }; 1498 };
1476 1499
1477 tdm_c 1500 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1478 1501 mux {
1479 1502 groups = "tdm_c_slv_fs_z";
1480 1503 function = "tdm_c";
1481 1504 bias-disable;
1482 1505 };
1483 }; 1506 };
1484 1507
1485 tdm_c 1508 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1486 1509 mux {
1487 1510 groups = "tdm_c_slv_sclk_a";
1488 1511 function = "tdm_c";
1489 1512 bias-disable;
1490 1513 };
1491 }; 1514 };
1492 1515
1493 tdm_c 1516 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1494 1517 mux {
1495 1518 groups = "tdm_c_slv_sclk_z";
1496 1519 function = "tdm_c";
1497 1520 bias-disable;
1498 1521 };
1499 }; 1522 };
1500 1523
1501 uart_ 1524 uart_a_pins: uart-a {
1502 1525 mux {
1503 1526 groups = "uart_a_tx",
1504 1527 "uart_a_rx";
1505 1528 function = "uart_a";
1506 1529 bias-disable;
1507 1530 };
1508 }; 1531 };
1509 1532
1510 uart_ 1533 uart_a_cts_rts_pins: uart-a-cts-rts {
1511 1534 mux {
1512 1535 groups = "uart_a_cts",
1513 1536 "uart_a_rts";
1514 1537 function = "uart_a";
1515 1538 bias-disable;
1516 1539 };
1517 }; 1540 };
1518 1541
1519 uart_ 1542 uart_b_pins: uart-b {
1520 1543 mux {
1521 1544 groups = "uart_b_tx",
1522 1545 "uart_b_rx";
1523 1546 function = "uart_b";
1524 1547 bias-disable;
1525 1548 };
1526 }; 1549 };
1527 1550
1528 uart_ 1551 uart_c_pins: uart-c {
1529 1552 mux {
1530 1553 groups = "uart_c_tx",
1531 1554 "uart_c_rx";
1532 1555 function = "uart_c";
1533 1556 bias-disable;
1534 1557 };
1535 }; 1558 };
1536 1559
1537 uart_ 1560 uart_c_cts_rts_pins: uart-c-cts-rts {
1538 1561 mux {
1539 1562 groups = "uart_c_cts",
1540 1563 "uart_c_rts";
1541 1564 function = "uart_c";
1542 1565 bias-disable;
1543 1566 };
1544 }; 1567 };
1545 }; 1568 };
1546 }; 1569 };
1547 1570
1548 cpu_temp: temperature 1571 cpu_temp: temperature-sensor@34800 {
1549 compatible = 1572 compatible = "amlogic,g12a-cpu-thermal",
1550 1573 "amlogic,g12a-thermal";
1551 reg = <0x0 0x 1574 reg = <0x0 0x34800 0x0 0x50>;
1552 interrupts = 1575 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1553 clocks = <&cl 1576 clocks = <&clkc CLKID_TS>;
1554 #thermal-sens 1577 #thermal-sensor-cells = <0>;
1555 amlogic,ao-se 1578 amlogic,ao-secure = <&sec_AO>;
1556 }; 1579 };
1557 1580
1558 ddr_temp: temperature 1581 ddr_temp: temperature-sensor@34c00 {
1559 compatible = 1582 compatible = "amlogic,g12a-ddr-thermal",
1560 1583 "amlogic,g12a-thermal";
1561 reg = <0x0 0x 1584 reg = <0x0 0x34c00 0x0 0x50>;
1562 interrupts = 1585 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1563 clocks = <&cl 1586 clocks = <&clkc CLKID_TS>;
1564 #thermal-sens 1587 #thermal-sensor-cells = <0>;
1565 amlogic,ao-se 1588 amlogic,ao-secure = <&sec_AO>;
1566 }; 1589 };
1567 1590
1568 usb2_phy0: phy@36000 1591 usb2_phy0: phy@36000 {
1569 compatible = 1592 compatible = "amlogic,g12a-usb2-phy";
1570 reg = <0x0 0x 1593 reg = <0x0 0x36000 0x0 0x2000>;
1571 clocks = <&xt 1594 clocks = <&xtal>;
1572 clock-names = 1595 clock-names = "xtal";
1573 resets = <&re 1596 resets = <&reset RESET_USB_PHY20>;
1574 reset-names = 1597 reset-names = "phy";
1575 #phy-cells = 1598 #phy-cells = <0>;
1576 }; 1599 };
1577 1600
1578 dmc: bus@38000 { 1601 dmc: bus@38000 {
1579 compatible = 1602 compatible = "simple-bus";
>> 1603 reg = <0x0 0x38000 0x0 0x400>;
1580 #address-cell 1604 #address-cells = <2>;
1581 #size-cells = 1605 #size-cells = <2>;
1582 ranges = <0x0 !! 1606 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1583 1607
1584 canvas: video 1608 canvas: video-lut@48 {
1585 compa 1609 compatible = "amlogic,canvas";
1586 reg = 1610 reg = <0x0 0x48 0x0 0x14>;
1587 }; 1611 };
1588 <<
1589 pmu: pmu@80 { <<
1590 reg = <<
1591 <<
1592 inter <<
1593 }; <<
1594 }; 1612 };
1595 1613
1596 usb2_phy1: phy@3a000 1614 usb2_phy1: phy@3a000 {
1597 compatible = 1615 compatible = "amlogic,g12a-usb2-phy";
1598 reg = <0x0 0x 1616 reg = <0x0 0x3a000 0x0 0x2000>;
1599 clocks = <&xt 1617 clocks = <&xtal>;
1600 clock-names = 1618 clock-names = "xtal";
1601 resets = <&re 1619 resets = <&reset RESET_USB_PHY21>;
1602 reset-names = 1620 reset-names = "phy";
1603 #phy-cells = 1621 #phy-cells = <0>;
1604 }; 1622 };
1605 1623
1606 hiu: bus@3c000 { 1624 hiu: bus@3c000 {
1607 compatible = 1625 compatible = "simple-bus";
1608 reg = <0x0 0x 1626 reg = <0x0 0x3c000 0x0 0x1400>;
1609 #address-cell 1627 #address-cells = <2>;
1610 #size-cells = 1628 #size-cells = <2>;
1611 ranges = <0x0 1629 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1612 1630
1613 hhi: system-c 1631 hhi: system-controller@0 {
1614 compa 1632 compatible = "amlogic,meson-gx-hhi-sysctrl",
1615 1633 "simple-mfd", "syscon";
1616 reg = 1634 reg = <0 0 0 0x400>;
1617 1635
1618 clkc: 1636 clkc: clock-controller {
1619 1637 compatible = "amlogic,g12a-clkc";
1620 1638 #clock-cells = <1>;
1621 1639 clocks = <&xtal>;
1622 1640 clock-names = "xtal";
1623 }; 1641 };
1624 1642
1625 pwrc: 1643 pwrc: power-controller {
1626 1644 compatible = "amlogic,meson-g12a-pwrc";
1627 1645 #power-domain-cells = <1>;
1628 1646 amlogic,ao-sysctrl = <&rti>;
1629 1647 resets = <&reset RESET_VIU>,
1630 1648 <&reset RESET_VENC>,
1631 1649 <&reset RESET_VCBUS>,
1632 1650 <&reset RESET_BT656>,
1633 1651 <&reset RESET_RDMA>,
1634 1652 <&reset RESET_VENCI>,
1635 1653 <&reset RESET_VENCP>,
1636 1654 <&reset RESET_VDAC>,
1637 1655 <&reset RESET_VDI6>,
1638 1656 <&reset RESET_VENCL>,
1639 1657 <&reset RESET_VID_LOCK>;
1640 1658 reset-names = "viu", "venc", "vcbus", "bt656",
1641 1659 "rdma", "venci", "vencp", "vdac",
1642 1660 "vdi6", "vencl", "vid_lock";
1643 1661 clocks = <&clkc CLKID_VPU>,
1644 1662 <&clkc CLKID_VAPB>;
1645 1663 clock-names = "vpu", "vapb";
1646 1664 /*
1647 1665 * VPU clocking is provided by two identical clock paths
1648 1666 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1649 1667 * free mux to safely change frequency while running.
1650 1668 * Same for VAPB but with a final gate after the glitch free mux.
1651 1669 */
1652 1670 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1653 1671 <&clkc CLKID_VPU_0>,
1654 1672 <&clkc CLKID_VPU>, /* Glitch free mux */
1655 1673 <&clkc CLKID_VAPB_0_SEL>,
1656 1674 <&clkc CLKID_VAPB_0>,
1657 1675 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1658 1676 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1659 1677 <0>, /* Do Nothing */
1660 1678 <&clkc CLKID_VPU_0>,
1661 1679 <&clkc CLKID_FCLK_DIV4>,
1662 1680 <0>, /* Do Nothing */
1663 1681 <&clkc CLKID_VAPB_0>;
1664 1682 assigned-clock-rates = <0>, /* Do Nothing */
1665 1683 <666666666>,
1666 1684 <0>, /* Do Nothing */
1667 1685 <0>, /* Do Nothing */
1668 1686 <250000000>,
1669 1687 <0>; /* Do Nothing */
1670 }; 1688 };
1671 <<
1672 mipi_ <<
1673 <<
1674 <<
1675 <<
1676 }; <<
1677 }; 1689 };
1678 }; 1690 };
1679 1691
1680 mipi_dphy: phy@44000 <<
1681 compatible = <<
1682 reg = <0x0 0x <<
1683 clocks = <&cl <<
1684 clock-names = <<
1685 resets = <&re <<
1686 reset-names = <<
1687 phys = <&mipi <<
1688 phy-names = " <<
1689 #phy-cells = <<
1690 status = "dis <<
1691 }; <<
1692 <<
1693 usb3_pcie_phy: phy@46 1692 usb3_pcie_phy: phy@46000 {
1694 compatible = 1693 compatible = "amlogic,g12a-usb3-pcie-phy";
1695 reg = <0x0 0x 1694 reg = <0x0 0x46000 0x0 0x2000>;
1696 clocks = <&cl 1695 clocks = <&clkc CLKID_PCIE_PLL>;
1697 clock-names = 1696 clock-names = "ref_clk";
1698 resets = <&re 1697 resets = <&reset RESET_PCIE_PHY>;
1699 reset-names = 1698 reset-names = "phy";
1700 assigned-cloc 1699 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1701 assigned-cloc 1700 assigned-clock-rates = <100000000>;
1702 #phy-cells = 1701 #phy-cells = <1>;
1703 }; 1702 };
1704 1703
1705 eth_phy: mdio-multipl 1704 eth_phy: mdio-multiplexer@4c000 {
1706 compatible = 1705 compatible = "amlogic,g12a-mdio-mux";
1707 reg = <0x0 0x 1706 reg = <0x0 0x4c000 0x0 0xa4>;
1708 clocks = <&cl 1707 clocks = <&clkc CLKID_ETH_PHY>,
1709 <&xt 1708 <&xtal>,
1710 <&cl 1709 <&clkc CLKID_MPLL_50M>;
1711 clock-names = 1710 clock-names = "pclk", "clkin0", "clkin1";
1712 mdio-parent-b 1711 mdio-parent-bus = <&mdio0>;
1713 #address-cell 1712 #address-cells = <1>;
1714 #size-cells = 1713 #size-cells = <0>;
1715 1714
1716 ext_mdio: mdi 1715 ext_mdio: mdio@0 {
1717 reg = 1716 reg = <0>;
1718 #addr 1717 #address-cells = <1>;
1719 #size 1718 #size-cells = <0>;
1720 }; 1719 };
1721 1720
1722 int_mdio: mdi 1721 int_mdio: mdio@1 {
1723 reg = 1722 reg = <1>;
1724 #addr 1723 #address-cells = <1>;
1725 #size 1724 #size-cells = <0>;
1726 1725
1727 inter !! 1726 internal_ephy: ethernet_phy@8 {
1728 1727 compatible = "ethernet-phy-id0180.3301",
1729 1728 "ethernet-phy-ieee802.3-c22";
1730 1729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1731 1730 reg = <8>;
1732 1731 max-speed = <100>;
1733 }; 1732 };
1734 }; 1733 };
1735 }; 1734 };
1736 }; 1735 };
1737 1736
1738 aobus: bus@ff800000 { 1737 aobus: bus@ff800000 {
1739 compatible = "simple- 1738 compatible = "simple-bus";
1740 reg = <0x0 0xff800000 1739 reg = <0x0 0xff800000 0x0 0x100000>;
1741 #address-cells = <2>; 1740 #address-cells = <2>;
1742 #size-cells = <2>; 1741 #size-cells = <2>;
1743 ranges = <0x0 0x0 0x0 1742 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1744 1743
1745 rti: sys-ctrl@0 { 1744 rti: sys-ctrl@0 {
1746 compatible = 1745 compatible = "amlogic,meson-gx-ao-sysctrl",
1747 1746 "simple-mfd", "syscon";
1748 reg = <0x0 0x 1747 reg = <0x0 0x0 0x0 0x100>;
>> 1748 #address-cells = <2>;
>> 1749 #size-cells = <2>;
>> 1750 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1749 1751
1750 clkc_AO: cloc 1752 clkc_AO: clock-controller {
1751 compa 1753 compatible = "amlogic,meson-g12a-aoclkc";
1752 #cloc 1754 #clock-cells = <1>;
1753 #rese 1755 #reset-cells = <1>;
1754 clock 1756 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1755 clock 1757 clock-names = "xtal", "mpeg-clk";
1756 }; 1758 };
1757 }; <<
1758 <<
1759 ao_pinctrl: pinctrl@1 <<
1760 compatible = <<
1761 #address-cell <<
1762 #size-cells = <<
1763 ranges; <<
1764 <<
1765 gpio_ao: bank <<
1766 reg = <<
1767 <<
1768 <<
1769 reg-n <<
1770 <<
1771 <<
1772 gpio- <<
1773 #gpio <<
1774 gpio- <<
1775 }; <<
1776 1759
1777 i2c_ao_sck_pi !! 1760 ao_pinctrl: pinctrl@14 {
1778 mux { !! 1761 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1779 !! 1762 #address-cells = <2>;
1780 !! 1763 #size-cells = <2>;
1781 !! 1764 ranges;
1782 <<
1783 }; <<
1784 }; <<
1785 <<
1786 i2c_ao_sda_pi <<
1787 mux { <<
1788 <<
1789 <<
1790 <<
1791 <<
1792 }; <<
1793 }; <<
1794 1765
1795 i2c_ao_sck_e_ !! 1766 gpio_ao: bank@14 {
1796 mux { !! 1767 reg = <0x0 0x14 0x0 0x8>,
1797 !! 1768 <0x0 0x1c 0x0 0x8>,
1798 !! 1769 <0x0 0x24 0x0 0x14>;
1799 !! 1770 reg-names = "mux",
1800 !! 1771 "ds",
>> 1772 "gpio";
>> 1773 gpio-controller;
>> 1774 #gpio-cells = <2>;
>> 1775 gpio-ranges = <&ao_pinctrl 0 0 15>;
1801 }; 1776 };
1802 }; <<
1803 1777
1804 i2c_ao_sda_e_ !! 1778 i2c_ao_sck_pins: i2c_ao_sck_pins {
1805 mux { !! 1779 mux {
1806 !! 1780 groups = "i2c_ao_sck";
1807 !! 1781 function = "i2c_ao";
1808 !! 1782 bias-disable;
1809 !! 1783 drive-strength-microamp = <3000>;
>> 1784 };
1810 }; 1785 };
1811 }; <<
1812 1786
1813 mclk0_ao_pins !! 1787 i2c_ao_sda_pins: i2c_ao_sda {
1814 mux { !! 1788 mux {
1815 !! 1789 groups = "i2c_ao_sda";
1816 !! 1790 function = "i2c_ao";
1817 !! 1791 bias-disable;
1818 !! 1792 drive-strength-microamp = <3000>;
>> 1793 };
1819 }; 1794 };
1820 }; <<
1821 1795
1822 tdm_ao_b_din0 !! 1796 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1823 mux { !! 1797 mux {
1824 !! 1798 groups = "i2c_ao_sck_e";
1825 !! 1799 function = "i2c_ao";
1826 !! 1800 bias-disable;
>> 1801 drive-strength-microamp = <3000>;
>> 1802 };
1827 }; 1803 };
1828 }; <<
1829 1804
1830 spdif_ao_out_ !! 1805 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1831 mux { !! 1806 mux {
1832 !! 1807 groups = "i2c_ao_sda_e";
1833 !! 1808 function = "i2c_ao";
1834 !! 1809 bias-disable;
1835 !! 1810 drive-strength-microamp = <3000>;
>> 1811 };
1836 }; 1812 };
1837 }; <<
1838 1813
1839 tdm_ao_b_din1 !! 1814 mclk0_ao_pins: mclk0-ao {
1840 mux { !! 1815 mux {
1841 !! 1816 groups = "mclk0_ao";
1842 !! 1817 function = "mclk0_ao";
1843 !! 1818 bias-disable;
>> 1819 drive-strength-microamp = <3000>;
>> 1820 };
1844 }; 1821 };
1845 }; <<
1846 1822
1847 tdm_ao_b_din2 !! 1823 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1848 mux { !! 1824 mux {
1849 !! 1825 groups = "tdm_ao_b_din0";
1850 !! 1826 function = "tdm_ao_b";
1851 !! 1827 bias-disable;
>> 1828 };
1852 }; 1829 };
1853 }; <<
1854 1830
1855 tdm_ao_b_dout !! 1831 spdif_ao_out_pins: spdif-ao-out {
1856 mux { !! 1832 mux {
1857 !! 1833 groups = "spdif_ao_out";
1858 !! 1834 function = "spdif_ao_out";
1859 !! 1835 drive-strength-microamp = <500>;
1860 !! 1836 bias-disable;
>> 1837 };
1861 }; 1838 };
1862 }; <<
1863 1839
1864 tdm_ao_b_dout !! 1840 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1865 mux { !! 1841 mux {
1866 !! 1842 groups = "tdm_ao_b_din1";
1867 !! 1843 function = "tdm_ao_b";
1868 !! 1844 bias-disable;
1869 !! 1845 };
1870 }; 1846 };
1871 }; <<
1872 1847
1873 tdm_ao_b_dout !! 1848 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1874 mux { !! 1849 mux {
1875 !! 1850 groups = "tdm_ao_b_din2";
1876 !! 1851 function = "tdm_ao_b";
1877 !! 1852 bias-disable;
1878 !! 1853 };
1879 }; 1854 };
1880 }; <<
1881 1855
1882 tdm_ao_b_fs_p !! 1856 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1883 mux { !! 1857 mux {
1884 !! 1858 groups = "tdm_ao_b_dout0";
1885 !! 1859 function = "tdm_ao_b";
1886 !! 1860 bias-disable;
1887 !! 1861 drive-strength-microamp = <3000>;
>> 1862 };
1888 }; 1863 };
1889 }; <<
1890 1864
1891 tdm_ao_b_sclk !! 1865 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1892 mux { !! 1866 mux {
1893 !! 1867 groups = "tdm_ao_b_dout1";
1894 !! 1868 function = "tdm_ao_b";
1895 !! 1869 bias-disable;
1896 !! 1870 drive-strength-microamp = <3000>;
>> 1871 };
1897 }; 1872 };
1898 }; <<
1899 1873
1900 tdm_ao_b_slv_ !! 1874 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1901 mux { !! 1875 mux {
1902 !! 1876 groups = "tdm_ao_b_dout2";
1903 !! 1877 function = "tdm_ao_b";
1904 !! 1878 bias-disable;
>> 1879 drive-strength-microamp = <3000>;
>> 1880 };
1905 }; 1881 };
1906 }; <<
1907 1882
1908 tdm_ao_b_slv_ !! 1883 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1909 mux { !! 1884 mux {
1910 !! 1885 groups = "tdm_ao_b_fs";
1911 !! 1886 function = "tdm_ao_b";
1912 !! 1887 bias-disable;
>> 1888 drive-strength-microamp = <3000>;
>> 1889 };
1913 }; 1890 };
1914 }; <<
1915 1891
1916 uart_ao_a_pin !! 1892 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1917 mux { !! 1893 mux {
1918 !! 1894 groups = "tdm_ao_b_sclk";
1919 !! 1895 function = "tdm_ao_b";
1920 !! 1896 bias-disable;
1921 !! 1897 drive-strength-microamp = <3000>;
>> 1898 };
1922 }; 1899 };
1923 }; <<
1924 1900
1925 uart_ao_a_cts !! 1901 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1926 mux { !! 1902 mux {
1927 !! 1903 groups = "tdm_ao_b_slv_fs";
1928 !! 1904 function = "tdm_ao_b";
1929 !! 1905 bias-disable;
1930 !! 1906 };
1931 }; 1907 };
1932 }; <<
1933 1908
1934 uart_ao_b_2_3 !! 1909 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1935 mux { !! 1910 mux {
1936 !! 1911 groups = "tdm_ao_b_slv_sclk";
1937 !! 1912 function = "tdm_ao_b";
1938 !! 1913 bias-disable;
1939 !! 1914 };
1940 }; 1915 };
1941 }; <<
1942 1916
1943 uart_ao_b_8_9 !! 1917 uart_ao_a_pins: uart-a-ao {
1944 mux { !! 1918 mux {
1945 !! 1919 groups = "uart_ao_a_tx",
1946 !! 1920 "uart_ao_a_rx";
1947 !! 1921 function = "uart_ao_a";
1948 !! 1922 bias-disable;
>> 1923 };
1949 }; 1924 };
1950 }; <<
1951 1925
1952 uart_ao_b_cts !! 1926 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1953 mux { !! 1927 mux {
1954 !! 1928 groups = "uart_ao_a_cts",
1955 !! 1929 "uart_ao_a_rts";
1956 !! 1930 function = "uart_ao_a";
1957 !! 1931 bias-disable;
>> 1932 };
1958 }; 1933 };
1959 }; <<
1960 1934
1961 pwm_a_e_pins: !! 1935 pwm_a_e_pins: pwm-a-e {
1962 mux { !! 1936 mux {
1963 !! 1937 groups = "pwm_a_e";
1964 !! 1938 function = "pwm_a_e";
1965 !! 1939 bias-disable;
>> 1940 };
1966 }; 1941 };
1967 }; <<
1968 1942
1969 pwm_ao_a_pins !! 1943 pwm_ao_a_pins: pwm-ao-a {
1970 mux { !! 1944 mux {
1971 !! 1945 groups = "pwm_ao_a";
1972 !! 1946 function = "pwm_ao_a";
1973 !! 1947 bias-disable;
>> 1948 };
1974 }; 1949 };
1975 }; <<
1976 1950
1977 pwm_ao_b_pins !! 1951 pwm_ao_b_pins: pwm-ao-b {
1978 mux { !! 1952 mux {
1979 !! 1953 groups = "pwm_ao_b";
1980 !! 1954 function = "pwm_ao_b";
1981 !! 1955 bias-disable;
>> 1956 };
1982 }; 1957 };
1983 }; <<
1984 1958
1985 pwm_ao_c_4_pi !! 1959 pwm_ao_c_4_pins: pwm-ao-c-4 {
1986 mux { !! 1960 mux {
1987 !! 1961 groups = "pwm_ao_c_4";
1988 !! 1962 function = "pwm_ao_c";
1989 !! 1963 bias-disable;
>> 1964 };
1990 }; 1965 };
1991 }; <<
1992 1966
1993 pwm_ao_c_6_pi !! 1967 pwm_ao_c_6_pins: pwm-ao-c-6 {
1994 mux { !! 1968 mux {
1995 !! 1969 groups = "pwm_ao_c_6";
1996 !! 1970 function = "pwm_ao_c";
1997 !! 1971 bias-disable;
>> 1972 };
1998 }; 1973 };
1999 }; <<
2000 1974
2001 pwm_ao_d_5_pi !! 1975 pwm_ao_d_5_pins: pwm-ao-d-5 {
2002 mux { !! 1976 mux {
2003 !! 1977 groups = "pwm_ao_d_5";
2004 !! 1978 function = "pwm_ao_d";
2005 !! 1979 bias-disable;
>> 1980 };
2006 }; 1981 };
2007 }; <<
2008 1982
2009 pwm_ao_d_10_p !! 1983 pwm_ao_d_10_pins: pwm-ao-d-10 {
2010 mux { !! 1984 mux {
2011 !! 1985 groups = "pwm_ao_d_10";
2012 !! 1986 function = "pwm_ao_d";
2013 !! 1987 bias-disable;
>> 1988 };
2014 }; 1989 };
2015 }; <<
2016 1990
2017 pwm_ao_d_e_pi !! 1991 pwm_ao_d_e_pins: pwm-ao-d-e {
2018 mux { !! 1992 mux {
2019 !! 1993 groups = "pwm_ao_d_e";
2020 !! 1994 function = "pwm_ao_d";
>> 1995 };
2021 }; 1996 };
2022 }; <<
2023 1997
2024 remote_input_ !! 1998 remote_input_ao_pins: remote-input-ao {
2025 mux { !! 1999 mux {
2026 !! 2000 groups = "remote_ao_input";
2027 !! 2001 function = "remote_ao_input";
2028 !! 2002 bias-disable;
>> 2003 };
2029 }; 2004 };
2030 }; 2005 };
2031 }; 2006 };
2032 2007
2033 vrtc: rtc@a8 { !! 2008 vrtc: rtc@0a8 {
2034 compatible = 2009 compatible = "amlogic,meson-vrtc";
2035 reg = <0x0 0x 2010 reg = <0x0 0x000a8 0x0 0x4>;
2036 }; 2011 };
2037 2012
2038 cec_AO: cec@100 { 2013 cec_AO: cec@100 {
2039 compatible = 2014 compatible = "amlogic,meson-gx-ao-cec";
2040 reg = <0x0 0x 2015 reg = <0x0 0x00100 0x0 0x14>;
2041 interrupts = 2016 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2042 clocks = <&cl 2017 clocks = <&clkc_AO CLKID_AO_CEC>;
2043 clock-names = 2018 clock-names = "core";
2044 status = "dis 2019 status = "disabled";
2045 }; 2020 };
2046 2021
2047 sec_AO: ao-secure@140 2022 sec_AO: ao-secure@140 {
2048 compatible = 2023 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2049 reg = <0x0 0x 2024 reg = <0x0 0x140 0x0 0x140>;
2050 amlogic,has-c 2025 amlogic,has-chip-id;
2051 }; 2026 };
2052 2027
2053 cecb_AO: cec@280 { 2028 cecb_AO: cec@280 {
2054 compatible = 2029 compatible = "amlogic,meson-g12a-ao-cec";
2055 reg = <0x0 0x 2030 reg = <0x0 0x00280 0x0 0x1c>;
2056 interrupts = 2031 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2057 clocks = <&cl 2032 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2058 clock-names = 2033 clock-names = "oscin";
2059 status = "dis 2034 status = "disabled";
2060 }; 2035 };
2061 2036
2062 pwm_AO_cd: pwm@2000 { 2037 pwm_AO_cd: pwm@2000 {
2063 compatible = 2038 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2064 reg = <0x0 0x 2039 reg = <0x0 0x2000 0x0 0x20>;
2065 #pwm-cells = 2040 #pwm-cells = <3>;
2066 status = "dis 2041 status = "disabled";
2067 }; 2042 };
2068 2043
2069 uart_AO: serial@3000 2044 uart_AO: serial@3000 {
2070 compatible = !! 2045 compatible = "amlogic,meson-gx-uart",
2071 <<
2072 2046 "amlogic,meson-ao-uart";
2073 reg = <0x0 0x 2047 reg = <0x0 0x3000 0x0 0x18>;
2074 interrupts = 2048 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2075 clocks = <&xt 2049 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2076 clock-names = 2050 clock-names = "xtal", "pclk", "baud";
2077 status = "dis 2051 status = "disabled";
2078 }; 2052 };
2079 2053
2080 uart_AO_B: serial@400 2054 uart_AO_B: serial@4000 {
2081 compatible = !! 2055 compatible = "amlogic,meson-gx-uart",
2082 <<
2083 2056 "amlogic,meson-ao-uart";
2084 reg = <0x0 0x 2057 reg = <0x0 0x4000 0x0 0x18>;
2085 interrupts = 2058 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2086 clocks = <&xt 2059 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2087 clock-names = 2060 clock-names = "xtal", "pclk", "baud";
2088 status = "dis 2061 status = "disabled";
2089 }; 2062 };
2090 2063
2091 i2c_AO: i2c@5000 { 2064 i2c_AO: i2c@5000 {
2092 compatible = 2065 compatible = "amlogic,meson-axg-i2c";
2093 status = "dis 2066 status = "disabled";
2094 reg = <0x0 0x 2067 reg = <0x0 0x05000 0x0 0x20>;
2095 interrupts = 2068 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2096 #address-cell 2069 #address-cells = <1>;
2097 #size-cells = 2070 #size-cells = <0>;
2098 clocks = <&cl 2071 clocks = <&clkc CLKID_I2C>;
2099 }; 2072 };
2100 2073
2101 pwm_AO_ab: pwm@7000 { 2074 pwm_AO_ab: pwm@7000 {
2102 compatible = 2075 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2103 reg = <0x0 0x 2076 reg = <0x0 0x7000 0x0 0x20>;
2104 #pwm-cells = 2077 #pwm-cells = <3>;
2105 status = "dis 2078 status = "disabled";
2106 }; 2079 };
2107 2080
2108 ir: ir@8000 { 2081 ir: ir@8000 {
2109 compatible = 2082 compatible = "amlogic,meson-gxbb-ir";
2110 reg = <0x0 0x 2083 reg = <0x0 0x8000 0x0 0x20>;
2111 interrupts = 2084 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2112 status = "dis 2085 status = "disabled";
2113 }; 2086 };
2114 2087
2115 saradc: adc@9000 { 2088 saradc: adc@9000 {
2116 compatible = 2089 compatible = "amlogic,meson-g12a-saradc",
2117 2090 "amlogic,meson-saradc";
2118 reg = <0x0 0x 2091 reg = <0x0 0x9000 0x0 0x48>;
2119 #io-channel-c 2092 #io-channel-cells = <1>;
2120 interrupts = 2093 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2121 clocks = <&xt 2094 clocks = <&xtal>,
2122 <&cl 2095 <&clkc_AO CLKID_AO_SAR_ADC>,
2123 <&cl 2096 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2124 <&cl 2097 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2125 clock-names = 2098 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2126 status = "dis 2099 status = "disabled";
2127 }; 2100 };
2128 }; 2101 };
2129 2102
2130 vdec: video-decoder@ff620000 2103 vdec: video-decoder@ff620000 {
2131 compatible = "amlogic 2104 compatible = "amlogic,g12a-vdec";
2132 reg = <0x0 0xff620000 2105 reg = <0x0 0xff620000 0x0 0x10000>,
2133 <0x0 0xffd0e180 2106 <0x0 0xffd0e180 0x0 0xe4>;
2134 reg-names = "dos", "e 2107 reg-names = "dos", "esparser";
2135 interrupts = <GIC_SPI 2108 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2136 <GIC_SPI 2109 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2137 interrupt-names = "vd 2110 interrupt-names = "vdec", "esparser";
2138 2111
2139 amlogic,ao-sysctrl = 2112 amlogic,ao-sysctrl = <&rti>;
2140 amlogic,canvas = <&ca 2113 amlogic,canvas = <&canvas>;
2141 2114
2142 clocks = <&clkc CLKID 2115 clocks = <&clkc CLKID_PARSER>,
2143 <&clkc CLKID 2116 <&clkc CLKID_DOS>,
2144 <&clkc CLKID 2117 <&clkc CLKID_VDEC_1>,
2145 <&clkc CLKID 2118 <&clkc CLKID_VDEC_HEVC>,
2146 <&clkc CLKID 2119 <&clkc CLKID_VDEC_HEVCF>;
2147 clock-names = "dos_pa 2120 clock-names = "dos_parser", "dos", "vdec_1",
2148 "vdec_h 2121 "vdec_hevc", "vdec_hevcf";
2149 resets = <&reset RESE 2122 resets = <&reset RESET_PARSER>;
2150 reset-names = "espars 2123 reset-names = "esparser";
2151 }; 2124 };
2152 2125
2153 vpu: vpu@ff900000 { 2126 vpu: vpu@ff900000 {
2154 compatible = "amlogic 2127 compatible = "amlogic,meson-g12a-vpu";
2155 reg = <0x0 0xff900000 2128 reg = <0x0 0xff900000 0x0 0x100000>,
2156 <0x0 0xff63c000 2129 <0x0 0xff63c000 0x0 0x1000>;
2157 reg-names = "vpu", "h 2130 reg-names = "vpu", "hhi";
2158 interrupts = <GIC_SPI 2131 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2159 #address-cells = <1>; 2132 #address-cells = <1>;
2160 #size-cells = <0>; 2133 #size-cells = <0>;
2161 amlogic,canvas = <&ca 2134 amlogic,canvas = <&canvas>;
2162 2135
2163 /* CVBS VDAC output p 2136 /* CVBS VDAC output port */
2164 cvbs_vdac_port: port@ 2137 cvbs_vdac_port: port@0 {
2165 reg = <0>; 2138 reg = <0>;
2166 }; 2139 };
2167 2140
2168 /* HDMI-TX output por 2141 /* HDMI-TX output port */
2169 hdmi_tx_port: port@1 2142 hdmi_tx_port: port@1 {
2170 reg = <1>; 2143 reg = <1>;
2171 2144
2172 hdmi_tx_out: 2145 hdmi_tx_out: endpoint {
2173 remot 2146 remote-endpoint = <&hdmi_tx_in>;
2174 }; 2147 };
2175 }; 2148 };
2176 <<
2177 /* DPI output port */ <<
2178 dpi_port: port@2 { <<
2179 reg = <2>; <<
2180 <<
2181 dpi_out: endp <<
2182 remot <<
2183 }; <<
2184 }; <<
2185 }; 2149 };
2186 2150
2187 gic: interrupt-controller@ffc 2151 gic: interrupt-controller@ffc01000 {
2188 compatible = "arm,gic 2152 compatible = "arm,gic-400";
2189 reg = <0x0 0xffc01000 2153 reg = <0x0 0xffc01000 0 0x1000>,
2190 <0x0 0xffc02000 2154 <0x0 0xffc02000 0 0x2000>,
2191 <0x0 0xffc04000 2155 <0x0 0xffc04000 0 0x2000>,
2192 <0x0 0xffc06000 2156 <0x0 0xffc06000 0 0x2000>;
2193 interrupt-controller; 2157 interrupt-controller;
2194 interrupts = <GIC_PPI 2158 interrupts = <GIC_PPI 9
2195 (GIC_CPU_MASK 2159 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2196 #interrupt-cells = <3 2160 #interrupt-cells = <3>;
2197 #address-cells = <0>; 2161 #address-cells = <0>;
2198 }; 2162 };
2199 2163
2200 cbus: bus@ffd00000 { 2164 cbus: bus@ffd00000 {
2201 compatible = "simple- 2165 compatible = "simple-bus";
2202 reg = <0x0 0xffd00000 2166 reg = <0x0 0xffd00000 0x0 0x100000>;
2203 #address-cells = <2>; 2167 #address-cells = <2>;
2204 #size-cells = <2>; 2168 #size-cells = <2>;
2205 ranges = <0x0 0x0 0x0 2169 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2206 2170
2207 reset: reset-controll 2171 reset: reset-controller@1004 {
2208 compatible = 2172 compatible = "amlogic,meson-axg-reset";
2209 reg = <0x0 0x 2173 reg = <0x0 0x1004 0x0 0x9c>;
2210 #reset-cells 2174 #reset-cells = <1>;
2211 }; 2175 };
2212 2176
2213 gpio_intc: interrupt- 2177 gpio_intc: interrupt-controller@f080 {
2214 compatible = 2178 compatible = "amlogic,meson-g12a-gpio-intc",
2215 2179 "amlogic,meson-gpio-intc";
2216 reg = <0x0 0x 2180 reg = <0x0 0xf080 0x0 0x10>;
2217 interrupt-con 2181 interrupt-controller;
2218 #interrupt-ce 2182 #interrupt-cells = <2>;
2219 amlogic,chann 2183 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2220 }; 2184 };
2221 2185
2222 mipi_dsi: dsi@7000 { <<
2223 compatible = <<
2224 reg = <0x0 0x <<
2225 resets = <&re <<
2226 reset-names = <<
2227 clocks = <&cl <<
2228 <&cl <<
2229 <&cl <<
2230 clock-names = <<
2231 phys = <&mipi <<
2232 phy-names = " <<
2233 #address-cell <<
2234 #size-cells = <<
2235 status = "dis <<
2236 <<
2237 assigned-cloc <<
2238 <&cl <<
2239 <&cl <<
2240 assigned-cloc <<
2241 <&cl <<
2242 <&cl <<
2243 <<
2244 ports { <<
2245 #addr <<
2246 #size <<
2247 <<
2248 /* VP <<
2249 mipi_ <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 <<
2257 /* DS <<
2258 mipi_ <<
2259 <<
2260 }; <<
2261 }; <<
2262 }; <<
2263 <<
2264 watchdog: watchdog@f0 <<
2265 compatible = <<
2266 reg = <0x0 0x <<
2267 clocks = <&xt <<
2268 }; <<
2269 <<
2270 spicc0: spi@13000 { 2186 spicc0: spi@13000 {
2271 compatible = 2187 compatible = "amlogic,meson-g12a-spicc";
2272 reg = <0x0 0x 2188 reg = <0x0 0x13000 0x0 0x44>;
2273 interrupts = 2189 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2274 clocks = <&cl 2190 clocks = <&clkc CLKID_SPICC0>,
2275 <&cl 2191 <&clkc CLKID_SPICC0_SCLK>;
2276 clock-names = 2192 clock-names = "core", "pclk";
2277 #address-cell 2193 #address-cells = <1>;
2278 #size-cells = 2194 #size-cells = <0>;
2279 status = "dis 2195 status = "disabled";
2280 }; 2196 };
2281 2197
2282 spicc1: spi@15000 { 2198 spicc1: spi@15000 {
2283 compatible = 2199 compatible = "amlogic,meson-g12a-spicc";
2284 reg = <0x0 0x 2200 reg = <0x0 0x15000 0x0 0x44>;
2285 interrupts = 2201 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2286 clocks = <&cl 2202 clocks = <&clkc CLKID_SPICC1>,
2287 <&cl 2203 <&clkc CLKID_SPICC1_SCLK>;
2288 clock-names = 2204 clock-names = "core", "pclk";
2289 #address-cell 2205 #address-cells = <1>;
2290 #size-cells = 2206 #size-cells = <0>;
2291 status = "dis 2207 status = "disabled";
2292 }; 2208 };
2293 2209
2294 spifc: spi@14000 { 2210 spifc: spi@14000 {
2295 compatible = 2211 compatible = "amlogic,meson-gxbb-spifc";
2296 status = "dis 2212 status = "disabled";
2297 reg = <0x0 0x 2213 reg = <0x0 0x14000 0x0 0x80>;
2298 #address-cell 2214 #address-cells = <1>;
2299 #size-cells = 2215 #size-cells = <0>;
2300 clocks = <&cl 2216 clocks = <&clkc CLKID_CLK81>;
2301 }; 2217 };
2302 2218
2303 pwm_ef: pwm@19000 { 2219 pwm_ef: pwm@19000 {
2304 compatible = 2220 compatible = "amlogic,meson-g12a-ee-pwm";
2305 reg = <0x0 0x 2221 reg = <0x0 0x19000 0x0 0x20>;
2306 #pwm-cells = 2222 #pwm-cells = <3>;
2307 status = "dis 2223 status = "disabled";
2308 }; 2224 };
2309 2225
2310 pwm_cd: pwm@1a000 { 2226 pwm_cd: pwm@1a000 {
2311 compatible = 2227 compatible = "amlogic,meson-g12a-ee-pwm";
2312 reg = <0x0 0x 2228 reg = <0x0 0x1a000 0x0 0x20>;
2313 #pwm-cells = 2229 #pwm-cells = <3>;
2314 status = "dis 2230 status = "disabled";
2315 }; 2231 };
2316 2232
2317 pwm_ab: pwm@1b000 { 2233 pwm_ab: pwm@1b000 {
2318 compatible = 2234 compatible = "amlogic,meson-g12a-ee-pwm";
2319 reg = <0x0 0x 2235 reg = <0x0 0x1b000 0x0 0x20>;
2320 #pwm-cells = 2236 #pwm-cells = <3>;
2321 status = "dis 2237 status = "disabled";
2322 }; 2238 };
2323 2239
2324 i2c3: i2c@1c000 { 2240 i2c3: i2c@1c000 {
2325 compatible = 2241 compatible = "amlogic,meson-axg-i2c";
2326 status = "dis 2242 status = "disabled";
2327 reg = <0x0 0x 2243 reg = <0x0 0x1c000 0x0 0x20>;
2328 interrupts = 2244 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2329 #address-cell 2245 #address-cells = <1>;
2330 #size-cells = 2246 #size-cells = <0>;
2331 clocks = <&cl 2247 clocks = <&clkc CLKID_I2C>;
2332 }; 2248 };
2333 2249
2334 i2c2: i2c@1d000 { 2250 i2c2: i2c@1d000 {
2335 compatible = 2251 compatible = "amlogic,meson-axg-i2c";
2336 status = "dis 2252 status = "disabled";
2337 reg = <0x0 0x 2253 reg = <0x0 0x1d000 0x0 0x20>;
2338 interrupts = 2254 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2339 #address-cell 2255 #address-cells = <1>;
2340 #size-cells = 2256 #size-cells = <0>;
2341 clocks = <&cl 2257 clocks = <&clkc CLKID_I2C>;
2342 }; 2258 };
2343 2259
2344 i2c1: i2c@1e000 { 2260 i2c1: i2c@1e000 {
2345 compatible = 2261 compatible = "amlogic,meson-axg-i2c";
2346 status = "dis 2262 status = "disabled";
2347 reg = <0x0 0x 2263 reg = <0x0 0x1e000 0x0 0x20>;
2348 interrupts = 2264 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2349 #address-cell 2265 #address-cells = <1>;
2350 #size-cells = 2266 #size-cells = <0>;
2351 clocks = <&cl 2267 clocks = <&clkc CLKID_I2C>;
2352 }; 2268 };
2353 2269
2354 i2c0: i2c@1f000 { 2270 i2c0: i2c@1f000 {
2355 compatible = 2271 compatible = "amlogic,meson-axg-i2c";
2356 status = "dis 2272 status = "disabled";
2357 reg = <0x0 0x 2273 reg = <0x0 0x1f000 0x0 0x20>;
2358 interrupts = 2274 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2359 #address-cell 2275 #address-cells = <1>;
2360 #size-cells = 2276 #size-cells = <0>;
2361 clocks = <&cl 2277 clocks = <&clkc CLKID_I2C>;
2362 }; 2278 };
2363 2279
2364 clk_msr: clock-measur 2280 clk_msr: clock-measure@18000 {
2365 compatible = 2281 compatible = "amlogic,meson-g12a-clk-measure";
2366 reg = <0x0 0x 2282 reg = <0x0 0x18000 0x0 0x10>;
2367 }; 2283 };
2368 2284
2369 uart_C: serial@22000 2285 uart_C: serial@22000 {
2370 compatible = !! 2286 compatible = "amlogic,meson-gx-uart";
2371 <<
2372 reg = <0x0 0x 2287 reg = <0x0 0x22000 0x0 0x18>;
2373 interrupts = 2288 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2374 clocks = <&xt 2289 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2375 clock-names = 2290 clock-names = "xtal", "pclk", "baud";
2376 status = "dis 2291 status = "disabled";
2377 }; 2292 };
2378 2293
2379 uart_B: serial@23000 2294 uart_B: serial@23000 {
2380 compatible = !! 2295 compatible = "amlogic,meson-gx-uart";
2381 <<
2382 reg = <0x0 0x 2296 reg = <0x0 0x23000 0x0 0x18>;
2383 interrupts = 2297 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2384 clocks = <&xt 2298 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2385 clock-names = 2299 clock-names = "xtal", "pclk", "baud";
2386 status = "dis 2300 status = "disabled";
2387 }; 2301 };
2388 2302
2389 uart_A: serial@24000 2303 uart_A: serial@24000 {
2390 compatible = !! 2304 compatible = "amlogic,meson-gx-uart";
2391 <<
2392 reg = <0x0 0x 2305 reg = <0x0 0x24000 0x0 0x18>;
2393 interrupts = 2306 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2394 clocks = <&xt 2307 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2395 clock-names = 2308 clock-names = "xtal", "pclk", "baud";
2396 status = "dis 2309 status = "disabled";
2397 fifo-size = < <<
2398 }; 2310 };
2399 }; 2311 };
2400 2312
2401 sd_emmc_a: mmc@ffe03000 { !! 2313 sd_emmc_a: sd@ffe03000 {
2402 compatible = "amlogic 2314 compatible = "amlogic,meson-axg-mmc";
2403 reg = <0x0 0xffe03000 2315 reg = <0x0 0xffe03000 0x0 0x800>;
2404 interrupts = <GIC_SPI !! 2316 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2405 status = "disabled"; 2317 status = "disabled";
2406 clocks = <&clkc CLKID 2318 clocks = <&clkc CLKID_SD_EMMC_A>,
2407 <&clkc CLKID 2319 <&clkc CLKID_SD_EMMC_A_CLK0>,
2408 <&clkc CLKID 2320 <&clkc CLKID_FCLK_DIV2>;
2409 clock-names = "core", 2321 clock-names = "core", "clkin0", "clkin1";
2410 resets = <&reset RESE 2322 resets = <&reset RESET_SD_EMMC_A>;
2411 }; 2323 };
2412 2324
2413 sd_emmc_b: mmc@ffe05000 { !! 2325 sd_emmc_b: sd@ffe05000 {
2414 compatible = "amlogic 2326 compatible = "amlogic,meson-axg-mmc";
2415 reg = <0x0 0xffe05000 2327 reg = <0x0 0xffe05000 0x0 0x800>;
2416 interrupts = <GIC_SPI !! 2328 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2417 status = "disabled"; 2329 status = "disabled";
2418 clocks = <&clkc CLKID 2330 clocks = <&clkc CLKID_SD_EMMC_B>,
2419 <&clkc CLKID 2331 <&clkc CLKID_SD_EMMC_B_CLK0>,
2420 <&clkc CLKID 2332 <&clkc CLKID_FCLK_DIV2>;
2421 clock-names = "core", 2333 clock-names = "core", "clkin0", "clkin1";
2422 resets = <&reset RESE 2334 resets = <&reset RESET_SD_EMMC_B>;
2423 }; 2335 };
2424 2336
2425 sd_emmc_c: mmc@ffe07000 { 2337 sd_emmc_c: mmc@ffe07000 {
2426 compatible = "amlogic 2338 compatible = "amlogic,meson-axg-mmc";
2427 reg = <0x0 0xffe07000 2339 reg = <0x0 0xffe07000 0x0 0x800>;
2428 interrupts = <GIC_SPI !! 2340 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2429 status = "disabled"; 2341 status = "disabled";
2430 clocks = <&clkc CLKID 2342 clocks = <&clkc CLKID_SD_EMMC_C>,
2431 <&clkc CLKID 2343 <&clkc CLKID_SD_EMMC_C_CLK0>,
2432 <&clkc CLKID 2344 <&clkc CLKID_FCLK_DIV2>;
2433 clock-names = "core", 2345 clock-names = "core", "clkin0", "clkin1";
2434 resets = <&reset RESE 2346 resets = <&reset RESET_SD_EMMC_C>;
2435 }; 2347 };
2436 2348
2437 usb: usb@ffe09000 { 2349 usb: usb@ffe09000 {
2438 status = "disabled"; 2350 status = "disabled";
2439 compatible = "amlogic 2351 compatible = "amlogic,meson-g12a-usb-ctrl";
2440 reg = <0x0 0xffe09000 2352 reg = <0x0 0xffe09000 0x0 0xa0>;
2441 interrupts = <GIC_SPI 2353 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2442 #address-cells = <2>; 2354 #address-cells = <2>;
2443 #size-cells = <2>; 2355 #size-cells = <2>;
2444 ranges; 2356 ranges;
2445 2357
2446 clocks = <&clkc CLKID 2358 clocks = <&clkc CLKID_USB>;
2447 resets = <&reset RESE 2359 resets = <&reset RESET_USB>;
2448 2360
2449 dr_mode = "otg"; 2361 dr_mode = "otg";
2450 2362
2451 phys = <&usb2_phy0>, 2363 phys = <&usb2_phy0>, <&usb2_phy1>,
2452 <&usb3_pcie_ph 2364 <&usb3_pcie_phy PHY_TYPE_USB3>;
2453 phy-names = "usb2-phy 2365 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2454 2366
2455 dwc2: usb@ff400000 { 2367 dwc2: usb@ff400000 {
2456 compatible = 2368 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2457 reg = <0x0 0x 2369 reg = <0x0 0xff400000 0x0 0x40000>;
2458 interrupts = 2370 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2459 clocks = <&cl 2371 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2460 clock-names = 2372 clock-names = "otg";
2461 phys = <&usb2 2373 phys = <&usb2_phy1>;
2462 phy-names = " 2374 phy-names = "usb2-phy";
2463 dr_mode = "pe 2375 dr_mode = "peripheral";
2464 g-rx-fifo-siz 2376 g-rx-fifo-size = <192>;
2465 g-np-tx-fifo- 2377 g-np-tx-fifo-size = <128>;
2466 g-tx-fifo-siz 2378 g-tx-fifo-size = <128 128 16 16 16>;
2467 }; 2379 };
2468 2380
2469 dwc3: usb@ff500000 { 2381 dwc3: usb@ff500000 {
2470 compatible = 2382 compatible = "snps,dwc3";
2471 reg = <0x0 0x 2383 reg = <0x0 0xff500000 0x0 0x100000>;
2472 interrupts = 2384 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2473 dr_mode = "ho 2385 dr_mode = "host";
2474 snps,dis_u2_s 2386 snps,dis_u2_susphy_quirk;
2475 snps,quirk-fr !! 2387 snps,quirk-frame-length-adjustment;
2476 snps,parkmode 2388 snps,parkmode-disable-ss-quirk;
2477 }; 2389 };
2478 }; 2390 };
2479 2391
2480 mali: gpu@ffe40000 { 2392 mali: gpu@ffe40000 {
2481 compatible = "amlogic 2393 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2482 reg = <0x0 0xffe40000 2394 reg = <0x0 0xffe40000 0x0 0x40000>;
2483 interrupt-parent = <& 2395 interrupt-parent = <&gic>;
2484 interrupts = <GIC_SPI 2396 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 2397 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 2398 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2487 interrupt-names = "jo 2399 interrupt-names = "job", "mmu", "gpu";
2488 clocks = <&clkc CLKID 2400 clocks = <&clkc CLKID_MALI>;
2489 resets = <&reset RESE 2401 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2490 operating-points-v2 = 2402 operating-points-v2 = <&gpu_opp_table>;
2491 #cooling-cells = <2>; 2403 #cooling-cells = <2>;
2492 }; 2404 };
2493 }; 2405 };
2494 2406
2495 thermal-zones { <<
2496 cpu_thermal: cpu-thermal { <<
2497 polling-delay = <1000 <<
2498 polling-delay-passive <<
2499 thermal-sensors = <&c <<
2500 <<
2501 trips { <<
2502 cpu_passive: <<
2503 tempe <<
2504 hyste <<
2505 type <<
2506 }; <<
2507 <<
2508 cpu_hot: cpu- <<
2509 tempe <<
2510 hyste <<
2511 type <<
2512 }; <<
2513 <<
2514 cpu_critical: <<
2515 tempe <<
2516 hyste <<
2517 type <<
2518 }; <<
2519 }; <<
2520 }; <<
2521 <<
2522 ddr_thermal: ddr-thermal { <<
2523 polling-delay = <1000 <<
2524 polling-delay-passive <<
2525 thermal-sensors = <&d <<
2526 <<
2527 trips { <<
2528 ddr_passive: <<
2529 tempe <<
2530 hyste <<
2531 type <<
2532 }; <<
2533 <<
2534 ddr_critical: <<
2535 tempe <<
2536 hyste <<
2537 type <<
2538 }; <<
2539 }; <<
2540 <<
2541 cooling-maps { <<
2542 map { <<
2543 trip <<
2544 cooli <<
2545 }; <<
2546 }; <<
2547 }; <<
2548 }; <<
2549 <<
2550 timer { 2407 timer {
2551 compatible = "arm,armv8-timer 2408 compatible = "arm,armv8-timer";
2552 interrupts = <GIC_PPI 13 2409 interrupts = <GIC_PPI 13
2553 (GIC_CPU_MASK_RAW(0xf 2410 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2554 <GIC_PPI 14 2411 <GIC_PPI 14
2555 (GIC_CPU_MASK_RAW(0xf 2412 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2556 <GIC_PPI 11 2413 <GIC_PPI 11
2557 (GIC_CPU_MASK_RAW(0xf 2414 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2558 <GIC_PPI 10 2415 <GIC_PPI 10
2559 (GIC_CPU_MASK_RAW(0xf 2416 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2560 arm,no-tick-in-suspend; 2417 arm,no-tick-in-suspend;
2561 }; 2418 };
2562 2419
2563 xtal: xtal-clk { 2420 xtal: xtal-clk {
2564 compatible = "fixed-clock"; 2421 compatible = "fixed-clock";
2565 clock-frequency = <24000000>; 2422 clock-frequency = <24000000>;
2566 clock-output-names = "xtal"; 2423 clock-output-names = "xtal";
2567 #clock-cells = <0>; 2424 #clock-cells = <0>;
2568 }; 2425 };
2569 2426
2570 npu: npu@ff100000 { <<
2571 compatible = "vivante,gc"; <<
2572 reg = <0x0 0xff100000 0x0 0x2 <<
2573 interrupts = <0 147 4>; <<
2574 clocks = <&clkc CLKID_NNA_COR <<
2575 <&clkc CLKID_NNA_AXI <<
2576 clock-names = "core", "bus"; <<
2577 assigned-clocks = <&clkc CLKI <<
2578 <&clkc CLKI <<
2579 assigned-clock-rates = <80000 <<
2580 resets = <&reset RESET_NNA>; <<
2581 status = "disabled"; <<
2582 }; <<
2583 }; 2427 };
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