1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy.h> 6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h> 8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h> 9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/aml 12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a 13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 aliases { 21 aliases {
22 mmc0 = &sd_emmc_b; /* SD card 22 mmc0 = &sd_emmc_b; /* SD card */
23 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc1 = &sd_emmc_c; /* eMMC */
24 mmc2 = &sd_emmc_a; /* SDIO */ 24 mmc2 = &sd_emmc_a; /* SDIO */
25 }; 25 };
26 26
27 chosen { 27 chosen {
28 #address-cells = <2>; 28 #address-cells = <2>;
29 #size-cells = <2>; 29 #size-cells = <2>;
30 ranges; 30 ranges;
31 31
32 simplefb_cvbs: framebuffer-cvb 32 simplefb_cvbs: framebuffer-cvbs {
33 compatible = "amlogic, 33 compatible = "amlogic,simple-framebuffer",
34 "simple-f 34 "simple-framebuffer";
35 amlogic,pipeline = "vp 35 amlogic,pipeline = "vpu-cvbs";
36 clocks = <&clkc CLKID_ 36 clocks = <&clkc CLKID_HDMI>,
37 <&clkc CLKID_ 37 <&clkc CLKID_HTX_PCLK>,
38 <&clkc CLKID_ 38 <&clkc CLKID_VPU_INTR>;
39 status = "disabled"; 39 status = "disabled";
40 }; 40 };
41 41
42 simplefb_hdmi: framebuffer-hdm 42 simplefb_hdmi: framebuffer-hdmi {
43 compatible = "amlogic, 43 compatible = "amlogic,simple-framebuffer",
44 "simple-fr 44 "simple-framebuffer";
45 amlogic,pipeline = "vp 45 amlogic,pipeline = "vpu-hdmi";
46 clocks = <&clkc CLKID_ 46 clocks = <&clkc CLKID_HDMI>,
47 <&clkc CLKID_ 47 <&clkc CLKID_HTX_PCLK>,
48 <&clkc CLKID_ 48 <&clkc CLKID_VPU_INTR>;
49 status = "disabled"; 49 status = "disabled";
50 }; 50 };
51 }; 51 };
52 52
53 efuse: efuse { 53 efuse: efuse {
54 compatible = "amlogic,meson-gx 54 compatible = "amlogic,meson-gxbb-efuse";
55 clocks = <&clkc CLKID_EFUSE>; 55 clocks = <&clkc CLKID_EFUSE>;
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 read-only; 58 read-only;
59 secure-monitor = <&sm>; 59 secure-monitor = <&sm>;
60 }; 60 };
61 61
62 gpu_opp_table: opp-table-gpu { 62 gpu_opp_table: opp-table-gpu {
63 compatible = "operating-points 63 compatible = "operating-points-v2";
64 64
65 opp-124999998 { 65 opp-124999998 {
66 opp-hz = /bits/ 64 <12 66 opp-hz = /bits/ 64 <124999998>;
67 opp-microvolt = <80000 67 opp-microvolt = <800000>;
68 }; 68 };
69 opp-249999996 { 69 opp-249999996 {
70 opp-hz = /bits/ 64 <24 70 opp-hz = /bits/ 64 <249999996>;
71 opp-microvolt = <80000 71 opp-microvolt = <800000>;
72 }; 72 };
73 opp-285714281 { 73 opp-285714281 {
74 opp-hz = /bits/ 64 <28 74 opp-hz = /bits/ 64 <285714281>;
75 opp-microvolt = <80000 75 opp-microvolt = <800000>;
76 }; 76 };
77 opp-399999994 { 77 opp-399999994 {
78 opp-hz = /bits/ 64 <39 78 opp-hz = /bits/ 64 <399999994>;
79 opp-microvolt = <80000 79 opp-microvolt = <800000>;
80 }; 80 };
81 opp-499999992 { 81 opp-499999992 {
82 opp-hz = /bits/ 64 <49 82 opp-hz = /bits/ 64 <499999992>;
83 opp-microvolt = <80000 83 opp-microvolt = <800000>;
84 }; 84 };
85 opp-666666656 { 85 opp-666666656 {
86 opp-hz = /bits/ 64 <66 86 opp-hz = /bits/ 64 <666666656>;
87 opp-microvolt = <80000 87 opp-microvolt = <800000>;
88 }; 88 };
89 opp-799999987 { 89 opp-799999987 {
90 opp-hz = /bits/ 64 <79 90 opp-hz = /bits/ 64 <799999987>;
91 opp-microvolt = <80000 91 opp-microvolt = <800000>;
92 }; 92 };
93 }; 93 };
94 94
95 psci { 95 psci {
96 compatible = "arm,psci-1.0"; 96 compatible = "arm,psci-1.0";
97 method = "smc"; 97 method = "smc";
98 }; 98 };
99 99
100 reserved-memory { 100 reserved-memory {
101 #address-cells = <2>; 101 #address-cells = <2>;
102 #size-cells = <2>; 102 #size-cells = <2>;
103 ranges; 103 ranges;
104 104
105 /* 3 MiB reserved for ARM Trus 105 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
106 secmon_reserved: secmon@500000 106 secmon_reserved: secmon@5000000 {
107 reg = <0x0 0x05000000 107 reg = <0x0 0x05000000 0x0 0x300000>;
108 no-map; 108 no-map;
109 }; 109 };
110 110
111 /* 32 MiB reserved for ARM Tru 111 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
112 secmon_reserved_bl32: secmon@5 112 secmon_reserved_bl32: secmon@5300000 {
113 reg = <0x0 0x05300000 113 reg = <0x0 0x05300000 0x0 0x2000000>;
114 no-map; 114 no-map;
115 }; 115 };
116 116
117 linux,cma { 117 linux,cma {
118 compatible = "shared-d 118 compatible = "shared-dma-pool";
119 reusable; 119 reusable;
120 size = <0x0 0x10000000 120 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400 121 alignment = <0x0 0x400000>;
122 linux,cma-default; 122 linux,cma-default;
123 }; 123 };
124 }; 124 };
125 125
126 sm: secure-monitor { 126 sm: secure-monitor {
127 compatible = "amlogic,meson-gx 127 compatible = "amlogic,meson-gxbb-sm";
128 }; 128 };
129 129
130 soc { 130 soc {
131 compatible = "simple-bus"; 131 compatible = "simple-bus";
132 #address-cells = <2>; 132 #address-cells = <2>;
133 #size-cells = <2>; 133 #size-cells = <2>;
134 ranges; 134 ranges;
135 135
136 pcie: pcie@fc000000 { 136 pcie: pcie@fc000000 {
137 compatible = "amlogic, 137 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
138 reg = <0x0 0xfc000000 138 reg = <0x0 0xfc000000 0x0 0x400000>,
139 <0x0 0xff648000 139 <0x0 0xff648000 0x0 0x2000>,
140 <0x0 0xfc400000 140 <0x0 0xfc400000 0x0 0x200000>;
141 reg-names = "elbi", "c 141 reg-names = "elbi", "cfg", "config";
142 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
143 #interrupt-cells = <1> 143 #interrupt-cells = <1>;
144 interrupt-map-mask = < 144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff> 146 bus-range = <0x0 0xff>;
147 #address-cells = <3>; 147 #address-cells = <3>;
148 #size-cells = <2>; 148 #size-cells = <2>;
149 device_type = "pci"; 149 device_type = "pci";
150 ranges = <0x81000000 0 150 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
151 <0x82000000 0 151 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
152 152
153 clocks = <&clkc CLKID_ 153 clocks = <&clkc CLKID_PCIE_PHY
154 &clkc CLKID_ 154 &clkc CLKID_PCIE_COMB
155 &clkc CLKID_ 155 &clkc CLKID_PCIE_PLL>;
156 clock-names = "general 156 clock-names = "general",
157 "pclk", 157 "pclk",
158 "port"; 158 "port";
159 resets = <&reset RESET 159 resets = <&reset RESET_PCIE_CTRL_A>,
160 <&reset RESET 160 <&reset RESET_PCIE_APB>;
161 reset-names = "port", 161 reset-names = "port",
162 "apb"; 162 "apb";
163 num-lanes = <1>; 163 num-lanes = <1>;
164 phys = <&usb3_pcie_phy 164 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
165 phy-names = "pcie"; 165 phy-names = "pcie";
166 status = "disabled"; 166 status = "disabled";
167 }; 167 };
168 168
169 ethmac: ethernet@ff3f0000 { 169 ethmac: ethernet@ff3f0000 {
170 compatible = "amlogic, 170 compatible = "amlogic,meson-g12a-dwmac",
171 "snps,dwm 171 "snps,dwmac-3.70a",
172 "snps,dwm 172 "snps,dwmac";
173 reg = <0x0 0xff3f0000 173 reg = <0x0 0xff3f0000 0x0 0x10000>,
174 <0x0 0xff634540 174 <0x0 0xff634540 0x0 0x8>;
175 interrupts = <GIC_SPI 175 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "mac 176 interrupt-names = "macirq";
177 clocks = <&clkc CLKID_ 177 clocks = <&clkc CLKID_ETH>,
178 <&clkc CLKID_ 178 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_ 179 <&clkc CLKID_MPLL2>,
180 <&clkc CLKID_ 180 <&clkc CLKID_FCLK_DIV2>;
181 clock-names = "stmmace 181 clock-names = "stmmaceth", "clkin0", "clkin1",
182 "timing- 182 "timing-adjustment";
183 rx-fifo-depth = <4096> 183 rx-fifo-depth = <4096>;
184 tx-fifo-depth = <2048> 184 tx-fifo-depth = <2048>;
185 status = "disabled"; 185 status = "disabled";
186 186
187 mdio0: mdio { 187 mdio0: mdio {
188 #address-cells 188 #address-cells = <1>;
189 #size-cells = 189 #size-cells = <0>;
190 compatible = " 190 compatible = "snps,dwmac-mdio";
191 }; 191 };
192 }; 192 };
193 193
194 apb: bus@ff600000 { 194 apb: bus@ff600000 {
195 compatible = "simple-b 195 compatible = "simple-bus";
196 reg = <0x0 0xff600000 196 reg = <0x0 0xff600000 0x0 0x200000>;
197 #address-cells = <2>; 197 #address-cells = <2>;
198 #size-cells = <2>; 198 #size-cells = <2>;
199 ranges = <0x0 0x0 0x0 199 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
200 200
201 hdmi_tx: hdmi-tx@0 { 201 hdmi_tx: hdmi-tx@0 {
202 compatible = " 202 compatible = "amlogic,meson-g12a-dw-hdmi";
203 reg = <0x0 0x0 203 reg = <0x0 0x0 0x0 0x10000>;
204 interrupts = < 204 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
205 resets = <&res 205 resets = <&reset RESET_HDMITX_CAPB3>,
206 <&res 206 <&reset RESET_HDMITX_PHY>,
207 <&res 207 <&reset RESET_HDMITX>;
208 reset-names = 208 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
209 clocks = <&clk 209 clocks = <&clkc CLKID_HDMI>,
210 <&clk 210 <&clkc CLKID_HTX_PCLK>,
211 <&clk 211 <&clkc CLKID_VPU_INTR>;
212 clock-names = 212 clock-names = "isfr", "iahb", "venci";
213 #address-cells 213 #address-cells = <1>;
214 #size-cells = 214 #size-cells = <0>;
215 #sound-dai-cel 215 #sound-dai-cells = <0>;
216 status = "disa 216 status = "disabled";
217 217
218 assigned-clock <<
219 <<
220 assigned-clock <<
221 assigned-clock <<
222 <<
223 /* VPU VENC In 218 /* VPU VENC Input */
224 hdmi_tx_venc_p 219 hdmi_tx_venc_port: port@0 {
225 reg = 220 reg = <0>;
226 221
227 hdmi_t 222 hdmi_tx_in: endpoint {
228 223 remote-endpoint = <&hdmi_tx_out>;
229 }; 224 };
230 }; 225 };
231 226
232 /* TMDS Output 227 /* TMDS Output */
233 hdmi_tx_tmds_p 228 hdmi_tx_tmds_port: port@1 {
234 reg = 229 reg = <1>;
235 }; 230 };
236 }; 231 };
237 232
238 apb_efuse: bus@30000 { 233 apb_efuse: bus@30000 {
239 compatible = " 234 compatible = "simple-bus";
240 reg = <0x0 0x3 235 reg = <0x0 0x30000 0x0 0x2000>;
241 #address-cells 236 #address-cells = <2>;
242 #size-cells = 237 #size-cells = <2>;
243 ranges = <0x0 238 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
244 239
245 hwrng: rng@218 240 hwrng: rng@218 {
246 compat 241 compatible = "amlogic,meson-rng";
247 reg = 242 reg = <0x0 0x218 0x0 0x4>;
248 clocks 243 clocks = <&clkc CLKID_RNG0>;
249 clock- 244 clock-names = "core";
250 }; 245 };
251 }; 246 };
252 247
253 acodec: audio-controll 248 acodec: audio-controller@32000 {
254 compatible = " 249 compatible = "amlogic,t9015";
255 reg = <0x0 0x3 250 reg = <0x0 0x32000 0x0 0x14>;
256 #sound-dai-cel 251 #sound-dai-cells = <0>;
257 sound-name-pre 252 sound-name-prefix = "ACODEC";
258 clocks = <&clk 253 clocks = <&clkc CLKID_AUDIO_CODEC>;
259 clock-names = 254 clock-names = "pclk";
260 resets = <&res 255 resets = <&reset RESET_AUDIO_CODEC>;
261 status = "disa 256 status = "disabled";
262 }; 257 };
263 258
264 periphs: bus@34400 { 259 periphs: bus@34400 {
265 compatible = " 260 compatible = "simple-bus";
266 reg = <0x0 0x3 261 reg = <0x0 0x34400 0x0 0x400>;
267 #address-cells 262 #address-cells = <2>;
268 #size-cells = 263 #size-cells = <2>;
269 ranges = <0x0 264 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
270 265
271 periphs_pinctr 266 periphs_pinctrl: pinctrl@40 {
272 compat 267 compatible = "amlogic,meson-g12a-periphs-pinctrl";
273 #addre 268 #address-cells = <2>;
274 #size- 269 #size-cells = <2>;
275 ranges 270 ranges;
276 271
277 gpio: 272 gpio: bank@40 {
278 273 reg = <0x0 0x40 0x0 0x4c>,
279 274 <0x0 0xe8 0x0 0x18>,
280 275 <0x0 0x120 0x0 0x18>,
281 276 <0x0 0x2c0 0x0 0x40>,
282 277 <0x0 0x340 0x0 0x1c>;
283 278 reg-names = "gpio",
284 279 "pull",
285 280 "pull-enable",
286 281 "mux",
287 282 "ds";
288 283 gpio-controller;
289 284 #gpio-cells = <2>;
290 285 gpio-ranges = <&periphs_pinctrl 0 0 86>;
291 }; 286 };
292 287
293 cec_ao 288 cec_ao_a_h_pins: cec_ao_a_h {
294 289 mux {
295 290 groups = "cec_ao_a_h";
296 291 function = "cec_ao_a_h";
297 292 bias-disable;
298 293 };
299 }; 294 };
300 295
301 cec_ao 296 cec_ao_b_h_pins: cec_ao_b_h {
302 297 mux {
303 298 groups = "cec_ao_b_h";
304 299 function = "cec_ao_b_h";
305 300 bias-disable;
306 301 };
307 }; 302 };
308 303
309 emmc_c 304 emmc_ctrl_pins: emmc-ctrl {
310 305 mux-0 {
311 306 groups = "emmc_cmd";
312 307 function = "emmc";
313 308 bias-pull-up;
314 309 drive-strength-microamp = <4000>;
315 310 };
316 311
317 312 mux-1 {
318 313 groups = "emmc_clk";
319 314 function = "emmc";
320 315 bias-disable;
321 316 drive-strength-microamp = <4000>;
322 317 };
323 }; 318 };
324 319
325 emmc_d 320 emmc_data_4b_pins: emmc-data-4b {
326 321 mux-0 {
327 322 groups = "emmc_nand_d0",
328 323 "emmc_nand_d1",
329 324 "emmc_nand_d2",
330 325 "emmc_nand_d3";
331 326 function = "emmc";
332 327 bias-pull-up;
333 328 drive-strength-microamp = <4000>;
334 329 };
335 }; 330 };
336 331
337 emmc_d 332 emmc_data_8b_pins: emmc-data-8b {
338 333 mux-0 {
339 334 groups = "emmc_nand_d0",
340 335 "emmc_nand_d1",
341 336 "emmc_nand_d2",
342 337 "emmc_nand_d3",
343 338 "emmc_nand_d4",
344 339 "emmc_nand_d5",
345 340 "emmc_nand_d6",
346 341 "emmc_nand_d7";
347 342 function = "emmc";
348 343 bias-pull-up;
349 344 drive-strength-microamp = <4000>;
350 345 };
351 }; 346 };
352 347
353 emmc_d 348 emmc_ds_pins: emmc-ds {
354 349 mux {
355 350 groups = "emmc_nand_ds";
356 351 function = "emmc";
357 352 bias-pull-down;
358 353 drive-strength-microamp = <4000>;
359 354 };
360 }; 355 };
361 356
362 emmc_c 357 emmc_clk_gate_pins: emmc_clk_gate {
363 358 mux {
364 359 groups = "BOOT_8";
365 360 function = "gpio_periphs";
366 361 bias-pull-down;
367 362 drive-strength-microamp = <4000>;
368 363 };
369 }; 364 };
370 365
371 hdmitx 366 hdmitx_ddc_pins: hdmitx_ddc {
372 367 mux {
373 368 groups = "hdmitx_sda",
374 369 "hdmitx_sck";
375 370 function = "hdmitx";
376 371 bias-disable;
377 372 drive-strength-microamp = <4000>;
378 373 };
379 }; 374 };
380 375
381 hdmitx 376 hdmitx_hpd_pins: hdmitx_hpd {
382 377 mux {
383 378 groups = "hdmitx_hpd_in";
384 379 function = "hdmitx";
385 380 bias-disable;
386 381 };
387 }; 382 };
388 383
389 384
390 i2c0_s 385 i2c0_sda_c_pins: i2c0-sda-c {
391 386 mux {
392 387 groups = "i2c0_sda_c";
393 388 function = "i2c0";
394 389 bias-disable;
395 390 drive-strength-microamp = <3000>;
396 391
397 392 };
398 }; 393 };
399 394
400 i2c0_s 395 i2c0_sck_c_pins: i2c0-sck-c {
401 396 mux {
402 397 groups = "i2c0_sck_c";
403 398 function = "i2c0";
404 399 bias-disable;
405 400 drive-strength-microamp = <3000>;
406 401 };
407 }; 402 };
408 403
409 i2c0_s 404 i2c0_sda_z0_pins: i2c0-sda-z0 {
410 405 mux {
411 406 groups = "i2c0_sda_z0";
412 407 function = "i2c0";
413 408 bias-disable;
414 409 drive-strength-microamp = <3000>;
415 410 };
416 }; 411 };
417 412
418 i2c0_s 413 i2c0_sck_z1_pins: i2c0-sck-z1 {
419 414 mux {
420 415 groups = "i2c0_sck_z1";
421 416 function = "i2c0";
422 417 bias-disable;
423 418 drive-strength-microamp = <3000>;
424 419 };
425 }; 420 };
426 421
427 i2c0_s 422 i2c0_sda_z7_pins: i2c0-sda-z7 {
428 423 mux {
429 424 groups = "i2c0_sda_z7";
430 425 function = "i2c0";
431 426 bias-disable;
432 427 drive-strength-microamp = <3000>;
433 428 };
434 }; 429 };
435 430
436 i2c0_s 431 i2c0_sda_z8_pins: i2c0-sda-z8 {
437 432 mux {
438 433 groups = "i2c0_sda_z8";
439 434 function = "i2c0";
440 435 bias-disable;
441 436 drive-strength-microamp = <3000>;
442 437 };
443 }; 438 };
444 439
445 i2c1_s 440 i2c1_sda_x_pins: i2c1-sda-x {
446 441 mux {
447 442 groups = "i2c1_sda_x";
448 443 function = "i2c1";
449 444 bias-disable;
450 445 drive-strength-microamp = <3000>;
451 446 };
452 }; 447 };
453 448
454 i2c1_s 449 i2c1_sck_x_pins: i2c1-sck-x {
455 450 mux {
456 451 groups = "i2c1_sck_x";
457 452 function = "i2c1";
458 453 bias-disable;
459 454 drive-strength-microamp = <3000>;
460 455 };
461 }; 456 };
462 457
463 i2c1_s 458 i2c1_sda_h2_pins: i2c1-sda-h2 {
464 459 mux {
465 460 groups = "i2c1_sda_h2";
466 461 function = "i2c1";
467 462 bias-disable;
468 463 drive-strength-microamp = <3000>;
469 464 };
470 }; 465 };
471 466
472 i2c1_s 467 i2c1_sck_h3_pins: i2c1-sck-h3 {
473 468 mux {
474 469 groups = "i2c1_sck_h3";
475 470 function = "i2c1";
476 471 bias-disable;
477 472 drive-strength-microamp = <3000>;
478 473 };
479 }; 474 };
480 475
481 i2c1_s 476 i2c1_sda_h6_pins: i2c1-sda-h6 {
482 477 mux {
483 478 groups = "i2c1_sda_h6";
484 479 function = "i2c1";
485 480 bias-disable;
486 481 drive-strength-microamp = <3000>;
487 482 };
488 }; 483 };
489 484
490 i2c1_s 485 i2c1_sck_h7_pins: i2c1-sck-h7 {
491 486 mux {
492 487 groups = "i2c1_sck_h7";
493 488 function = "i2c1";
494 489 bias-disable;
495 490 drive-strength-microamp = <3000>;
496 491 };
497 }; 492 };
498 493
499 i2c2_s 494 i2c2_sda_x_pins: i2c2-sda-x {
500 495 mux {
501 496 groups = "i2c2_sda_x";
502 497 function = "i2c2";
503 498 bias-disable;
504 499 drive-strength-microamp = <3000>;
505 500 };
506 }; 501 };
507 502
508 i2c2_s 503 i2c2_sck_x_pins: i2c2-sck-x {
509 504 mux {
510 505 groups = "i2c2_sck_x";
511 506 function = "i2c2";
512 507 bias-disable;
513 508 drive-strength-microamp = <3000>;
514 509 };
515 }; 510 };
516 511
517 i2c2_s 512 i2c2_sda_z_pins: i2c2-sda-z {
518 513 mux {
519 514 groups = "i2c2_sda_z";
520 515 function = "i2c2";
521 516 bias-disable;
522 517 drive-strength-microamp = <3000>;
523 518 };
524 }; 519 };
525 520
526 i2c2_s 521 i2c2_sck_z_pins: i2c2-sck-z {
527 522 mux {
528 523 groups = "i2c2_sck_z";
529 524 function = "i2c2";
530 525 bias-disable;
531 526 drive-strength-microamp = <3000>;
532 527 };
533 }; 528 };
534 529
535 i2c3_s 530 i2c3_sda_h_pins: i2c3-sda-h {
536 531 mux {
537 532 groups = "i2c3_sda_h";
538 533 function = "i2c3";
539 534 bias-disable;
540 535 drive-strength-microamp = <3000>;
541 536 };
542 }; 537 };
543 538
544 i2c3_s 539 i2c3_sck_h_pins: i2c3-sck-h {
545 540 mux {
546 541 groups = "i2c3_sck_h";
547 542 function = "i2c3";
548 543 bias-disable;
549 544 drive-strength-microamp = <3000>;
550 545 };
551 }; 546 };
552 547
553 i2c3_s 548 i2c3_sda_a_pins: i2c3-sda-a {
554 549 mux {
555 550 groups = "i2c3_sda_a";
556 551 function = "i2c3";
557 552 bias-disable;
558 553 drive-strength-microamp = <3000>;
559 554 };
560 }; 555 };
561 556
562 i2c3_s 557 i2c3_sck_a_pins: i2c3-sck-a {
563 558 mux {
564 559 groups = "i2c3_sck_a";
565 560 function = "i2c3";
566 561 bias-disable;
567 562 drive-strength-microamp = <3000>;
568 563 };
569 }; 564 };
570 565
571 mclk0_ 566 mclk0_a_pins: mclk0-a {
572 567 mux {
573 568 groups = "mclk0_a";
574 569 function = "mclk0";
575 570 bias-disable;
576 571 drive-strength-microamp = <3000>;
577 572 };
578 }; 573 };
579 574
580 mclk1_ 575 mclk1_a_pins: mclk1-a {
581 576 mux {
582 577 groups = "mclk1_a";
583 578 function = "mclk1";
584 579 bias-disable;
585 580 drive-strength-microamp = <3000>;
586 581 };
587 }; 582 };
588 583
589 mclk1_ 584 mclk1_x_pins: mclk1-x {
590 585 mux {
591 586 groups = "mclk1_x";
592 587 function = "mclk1";
593 588 bias-disable;
594 589 drive-strength-microamp = <3000>;
595 590 };
596 }; 591 };
597 592
598 mclk1_ 593 mclk1_z_pins: mclk1-z {
599 594 mux {
600 595 groups = "mclk1_z";
601 596 function = "mclk1";
602 597 bias-disable;
603 598 drive-strength-microamp = <3000>;
604 599 };
605 }; 600 };
606 601
607 nor_pi 602 nor_pins: nor {
608 603 mux {
609 604 groups = "nor_d",
610 605 "nor_q",
611 606 "nor_c",
612 607 "nor_cs";
613 608 function = "nor";
614 609 bias-disable;
615 610 };
616 }; 611 };
617 612
618 pdm_di 613 pdm_din0_a_pins: pdm-din0-a {
619 614 mux {
620 615 groups = "pdm_din0_a";
621 616 function = "pdm";
622 617 bias-disable;
623 618 };
624 }; 619 };
625 620
626 pdm_di 621 pdm_din0_c_pins: pdm-din0-c {
627 622 mux {
628 623 groups = "pdm_din0_c";
629 624 function = "pdm";
630 625 bias-disable;
631 626 };
632 }; 627 };
633 628
634 pdm_di 629 pdm_din0_x_pins: pdm-din0-x {
635 630 mux {
636 631 groups = "pdm_din0_x";
637 632 function = "pdm";
638 633 bias-disable;
639 634 };
640 }; 635 };
641 636
642 pdm_di 637 pdm_din0_z_pins: pdm-din0-z {
643 638 mux {
644 639 groups = "pdm_din0_z";
645 640 function = "pdm";
646 641 bias-disable;
647 642 };
648 }; 643 };
649 644
650 pdm_di 645 pdm_din1_a_pins: pdm-din1-a {
651 646 mux {
652 647 groups = "pdm_din1_a";
653 648 function = "pdm";
654 649 bias-disable;
655 650 };
656 }; 651 };
657 652
658 pdm_di 653 pdm_din1_c_pins: pdm-din1-c {
659 654 mux {
660 655 groups = "pdm_din1_c";
661 656 function = "pdm";
662 657 bias-disable;
663 658 };
664 }; 659 };
665 660
666 pdm_di 661 pdm_din1_x_pins: pdm-din1-x {
667 662 mux {
668 663 groups = "pdm_din1_x";
669 664 function = "pdm";
670 665 bias-disable;
671 666 };
672 }; 667 };
673 668
674 pdm_di 669 pdm_din1_z_pins: pdm-din1-z {
675 670 mux {
676 671 groups = "pdm_din1_z";
677 672 function = "pdm";
678 673 bias-disable;
679 674 };
680 }; 675 };
681 676
682 pdm_di 677 pdm_din2_a_pins: pdm-din2-a {
683 678 mux {
684 679 groups = "pdm_din2_a";
685 680 function = "pdm";
686 681 bias-disable;
687 682 };
688 }; 683 };
689 684
690 pdm_di 685 pdm_din2_c_pins: pdm-din2-c {
691 686 mux {
692 687 groups = "pdm_din2_c";
693 688 function = "pdm";
694 689 bias-disable;
695 690 };
696 }; 691 };
697 692
698 pdm_di 693 pdm_din2_x_pins: pdm-din2-x {
699 694 mux {
700 695 groups = "pdm_din2_x";
701 696 function = "pdm";
702 697 bias-disable;
703 698 };
704 }; 699 };
705 700
706 pdm_di 701 pdm_din2_z_pins: pdm-din2-z {
707 702 mux {
708 703 groups = "pdm_din2_z";
709 704 function = "pdm";
710 705 bias-disable;
711 706 };
712 }; 707 };
713 708
714 pdm_di 709 pdm_din3_a_pins: pdm-din3-a {
715 710 mux {
716 711 groups = "pdm_din3_a";
717 712 function = "pdm";
718 713 bias-disable;
719 714 };
720 }; 715 };
721 716
722 pdm_di 717 pdm_din3_c_pins: pdm-din3-c {
723 718 mux {
724 719 groups = "pdm_din3_c";
725 720 function = "pdm";
726 721 bias-disable;
727 722 };
728 }; 723 };
729 724
730 pdm_di 725 pdm_din3_x_pins: pdm-din3-x {
731 726 mux {
732 727 groups = "pdm_din3_x";
733 728 function = "pdm";
734 729 bias-disable;
735 730 };
736 }; 731 };
737 732
738 pdm_di 733 pdm_din3_z_pins: pdm-din3-z {
739 734 mux {
740 735 groups = "pdm_din3_z";
741 736 function = "pdm";
742 737 bias-disable;
743 738 };
744 }; 739 };
745 740
746 pdm_dc 741 pdm_dclk_a_pins: pdm-dclk-a {
747 742 mux {
748 743 groups = "pdm_dclk_a";
749 744 function = "pdm";
750 745 bias-disable;
751 746 drive-strength-microamp = <500>;
752 747 };
753 }; 748 };
754 749
755 pdm_dc 750 pdm_dclk_c_pins: pdm-dclk-c {
756 751 mux {
757 752 groups = "pdm_dclk_c";
758 753 function = "pdm";
759 754 bias-disable;
760 755 drive-strength-microamp = <500>;
761 756 };
762 }; 757 };
763 758
764 pdm_dc 759 pdm_dclk_x_pins: pdm-dclk-x {
765 760 mux {
766 761 groups = "pdm_dclk_x";
767 762 function = "pdm";
768 763 bias-disable;
769 764 drive-strength-microamp = <500>;
770 765 };
771 }; 766 };
772 767
773 pdm_dc 768 pdm_dclk_z_pins: pdm-dclk-z {
774 769 mux {
775 770 groups = "pdm_dclk_z";
776 771 function = "pdm";
777 772 bias-disable;
778 773 drive-strength-microamp = <500>;
779 774 };
780 }; 775 };
781 776
782 pwm_a_ 777 pwm_a_pins: pwm-a {
783 778 mux {
784 779 groups = "pwm_a";
785 780 function = "pwm_a";
786 781 bias-disable;
787 782 };
788 }; 783 };
789 784
790 pwm_b_ 785 pwm_b_x7_pins: pwm-b-x7 {
791 786 mux {
792 787 groups = "pwm_b_x7";
793 788 function = "pwm_b";
794 789 bias-disable;
795 790 };
796 }; 791 };
797 792
798 pwm_b_ 793 pwm_b_x19_pins: pwm-b-x19 {
799 794 mux {
800 795 groups = "pwm_b_x19";
801 796 function = "pwm_b";
802 797 bias-disable;
803 798 };
804 }; 799 };
805 800
806 pwm_c_ 801 pwm_c_c_pins: pwm-c-c {
807 802 mux {
808 803 groups = "pwm_c_c";
809 804 function = "pwm_c";
810 805 bias-disable;
811 806 };
812 }; 807 };
813 808
814 pwm_c_ 809 pwm_c_x5_pins: pwm-c-x5 {
815 810 mux {
816 811 groups = "pwm_c_x5";
817 812 function = "pwm_c";
818 813 bias-disable;
819 814 };
820 }; 815 };
821 816
822 pwm_c_ 817 pwm_c_x8_pins: pwm-c-x8 {
823 818 mux {
824 819 groups = "pwm_c_x8";
825 820 function = "pwm_c";
826 821 bias-disable;
827 822 };
828 }; 823 };
829 824
830 pwm_d_ 825 pwm_d_x3_pins: pwm-d-x3 {
831 826 mux {
832 827 groups = "pwm_d_x3";
833 828 function = "pwm_d";
834 829 bias-disable;
835 830 };
836 }; 831 };
837 832
838 pwm_d_ 833 pwm_d_x6_pins: pwm-d-x6 {
839 834 mux {
840 835 groups = "pwm_d_x6";
841 836 function = "pwm_d";
842 837 bias-disable;
843 838 };
844 }; 839 };
845 840
846 pwm_e_ 841 pwm_e_pins: pwm-e {
847 842 mux {
848 843 groups = "pwm_e";
849 844 function = "pwm_e";
850 845 bias-disable;
851 846 };
852 }; 847 };
853 848
854 pwm_f_ 849 pwm_f_z_pins: pwm-f-z {
855 850 mux {
856 851 groups = "pwm_f_z";
857 852 function = "pwm_f";
858 853 bias-disable;
859 854 };
860 }; 855 };
861 856
862 pwm_f_ 857 pwm_f_a_pins: pwm-f-a {
863 858 mux {
864 859 groups = "pwm_f_a";
865 860 function = "pwm_f";
866 861 bias-disable;
867 862 };
868 }; 863 };
869 864
870 pwm_f_ 865 pwm_f_x_pins: pwm-f-x {
871 866 mux {
872 867 groups = "pwm_f_x";
873 868 function = "pwm_f";
874 869 bias-disable;
875 870 };
876 }; 871 };
877 872
878 pwm_f_ 873 pwm_f_h_pins: pwm-f-h {
879 874 mux {
880 875 groups = "pwm_f_h";
881 876 function = "pwm_f";
882 877 bias-disable;
883 878 };
884 }; 879 };
885 880
886 sdcard 881 sdcard_c_pins: sdcard_c {
887 882 mux-0 {
888 883 groups = "sdcard_d0_c",
889 884 "sdcard_d1_c",
890 885 "sdcard_d2_c",
891 886 "sdcard_d3_c",
892 887 "sdcard_cmd_c";
893 888 function = "sdcard";
894 889 bias-pull-up;
895 890 drive-strength-microamp = <4000>;
896 891 };
897 892
898 893 mux-1 {
899 894 groups = "sdcard_clk_c";
900 895 function = "sdcard";
901 896 bias-disable;
902 897 drive-strength-microamp = <4000>;
903 898 };
904 }; 899 };
905 900
906 sdcard 901 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
907 902 mux {
908 903 groups = "GPIOC_4";
909 904 function = "gpio_periphs";
910 905 bias-pull-down;
911 906 drive-strength-microamp = <4000>;
912 907 };
913 }; 908 };
914 909
915 sdcard 910 sdcard_z_pins: sdcard_z {
916 911 mux-0 {
917 912 groups = "sdcard_d0_z",
918 913 "sdcard_d1_z",
919 914 "sdcard_d2_z",
920 915 "sdcard_d3_z",
921 916 "sdcard_cmd_z";
922 917 function = "sdcard";
923 918 bias-pull-up;
924 919 drive-strength-microamp = <4000>;
925 920 };
926 921
927 922 mux-1 {
928 923 groups = "sdcard_clk_z";
929 924 function = "sdcard";
930 925 bias-disable;
931 926 drive-strength-microamp = <4000>;
932 927 };
933 }; 928 };
934 929
935 sdcard 930 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
936 931 mux {
937 932 groups = "GPIOZ_6";
938 933 function = "gpio_periphs";
939 934 bias-pull-down;
940 935 drive-strength-microamp = <4000>;
941 936 };
942 }; 937 };
943 938
944 sdio_p 939 sdio_pins: sdio {
945 940 mux {
946 941 groups = "sdio_d0",
947 942 "sdio_d1",
948 943 "sdio_d2",
949 944 "sdio_d3",
950 945 "sdio_clk",
951 946 "sdio_cmd";
952 947 function = "sdio";
953 948 bias-disable;
954 949 drive-strength-microamp = <4000>;
955 950 };
956 }; 951 };
957 952
958 sdio_c 953 sdio_clk_gate_pins: sdio_clk_gate {
959 954 mux {
960 955 groups = "GPIOX_4";
961 956 function = "gpio_periphs";
962 957 bias-pull-down;
963 958 drive-strength-microamp = <4000>;
964 959 };
965 }; 960 };
966 961
967 spdif_ 962 spdif_in_a10_pins: spdif-in-a10 {
968 963 mux {
969 964 groups = "spdif_in_a10";
970 965 function = "spdif_in";
971 966 bias-disable;
972 967 };
973 }; 968 };
974 969
975 spdif_ 970 spdif_in_a12_pins: spdif-in-a12 {
976 971 mux {
977 972 groups = "spdif_in_a12";
978 973 function = "spdif_in";
979 974 bias-disable;
980 975 };
981 }; 976 };
982 977
983 spdif_ 978 spdif_in_h_pins: spdif-in-h {
984 979 mux {
985 980 groups = "spdif_in_h";
986 981 function = "spdif_in";
987 982 bias-disable;
988 983 };
989 }; 984 };
990 985
991 spdif_ 986 spdif_out_h_pins: spdif-out-h {
992 987 mux {
993 988 groups = "spdif_out_h";
994 989 function = "spdif_out";
995 !! 990 drive-strength-microamp = <500>;
996 991 bias-disable;
997 992 };
998 }; 993 };
999 994
1000 spdif 995 spdif_out_a11_pins: spdif-out-a11 {
1001 996 mux {
1002 997 groups = "spdif_out_a11";
1003 998 function = "spdif_out";
1004 !! 999 drive-strength-microamp = <500>;
1005 1000 bias-disable;
1006 1001 };
1007 }; 1002 };
1008 1003
1009 spdif 1004 spdif_out_a13_pins: spdif-out-a13 {
1010 1005 mux {
1011 1006 groups = "spdif_out_a13";
1012 1007 function = "spdif_out";
1013 !! 1008 drive-strength-microamp = <500>;
1014 1009 bias-disable;
1015 1010 };
1016 }; 1011 };
1017 1012
1018 spicc 1013 spicc0_x_pins: spicc0-x {
1019 1014 mux {
1020 1015 groups = "spi0_mosi_x",
1021 1016 "spi0_miso_x",
1022 1017 "spi0_clk_x";
1023 1018 function = "spi0";
1024 1019 drive-strength-microamp = <4000>;
1025 1020 bias-disable;
1026 1021 };
1027 }; 1022 };
1028 1023
1029 spicc 1024 spicc0_ss0_x_pins: spicc0-ss0-x {
1030 1025 mux {
1031 1026 groups = "spi0_ss0_x";
1032 1027 function = "spi0";
1033 1028 drive-strength-microamp = <4000>;
1034 1029 bias-disable;
1035 1030 };
1036 }; 1031 };
1037 1032
1038 spicc 1033 spicc0_c_pins: spicc0-c {
1039 1034 mux {
1040 1035 groups = "spi0_mosi_c",
1041 1036 "spi0_miso_c",
1042 1037 "spi0_ss0_c",
1043 1038 "spi0_clk_c";
1044 1039 function = "spi0";
1045 1040 drive-strength-microamp = <4000>;
1046 1041 bias-disable;
1047 1042 };
1048 }; 1043 };
1049 1044
1050 spicc 1045 spicc1_pins: spicc1 {
1051 1046 mux {
1052 1047 groups = "spi1_mosi",
1053 1048 "spi1_miso",
1054 1049 "spi1_clk";
1055 1050 function = "spi1";
1056 1051 drive-strength-microamp = <4000>;
1057 1052 };
1058 }; 1053 };
1059 1054
1060 spicc 1055 spicc1_ss0_pins: spicc1-ss0 {
1061 1056 mux {
1062 1057 groups = "spi1_ss0";
1063 1058 function = "spi1";
1064 1059 drive-strength-microamp = <4000>;
1065 1060 bias-disable;
1066 1061 };
1067 }; 1062 };
1068 1063
1069 tdm_a 1064 tdm_a_din0_pins: tdm-a-din0 {
1070 1065 mux {
1071 1066 groups = "tdm_a_din0";
1072 1067 function = "tdm_a";
1073 1068 bias-disable;
1074 1069 };
1075 }; 1070 };
1076 1071
1077 1072
1078 tdm_a 1073 tdm_a_din1_pins: tdm-a-din1 {
1079 1074 mux {
1080 1075 groups = "tdm_a_din1";
1081 1076 function = "tdm_a";
1082 1077 bias-disable;
1083 1078 };
1084 }; 1079 };
1085 1080
1086 tdm_a 1081 tdm_a_dout0_pins: tdm-a-dout0 {
1087 1082 mux {
1088 1083 groups = "tdm_a_dout0";
1089 1084 function = "tdm_a";
1090 1085 bias-disable;
1091 1086 drive-strength-microamp = <3000>;
1092 1087 };
1093 }; 1088 };
1094 1089
1095 tdm_a 1090 tdm_a_dout1_pins: tdm-a-dout1 {
1096 1091 mux {
1097 1092 groups = "tdm_a_dout1";
1098 1093 function = "tdm_a";
1099 1094 bias-disable;
1100 1095 drive-strength-microamp = <3000>;
1101 1096 };
1102 }; 1097 };
1103 1098
1104 tdm_a 1099 tdm_a_fs_pins: tdm-a-fs {
1105 1100 mux {
1106 1101 groups = "tdm_a_fs";
1107 1102 function = "tdm_a";
1108 1103 bias-disable;
1109 1104 drive-strength-microamp = <3000>;
1110 1105 };
1111 }; 1106 };
1112 1107
1113 tdm_a 1108 tdm_a_sclk_pins: tdm-a-sclk {
1114 1109 mux {
1115 1110 groups = "tdm_a_sclk";
1116 1111 function = "tdm_a";
1117 1112 bias-disable;
1118 1113 drive-strength-microamp = <3000>;
1119 1114 };
1120 }; 1115 };
1121 1116
1122 tdm_a 1117 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1123 1118 mux {
1124 1119 groups = "tdm_a_slv_fs";
1125 1120 function = "tdm_a";
1126 1121 bias-disable;
1127 1122 };
1128 }; 1123 };
1129 1124
1130 1125
1131 tdm_a 1126 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1132 1127 mux {
1133 1128 groups = "tdm_a_slv_sclk";
1134 1129 function = "tdm_a";
1135 1130 bias-disable;
1136 1131 };
1137 }; 1132 };
1138 1133
1139 tdm_b 1134 tdm_b_din0_pins: tdm-b-din0 {
1140 1135 mux {
1141 1136 groups = "tdm_b_din0";
1142 1137 function = "tdm_b";
1143 1138 bias-disable;
1144 1139 };
1145 }; 1140 };
1146 1141
1147 tdm_b 1142 tdm_b_din1_pins: tdm-b-din1 {
1148 1143 mux {
1149 1144 groups = "tdm_b_din1";
1150 1145 function = "tdm_b";
1151 1146 bias-disable;
1152 1147 };
1153 }; 1148 };
1154 1149
1155 tdm_b 1150 tdm_b_din2_pins: tdm-b-din2 {
1156 1151 mux {
1157 1152 groups = "tdm_b_din2";
1158 1153 function = "tdm_b";
1159 1154 bias-disable;
1160 1155 };
1161 }; 1156 };
1162 1157
1163 tdm_b 1158 tdm_b_din3_a_pins: tdm-b-din3-a {
1164 1159 mux {
1165 1160 groups = "tdm_b_din3_a";
1166 1161 function = "tdm_b";
1167 1162 bias-disable;
1168 1163 };
1169 }; 1164 };
1170 1165
1171 tdm_b 1166 tdm_b_din3_h_pins: tdm-b-din3-h {
1172 1167 mux {
1173 1168 groups = "tdm_b_din3_h";
1174 1169 function = "tdm_b";
1175 1170 bias-disable;
1176 1171 };
1177 }; 1172 };
1178 1173
1179 tdm_b 1174 tdm_b_dout0_pins: tdm-b-dout0 {
1180 1175 mux {
1181 1176 groups = "tdm_b_dout0";
1182 1177 function = "tdm_b";
1183 1178 bias-disable;
1184 1179 drive-strength-microamp = <3000>;
1185 1180 };
1186 }; 1181 };
1187 1182
1188 tdm_b 1183 tdm_b_dout1_pins: tdm-b-dout1 {
1189 1184 mux {
1190 1185 groups = "tdm_b_dout1";
1191 1186 function = "tdm_b";
1192 1187 bias-disable;
1193 1188 drive-strength-microamp = <3000>;
1194 1189 };
1195 }; 1190 };
1196 1191
1197 tdm_b 1192 tdm_b_dout2_pins: tdm-b-dout2 {
1198 1193 mux {
1199 1194 groups = "tdm_b_dout2";
1200 1195 function = "tdm_b";
1201 1196 bias-disable;
1202 1197 drive-strength-microamp = <3000>;
1203 1198 };
1204 }; 1199 };
1205 1200
1206 tdm_b 1201 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1207 1202 mux {
1208 1203 groups = "tdm_b_dout3_a";
1209 1204 function = "tdm_b";
1210 1205 bias-disable;
1211 1206 drive-strength-microamp = <3000>;
1212 1207 };
1213 }; 1208 };
1214 1209
1215 tdm_b 1210 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1216 1211 mux {
1217 1212 groups = "tdm_b_dout3_h";
1218 1213 function = "tdm_b";
1219 1214 bias-disable;
1220 1215 drive-strength-microamp = <3000>;
1221 1216 };
1222 }; 1217 };
1223 1218
1224 tdm_b 1219 tdm_b_fs_pins: tdm-b-fs {
1225 1220 mux {
1226 1221 groups = "tdm_b_fs";
1227 1222 function = "tdm_b";
1228 1223 bias-disable;
1229 1224 drive-strength-microamp = <3000>;
1230 1225 };
1231 }; 1226 };
1232 1227
1233 tdm_b 1228 tdm_b_sclk_pins: tdm-b-sclk {
1234 1229 mux {
1235 1230 groups = "tdm_b_sclk";
1236 1231 function = "tdm_b";
1237 1232 bias-disable;
1238 1233 drive-strength-microamp = <3000>;
1239 1234 };
1240 }; 1235 };
1241 1236
1242 tdm_b 1237 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1243 1238 mux {
1244 1239 groups = "tdm_b_slv_fs";
1245 1240 function = "tdm_b";
1246 1241 bias-disable;
1247 1242 };
1248 }; 1243 };
1249 1244
1250 tdm_b 1245 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1251 1246 mux {
1252 1247 groups = "tdm_b_slv_sclk";
1253 1248 function = "tdm_b";
1254 1249 bias-disable;
1255 1250 };
1256 }; 1251 };
1257 1252
1258 tdm_c 1253 tdm_c_din0_a_pins: tdm-c-din0-a {
1259 1254 mux {
1260 1255 groups = "tdm_c_din0_a";
1261 1256 function = "tdm_c";
1262 1257 bias-disable;
1263 1258 };
1264 }; 1259 };
1265 1260
1266 tdm_c 1261 tdm_c_din0_z_pins: tdm-c-din0-z {
1267 1262 mux {
1268 1263 groups = "tdm_c_din0_z";
1269 1264 function = "tdm_c";
1270 1265 bias-disable;
1271 1266 };
1272 }; 1267 };
1273 1268
1274 tdm_c 1269 tdm_c_din1_a_pins: tdm-c-din1-a {
1275 1270 mux {
1276 1271 groups = "tdm_c_din1_a";
1277 1272 function = "tdm_c";
1278 1273 bias-disable;
1279 1274 };
1280 }; 1275 };
1281 1276
1282 tdm_c 1277 tdm_c_din1_z_pins: tdm-c-din1-z {
1283 1278 mux {
1284 1279 groups = "tdm_c_din1_z";
1285 1280 function = "tdm_c";
1286 1281 bias-disable;
1287 1282 };
1288 }; 1283 };
1289 1284
1290 tdm_c 1285 tdm_c_din2_a_pins: tdm-c-din2-a {
1291 1286 mux {
1292 1287 groups = "tdm_c_din2_a";
1293 1288 function = "tdm_c";
1294 1289 bias-disable;
1295 1290 };
1296 }; 1291 };
1297 1292
1298 eth_l 1293 eth_leds_pins: eth-leds {
1299 1294 mux {
1300 1295 groups = "eth_link_led",
1301 1296 "eth_act_led";
1302 1297 function = "eth";
1303 1298 bias-disable;
1304 1299 };
1305 }; 1300 };
1306 1301
1307 eth_p 1302 eth_pins: eth {
1308 1303 mux {
1309 1304 groups = "eth_mdio",
1310 1305 "eth_mdc",
1311 1306 "eth_rgmii_rx_clk",
1312 1307 "eth_rx_dv",
1313 1308 "eth_rxd0",
1314 1309 "eth_rxd1",
1315 1310 "eth_txen",
1316 1311 "eth_txd0",
1317 1312 "eth_txd1";
1318 1313 function = "eth";
1319 1314 drive-strength-microamp = <4000>;
1320 1315 bias-disable;
1321 1316 };
1322 }; 1317 };
1323 1318
1324 eth_r 1319 eth_rgmii_pins: eth-rgmii {
1325 1320 mux {
1326 1321 groups = "eth_rxd2_rgmii",
1327 1322 "eth_rxd3_rgmii",
1328 1323 "eth_rgmii_tx_clk",
1329 1324 "eth_txd2_rgmii",
1330 1325 "eth_txd3_rgmii";
1331 1326 function = "eth";
1332 1327 drive-strength-microamp = <4000>;
1333 1328 bias-disable;
1334 1329 };
1335 }; 1330 };
1336 1331
1337 tdm_c 1332 tdm_c_din2_z_pins: tdm-c-din2-z {
1338 1333 mux {
1339 1334 groups = "tdm_c_din2_z";
1340 1335 function = "tdm_c";
1341 1336 bias-disable;
1342 1337 };
1343 }; 1338 };
1344 1339
1345 tdm_c 1340 tdm_c_din3_a_pins: tdm-c-din3-a {
1346 1341 mux {
1347 1342 groups = "tdm_c_din3_a";
1348 1343 function = "tdm_c";
1349 1344 bias-disable;
1350 1345 };
1351 }; 1346 };
1352 1347
1353 tdm_c 1348 tdm_c_din3_z_pins: tdm-c-din3-z {
1354 1349 mux {
1355 1350 groups = "tdm_c_din3_z";
1356 1351 function = "tdm_c";
1357 1352 bias-disable;
1358 1353 };
1359 }; 1354 };
1360 1355
1361 tdm_c 1356 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1362 1357 mux {
1363 1358 groups = "tdm_c_dout0_a";
1364 1359 function = "tdm_c";
1365 1360 bias-disable;
1366 1361 drive-strength-microamp = <3000>;
1367 1362 };
1368 }; 1363 };
1369 1364
1370 tdm_c 1365 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1371 1366 mux {
1372 1367 groups = "tdm_c_dout0_z";
1373 1368 function = "tdm_c";
1374 1369 bias-disable;
1375 1370 drive-strength-microamp = <3000>;
1376 1371 };
1377 }; 1372 };
1378 1373
1379 tdm_c 1374 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1380 1375 mux {
1381 1376 groups = "tdm_c_dout1_a";
1382 1377 function = "tdm_c";
1383 1378 bias-disable;
1384 1379 drive-strength-microamp = <3000>;
1385 1380 };
1386 }; 1381 };
1387 1382
1388 tdm_c 1383 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1389 1384 mux {
1390 1385 groups = "tdm_c_dout1_z";
1391 1386 function = "tdm_c";
1392 1387 bias-disable;
1393 1388 drive-strength-microamp = <3000>;
1394 1389 };
1395 }; 1390 };
1396 1391
1397 tdm_c 1392 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1398 1393 mux {
1399 1394 groups = "tdm_c_dout2_a";
1400 1395 function = "tdm_c";
1401 1396 bias-disable;
1402 1397 drive-strength-microamp = <3000>;
1403 1398 };
1404 }; 1399 };
1405 1400
1406 tdm_c 1401 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1407 1402 mux {
1408 1403 groups = "tdm_c_dout2_z";
1409 1404 function = "tdm_c";
1410 1405 bias-disable;
1411 1406 drive-strength-microamp = <3000>;
1412 1407 };
1413 }; 1408 };
1414 1409
1415 tdm_c 1410 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1416 1411 mux {
1417 1412 groups = "tdm_c_dout3_a";
1418 1413 function = "tdm_c";
1419 1414 bias-disable;
1420 1415 drive-strength-microamp = <3000>;
1421 1416 };
1422 }; 1417 };
1423 1418
1424 tdm_c 1419 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1425 1420 mux {
1426 1421 groups = "tdm_c_dout3_z";
1427 1422 function = "tdm_c";
1428 1423 bias-disable;
1429 1424 drive-strength-microamp = <3000>;
1430 1425 };
1431 }; 1426 };
1432 1427
1433 tdm_c 1428 tdm_c_fs_a_pins: tdm-c-fs-a {
1434 1429 mux {
1435 1430 groups = "tdm_c_fs_a";
1436 1431 function = "tdm_c";
1437 1432 bias-disable;
1438 1433 drive-strength-microamp = <3000>;
1439 1434 };
1440 }; 1435 };
1441 1436
1442 tdm_c 1437 tdm_c_fs_z_pins: tdm-c-fs-z {
1443 1438 mux {
1444 1439 groups = "tdm_c_fs_z";
1445 1440 function = "tdm_c";
1446 1441 bias-disable;
1447 1442 drive-strength-microamp = <3000>;
1448 1443 };
1449 }; 1444 };
1450 1445
1451 tdm_c 1446 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1452 1447 mux {
1453 1448 groups = "tdm_c_sclk_a";
1454 1449 function = "tdm_c";
1455 1450 bias-disable;
1456 1451 drive-strength-microamp = <3000>;
1457 1452 };
1458 }; 1453 };
1459 1454
1460 tdm_c 1455 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1461 1456 mux {
1462 1457 groups = "tdm_c_sclk_z";
1463 1458 function = "tdm_c";
1464 1459 bias-disable;
1465 1460 drive-strength-microamp = <3000>;
1466 1461 };
1467 }; 1462 };
1468 1463
1469 tdm_c 1464 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1470 1465 mux {
1471 1466 groups = "tdm_c_slv_fs_a";
1472 1467 function = "tdm_c";
1473 1468 bias-disable;
1474 1469 };
1475 }; 1470 };
1476 1471
1477 tdm_c 1472 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1478 1473 mux {
1479 1474 groups = "tdm_c_slv_fs_z";
1480 1475 function = "tdm_c";
1481 1476 bias-disable;
1482 1477 };
1483 }; 1478 };
1484 1479
1485 tdm_c 1480 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1486 1481 mux {
1487 1482 groups = "tdm_c_slv_sclk_a";
1488 1483 function = "tdm_c";
1489 1484 bias-disable;
1490 1485 };
1491 }; 1486 };
1492 1487
1493 tdm_c 1488 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1494 1489 mux {
1495 1490 groups = "tdm_c_slv_sclk_z";
1496 1491 function = "tdm_c";
1497 1492 bias-disable;
1498 1493 };
1499 }; 1494 };
1500 1495
1501 uart_ 1496 uart_a_pins: uart-a {
1502 1497 mux {
1503 1498 groups = "uart_a_tx",
1504 1499 "uart_a_rx";
1505 1500 function = "uart_a";
1506 1501 bias-disable;
1507 1502 };
1508 }; 1503 };
1509 1504
1510 uart_ 1505 uart_a_cts_rts_pins: uart-a-cts-rts {
1511 1506 mux {
1512 1507 groups = "uart_a_cts",
1513 1508 "uart_a_rts";
1514 1509 function = "uart_a";
1515 1510 bias-disable;
1516 1511 };
1517 }; 1512 };
1518 1513
1519 uart_ 1514 uart_b_pins: uart-b {
1520 1515 mux {
1521 1516 groups = "uart_b_tx",
1522 1517 "uart_b_rx";
1523 1518 function = "uart_b";
1524 1519 bias-disable;
1525 1520 };
1526 }; 1521 };
1527 1522
1528 uart_ 1523 uart_c_pins: uart-c {
1529 1524 mux {
1530 1525 groups = "uart_c_tx",
1531 1526 "uart_c_rx";
1532 1527 function = "uart_c";
1533 1528 bias-disable;
1534 1529 };
1535 }; 1530 };
1536 1531
1537 uart_ 1532 uart_c_cts_rts_pins: uart-c-cts-rts {
1538 1533 mux {
1539 1534 groups = "uart_c_cts",
1540 1535 "uart_c_rts";
1541 1536 function = "uart_c";
1542 1537 bias-disable;
1543 1538 };
1544 }; 1539 };
1545 }; 1540 };
1546 }; 1541 };
1547 1542
1548 cpu_temp: temperature 1543 cpu_temp: temperature-sensor@34800 {
1549 compatible = 1544 compatible = "amlogic,g12a-cpu-thermal",
1550 1545 "amlogic,g12a-thermal";
1551 reg = <0x0 0x 1546 reg = <0x0 0x34800 0x0 0x50>;
1552 interrupts = 1547 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1553 clocks = <&cl 1548 clocks = <&clkc CLKID_TS>;
1554 #thermal-sens 1549 #thermal-sensor-cells = <0>;
1555 amlogic,ao-se 1550 amlogic,ao-secure = <&sec_AO>;
1556 }; 1551 };
1557 1552
1558 ddr_temp: temperature 1553 ddr_temp: temperature-sensor@34c00 {
1559 compatible = 1554 compatible = "amlogic,g12a-ddr-thermal",
1560 1555 "amlogic,g12a-thermal";
1561 reg = <0x0 0x 1556 reg = <0x0 0x34c00 0x0 0x50>;
1562 interrupts = 1557 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1563 clocks = <&cl 1558 clocks = <&clkc CLKID_TS>;
1564 #thermal-sens 1559 #thermal-sensor-cells = <0>;
1565 amlogic,ao-se 1560 amlogic,ao-secure = <&sec_AO>;
1566 }; 1561 };
1567 1562
1568 usb2_phy0: phy@36000 1563 usb2_phy0: phy@36000 {
1569 compatible = 1564 compatible = "amlogic,g12a-usb2-phy";
1570 reg = <0x0 0x 1565 reg = <0x0 0x36000 0x0 0x2000>;
1571 clocks = <&xt 1566 clocks = <&xtal>;
1572 clock-names = 1567 clock-names = "xtal";
1573 resets = <&re 1568 resets = <&reset RESET_USB_PHY20>;
1574 reset-names = 1569 reset-names = "phy";
1575 #phy-cells = 1570 #phy-cells = <0>;
1576 }; 1571 };
1577 1572
1578 dmc: bus@38000 { 1573 dmc: bus@38000 {
1579 compatible = 1574 compatible = "simple-bus";
1580 #address-cell 1575 #address-cells = <2>;
1581 #size-cells = 1576 #size-cells = <2>;
1582 ranges = <0x0 1577 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>;
1583 1578
1584 canvas: video 1579 canvas: video-lut@48 {
1585 compa 1580 compatible = "amlogic,canvas";
1586 reg = 1581 reg = <0x0 0x48 0x0 0x14>;
1587 }; 1582 };
1588 1583
1589 pmu: pmu@80 { 1584 pmu: pmu@80 {
1590 reg = 1585 reg = <0x0 0x80 0x0 0x40>,
1591 1586 <0x0 0xc00 0x0 0x40>;
1592 inter 1587 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
1593 }; 1588 };
1594 }; 1589 };
1595 1590
1596 usb2_phy1: phy@3a000 1591 usb2_phy1: phy@3a000 {
1597 compatible = 1592 compatible = "amlogic,g12a-usb2-phy";
1598 reg = <0x0 0x 1593 reg = <0x0 0x3a000 0x0 0x2000>;
1599 clocks = <&xt 1594 clocks = <&xtal>;
1600 clock-names = 1595 clock-names = "xtal";
1601 resets = <&re 1596 resets = <&reset RESET_USB_PHY21>;
1602 reset-names = 1597 reset-names = "phy";
1603 #phy-cells = 1598 #phy-cells = <0>;
1604 }; 1599 };
1605 1600
1606 hiu: bus@3c000 { 1601 hiu: bus@3c000 {
1607 compatible = 1602 compatible = "simple-bus";
1608 reg = <0x0 0x 1603 reg = <0x0 0x3c000 0x0 0x1400>;
1609 #address-cell 1604 #address-cells = <2>;
1610 #size-cells = 1605 #size-cells = <2>;
1611 ranges = <0x0 1606 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1612 1607
1613 hhi: system-c 1608 hhi: system-controller@0 {
1614 compa 1609 compatible = "amlogic,meson-gx-hhi-sysctrl",
1615 1610 "simple-mfd", "syscon";
1616 reg = 1611 reg = <0 0 0 0x400>;
1617 1612
1618 clkc: 1613 clkc: clock-controller {
1619 1614 compatible = "amlogic,g12a-clkc";
1620 1615 #clock-cells = <1>;
1621 1616 clocks = <&xtal>;
1622 1617 clock-names = "xtal";
1623 }; 1618 };
1624 1619
1625 pwrc: 1620 pwrc: power-controller {
1626 1621 compatible = "amlogic,meson-g12a-pwrc";
1627 1622 #power-domain-cells = <1>;
1628 1623 amlogic,ao-sysctrl = <&rti>;
1629 1624 resets = <&reset RESET_VIU>,
1630 1625 <&reset RESET_VENC>,
1631 1626 <&reset RESET_VCBUS>,
1632 1627 <&reset RESET_BT656>,
1633 1628 <&reset RESET_RDMA>,
1634 1629 <&reset RESET_VENCI>,
1635 1630 <&reset RESET_VENCP>,
1636 1631 <&reset RESET_VDAC>,
1637 1632 <&reset RESET_VDI6>,
1638 1633 <&reset RESET_VENCL>,
1639 1634 <&reset RESET_VID_LOCK>;
1640 1635 reset-names = "viu", "venc", "vcbus", "bt656",
1641 1636 "rdma", "venci", "vencp", "vdac",
1642 1637 "vdi6", "vencl", "vid_lock";
1643 1638 clocks = <&clkc CLKID_VPU>,
1644 1639 <&clkc CLKID_VAPB>;
1645 1640 clock-names = "vpu", "vapb";
1646 1641 /*
1647 1642 * VPU clocking is provided by two identical clock paths
1648 1643 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1649 1644 * free mux to safely change frequency while running.
1650 1645 * Same for VAPB but with a final gate after the glitch free mux.
1651 1646 */
1652 1647 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1653 1648 <&clkc CLKID_VPU_0>,
1654 1649 <&clkc CLKID_VPU>, /* Glitch free mux */
1655 1650 <&clkc CLKID_VAPB_0_SEL>,
1656 1651 <&clkc CLKID_VAPB_0>,
1657 1652 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1658 1653 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1659 1654 <0>, /* Do Nothing */
1660 1655 <&clkc CLKID_VPU_0>,
1661 1656 <&clkc CLKID_FCLK_DIV4>,
1662 1657 <0>, /* Do Nothing */
1663 1658 <&clkc CLKID_VAPB_0>;
1664 1659 assigned-clock-rates = <0>, /* Do Nothing */
1665 1660 <666666666>,
1666 1661 <0>, /* Do Nothing */
1667 1662 <0>, /* Do Nothing */
1668 1663 <250000000>,
1669 1664 <0>; /* Do Nothing */
1670 }; 1665 };
1671 <<
1672 mipi_ <<
1673 <<
1674 <<
1675 <<
1676 }; <<
1677 }; 1666 };
1678 }; 1667 };
1679 1668
1680 mipi_dphy: phy@44000 <<
1681 compatible = <<
1682 reg = <0x0 0x <<
1683 clocks = <&cl <<
1684 clock-names = <<
1685 resets = <&re <<
1686 reset-names = <<
1687 phys = <&mipi <<
1688 phy-names = " <<
1689 #phy-cells = <<
1690 status = "dis <<
1691 }; <<
1692 <<
1693 usb3_pcie_phy: phy@46 1669 usb3_pcie_phy: phy@46000 {
1694 compatible = 1670 compatible = "amlogic,g12a-usb3-pcie-phy";
1695 reg = <0x0 0x 1671 reg = <0x0 0x46000 0x0 0x2000>;
1696 clocks = <&cl 1672 clocks = <&clkc CLKID_PCIE_PLL>;
1697 clock-names = 1673 clock-names = "ref_clk";
1698 resets = <&re 1674 resets = <&reset RESET_PCIE_PHY>;
1699 reset-names = 1675 reset-names = "phy";
1700 assigned-cloc 1676 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1701 assigned-cloc 1677 assigned-clock-rates = <100000000>;
1702 #phy-cells = 1678 #phy-cells = <1>;
1703 }; 1679 };
1704 1680
1705 eth_phy: mdio-multipl 1681 eth_phy: mdio-multiplexer@4c000 {
1706 compatible = 1682 compatible = "amlogic,g12a-mdio-mux";
1707 reg = <0x0 0x 1683 reg = <0x0 0x4c000 0x0 0xa4>;
1708 clocks = <&cl 1684 clocks = <&clkc CLKID_ETH_PHY>,
1709 <&xt 1685 <&xtal>,
1710 <&cl 1686 <&clkc CLKID_MPLL_50M>;
1711 clock-names = 1687 clock-names = "pclk", "clkin0", "clkin1";
1712 mdio-parent-b 1688 mdio-parent-bus = <&mdio0>;
1713 #address-cell 1689 #address-cells = <1>;
1714 #size-cells = 1690 #size-cells = <0>;
1715 1691
1716 ext_mdio: mdi 1692 ext_mdio: mdio@0 {
1717 reg = 1693 reg = <0>;
1718 #addr 1694 #address-cells = <1>;
1719 #size 1695 #size-cells = <0>;
1720 }; 1696 };
1721 1697
1722 int_mdio: mdi 1698 int_mdio: mdio@1 {
1723 reg = 1699 reg = <1>;
1724 #addr 1700 #address-cells = <1>;
1725 #size 1701 #size-cells = <0>;
1726 1702
1727 inter 1703 internal_ephy: ethernet-phy@8 {
1728 1704 compatible = "ethernet-phy-id0180.3301",
1729 1705 "ethernet-phy-ieee802.3-c22";
1730 1706 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1731 1707 reg = <8>;
1732 1708 max-speed = <100>;
1733 }; 1709 };
1734 }; 1710 };
1735 }; 1711 };
1736 }; 1712 };
1737 1713
1738 aobus: bus@ff800000 { 1714 aobus: bus@ff800000 {
1739 compatible = "simple- 1715 compatible = "simple-bus";
1740 reg = <0x0 0xff800000 1716 reg = <0x0 0xff800000 0x0 0x100000>;
1741 #address-cells = <2>; 1717 #address-cells = <2>;
1742 #size-cells = <2>; 1718 #size-cells = <2>;
1743 ranges = <0x0 0x0 0x0 1719 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1744 1720
1745 rti: sys-ctrl@0 { 1721 rti: sys-ctrl@0 {
1746 compatible = 1722 compatible = "amlogic,meson-gx-ao-sysctrl",
1747 1723 "simple-mfd", "syscon";
1748 reg = <0x0 0x 1724 reg = <0x0 0x0 0x0 0x100>;
>> 1725 #address-cells = <2>;
>> 1726 #size-cells = <2>;
>> 1727 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1749 1728
1750 clkc_AO: cloc 1729 clkc_AO: clock-controller {
1751 compa 1730 compatible = "amlogic,meson-g12a-aoclkc";
1752 #cloc 1731 #clock-cells = <1>;
1753 #rese 1732 #reset-cells = <1>;
1754 clock 1733 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1755 clock 1734 clock-names = "xtal", "mpeg-clk";
1756 }; 1735 };
1757 }; <<
1758 1736
1759 ao_pinctrl: pinctrl@1 !! 1737 ao_pinctrl: pinctrl {
1760 compatible = !! 1738 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1761 #address-cell !! 1739 #address-cells = <2>;
1762 #size-cells = !! 1740 #size-cells = <2>;
1763 ranges; !! 1741 ranges;
1764 1742
1765 gpio_ao: bank !! 1743 gpio_ao: bank@14 {
1766 reg = !! 1744 reg = <0x0 0x14 0x0 0x8>,
1767 !! 1745 <0x0 0x1c 0x0 0x8>,
1768 !! 1746 <0x0 0x24 0x0 0x14>;
1769 reg-n !! 1747 reg-names = "mux",
1770 !! 1748 "ds",
1771 !! 1749 "gpio";
1772 gpio- !! 1750 gpio-controller;
1773 #gpio !! 1751 #gpio-cells = <2>;
1774 gpio- !! 1752 gpio-ranges = <&ao_pinctrl 0 0 15>;
1775 }; !! 1753 };
1776 1754
1777 i2c_ao_sck_pi !! 1755 i2c_ao_sck_pins: i2c_ao_sck_pins {
1778 mux { !! 1756 mux {
1779 !! 1757 groups = "i2c_ao_sck";
1780 !! 1758 function = "i2c_ao";
1781 !! 1759 bias-disable;
1782 !! 1760 drive-strength-microamp = <3000>;
>> 1761 };
1783 }; 1762 };
1784 }; <<
1785 1763
1786 i2c_ao_sda_pi !! 1764 i2c_ao_sda_pins: i2c_ao_sda {
1787 mux { !! 1765 mux {
1788 !! 1766 groups = "i2c_ao_sda";
1789 !! 1767 function = "i2c_ao";
1790 !! 1768 bias-disable;
1791 !! 1769 drive-strength-microamp = <3000>;
>> 1770 };
1792 }; 1771 };
1793 }; <<
1794 1772
1795 i2c_ao_sck_e_ !! 1773 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1796 mux { !! 1774 mux {
1797 !! 1775 groups = "i2c_ao_sck_e";
1798 !! 1776 function = "i2c_ao";
1799 !! 1777 bias-disable;
1800 !! 1778 drive-strength-microamp = <3000>;
>> 1779 };
1801 }; 1780 };
1802 }; <<
1803 1781
1804 i2c_ao_sda_e_ !! 1782 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1805 mux { !! 1783 mux {
1806 !! 1784 groups = "i2c_ao_sda_e";
1807 !! 1785 function = "i2c_ao";
1808 !! 1786 bias-disable;
1809 !! 1787 drive-strength-microamp = <3000>;
>> 1788 };
1810 }; 1789 };
1811 }; <<
1812 1790
1813 mclk0_ao_pins !! 1791 mclk0_ao_pins: mclk0-ao {
1814 mux { !! 1792 mux {
1815 !! 1793 groups = "mclk0_ao";
1816 !! 1794 function = "mclk0_ao";
1817 !! 1795 bias-disable;
1818 !! 1796 drive-strength-microamp = <3000>;
>> 1797 };
1819 }; 1798 };
1820 }; <<
1821 1799
1822 tdm_ao_b_din0 !! 1800 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1823 mux { !! 1801 mux {
1824 !! 1802 groups = "tdm_ao_b_din0";
1825 !! 1803 function = "tdm_ao_b";
1826 !! 1804 bias-disable;
>> 1805 };
1827 }; 1806 };
1828 }; <<
1829 1807
1830 spdif_ao_out_ !! 1808 spdif_ao_out_pins: spdif-ao-out {
1831 mux { !! 1809 mux {
1832 !! 1810 groups = "spdif_ao_out";
1833 !! 1811 function = "spdif_ao_out";
1834 !! 1812 drive-strength-microamp = <500>;
1835 !! 1813 bias-disable;
>> 1814 };
1836 }; 1815 };
1837 }; <<
1838 1816
1839 tdm_ao_b_din1 !! 1817 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1840 mux { !! 1818 mux {
1841 !! 1819 groups = "tdm_ao_b_din1";
1842 !! 1820 function = "tdm_ao_b";
1843 !! 1821 bias-disable;
>> 1822 };
1844 }; 1823 };
1845 }; <<
1846 1824
1847 tdm_ao_b_din2 !! 1825 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1848 mux { !! 1826 mux {
1849 !! 1827 groups = "tdm_ao_b_din2";
1850 !! 1828 function = "tdm_ao_b";
1851 !! 1829 bias-disable;
>> 1830 };
1852 }; 1831 };
1853 }; <<
1854 1832
1855 tdm_ao_b_dout !! 1833 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1856 mux { !! 1834 mux {
1857 !! 1835 groups = "tdm_ao_b_dout0";
1858 !! 1836 function = "tdm_ao_b";
1859 !! 1837 bias-disable;
1860 !! 1838 drive-strength-microamp = <3000>;
>> 1839 };
1861 }; 1840 };
1862 }; <<
1863 1841
1864 tdm_ao_b_dout !! 1842 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1865 mux { !! 1843 mux {
1866 !! 1844 groups = "tdm_ao_b_dout1";
1867 !! 1845 function = "tdm_ao_b";
1868 !! 1846 bias-disable;
1869 !! 1847 drive-strength-microamp = <3000>;
>> 1848 };
1870 }; 1849 };
1871 }; <<
1872 1850
1873 tdm_ao_b_dout !! 1851 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1874 mux { !! 1852 mux {
1875 !! 1853 groups = "tdm_ao_b_dout2";
1876 !! 1854 function = "tdm_ao_b";
1877 !! 1855 bias-disable;
1878 !! 1856 drive-strength-microamp = <3000>;
>> 1857 };
1879 }; 1858 };
1880 }; <<
1881 1859
1882 tdm_ao_b_fs_p !! 1860 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1883 mux { !! 1861 mux {
1884 !! 1862 groups = "tdm_ao_b_fs";
1885 !! 1863 function = "tdm_ao_b";
1886 !! 1864 bias-disable;
1887 !! 1865 drive-strength-microamp = <3000>;
>> 1866 };
1888 }; 1867 };
1889 }; <<
1890 1868
1891 tdm_ao_b_sclk !! 1869 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1892 mux { !! 1870 mux {
1893 !! 1871 groups = "tdm_ao_b_sclk";
1894 !! 1872 function = "tdm_ao_b";
1895 !! 1873 bias-disable;
1896 !! 1874 drive-strength-microamp = <3000>;
>> 1875 };
1897 }; 1876 };
1898 }; <<
1899 1877
1900 tdm_ao_b_slv_ !! 1878 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1901 mux { !! 1879 mux {
1902 !! 1880 groups = "tdm_ao_b_slv_fs";
1903 !! 1881 function = "tdm_ao_b";
1904 !! 1882 bias-disable;
>> 1883 };
1905 }; 1884 };
1906 }; <<
1907 1885
1908 tdm_ao_b_slv_ !! 1886 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1909 mux { !! 1887 mux {
1910 !! 1888 groups = "tdm_ao_b_slv_sclk";
1911 !! 1889 function = "tdm_ao_b";
1912 !! 1890 bias-disable;
>> 1891 };
1913 }; 1892 };
1914 }; <<
1915 1893
1916 uart_ao_a_pin !! 1894 uart_ao_a_pins: uart-a-ao {
1917 mux { !! 1895 mux {
1918 !! 1896 groups = "uart_ao_a_tx",
1919 !! 1897 "uart_ao_a_rx";
1920 !! 1898 function = "uart_ao_a";
1921 !! 1899 bias-disable;
>> 1900 };
1922 }; 1901 };
1923 }; <<
1924 1902
1925 uart_ao_a_cts !! 1903 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1926 mux { !! 1904 mux {
1927 !! 1905 groups = "uart_ao_a_cts",
1928 !! 1906 "uart_ao_a_rts";
1929 !! 1907 function = "uart_ao_a";
1930 !! 1908 bias-disable;
>> 1909 };
1931 }; 1910 };
1932 }; <<
1933 1911
1934 uart_ao_b_2_3 !! 1912 uart_ao_b_2_3_pins: uart-ao-b-2-3 {
1935 mux { !! 1913 mux {
1936 !! 1914 groups = "uart_ao_b_tx_2",
1937 !! 1915 "uart_ao_b_rx_3";
1938 !! 1916 function = "uart_ao_b";
1939 !! 1917 bias-disable;
>> 1918 };
1940 }; 1919 };
1941 }; <<
1942 1920
1943 uart_ao_b_8_9 !! 1921 uart_ao_b_8_9_pins: uart-ao-b-8-9 {
1944 mux { !! 1922 mux {
1945 !! 1923 groups = "uart_ao_b_tx_8",
1946 !! 1924 "uart_ao_b_rx_9";
1947 !! 1925 function = "uart_ao_b";
1948 !! 1926 bias-disable;
>> 1927 };
1949 }; 1928 };
1950 }; <<
1951 1929
1952 uart_ao_b_cts !! 1930 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
1953 mux { !! 1931 mux {
1954 !! 1932 groups = "uart_ao_b_cts",
1955 !! 1933 "uart_ao_b_rts";
1956 !! 1934 function = "uart_ao_b";
1957 !! 1935 bias-disable;
>> 1936 };
1958 }; 1937 };
1959 }; <<
1960 1938
1961 pwm_a_e_pins: !! 1939 pwm_a_e_pins: pwm-a-e {
1962 mux { !! 1940 mux {
1963 !! 1941 groups = "pwm_a_e";
1964 !! 1942 function = "pwm_a_e";
1965 !! 1943 bias-disable;
>> 1944 };
1966 }; 1945 };
1967 }; <<
1968 1946
1969 pwm_ao_a_pins !! 1947 pwm_ao_a_pins: pwm-ao-a {
1970 mux { !! 1948 mux {
1971 !! 1949 groups = "pwm_ao_a";
1972 !! 1950 function = "pwm_ao_a";
1973 !! 1951 bias-disable;
>> 1952 };
1974 }; 1953 };
1975 }; <<
1976 1954
1977 pwm_ao_b_pins !! 1955 pwm_ao_b_pins: pwm-ao-b {
1978 mux { !! 1956 mux {
1979 !! 1957 groups = "pwm_ao_b";
1980 !! 1958 function = "pwm_ao_b";
1981 !! 1959 bias-disable;
>> 1960 };
1982 }; 1961 };
1983 }; <<
1984 1962
1985 pwm_ao_c_4_pi !! 1963 pwm_ao_c_4_pins: pwm-ao-c-4 {
1986 mux { !! 1964 mux {
1987 !! 1965 groups = "pwm_ao_c_4";
1988 !! 1966 function = "pwm_ao_c";
1989 !! 1967 bias-disable;
>> 1968 };
1990 }; 1969 };
1991 }; <<
1992 1970
1993 pwm_ao_c_6_pi !! 1971 pwm_ao_c_6_pins: pwm-ao-c-6 {
1994 mux { !! 1972 mux {
1995 !! 1973 groups = "pwm_ao_c_6";
1996 !! 1974 function = "pwm_ao_c";
1997 !! 1975 bias-disable;
>> 1976 };
1998 }; 1977 };
1999 }; <<
2000 1978
2001 pwm_ao_d_5_pi !! 1979 pwm_ao_d_5_pins: pwm-ao-d-5 {
2002 mux { !! 1980 mux {
2003 !! 1981 groups = "pwm_ao_d_5";
2004 !! 1982 function = "pwm_ao_d";
2005 !! 1983 bias-disable;
>> 1984 };
2006 }; 1985 };
2007 }; <<
2008 1986
2009 pwm_ao_d_10_p !! 1987 pwm_ao_d_10_pins: pwm-ao-d-10 {
2010 mux { !! 1988 mux {
2011 !! 1989 groups = "pwm_ao_d_10";
2012 !! 1990 function = "pwm_ao_d";
2013 !! 1991 bias-disable;
>> 1992 };
2014 }; 1993 };
2015 }; <<
2016 1994
2017 pwm_ao_d_e_pi !! 1995 pwm_ao_d_e_pins: pwm-ao-d-e {
2018 mux { !! 1996 mux {
2019 !! 1997 groups = "pwm_ao_d_e";
2020 !! 1998 function = "pwm_ao_d";
>> 1999 };
2021 }; 2000 };
2022 }; <<
2023 2001
2024 remote_input_ !! 2002 remote_input_ao_pins: remote-input-ao {
2025 mux { !! 2003 mux {
2026 !! 2004 groups = "remote_ao_input";
2027 !! 2005 function = "remote_ao_input";
2028 !! 2006 bias-disable;
>> 2007 };
2029 }; 2008 };
2030 }; 2009 };
2031 }; 2010 };
2032 2011
2033 vrtc: rtc@a8 { 2012 vrtc: rtc@a8 {
2034 compatible = 2013 compatible = "amlogic,meson-vrtc";
2035 reg = <0x0 0x 2014 reg = <0x0 0x000a8 0x0 0x4>;
2036 }; 2015 };
2037 2016
2038 cec_AO: cec@100 { 2017 cec_AO: cec@100 {
2039 compatible = 2018 compatible = "amlogic,meson-gx-ao-cec";
2040 reg = <0x0 0x 2019 reg = <0x0 0x00100 0x0 0x14>;
2041 interrupts = 2020 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2042 clocks = <&cl 2021 clocks = <&clkc_AO CLKID_AO_CEC>;
2043 clock-names = 2022 clock-names = "core";
2044 status = "dis 2023 status = "disabled";
2045 }; 2024 };
2046 2025
2047 sec_AO: ao-secure@140 2026 sec_AO: ao-secure@140 {
2048 compatible = 2027 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2049 reg = <0x0 0x 2028 reg = <0x0 0x140 0x0 0x140>;
2050 amlogic,has-c 2029 amlogic,has-chip-id;
2051 }; 2030 };
2052 2031
2053 cecb_AO: cec@280 { 2032 cecb_AO: cec@280 {
2054 compatible = 2033 compatible = "amlogic,meson-g12a-ao-cec";
2055 reg = <0x0 0x 2034 reg = <0x0 0x00280 0x0 0x1c>;
2056 interrupts = 2035 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2057 clocks = <&cl 2036 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2058 clock-names = 2037 clock-names = "oscin";
2059 status = "dis 2038 status = "disabled";
2060 }; 2039 };
2061 2040
2062 pwm_AO_cd: pwm@2000 { 2041 pwm_AO_cd: pwm@2000 {
2063 compatible = 2042 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2064 reg = <0x0 0x 2043 reg = <0x0 0x2000 0x0 0x20>;
2065 #pwm-cells = 2044 #pwm-cells = <3>;
2066 status = "dis 2045 status = "disabled";
2067 }; 2046 };
2068 2047
2069 uart_AO: serial@3000 2048 uart_AO: serial@3000 {
2070 compatible = 2049 compatible = "amlogic,meson-g12a-uart",
2071 2050 "amlogic,meson-gx-uart",
2072 2051 "amlogic,meson-ao-uart";
2073 reg = <0x0 0x 2052 reg = <0x0 0x3000 0x0 0x18>;
2074 interrupts = 2053 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2075 clocks = <&xt 2054 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2076 clock-names = 2055 clock-names = "xtal", "pclk", "baud";
2077 status = "dis 2056 status = "disabled";
2078 }; 2057 };
2079 2058
2080 uart_AO_B: serial@400 2059 uart_AO_B: serial@4000 {
2081 compatible = 2060 compatible = "amlogic,meson-g12a-uart",
2082 2061 "amlogic,meson-gx-uart",
2083 2062 "amlogic,meson-ao-uart";
2084 reg = <0x0 0x 2063 reg = <0x0 0x4000 0x0 0x18>;
2085 interrupts = 2064 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2086 clocks = <&xt 2065 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2087 clock-names = 2066 clock-names = "xtal", "pclk", "baud";
2088 status = "dis 2067 status = "disabled";
2089 }; 2068 };
2090 2069
2091 i2c_AO: i2c@5000 { 2070 i2c_AO: i2c@5000 {
2092 compatible = 2071 compatible = "amlogic,meson-axg-i2c";
2093 status = "dis 2072 status = "disabled";
2094 reg = <0x0 0x 2073 reg = <0x0 0x05000 0x0 0x20>;
2095 interrupts = 2074 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2096 #address-cell 2075 #address-cells = <1>;
2097 #size-cells = 2076 #size-cells = <0>;
2098 clocks = <&cl 2077 clocks = <&clkc CLKID_I2C>;
2099 }; 2078 };
2100 2079
2101 pwm_AO_ab: pwm@7000 { 2080 pwm_AO_ab: pwm@7000 {
2102 compatible = 2081 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2103 reg = <0x0 0x 2082 reg = <0x0 0x7000 0x0 0x20>;
2104 #pwm-cells = 2083 #pwm-cells = <3>;
2105 status = "dis 2084 status = "disabled";
2106 }; 2085 };
2107 2086
2108 ir: ir@8000 { 2087 ir: ir@8000 {
2109 compatible = 2088 compatible = "amlogic,meson-gxbb-ir";
2110 reg = <0x0 0x 2089 reg = <0x0 0x8000 0x0 0x20>;
2111 interrupts = 2090 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2112 status = "dis 2091 status = "disabled";
2113 }; 2092 };
2114 2093
2115 saradc: adc@9000 { 2094 saradc: adc@9000 {
2116 compatible = 2095 compatible = "amlogic,meson-g12a-saradc",
2117 2096 "amlogic,meson-saradc";
2118 reg = <0x0 0x 2097 reg = <0x0 0x9000 0x0 0x48>;
2119 #io-channel-c 2098 #io-channel-cells = <1>;
2120 interrupts = 2099 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2121 clocks = <&xt 2100 clocks = <&xtal>,
2122 <&cl 2101 <&clkc_AO CLKID_AO_SAR_ADC>,
2123 <&cl 2102 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2124 <&cl 2103 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2125 clock-names = 2104 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2126 status = "dis 2105 status = "disabled";
2127 }; 2106 };
2128 }; 2107 };
2129 2108
2130 vdec: video-decoder@ff620000 2109 vdec: video-decoder@ff620000 {
2131 compatible = "amlogic 2110 compatible = "amlogic,g12a-vdec";
2132 reg = <0x0 0xff620000 2111 reg = <0x0 0xff620000 0x0 0x10000>,
2133 <0x0 0xffd0e180 2112 <0x0 0xffd0e180 0x0 0xe4>;
2134 reg-names = "dos", "e 2113 reg-names = "dos", "esparser";
2135 interrupts = <GIC_SPI 2114 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2136 <GIC_SPI 2115 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2137 interrupt-names = "vd 2116 interrupt-names = "vdec", "esparser";
2138 2117
2139 amlogic,ao-sysctrl = 2118 amlogic,ao-sysctrl = <&rti>;
2140 amlogic,canvas = <&ca 2119 amlogic,canvas = <&canvas>;
2141 2120
2142 clocks = <&clkc CLKID 2121 clocks = <&clkc CLKID_PARSER>,
2143 <&clkc CLKID 2122 <&clkc CLKID_DOS>,
2144 <&clkc CLKID 2123 <&clkc CLKID_VDEC_1>,
2145 <&clkc CLKID 2124 <&clkc CLKID_VDEC_HEVC>,
2146 <&clkc CLKID 2125 <&clkc CLKID_VDEC_HEVCF>;
2147 clock-names = "dos_pa 2126 clock-names = "dos_parser", "dos", "vdec_1",
2148 "vdec_h 2127 "vdec_hevc", "vdec_hevcf";
2149 resets = <&reset RESE 2128 resets = <&reset RESET_PARSER>;
2150 reset-names = "espars 2129 reset-names = "esparser";
2151 }; 2130 };
2152 2131
2153 vpu: vpu@ff900000 { 2132 vpu: vpu@ff900000 {
2154 compatible = "amlogic 2133 compatible = "amlogic,meson-g12a-vpu";
2155 reg = <0x0 0xff900000 2134 reg = <0x0 0xff900000 0x0 0x100000>,
2156 <0x0 0xff63c000 2135 <0x0 0xff63c000 0x0 0x1000>;
2157 reg-names = "vpu", "h 2136 reg-names = "vpu", "hhi";
2158 interrupts = <GIC_SPI 2137 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2159 #address-cells = <1>; 2138 #address-cells = <1>;
2160 #size-cells = <0>; 2139 #size-cells = <0>;
2161 amlogic,canvas = <&ca 2140 amlogic,canvas = <&canvas>;
2162 2141
2163 /* CVBS VDAC output p 2142 /* CVBS VDAC output port */
2164 cvbs_vdac_port: port@ 2143 cvbs_vdac_port: port@0 {
2165 reg = <0>; 2144 reg = <0>;
2166 }; 2145 };
2167 2146
2168 /* HDMI-TX output por 2147 /* HDMI-TX output port */
2169 hdmi_tx_port: port@1 2148 hdmi_tx_port: port@1 {
2170 reg = <1>; 2149 reg = <1>;
2171 2150
2172 hdmi_tx_out: 2151 hdmi_tx_out: endpoint {
2173 remot 2152 remote-endpoint = <&hdmi_tx_in>;
2174 }; 2153 };
2175 }; 2154 };
2176 <<
2177 /* DPI output port */ <<
2178 dpi_port: port@2 { <<
2179 reg = <2>; <<
2180 <<
2181 dpi_out: endp <<
2182 remot <<
2183 }; <<
2184 }; <<
2185 }; 2155 };
2186 2156
2187 gic: interrupt-controller@ffc 2157 gic: interrupt-controller@ffc01000 {
2188 compatible = "arm,gic 2158 compatible = "arm,gic-400";
2189 reg = <0x0 0xffc01000 2159 reg = <0x0 0xffc01000 0 0x1000>,
2190 <0x0 0xffc02000 2160 <0x0 0xffc02000 0 0x2000>,
2191 <0x0 0xffc04000 2161 <0x0 0xffc04000 0 0x2000>,
2192 <0x0 0xffc06000 2162 <0x0 0xffc06000 0 0x2000>;
2193 interrupt-controller; 2163 interrupt-controller;
2194 interrupts = <GIC_PPI 2164 interrupts = <GIC_PPI 9
2195 (GIC_CPU_MASK 2165 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2196 #interrupt-cells = <3 2166 #interrupt-cells = <3>;
2197 #address-cells = <0>; 2167 #address-cells = <0>;
2198 }; 2168 };
2199 2169
2200 cbus: bus@ffd00000 { 2170 cbus: bus@ffd00000 {
2201 compatible = "simple- 2171 compatible = "simple-bus";
2202 reg = <0x0 0xffd00000 2172 reg = <0x0 0xffd00000 0x0 0x100000>;
2203 #address-cells = <2>; 2173 #address-cells = <2>;
2204 #size-cells = <2>; 2174 #size-cells = <2>;
2205 ranges = <0x0 0x0 0x0 2175 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2206 2176
2207 reset: reset-controll 2177 reset: reset-controller@1004 {
2208 compatible = 2178 compatible = "amlogic,meson-axg-reset";
2209 reg = <0x0 0x 2179 reg = <0x0 0x1004 0x0 0x9c>;
2210 #reset-cells 2180 #reset-cells = <1>;
2211 }; 2181 };
2212 2182
2213 gpio_intc: interrupt- 2183 gpio_intc: interrupt-controller@f080 {
2214 compatible = 2184 compatible = "amlogic,meson-g12a-gpio-intc",
2215 2185 "amlogic,meson-gpio-intc";
2216 reg = <0x0 0x 2186 reg = <0x0 0xf080 0x0 0x10>;
2217 interrupt-con 2187 interrupt-controller;
2218 #interrupt-ce 2188 #interrupt-cells = <2>;
2219 amlogic,chann 2189 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2220 }; 2190 };
2221 2191
2222 mipi_dsi: dsi@7000 { <<
2223 compatible = <<
2224 reg = <0x0 0x <<
2225 resets = <&re <<
2226 reset-names = <<
2227 clocks = <&cl <<
2228 <&cl <<
2229 <&cl <<
2230 clock-names = <<
2231 phys = <&mipi <<
2232 phy-names = " <<
2233 #address-cell <<
2234 #size-cells = <<
2235 status = "dis <<
2236 <<
2237 assigned-cloc <<
2238 <&cl <<
2239 <&cl <<
2240 assigned-cloc <<
2241 <&cl <<
2242 <&cl <<
2243 <<
2244 ports { <<
2245 #addr <<
2246 #size <<
2247 <<
2248 /* VP <<
2249 mipi_ <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 <<
2257 /* DS <<
2258 mipi_ <<
2259 <<
2260 }; <<
2261 }; <<
2262 }; <<
2263 <<
2264 watchdog: watchdog@f0 2192 watchdog: watchdog@f0d0 {
2265 compatible = 2193 compatible = "amlogic,meson-gxbb-wdt";
2266 reg = <0x0 0x 2194 reg = <0x0 0xf0d0 0x0 0x10>;
2267 clocks = <&xt 2195 clocks = <&xtal>;
2268 }; 2196 };
2269 2197
2270 spicc0: spi@13000 { 2198 spicc0: spi@13000 {
2271 compatible = 2199 compatible = "amlogic,meson-g12a-spicc";
2272 reg = <0x0 0x 2200 reg = <0x0 0x13000 0x0 0x44>;
2273 interrupts = 2201 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2274 clocks = <&cl 2202 clocks = <&clkc CLKID_SPICC0>,
2275 <&cl 2203 <&clkc CLKID_SPICC0_SCLK>;
2276 clock-names = 2204 clock-names = "core", "pclk";
2277 #address-cell 2205 #address-cells = <1>;
2278 #size-cells = 2206 #size-cells = <0>;
2279 status = "dis 2207 status = "disabled";
2280 }; 2208 };
2281 2209
2282 spicc1: spi@15000 { 2210 spicc1: spi@15000 {
2283 compatible = 2211 compatible = "amlogic,meson-g12a-spicc";
2284 reg = <0x0 0x 2212 reg = <0x0 0x15000 0x0 0x44>;
2285 interrupts = 2213 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2286 clocks = <&cl 2214 clocks = <&clkc CLKID_SPICC1>,
2287 <&cl 2215 <&clkc CLKID_SPICC1_SCLK>;
2288 clock-names = 2216 clock-names = "core", "pclk";
2289 #address-cell 2217 #address-cells = <1>;
2290 #size-cells = 2218 #size-cells = <0>;
2291 status = "dis 2219 status = "disabled";
2292 }; 2220 };
2293 2221
2294 spifc: spi@14000 { 2222 spifc: spi@14000 {
2295 compatible = 2223 compatible = "amlogic,meson-gxbb-spifc";
2296 status = "dis 2224 status = "disabled";
2297 reg = <0x0 0x 2225 reg = <0x0 0x14000 0x0 0x80>;
2298 #address-cell 2226 #address-cells = <1>;
2299 #size-cells = 2227 #size-cells = <0>;
2300 clocks = <&cl 2228 clocks = <&clkc CLKID_CLK81>;
2301 }; 2229 };
2302 2230
2303 pwm_ef: pwm@19000 { 2231 pwm_ef: pwm@19000 {
2304 compatible = 2232 compatible = "amlogic,meson-g12a-ee-pwm";
2305 reg = <0x0 0x 2233 reg = <0x0 0x19000 0x0 0x20>;
2306 #pwm-cells = 2234 #pwm-cells = <3>;
2307 status = "dis 2235 status = "disabled";
2308 }; 2236 };
2309 2237
2310 pwm_cd: pwm@1a000 { 2238 pwm_cd: pwm@1a000 {
2311 compatible = 2239 compatible = "amlogic,meson-g12a-ee-pwm";
2312 reg = <0x0 0x 2240 reg = <0x0 0x1a000 0x0 0x20>;
2313 #pwm-cells = 2241 #pwm-cells = <3>;
2314 status = "dis 2242 status = "disabled";
2315 }; 2243 };
2316 2244
2317 pwm_ab: pwm@1b000 { 2245 pwm_ab: pwm@1b000 {
2318 compatible = 2246 compatible = "amlogic,meson-g12a-ee-pwm";
2319 reg = <0x0 0x 2247 reg = <0x0 0x1b000 0x0 0x20>;
2320 #pwm-cells = 2248 #pwm-cells = <3>;
2321 status = "dis 2249 status = "disabled";
2322 }; 2250 };
2323 2251
2324 i2c3: i2c@1c000 { 2252 i2c3: i2c@1c000 {
2325 compatible = 2253 compatible = "amlogic,meson-axg-i2c";
2326 status = "dis 2254 status = "disabled";
2327 reg = <0x0 0x 2255 reg = <0x0 0x1c000 0x0 0x20>;
2328 interrupts = 2256 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2329 #address-cell 2257 #address-cells = <1>;
2330 #size-cells = 2258 #size-cells = <0>;
2331 clocks = <&cl 2259 clocks = <&clkc CLKID_I2C>;
2332 }; 2260 };
2333 2261
2334 i2c2: i2c@1d000 { 2262 i2c2: i2c@1d000 {
2335 compatible = 2263 compatible = "amlogic,meson-axg-i2c";
2336 status = "dis 2264 status = "disabled";
2337 reg = <0x0 0x 2265 reg = <0x0 0x1d000 0x0 0x20>;
2338 interrupts = 2266 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2339 #address-cell 2267 #address-cells = <1>;
2340 #size-cells = 2268 #size-cells = <0>;
2341 clocks = <&cl 2269 clocks = <&clkc CLKID_I2C>;
2342 }; 2270 };
2343 2271
2344 i2c1: i2c@1e000 { 2272 i2c1: i2c@1e000 {
2345 compatible = 2273 compatible = "amlogic,meson-axg-i2c";
2346 status = "dis 2274 status = "disabled";
2347 reg = <0x0 0x 2275 reg = <0x0 0x1e000 0x0 0x20>;
2348 interrupts = 2276 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2349 #address-cell 2277 #address-cells = <1>;
2350 #size-cells = 2278 #size-cells = <0>;
2351 clocks = <&cl 2279 clocks = <&clkc CLKID_I2C>;
2352 }; 2280 };
2353 2281
2354 i2c0: i2c@1f000 { 2282 i2c0: i2c@1f000 {
2355 compatible = 2283 compatible = "amlogic,meson-axg-i2c";
2356 status = "dis 2284 status = "disabled";
2357 reg = <0x0 0x 2285 reg = <0x0 0x1f000 0x0 0x20>;
2358 interrupts = 2286 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2359 #address-cell 2287 #address-cells = <1>;
2360 #size-cells = 2288 #size-cells = <0>;
2361 clocks = <&cl 2289 clocks = <&clkc CLKID_I2C>;
2362 }; 2290 };
2363 2291
2364 clk_msr: clock-measur 2292 clk_msr: clock-measure@18000 {
2365 compatible = 2293 compatible = "amlogic,meson-g12a-clk-measure";
2366 reg = <0x0 0x 2294 reg = <0x0 0x18000 0x0 0x10>;
2367 }; 2295 };
2368 2296
2369 uart_C: serial@22000 2297 uart_C: serial@22000 {
2370 compatible = 2298 compatible = "amlogic,meson-g12a-uart",
2371 2299 "amlogic,meson-gx-uart";
2372 reg = <0x0 0x 2300 reg = <0x0 0x22000 0x0 0x18>;
2373 interrupts = 2301 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2374 clocks = <&xt 2302 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2375 clock-names = 2303 clock-names = "xtal", "pclk", "baud";
2376 status = "dis 2304 status = "disabled";
2377 }; 2305 };
2378 2306
2379 uart_B: serial@23000 2307 uart_B: serial@23000 {
2380 compatible = 2308 compatible = "amlogic,meson-g12a-uart",
2381 2309 "amlogic,meson-gx-uart";
2382 reg = <0x0 0x 2310 reg = <0x0 0x23000 0x0 0x18>;
2383 interrupts = 2311 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2384 clocks = <&xt 2312 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2385 clock-names = 2313 clock-names = "xtal", "pclk", "baud";
2386 status = "dis 2314 status = "disabled";
2387 }; 2315 };
2388 2316
2389 uart_A: serial@24000 2317 uart_A: serial@24000 {
2390 compatible = 2318 compatible = "amlogic,meson-g12a-uart",
2391 2319 "amlogic,meson-gx-uart";
2392 reg = <0x0 0x 2320 reg = <0x0 0x24000 0x0 0x18>;
2393 interrupts = 2321 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2394 clocks = <&xt 2322 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2395 clock-names = 2323 clock-names = "xtal", "pclk", "baud";
2396 status = "dis 2324 status = "disabled";
2397 fifo-size = < 2325 fifo-size = <128>;
2398 }; 2326 };
2399 }; 2327 };
2400 2328
2401 sd_emmc_a: mmc@ffe03000 { 2329 sd_emmc_a: mmc@ffe03000 {
2402 compatible = "amlogic 2330 compatible = "amlogic,meson-axg-mmc";
2403 reg = <0x0 0xffe03000 2331 reg = <0x0 0xffe03000 0x0 0x800>;
2404 interrupts = <GIC_SPI 2332 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2405 status = "disabled"; 2333 status = "disabled";
2406 clocks = <&clkc CLKID 2334 clocks = <&clkc CLKID_SD_EMMC_A>,
2407 <&clkc CLKID 2335 <&clkc CLKID_SD_EMMC_A_CLK0>,
2408 <&clkc CLKID 2336 <&clkc CLKID_FCLK_DIV2>;
2409 clock-names = "core", 2337 clock-names = "core", "clkin0", "clkin1";
2410 resets = <&reset RESE 2338 resets = <&reset RESET_SD_EMMC_A>;
2411 }; 2339 };
2412 2340
2413 sd_emmc_b: mmc@ffe05000 { 2341 sd_emmc_b: mmc@ffe05000 {
2414 compatible = "amlogic 2342 compatible = "amlogic,meson-axg-mmc";
2415 reg = <0x0 0xffe05000 2343 reg = <0x0 0xffe05000 0x0 0x800>;
2416 interrupts = <GIC_SPI 2344 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2417 status = "disabled"; 2345 status = "disabled";
2418 clocks = <&clkc CLKID 2346 clocks = <&clkc CLKID_SD_EMMC_B>,
2419 <&clkc CLKID 2347 <&clkc CLKID_SD_EMMC_B_CLK0>,
2420 <&clkc CLKID 2348 <&clkc CLKID_FCLK_DIV2>;
2421 clock-names = "core", 2349 clock-names = "core", "clkin0", "clkin1";
2422 resets = <&reset RESE 2350 resets = <&reset RESET_SD_EMMC_B>;
2423 }; 2351 };
2424 2352
2425 sd_emmc_c: mmc@ffe07000 { 2353 sd_emmc_c: mmc@ffe07000 {
2426 compatible = "amlogic 2354 compatible = "amlogic,meson-axg-mmc";
2427 reg = <0x0 0xffe07000 2355 reg = <0x0 0xffe07000 0x0 0x800>;
2428 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2429 status = "disabled"; 2357 status = "disabled";
2430 clocks = <&clkc CLKID 2358 clocks = <&clkc CLKID_SD_EMMC_C>,
2431 <&clkc CLKID 2359 <&clkc CLKID_SD_EMMC_C_CLK0>,
2432 <&clkc CLKID 2360 <&clkc CLKID_FCLK_DIV2>;
2433 clock-names = "core", 2361 clock-names = "core", "clkin0", "clkin1";
2434 resets = <&reset RESE 2362 resets = <&reset RESET_SD_EMMC_C>;
2435 }; 2363 };
2436 2364
2437 usb: usb@ffe09000 { 2365 usb: usb@ffe09000 {
2438 status = "disabled"; 2366 status = "disabled";
2439 compatible = "amlogic 2367 compatible = "amlogic,meson-g12a-usb-ctrl";
2440 reg = <0x0 0xffe09000 2368 reg = <0x0 0xffe09000 0x0 0xa0>;
2441 interrupts = <GIC_SPI 2369 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2442 #address-cells = <2>; 2370 #address-cells = <2>;
2443 #size-cells = <2>; 2371 #size-cells = <2>;
2444 ranges; 2372 ranges;
2445 2373
2446 clocks = <&clkc CLKID 2374 clocks = <&clkc CLKID_USB>;
2447 resets = <&reset RESE 2375 resets = <&reset RESET_USB>;
2448 2376
2449 dr_mode = "otg"; 2377 dr_mode = "otg";
2450 2378
2451 phys = <&usb2_phy0>, 2379 phys = <&usb2_phy0>, <&usb2_phy1>,
2452 <&usb3_pcie_ph 2380 <&usb3_pcie_phy PHY_TYPE_USB3>;
2453 phy-names = "usb2-phy 2381 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2454 2382
2455 dwc2: usb@ff400000 { 2383 dwc2: usb@ff400000 {
2456 compatible = 2384 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2457 reg = <0x0 0x 2385 reg = <0x0 0xff400000 0x0 0x40000>;
2458 interrupts = 2386 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2459 clocks = <&cl 2387 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2460 clock-names = 2388 clock-names = "otg";
2461 phys = <&usb2 2389 phys = <&usb2_phy1>;
2462 phy-names = " 2390 phy-names = "usb2-phy";
2463 dr_mode = "pe 2391 dr_mode = "peripheral";
2464 g-rx-fifo-siz 2392 g-rx-fifo-size = <192>;
2465 g-np-tx-fifo- 2393 g-np-tx-fifo-size = <128>;
2466 g-tx-fifo-siz 2394 g-tx-fifo-size = <128 128 16 16 16>;
2467 }; 2395 };
2468 2396
2469 dwc3: usb@ff500000 { 2397 dwc3: usb@ff500000 {
2470 compatible = 2398 compatible = "snps,dwc3";
2471 reg = <0x0 0x 2399 reg = <0x0 0xff500000 0x0 0x100000>;
2472 interrupts = 2400 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2473 dr_mode = "ho 2401 dr_mode = "host";
2474 snps,dis_u2_s 2402 snps,dis_u2_susphy_quirk;
2475 snps,quirk-fr 2403 snps,quirk-frame-length-adjustment = <0x20>;
2476 snps,parkmode 2404 snps,parkmode-disable-ss-quirk;
2477 }; 2405 };
2478 }; 2406 };
2479 2407
2480 mali: gpu@ffe40000 { 2408 mali: gpu@ffe40000 {
2481 compatible = "amlogic 2409 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2482 reg = <0x0 0xffe40000 2410 reg = <0x0 0xffe40000 0x0 0x40000>;
2483 interrupt-parent = <& 2411 interrupt-parent = <&gic>;
2484 interrupts = <GIC_SPI 2412 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 2413 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 2414 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2487 interrupt-names = "jo 2415 interrupt-names = "job", "mmu", "gpu";
2488 clocks = <&clkc CLKID 2416 clocks = <&clkc CLKID_MALI>;
2489 resets = <&reset RESE 2417 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2490 operating-points-v2 = 2418 operating-points-v2 = <&gpu_opp_table>;
2491 #cooling-cells = <2>; 2419 #cooling-cells = <2>;
2492 }; 2420 };
2493 }; 2421 };
2494 2422
2495 thermal-zones { 2423 thermal-zones {
2496 cpu_thermal: cpu-thermal { 2424 cpu_thermal: cpu-thermal {
2497 polling-delay = <1000 2425 polling-delay = <1000>;
2498 polling-delay-passive 2426 polling-delay-passive = <100>;
2499 thermal-sensors = <&c 2427 thermal-sensors = <&cpu_temp>;
2500 2428
2501 trips { 2429 trips {
2502 cpu_passive: 2430 cpu_passive: cpu-passive {
2503 tempe 2431 temperature = <85000>; /* millicelsius */
2504 hyste 2432 hysteresis = <2000>; /* millicelsius */
2505 type 2433 type = "passive";
2506 }; 2434 };
2507 2435
2508 cpu_hot: cpu- 2436 cpu_hot: cpu-hot {
2509 tempe 2437 temperature = <95000>; /* millicelsius */
2510 hyste 2438 hysteresis = <2000>; /* millicelsius */
2511 type 2439 type = "hot";
2512 }; 2440 };
2513 2441
2514 cpu_critical: 2442 cpu_critical: cpu-critical {
2515 tempe 2443 temperature = <110000>; /* millicelsius */
2516 hyste 2444 hysteresis = <2000>; /* millicelsius */
2517 type 2445 type = "critical";
2518 }; 2446 };
2519 }; 2447 };
2520 }; 2448 };
2521 2449
2522 ddr_thermal: ddr-thermal { 2450 ddr_thermal: ddr-thermal {
2523 polling-delay = <1000 2451 polling-delay = <1000>;
2524 polling-delay-passive 2452 polling-delay-passive = <100>;
2525 thermal-sensors = <&d 2453 thermal-sensors = <&ddr_temp>;
2526 2454
2527 trips { 2455 trips {
2528 ddr_passive: 2456 ddr_passive: ddr-passive {
2529 tempe 2457 temperature = <85000>; /* millicelsius */
2530 hyste 2458 hysteresis = <2000>; /* millicelsius */
2531 type 2459 type = "passive";
2532 }; 2460 };
2533 2461
2534 ddr_critical: 2462 ddr_critical: ddr-critical {
2535 tempe 2463 temperature = <110000>; /* millicelsius */
2536 hyste 2464 hysteresis = <2000>; /* millicelsius */
2537 type 2465 type = "critical";
2538 }; 2466 };
2539 }; 2467 };
2540 2468
2541 cooling-maps { 2469 cooling-maps {
2542 map { 2470 map {
2543 trip 2471 trip = <&ddr_passive>;
2544 cooli 2472 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2545 }; 2473 };
2546 }; 2474 };
2547 }; 2475 };
2548 }; 2476 };
2549 2477
2550 timer { 2478 timer {
2551 compatible = "arm,armv8-timer 2479 compatible = "arm,armv8-timer";
2552 interrupts = <GIC_PPI 13 2480 interrupts = <GIC_PPI 13
2553 (GIC_CPU_MASK_RAW(0xf 2481 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2554 <GIC_PPI 14 2482 <GIC_PPI 14
2555 (GIC_CPU_MASK_RAW(0xf 2483 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2556 <GIC_PPI 11 2484 <GIC_PPI 11
2557 (GIC_CPU_MASK_RAW(0xf 2485 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2558 <GIC_PPI 10 2486 <GIC_PPI 10
2559 (GIC_CPU_MASK_RAW(0xf 2487 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2560 arm,no-tick-in-suspend; 2488 arm,no-tick-in-suspend;
2561 }; 2489 };
2562 2490
2563 xtal: xtal-clk { 2491 xtal: xtal-clk {
2564 compatible = "fixed-clock"; 2492 compatible = "fixed-clock";
2565 clock-frequency = <24000000>; 2493 clock-frequency = <24000000>;
2566 clock-output-names = "xtal"; 2494 clock-output-names = "xtal";
2567 #clock-cells = <0>; 2495 #clock-cells = <0>;
2568 }; 2496 };
2569 2497
2570 npu: npu@ff100000 { 2498 npu: npu@ff100000 {
2571 compatible = "vivante,gc"; 2499 compatible = "vivante,gc";
2572 reg = <0x0 0xff100000 0x0 0x2 2500 reg = <0x0 0xff100000 0x0 0x20000>;
2573 interrupts = <0 147 4>; 2501 interrupts = <0 147 4>;
2574 clocks = <&clkc CLKID_NNA_COR 2502 clocks = <&clkc CLKID_NNA_CORE_CLK>,
2575 <&clkc CLKID_NNA_AXI 2503 <&clkc CLKID_NNA_AXI_CLK>;
2576 clock-names = "core", "bus"; 2504 clock-names = "core", "bus";
2577 assigned-clocks = <&clkc CLKI <<
2578 <&clkc CLKI <<
2579 assigned-clock-rates = <80000 <<
2580 resets = <&reset RESET_NNA>; 2505 resets = <&reset RESET_NNA>;
2581 status = "disabled"; 2506 status = "disabled";
2582 }; 2507 };
2583 }; 2508 };
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