1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 BayLibre, SAS 3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre. 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2019 Christian Hewitt <christi 5 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
6 */ 6 */
7 7
8 / { !! 8 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
9 model = "Khadas VIM3"; <<
10 9
>> 10 / {
11 vddcpu_a: regulator-vddcpu-a { 11 vddcpu_a: regulator-vddcpu-a {
12 /* 12 /*
13 * MP8756GD Regulator. 13 * MP8756GD Regulator.
14 */ 14 */
15 compatible = "pwm-regulator"; 15 compatible = "pwm-regulator";
16 16
17 regulator-name = "VDDCPU_A"; 17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690 18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <105 19 regulator-max-microvolt = <1050000>;
20 20
21 pwm-supply = <&dc_in>; !! 21 vin-supply = <&dc_in>;
22 22
23 pwms = <&pwm_ab 0 1250 0>; 23 pwms = <&pwm_ab 0 1250 0>;
24 pwm-dutycycle-range = <100 0>; 24 pwm-dutycycle-range = <100 0>;
25 25
26 regulator-boot-on; 26 regulator-boot-on;
27 regulator-always-on; 27 regulator-always-on;
28 }; 28 };
29 29
30 vddcpu_b: regulator-vddcpu-b { 30 vddcpu_b: regulator-vddcpu-b {
31 /* 31 /*
32 * Silergy SY8030DEC Regulator 32 * Silergy SY8030DEC Regulator.
33 */ 33 */
34 compatible = "pwm-regulator"; 34 compatible = "pwm-regulator";
35 35
36 regulator-name = "VDDCPU_B"; 36 regulator-name = "VDDCPU_B";
37 regulator-min-microvolt = <690 37 regulator-min-microvolt = <690000>;
38 regulator-max-microvolt = <105 38 regulator-max-microvolt = <1050000>;
39 39
40 pwm-supply = <&vsys_3v3>; !! 40 vin-supply = <&vsys_3v3>;
41 41
42 pwms = <&pwm_AO_cd 1 1250 0>; 42 pwms = <&pwm_AO_cd 1 1250 0>;
43 pwm-dutycycle-range = <100 0>; 43 pwm-dutycycle-range = <100 0>;
44 44
45 regulator-boot-on; 45 regulator-boot-on;
46 regulator-always-on; 46 regulator-always-on;
47 }; 47 };
>> 48
>> 49 sound {
>> 50 compatible = "amlogic,axg-sound-card";
>> 51 model = "G12A-KHADAS-VIM3";
>> 52 audio-aux-devs = <&tdmout_b>;
>> 53 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
>> 54 "TDMOUT_B IN 1", "FRDDR_B OUT 1",
>> 55 "TDMOUT_B IN 2", "FRDDR_C OUT 1",
>> 56 "TDM_B Playback", "TDMOUT_B OUT";
>> 57
>> 58 assigned-clocks = <&clkc CLKID_MPLL2>,
>> 59 <&clkc CLKID_MPLL0>,
>> 60 <&clkc CLKID_MPLL1>;
>> 61 assigned-clock-parents = <0>, <0>, <0>;
>> 62 assigned-clock-rates = <294912000>,
>> 63 <270950400>,
>> 64 <393216000>;
>> 65 status = "okay";
>> 66
>> 67 dai-link-0 {
>> 68 sound-dai = <&frddr_a>;
>> 69 };
>> 70
>> 71 dai-link-1 {
>> 72 sound-dai = <&frddr_b>;
>> 73 };
>> 74
>> 75 dai-link-2 {
>> 76 sound-dai = <&frddr_c>;
>> 77 };
>> 78
>> 79 /* 8ch hdmi interface */
>> 80 dai-link-3 {
>> 81 sound-dai = <&tdmif_b>;
>> 82 dai-format = "i2s";
>> 83 dai-tdm-slot-tx-mask-0 = <1 1>;
>> 84 dai-tdm-slot-tx-mask-1 = <1 1>;
>> 85 dai-tdm-slot-tx-mask-2 = <1 1>;
>> 86 dai-tdm-slot-tx-mask-3 = <1 1>;
>> 87 mclk-fs = <256>;
>> 88
>> 89 codec {
>> 90 sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
>> 91 };
>> 92 };
>> 93
>> 94 /* hdmi glue */
>> 95 dai-link-4 {
>> 96 sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
>> 97
>> 98 codec {
>> 99 sound-dai = <&hdmi_tx>;
>> 100 };
>> 101 };
>> 102 };
>> 103 };
>> 104
>> 105 &arb {
>> 106 status = "okay";
>> 107 };
>> 108
>> 109 &clkc_audio {
>> 110 status = "okay";
48 }; 111 };
49 112
50 &cpu0 { 113 &cpu0 {
51 cpu-supply = <&vddcpu_b>; 114 cpu-supply = <&vddcpu_b>;
52 operating-points-v2 = <&cpu_opp_table_ 115 operating-points-v2 = <&cpu_opp_table_0>;
53 clocks = <&clkc CLKID_CPU_CLK>; 116 clocks = <&clkc CLKID_CPU_CLK>;
54 clock-latency = <50000>; 117 clock-latency = <50000>;
55 }; 118 };
56 119
57 &cpu1 { 120 &cpu1 {
58 cpu-supply = <&vddcpu_b>; 121 cpu-supply = <&vddcpu_b>;
59 operating-points-v2 = <&cpu_opp_table_ 122 operating-points-v2 = <&cpu_opp_table_0>;
60 clocks = <&clkc CLKID_CPU_CLK>; 123 clocks = <&clkc CLKID_CPU_CLK>;
61 clock-latency = <50000>; 124 clock-latency = <50000>;
62 }; 125 };
63 126
64 &cpu100 { 127 &cpu100 {
65 cpu-supply = <&vddcpu_a>; 128 cpu-supply = <&vddcpu_a>;
66 operating-points-v2 = <&cpub_opp_table 129 operating-points-v2 = <&cpub_opp_table_1>;
67 clocks = <&clkc CLKID_CPUB_CLK>; 130 clocks = <&clkc CLKID_CPUB_CLK>;
68 clock-latency = <50000>; 131 clock-latency = <50000>;
69 }; 132 };
70 133
71 &cpu101 { 134 &cpu101 {
72 cpu-supply = <&vddcpu_a>; 135 cpu-supply = <&vddcpu_a>;
73 operating-points-v2 = <&cpub_opp_table 136 operating-points-v2 = <&cpub_opp_table_1>;
74 clocks = <&clkc CLKID_CPUB_CLK>; 137 clocks = <&clkc CLKID_CPUB_CLK>;
75 clock-latency = <50000>; 138 clock-latency = <50000>;
76 }; 139 };
77 140
78 &cpu102 { 141 &cpu102 {
79 cpu-supply = <&vddcpu_a>; 142 cpu-supply = <&vddcpu_a>;
80 operating-points-v2 = <&cpub_opp_table 143 operating-points-v2 = <&cpub_opp_table_1>;
81 clocks = <&clkc CLKID_CPUB_CLK>; 144 clocks = <&clkc CLKID_CPUB_CLK>;
82 clock-latency = <50000>; 145 clock-latency = <50000>;
83 }; 146 };
84 147
85 &cpu103 { 148 &cpu103 {
86 cpu-supply = <&vddcpu_a>; 149 cpu-supply = <&vddcpu_a>;
87 operating-points-v2 = <&cpub_opp_table 150 operating-points-v2 = <&cpub_opp_table_1>;
88 clocks = <&clkc CLKID_CPUB_CLK>; 151 clocks = <&clkc CLKID_CPUB_CLK>;
89 clock-latency = <50000>; 152 clock-latency = <50000>;
90 }; 153 };
91 154
>> 155 &frddr_a {
>> 156 status = "okay";
>> 157 };
>> 158
>> 159 &frddr_b {
>> 160 status = "okay";
>> 161 };
>> 162
>> 163 &frddr_c {
>> 164 status = "okay";
>> 165 };
>> 166
92 &pwm_ab { 167 &pwm_ab {
93 pinctrl-0 = <&pwm_a_e_pins>; 168 pinctrl-0 = <&pwm_a_e_pins>;
94 pinctrl-names = "default"; 169 pinctrl-names = "default";
95 clocks = <&xtal>; 170 clocks = <&xtal>;
96 clock-names = "clkin0"; 171 clock-names = "clkin0";
97 status = "okay"; 172 status = "okay";
98 }; 173 };
99 174
100 &pwm_AO_cd { 175 &pwm_AO_cd {
101 pinctrl-0 = <&pwm_ao_d_e_pins>; 176 pinctrl-0 = <&pwm_ao_d_e_pins>;
102 pinctrl-names = "default"; 177 pinctrl-names = "default";
103 clocks = <&xtal>; 178 clocks = <&xtal>;
104 clock-names = "clkin1"; 179 clock-names = "clkin1";
105 status = "okay"; 180 status = "okay";
106 }; 181 };
107 182
>> 183 &tdmif_b {
>> 184 status = "okay";
>> 185 };
>> 186
>> 187 &tdmout_b {
>> 188 status = "okay";
>> 189 };
>> 190
>> 191 &tohdmitx {
>> 192 status = "okay";
>> 193 };
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