1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 BayLibre, SAS 3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre. 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2019 Christian Hewitt <christi 5 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
6 */ 6 */
7 7
>> 8 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
>> 9
8 / { 10 / {
9 model = "Khadas VIM3"; 11 model = "Khadas VIM3";
10 12
11 vddcpu_a: regulator-vddcpu-a { 13 vddcpu_a: regulator-vddcpu-a {
12 /* 14 /*
13 * MP8756GD Regulator. 15 * MP8756GD Regulator.
14 */ 16 */
15 compatible = "pwm-regulator"; 17 compatible = "pwm-regulator";
16 18
17 regulator-name = "VDDCPU_A"; 19 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690 20 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <105 21 regulator-max-microvolt = <1050000>;
20 22
21 pwm-supply = <&dc_in>; !! 23 vin-supply = <&dc_in>;
22 24
23 pwms = <&pwm_ab 0 1250 0>; 25 pwms = <&pwm_ab 0 1250 0>;
24 pwm-dutycycle-range = <100 0>; 26 pwm-dutycycle-range = <100 0>;
25 27
26 regulator-boot-on; 28 regulator-boot-on;
27 regulator-always-on; 29 regulator-always-on;
28 }; 30 };
29 31
30 vddcpu_b: regulator-vddcpu-b { 32 vddcpu_b: regulator-vddcpu-b {
31 /* 33 /*
32 * Silergy SY8030DEC Regulator 34 * Silergy SY8030DEC Regulator.
33 */ 35 */
34 compatible = "pwm-regulator"; 36 compatible = "pwm-regulator";
35 37
36 regulator-name = "VDDCPU_B"; 38 regulator-name = "VDDCPU_B";
37 regulator-min-microvolt = <690 39 regulator-min-microvolt = <690000>;
38 regulator-max-microvolt = <105 40 regulator-max-microvolt = <1050000>;
39 41
40 pwm-supply = <&vsys_3v3>; !! 42 vin-supply = <&vsys_3v3>;
41 43
42 pwms = <&pwm_AO_cd 1 1250 0>; 44 pwms = <&pwm_AO_cd 1 1250 0>;
43 pwm-dutycycle-range = <100 0>; 45 pwm-dutycycle-range = <100 0>;
44 46
45 regulator-boot-on; 47 regulator-boot-on;
46 regulator-always-on; 48 regulator-always-on;
47 }; 49 };
>> 50
>> 51 sound {
>> 52 compatible = "amlogic,axg-sound-card";
>> 53 model = "G12B-KHADAS-VIM3";
>> 54 audio-aux-devs = <&tdmout_a>;
>> 55 audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
>> 56 "TDMOUT_A IN 1", "FRDDR_B OUT 0",
>> 57 "TDMOUT_A IN 2", "FRDDR_C OUT 0",
>> 58 "TDM_A Playback", "TDMOUT_A OUT";
>> 59
>> 60 assigned-clocks = <&clkc CLKID_MPLL2>,
>> 61 <&clkc CLKID_MPLL0>,
>> 62 <&clkc CLKID_MPLL1>;
>> 63 assigned-clock-parents = <0>, <0>, <0>;
>> 64 assigned-clock-rates = <294912000>,
>> 65 <270950400>,
>> 66 <393216000>;
>> 67 status = "okay";
>> 68
>> 69 dai-link-0 {
>> 70 sound-dai = <&frddr_a>;
>> 71 };
>> 72
>> 73 dai-link-1 {
>> 74 sound-dai = <&frddr_b>;
>> 75 };
>> 76
>> 77 dai-link-2 {
>> 78 sound-dai = <&frddr_c>;
>> 79 };
>> 80
>> 81 /* 8ch hdmi interface */
>> 82 dai-link-3 {
>> 83 sound-dai = <&tdmif_a>;
>> 84 dai-format = "i2s";
>> 85 dai-tdm-slot-tx-mask-0 = <1 1>;
>> 86 dai-tdm-slot-tx-mask-1 = <1 1>;
>> 87 dai-tdm-slot-tx-mask-2 = <1 1>;
>> 88 dai-tdm-slot-tx-mask-3 = <1 1>;
>> 89 mclk-fs = <256>;
>> 90
>> 91 codec {
>> 92 sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
>> 93 };
>> 94 };
>> 95
>> 96 /* hdmi glue */
>> 97 dai-link-4 {
>> 98 sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
>> 99
>> 100 codec {
>> 101 sound-dai = <&hdmi_tx>;
>> 102 };
>> 103 };
>> 104 };
>> 105 };
>> 106
>> 107 &arb {
>> 108 status = "okay";
>> 109 };
>> 110
>> 111 &clkc_audio {
>> 112 status = "okay";
48 }; 113 };
49 114
50 &cpu0 { 115 &cpu0 {
51 cpu-supply = <&vddcpu_b>; 116 cpu-supply = <&vddcpu_b>;
52 operating-points-v2 = <&cpu_opp_table_ 117 operating-points-v2 = <&cpu_opp_table_0>;
53 clocks = <&clkc CLKID_CPU_CLK>; 118 clocks = <&clkc CLKID_CPU_CLK>;
54 clock-latency = <50000>; 119 clock-latency = <50000>;
55 }; 120 };
56 121
57 &cpu1 { 122 &cpu1 {
58 cpu-supply = <&vddcpu_b>; 123 cpu-supply = <&vddcpu_b>;
59 operating-points-v2 = <&cpu_opp_table_ 124 operating-points-v2 = <&cpu_opp_table_0>;
60 clocks = <&clkc CLKID_CPU_CLK>; 125 clocks = <&clkc CLKID_CPU_CLK>;
61 clock-latency = <50000>; 126 clock-latency = <50000>;
62 }; 127 };
63 128
64 &cpu100 { 129 &cpu100 {
65 cpu-supply = <&vddcpu_a>; 130 cpu-supply = <&vddcpu_a>;
66 operating-points-v2 = <&cpub_opp_table 131 operating-points-v2 = <&cpub_opp_table_1>;
67 clocks = <&clkc CLKID_CPUB_CLK>; 132 clocks = <&clkc CLKID_CPUB_CLK>;
68 clock-latency = <50000>; 133 clock-latency = <50000>;
69 }; 134 };
70 135
71 &cpu101 { 136 &cpu101 {
72 cpu-supply = <&vddcpu_a>; 137 cpu-supply = <&vddcpu_a>;
73 operating-points-v2 = <&cpub_opp_table 138 operating-points-v2 = <&cpub_opp_table_1>;
74 clocks = <&clkc CLKID_CPUB_CLK>; 139 clocks = <&clkc CLKID_CPUB_CLK>;
75 clock-latency = <50000>; 140 clock-latency = <50000>;
76 }; 141 };
77 142
78 &cpu102 { 143 &cpu102 {
79 cpu-supply = <&vddcpu_a>; 144 cpu-supply = <&vddcpu_a>;
80 operating-points-v2 = <&cpub_opp_table 145 operating-points-v2 = <&cpub_opp_table_1>;
81 clocks = <&clkc CLKID_CPUB_CLK>; 146 clocks = <&clkc CLKID_CPUB_CLK>;
82 clock-latency = <50000>; 147 clock-latency = <50000>;
83 }; 148 };
84 149
85 &cpu103 { 150 &cpu103 {
86 cpu-supply = <&vddcpu_a>; 151 cpu-supply = <&vddcpu_a>;
87 operating-points-v2 = <&cpub_opp_table 152 operating-points-v2 = <&cpub_opp_table_1>;
88 clocks = <&clkc CLKID_CPUB_CLK>; 153 clocks = <&clkc CLKID_CPUB_CLK>;
89 clock-latency = <50000>; 154 clock-latency = <50000>;
90 }; 155 };
91 156
>> 157 &frddr_a {
>> 158 status = "okay";
>> 159 };
>> 160
>> 161 &frddr_b {
>> 162 status = "okay";
>> 163 };
>> 164
>> 165 &frddr_c {
>> 166 status = "okay";
>> 167 };
>> 168
92 &pwm_ab { 169 &pwm_ab {
93 pinctrl-0 = <&pwm_a_e_pins>; 170 pinctrl-0 = <&pwm_a_e_pins>;
94 pinctrl-names = "default"; 171 pinctrl-names = "default";
95 clocks = <&xtal>; 172 clocks = <&xtal>;
96 clock-names = "clkin0"; 173 clock-names = "clkin0";
97 status = "okay"; 174 status = "okay";
98 }; 175 };
99 176
100 &pwm_AO_cd { 177 &pwm_AO_cd {
101 pinctrl-0 = <&pwm_ao_d_e_pins>; 178 pinctrl-0 = <&pwm_ao_d_e_pins>;
102 pinctrl-names = "default"; 179 pinctrl-names = "default";
103 clocks = <&xtal>; 180 clocks = <&xtal>;
104 clock-names = "clkin1"; 181 clock-names = "clkin1";
105 status = "okay"; 182 status = "okay";
106 }; 183 };
107 184
>> 185 &tdmif_a {
>> 186 status = "okay";
>> 187 };
>> 188
>> 189 &tdmout_a {
>> 190 status = "okay";
>> 191 };
>> 192
>> 193 &tohdmitx {
>> 194 status = "okay";
>> 195 };
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