1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 BayLibre, SAS 3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre. 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2019 Christian Hewitt <christi 5 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
6 */ 6 */
7 7
8 / { 8 / {
9 model = "Khadas VIM3"; 9 model = "Khadas VIM3";
10 10
11 vddcpu_a: regulator-vddcpu-a { 11 vddcpu_a: regulator-vddcpu-a {
12 /* 12 /*
13 * MP8756GD Regulator. 13 * MP8756GD Regulator.
14 */ 14 */
15 compatible = "pwm-regulator"; 15 compatible = "pwm-regulator";
16 16
17 regulator-name = "VDDCPU_A"; 17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690 18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <105 19 regulator-max-microvolt = <1050000>;
20 20
21 pwm-supply = <&dc_in>; 21 pwm-supply = <&dc_in>;
22 22
23 pwms = <&pwm_ab 0 1250 0>; 23 pwms = <&pwm_ab 0 1250 0>;
24 pwm-dutycycle-range = <100 0>; 24 pwm-dutycycle-range = <100 0>;
25 25
26 regulator-boot-on; 26 regulator-boot-on;
27 regulator-always-on; 27 regulator-always-on;
28 }; 28 };
29 29
30 vddcpu_b: regulator-vddcpu-b { 30 vddcpu_b: regulator-vddcpu-b {
31 /* 31 /*
32 * Silergy SY8030DEC Regulator 32 * Silergy SY8030DEC Regulator.
33 */ 33 */
34 compatible = "pwm-regulator"; 34 compatible = "pwm-regulator";
35 35
36 regulator-name = "VDDCPU_B"; 36 regulator-name = "VDDCPU_B";
37 regulator-min-microvolt = <690 37 regulator-min-microvolt = <690000>;
38 regulator-max-microvolt = <105 38 regulator-max-microvolt = <1050000>;
39 39
40 pwm-supply = <&vsys_3v3>; 40 pwm-supply = <&vsys_3v3>;
41 41
42 pwms = <&pwm_AO_cd 1 1250 0>; 42 pwms = <&pwm_AO_cd 1 1250 0>;
43 pwm-dutycycle-range = <100 0>; 43 pwm-dutycycle-range = <100 0>;
44 44
45 regulator-boot-on; 45 regulator-boot-on;
46 regulator-always-on; 46 regulator-always-on;
47 }; 47 };
48 }; 48 };
49 49
50 &cpu0 { 50 &cpu0 {
51 cpu-supply = <&vddcpu_b>; 51 cpu-supply = <&vddcpu_b>;
52 operating-points-v2 = <&cpu_opp_table_ 52 operating-points-v2 = <&cpu_opp_table_0>;
53 clocks = <&clkc CLKID_CPU_CLK>; 53 clocks = <&clkc CLKID_CPU_CLK>;
54 clock-latency = <50000>; 54 clock-latency = <50000>;
55 }; 55 };
56 56
57 &cpu1 { 57 &cpu1 {
58 cpu-supply = <&vddcpu_b>; 58 cpu-supply = <&vddcpu_b>;
59 operating-points-v2 = <&cpu_opp_table_ 59 operating-points-v2 = <&cpu_opp_table_0>;
60 clocks = <&clkc CLKID_CPU_CLK>; 60 clocks = <&clkc CLKID_CPU_CLK>;
61 clock-latency = <50000>; 61 clock-latency = <50000>;
62 }; 62 };
63 63
64 &cpu100 { 64 &cpu100 {
65 cpu-supply = <&vddcpu_a>; 65 cpu-supply = <&vddcpu_a>;
66 operating-points-v2 = <&cpub_opp_table 66 operating-points-v2 = <&cpub_opp_table_1>;
67 clocks = <&clkc CLKID_CPUB_CLK>; 67 clocks = <&clkc CLKID_CPUB_CLK>;
68 clock-latency = <50000>; 68 clock-latency = <50000>;
69 }; 69 };
70 70
71 &cpu101 { 71 &cpu101 {
72 cpu-supply = <&vddcpu_a>; 72 cpu-supply = <&vddcpu_a>;
73 operating-points-v2 = <&cpub_opp_table 73 operating-points-v2 = <&cpub_opp_table_1>;
74 clocks = <&clkc CLKID_CPUB_CLK>; 74 clocks = <&clkc CLKID_CPUB_CLK>;
75 clock-latency = <50000>; 75 clock-latency = <50000>;
76 }; 76 };
77 77
78 &cpu102 { 78 &cpu102 {
79 cpu-supply = <&vddcpu_a>; 79 cpu-supply = <&vddcpu_a>;
80 operating-points-v2 = <&cpub_opp_table 80 operating-points-v2 = <&cpub_opp_table_1>;
81 clocks = <&clkc CLKID_CPUB_CLK>; 81 clocks = <&clkc CLKID_CPUB_CLK>;
82 clock-latency = <50000>; 82 clock-latency = <50000>;
83 }; 83 };
84 84
85 &cpu103 { 85 &cpu103 {
86 cpu-supply = <&vddcpu_a>; 86 cpu-supply = <&vddcpu_a>;
87 operating-points-v2 = <&cpub_opp_table 87 operating-points-v2 = <&cpub_opp_table_1>;
88 clocks = <&clkc CLKID_CPUB_CLK>; 88 clocks = <&clkc CLKID_CPUB_CLK>;
89 clock-latency = <50000>; 89 clock-latency = <50000>;
90 }; 90 };
91 91
92 &pwm_ab { 92 &pwm_ab {
93 pinctrl-0 = <&pwm_a_e_pins>; 93 pinctrl-0 = <&pwm_a_e_pins>;
94 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 clocks = <&xtal>; 95 clocks = <&xtal>;
96 clock-names = "clkin0"; 96 clock-names = "clkin0";
97 status = "okay"; 97 status = "okay";
98 }; 98 };
99 99
100 &pwm_AO_cd { 100 &pwm_AO_cd {
101 pinctrl-0 = <&pwm_ao_d_e_pins>; 101 pinctrl-0 = <&pwm_ao_d_e_pins>;
102 pinctrl-names = "default"; 102 pinctrl-names = "default";
103 clocks = <&xtal>; 103 clocks = <&xtal>;
104 clock-names = "clkin1"; 104 clock-names = "clkin1";
105 status = "okay"; 105 status = "okay";
106 }; 106 };
107 107
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