1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 BayLibre, SAS 3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre. 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2019 Christian Hewitt <christi 5 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "meson-g12b-s922x.dtsi" 10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi" 11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi" 12 #include "meson-g12b-khadas-vim3.dtsi"
13 13
14 / { 14 / {
15 compatible = "khadas,vim3", "amlogic,s 15 compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b";
16 }; 16 };
17 <<
18 /* <<
19 * The VIM3 on-board MCU can mux the PCIe/USB <<
20 * lines using a FUSB340TMX USB 3.1 SuperSpeed <<
21 * an USB3.0 Type A connector and a M.2 Key M <<
22 * The PHY driving these differential lines is <<
23 * the USB3.0 controller and the PCIe Controll <<
24 * a single controller can use it. <<
25 * If the MCU is configured to mux the PCIe/US <<
26 * to the M.2 Key M slot, uncomment the follow <<
27 * USB3.0 from the USB Complex and enable the <<
28 * The End User is not expected to uncomment t <<
29 * testing purposes, but instead rely on the f <<
30 * update these nodes accordingly if PCIe mode <<
31 */ <<
32 /* <<
33 &pcie { <<
34 status = "okay"; <<
35 }; <<
36 <<
37 &usb { <<
38 phys = <&usb2_phy0>, <&usb2_phy1>; <<
39 phy-names = "usb2-phy0", "usb2-phy1"; <<
40 }; <<
41 */ <<
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