1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Copyright (c) 2017 BayLibre SAS 2 * Copyright (c) 2017 BayLibre SAS
4 * Author: Neil Armstrong <narmstrong@baylibre. 3 * Author: Neil Armstrong <narmstrong@baylibre.com>
>> 4 *
>> 5 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */ 6 */
6 7
7 #include "meson-gx-mali450.dtsi" !! 8 &apb {
>> 9 mali: gpu@c0000 {
>> 10 compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
>> 11 reg = <0x0 0xc0000 0x0 0x40000>;
>> 12 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
>> 13 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
>> 14 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
>> 15 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
>> 16 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>> 17 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
>> 18 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
>> 19 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
>> 20 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
>> 21 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
>> 22 interrupt-names = "gp", "gpmmu", "pp", "pmu",
>> 23 "pp0", "ppmmu0", "pp1", "ppmmu1",
>> 24 "pp2", "ppmmu2";
>> 25 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
>> 26 clock-names = "bus", "core";
8 27
9 &mali { !! 28 /*
10 compatible = "amlogic,meson-gxl-mali", !! 29 * Mali clocking is provided by two identical clock paths
11 !! 30 * MALI_0 and MALI_1 muxed to a single clock by a glitch
12 clocks = <&clkc CLKID_CLK81>, <&clkc C !! 31 * free mux to safely change frequency while running.
13 clock-names = "bus", "core"; !! 32 */
14 !! 33 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
15 assigned-clocks = <&clkc CLKID_GP0_PLL !! 34 <&clkc CLKID_MALI_0>,
16 assigned-clock-rates = <744000000>; !! 35 <&clkc CLKID_MALI>; /* Glitch free mux */
>> 36 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
>> 37 <0>, /* Do Nothing */
>> 38 <&clkc CLKID_MALI_0>;
>> 39 assigned-clock-rates = <0>, /* Do Nothing */
>> 40 <666666666>,
>> 41 <0>; /* Do Nothing */
>> 42 };
17 }; 43 };
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