1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Common Apple T6000 / T6001 / T6002 "M1 Pro/
4 *
5 * Other names: H13J, "Jade Chop", "Jade", "Ja
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10 / {
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu-map {
19 cluster0 {
20 core0 {
21 cpu =
22 };
23 core1 {
24 cpu =
25 };
26 };
27
28 cluster1 {
29 core0 {
30 cpu =
31 };
32 core1 {
33 cpu =
34 };
35 core2 {
36 cpu =
37 };
38 core3 {
39 cpu =
40 };
41 };
42
43 cluster2 {
44 core0 {
45 cpu =
46 };
47 core1 {
48 cpu =
49 };
50 core2 {
51 cpu =
52 };
53 core3 {
54 cpu =
55 };
56 };
57 };
58
59 cpu_e00: cpu@0 {
60 compatible = "apple,ic
61 device_type = "cpu";
62 reg = <0x0 0x0>;
63 enable-method = "spin-
64 cpu-release-addr = <0
65 next-level-cache = <&l
66 i-cache-size = <0x2000
67 d-cache-size = <0x1000
68 operating-points-v2 =
69 capacity-dmips-mhz = <
70 performance-domains =
71 };
72
73 cpu_e01: cpu@1 {
74 compatible = "apple,ic
75 device_type = "cpu";
76 reg = <0x0 0x1>;
77 enable-method = "spin-
78 cpu-release-addr = <0
79 next-level-cache = <&l
80 i-cache-size = <0x2000
81 d-cache-size = <0x1000
82 operating-points-v2 =
83 capacity-dmips-mhz = <
84 performance-domains =
85 };
86
87 cpu_p00: cpu@10100 {
88 compatible = "apple,fi
89 device_type = "cpu";
90 reg = <0x0 0x10100>;
91 enable-method = "spin-
92 cpu-release-addr = <0
93 next-level-cache = <&l
94 i-cache-size = <0x3000
95 d-cache-size = <0x2000
96 operating-points-v2 =
97 capacity-dmips-mhz = <
98 performance-domains =
99 };
100
101 cpu_p01: cpu@10101 {
102 compatible = "apple,fi
103 device_type = "cpu";
104 reg = <0x0 0x10101>;
105 enable-method = "spin-
106 cpu-release-addr = <0
107 next-level-cache = <&l
108 i-cache-size = <0x3000
109 d-cache-size = <0x2000
110 operating-points-v2 =
111 capacity-dmips-mhz = <
112 performance-domains =
113 };
114
115 cpu_p02: cpu@10102 {
116 compatible = "apple,fi
117 device_type = "cpu";
118 reg = <0x0 0x10102>;
119 enable-method = "spin-
120 cpu-release-addr = <0
121 next-level-cache = <&l
122 i-cache-size = <0x3000
123 d-cache-size = <0x2000
124 operating-points-v2 =
125 capacity-dmips-mhz = <
126 performance-domains =
127 };
128
129 cpu_p03: cpu@10103 {
130 compatible = "apple,fi
131 device_type = "cpu";
132 reg = <0x0 0x10103>;
133 enable-method = "spin-
134 cpu-release-addr = <0
135 next-level-cache = <&l
136 i-cache-size = <0x3000
137 d-cache-size = <0x2000
138 operating-points-v2 =
139 capacity-dmips-mhz = <
140 performance-domains =
141 };
142
143 cpu_p10: cpu@10200 {
144 compatible = "apple,fi
145 device_type = "cpu";
146 reg = <0x0 0x10200>;
147 enable-method = "spin-
148 cpu-release-addr = <0
149 next-level-cache = <&l
150 i-cache-size = <0x3000
151 d-cache-size = <0x2000
152 operating-points-v2 =
153 capacity-dmips-mhz = <
154 performance-domains =
155 };
156
157 cpu_p11: cpu@10201 {
158 compatible = "apple,fi
159 device_type = "cpu";
160 reg = <0x0 0x10201>;
161 enable-method = "spin-
162 cpu-release-addr = <0
163 next-level-cache = <&l
164 i-cache-size = <0x3000
165 d-cache-size = <0x2000
166 operating-points-v2 =
167 capacity-dmips-mhz = <
168 performance-domains =
169 };
170
171 cpu_p12: cpu@10202 {
172 compatible = "apple,fi
173 device_type = "cpu";
174 reg = <0x0 0x10202>;
175 enable-method = "spin-
176 cpu-release-addr = <0
177 next-level-cache = <&l
178 i-cache-size = <0x3000
179 d-cache-size = <0x2000
180 operating-points-v2 =
181 capacity-dmips-mhz = <
182 performance-domains =
183 };
184
185 cpu_p13: cpu@10203 {
186 compatible = "apple,fi
187 device_type = "cpu";
188 reg = <0x0 0x10203>;
189 enable-method = "spin-
190 cpu-release-addr = <0
191 next-level-cache = <&l
192 i-cache-size = <0x3000
193 d-cache-size = <0x2000
194 operating-points-v2 =
195 capacity-dmips-mhz = <
196 performance-domains =
197 };
198
199 l2_cache_0: l2-cache-0 {
200 compatible = "cache";
201 cache-level = <2>;
202 cache-unified;
203 cache-size = <0x400000
204 };
205
206 l2_cache_1: l2-cache-1 {
207 compatible = "cache";
208 cache-level = <2>;
209 cache-unified;
210 cache-size = <0xc00000
211 };
212
213 l2_cache_2: l2-cache-2 {
214 compatible = "cache";
215 cache-level = <2>;
216 cache-unified;
217 cache-size = <0xc00000
218 };
219 };
220
221 icestorm_opp: opp-table-0 {
222 compatible = "operating-points
223
224 opp01 {
225 opp-hz = /bits/ 64 <60
226 opp-level = <1>;
227 clock-latency-ns = <75
228 };
229 opp02 {
230 opp-hz = /bits/ 64 <97
231 opp-level = <2>;
232 clock-latency-ns = <23
233 };
234 opp03 {
235 opp-hz = /bits/ 64 <13
236 opp-level = <3>;
237 clock-latency-ns = <29
238 };
239 opp04 {
240 opp-hz = /bits/ 64 <17
241 opp-level = <4>;
242 clock-latency-ns = <40
243 };
244 opp05 {
245 opp-hz = /bits/ 64 <20
246 opp-level = <5>;
247 clock-latency-ns = <50
248 };
249 };
250
251 firestorm_opp: opp-table-1 {
252 compatible = "operating-points
253
254 opp01 {
255 opp-hz = /bits/ 64 <60
256 opp-level = <1>;
257 clock-latency-ns = <80
258 };
259 opp02 {
260 opp-hz = /bits/ 64 <82
261 opp-level = <2>;
262 clock-latency-ns = <18
263 };
264 opp03 {
265 opp-hz = /bits/ 64 <10
266 opp-level = <3>;
267 clock-latency-ns = <19
268 };
269 opp04 {
270 opp-hz = /bits/ 64 <12
271 opp-level = <4>;
272 clock-latency-ns = <23
273 };
274 opp05 {
275 opp-hz = /bits/ 64 <15
276 opp-level = <5>;
277 clock-latency-ns = <24
278 };
279 opp06 {
280 opp-hz = /bits/ 64 <17
281 opp-level = <6>;
282 clock-latency-ns = <28
283 };
284 opp07 {
285 opp-hz = /bits/ 64 <19
286 opp-level = <7>;
287 clock-latency-ns = <31
288 };
289 opp08 {
290 opp-hz = /bits/ 64 <22
291 opp-level = <8>;
292 clock-latency-ns = <45
293 };
294 opp09 {
295 opp-hz = /bits/ 64 <24
296 opp-level = <9>;
297 clock-latency-ns = <49
298 };
299 opp10 {
300 opp-hz = /bits/ 64 <26
301 opp-level = <10>;
302 clock-latency-ns = <53
303 };
304 opp11 {
305 opp-hz = /bits/ 64 <29
306 opp-level = <11>;
307 clock-latency-ns = <56
308 };
309 opp12 {
310 opp-hz = /bits/ 64 <30
311 opp-level = <12>;
312 clock-latency-ns = <56
313 };
314 /* Not available until CPU dee
315 opp13 {
316 opp-hz = /bits/ 64 <31
317 opp-level = <13>;
318 clock-latency-ns = <56
319 turbo-mode;
320 };
321 opp14 {
322 opp-hz = /bits/ 64 <31
323 opp-level = <14>;
324 clock-latency-ns = <56
325 turbo-mode;
326 };
327 opp15 {
328 opp-hz = /bits/ 64 <32
329 opp-level = <15>;
330 clock-latency-ns = <56
331 turbo-mode;
332 };
333 */
334 };
335
336 pmu-e {
337 compatible = "apple,icestorm-p
338 interrupt-parent = <&aic>;
339 interrupts = <AIC_FIQ 0 AIC_CP
340 };
341
342 pmu-p {
343 compatible = "apple,firestorm-
344 interrupt-parent = <&aic>;
345 interrupts = <AIC_FIQ 0 AIC_CP
346 };
347
348 timer {
349 compatible = "arm,armv8-timer"
350 interrupt-parent = <&aic>;
351 interrupt-names = "phys", "vir
352 interrupts = <AIC_FIQ 0 AIC_TM
353 <AIC_FIQ 0 AIC_TM
354 <AIC_FIQ 0 AIC_TM
355 <AIC_FIQ 0 AIC_TM
356 };
357
358 clkref: clock-ref {
359 compatible = "fixed-clock";
360 #clock-cells = <0>;
361 clock-frequency = <24000000>;
362 clock-output-names = "clkref";
363 };
364
365 /*
366 * This is a fabulated representation
367 * to NCO since we don't know the true
368 */
369 nco_clkref: clock-ref-nco {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 clock-output-names = "nco_ref"
373 };
374 };
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