1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi" 2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi" <<
4 3
5 / { 4 / {
6 /* 5 /*
7 * Devices shared by all Juno boards 6 * Devices shared by all Juno boards
8 */ 7 */
>> 8 dma-ranges = <0 0 0 0 0x100 0>;
9 9
10 memtimer: timer@2a810000 { 10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer- 11 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10 12 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>; 13 clock-frequency = <50000000>;
14 #address-cells = <1>; !! 14 #address-cells = <2>;
15 #size-cells = <1>; !! 15 #size-cells = <2>;
16 ranges = <0 0x0 0x2a820000 0x2 !! 16 ranges;
17 status = "disabled"; 17 status = "disabled";
18 frame@2a830000 { 18 frame@2a830000 {
19 frame-number = <1>; 19 frame-number = <1>;
20 interrupts = <GIC_SPI !! 20 interrupts = <0 60 4>;
21 reg = <0x10000 0x10000 !! 21 reg = <0x0 0x2a830000 0x0 0x10000>;
22 }; 22 };
23 }; 23 };
24 24
25 mailbox: mhu@2b1f0000 { 25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p 26 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x10 27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_T 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_T !! 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 <GIC_SPI 37 IRQ_T !! 30 interrupt-names = "mhu_lpri_rx",
>> 31 "mhu_hpri_rx";
31 #mbox-cells = <1>; 32 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>; 33 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk"; 34 clock-names = "apb_pclk";
34 }; 35 };
35 36
36 smmu_gpu: iommu@2b400000 { <<
37 compatible = "arm,mmu-400", "a <<
38 reg = <0x0 0x2b400000 0x0 0x10 <<
39 interrupts = <GIC_SPI 38 IRQ_T <<
40 <GIC_SPI 38 IRQ_T <<
41 #iommu-cells = <1>; <<
42 #global-interrupts = <1>; <<
43 power-domains = <&scpi_devpd 1 <<
44 dma-coherent; <<
45 status = "disabled"; <<
46 }; <<
47 <<
48 smmu_pcie: iommu@2b500000 { 37 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a 38 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b500000 0x0 0x10 39 reg = <0x0 0x2b500000 0x0 0x10000>;
51 interrupts = <GIC_SPI 40 IRQ_T 40 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 40 IRQ_T 41 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
53 #iommu-cells = <1>; 42 #iommu-cells = <1>;
54 #global-interrupts = <1>; 43 #global-interrupts = <1>;
55 dma-coherent; 44 dma-coherent;
56 status = "disabled"; 45 status = "disabled";
57 }; 46 };
58 47
59 smmu_etr: iommu@2b600000 { 48 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a 49 compatible = "arm,mmu-401", "arm,smmu-v1";
61 reg = <0x0 0x2b600000 0x0 0x10 50 reg = <0x0 0x2b600000 0x0 0x10000>;
62 interrupts = <GIC_SPI 42 IRQ_T 51 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 42 IRQ_T 52 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
64 #iommu-cells = <1>; 53 #iommu-cells = <1>;
65 #global-interrupts = <1>; 54 #global-interrupts = <1>;
66 dma-coherent; 55 dma-coherent;
67 power-domains = <&scpi_devpd 0 56 power-domains = <&scpi_devpd 0>;
68 }; 57 };
69 58
70 gic: interrupt-controller@2c010000 { 59 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a 60 compatible = "arm,gic-400", "arm,cortex-a15-gic";
72 reg = <0x0 0x2c010000 0 0x1000 61 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000 62 <0x0 0x2c02f000 0 0x2000>,
74 <0x0 0x2c04f000 0 0x2000 63 <0x0 0x2c04f000 0 0x2000>,
75 <0x0 0x2c06f000 0 0x2000 64 <0x0 0x2c06f000 0 0x2000>;
76 #address-cells = <1>; !! 65 #address-cells = <2>;
77 #interrupt-cells = <3>; 66 #interrupt-cells = <3>;
78 #size-cells = <1>; !! 67 #size-cells = <2>;
79 interrupt-controller; 68 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C 69 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
81 ranges = <0 0 0x2c1c0000 0x400 !! 70 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
82 <<
83 v2m_0: v2m@0 { 71 v2m_0: v2m@0 {
84 compatible = "arm,gic- 72 compatible = "arm,gic-v2m-frame";
85 msi-controller; 73 msi-controller;
86 reg = <0 0x10000>; !! 74 reg = <0 0 0 0x1000>;
87 }; <<
88 <<
89 v2m@10000 { <<
90 compatible = "arm,gic- <<
91 msi-controller; <<
92 reg = <0x10000 0x10000 <<
93 }; <<
94 <<
95 v2m@20000 { <<
96 compatible = "arm,gic- <<
97 msi-controller; <<
98 reg = <0x20000 0x10000 <<
99 }; <<
100 <<
101 v2m@30000 { <<
102 compatible = "arm,gic- <<
103 msi-controller; <<
104 reg = <0x30000 0x10000 <<
105 }; 75 };
106 }; 76 };
107 77
108 timer { 78 timer {
109 compatible = "arm,armv8-timer" 79 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_ 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_ 81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_ 82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_ 83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
114 }; 84 };
115 85
116 /* 86 /*
117 * Juno TRMs specify the size for thes 87 * Juno TRMs specify the size for these coresight components as 64K.
118 * The actual size is just 4K though 6 88 * The actual size is just 4K though 64K is reserved. Access to the
119 * unmapped reserved region results in 89 * unmapped reserved region results in a DECERR response.
120 */ 90 */
121 etf_sys0: etf@20010000 { /* etf0 */ !! 91 etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm 92 compatible = "arm,coresight-tmc", "arm,primecell";
123 reg = <0 0x20010000 0 0x1000>; 93 reg = <0 0x20010000 0 0x1000>;
124 94
125 clocks = <&soc_smc50mhz>; 95 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk"; 96 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0 97 power-domains = <&scpi_devpd 0>;
>> 98 ports {
>> 99 #address-cells = <1>;
>> 100 #size-cells = <0>;
128 101
129 in-ports { !! 102 /* input port */
130 port { !! 103 port@0 {
>> 104 reg = <0>;
131 etf0_in_port: 105 etf0_in_port: endpoint {
>> 106 slave-mode;
132 remote 107 remote-endpoint = <&main_funnel_out_port>;
133 }; 108 };
134 }; 109 };
135 }; <<
136 110
137 out-ports { !! 111 /* output port */
138 port { !! 112 port@1 {
>> 113 reg = <0>;
139 etf0_out_port: 114 etf0_out_port: endpoint {
140 }; 115 };
141 }; 116 };
142 }; 117 };
143 }; 118 };
144 119
145 tpiu_sys: tpiu@20030000 { !! 120 tpiu@20030000 {
146 compatible = "arm,coresight-tp 121 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0 0x20030000 0 0x1000>; 122 reg = <0 0x20030000 0 0x1000>;
148 123
149 clocks = <&soc_smc50mhz>; 124 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk"; 125 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0 126 power-domains = <&scpi_devpd 0>;
152 in-ports { !! 127 port {
153 port { !! 128 tpiu_in_port: endpoint {
154 tpiu_in_port: !! 129 slave-mode;
155 remote !! 130 remote-endpoint = <&replicator_out_port0>;
156 }; <<
157 }; 131 };
158 }; 132 };
159 }; 133 };
160 134
161 /* main funnel on Juno r0, cssys0 funn 135 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
162 main_funnel: funnel@20040000 { 136 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy !! 137 compatible = "arm,coresight-funnel", "arm,primecell";
164 reg = <0 0x20040000 0 0x1000>; 138 reg = <0 0x20040000 0 0x1000>;
165 139
166 clocks = <&soc_smc50mhz>; 140 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk"; 141 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0 142 power-domains = <&scpi_devpd 0>;
>> 143 ports {
>> 144 #address-cells = <1>;
>> 145 #size-cells = <0>;
169 146
170 out-ports { !! 147 /* output port */
171 port { !! 148 port@0 {
>> 149 reg = <0>;
172 main_funnel_ou 150 main_funnel_out_port: endpoint {
173 remote 151 remote-endpoint = <&etf0_in_port>;
174 }; 152 };
175 }; 153 };
176 }; <<
177 154
178 main_funnel_in_ports: in-ports !! 155 /* input ports */
179 #address-cells = <1>; !! 156 port@1 {
180 #size-cells = <0>; <<
181 <<
182 port@0 { <<
183 reg = <0>; 157 reg = <0>;
184 main_funnel_in 158 main_funnel_in_port0: endpoint {
>> 159 slave-mode;
185 remote 160 remote-endpoint = <&cluster0_funnel_out_port>;
186 }; 161 };
187 }; 162 };
188 163
189 port@1 { !! 164 port@2 {
190 reg = <1>; 165 reg = <1>;
191 main_funnel_in 166 main_funnel_in_port1: endpoint {
>> 167 slave-mode;
192 remote 168 remote-endpoint = <&cluster1_funnel_out_port>;
193 }; 169 };
194 }; 170 };
195 }; 171 };
196 }; 172 };
197 173
198 etr_sys: etr@20070000 { !! 174 etr@20070000 {
199 compatible = "arm,coresight-tm 175 compatible = "arm,coresight-tmc", "arm,primecell";
200 reg = <0 0x20070000 0 0x1000>; 176 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>; 177 iommus = <&smmu_etr 0>;
202 178
203 clocks = <&soc_smc50mhz>; 179 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk"; 180 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0 181 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather; !! 182 port {
207 in-ports { !! 183 etr_in_port: endpoint {
208 port { !! 184 slave-mode;
209 etr_in_port: e !! 185 remote-endpoint = <&replicator_out_port1>;
210 remote <<
211 }; <<
212 }; 186 };
213 }; 187 };
214 }; 188 };
215 189
216 stm_sys: stm@20100000 { !! 190 stm@20100000 {
217 compatible = "arm,coresight-st 191 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>, 192 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000 193 <0 0x28000000 0 0x1000000>;
220 reg-names = "stm-base", "stm-s 194 reg-names = "stm-base", "stm-stimulus-base";
221 195
222 clocks = <&soc_smc50mhz>; 196 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk"; 197 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0 198 power-domains = <&scpi_devpd 0>;
225 out-ports { !! 199 port {
226 port { !! 200 stm_out_port: endpoint {
227 stm_out_port: <<
228 }; <<
229 }; <<
230 }; <<
231 }; <<
232 <<
233 replicator@20120000 { <<
234 compatible = "arm,coresight-dy <<
235 reg = <0 0x20120000 0 0x1000>; <<
236 <<
237 clocks = <&soc_smc50mhz>; <<
238 clock-names = "apb_pclk"; <<
239 power-domains = <&scpi_devpd 0 <<
240 <<
241 out-ports { <<
242 #address-cells = <1>; <<
243 #size-cells = <0>; <<
244 <<
245 /* replicator output p <<
246 port@0 { <<
247 reg = <0>; <<
248 replicator_out <<
249 remote <<
250 }; <<
251 }; <<
252 <<
253 port@1 { <<
254 reg = <1>; <<
255 replicator_out <<
256 remote <<
257 }; <<
258 }; <<
259 }; <<
260 in-ports { <<
261 port { <<
262 replicator_in_ <<
263 }; <<
264 }; 201 };
265 }; 202 };
266 }; 203 };
267 204
268 cpu_debug0: cpu-debug@22010000 { 205 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp 206 compatible = "arm,coresight-cpu-debug", "arm,primecell";
270 reg = <0x0 0x22010000 0x0 0x10 207 reg = <0x0 0x22010000 0x0 0x1000>;
271 208
272 clocks = <&soc_smc50mhz>; 209 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk"; 210 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0 211 power-domains = <&scpi_devpd 0>;
275 }; 212 };
276 213
277 etm0: etm@22040000 { 214 etm0: etm@22040000 {
278 compatible = "arm,coresight-et 215 compatible = "arm,coresight-etm4x", "arm,primecell";
279 reg = <0 0x22040000 0 0x1000>; 216 reg = <0 0x22040000 0 0x1000>;
280 217
281 clocks = <&soc_smc50mhz>; 218 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk"; 219 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0 220 power-domains = <&scpi_devpd 0>;
284 out-ports { !! 221 port {
285 port { !! 222 cluster0_etm0_out_port: endpoint {
286 cluster0_etm0_ !! 223 remote-endpoint = <&cluster0_funnel_in_port0>;
287 remote <<
288 }; <<
289 }; 224 };
290 }; 225 };
291 }; 226 };
292 227
293 cti0: cti@22020000 { <<
294 compatible = "arm,coresight-ct <<
295 "arm,primecell"; <<
296 reg = <0 0x22020000 0 0x1000>; <<
297 <<
298 clocks = <&soc_smc50mhz>; <<
299 clock-names = "apb_pclk"; <<
300 power-domains = <&scpi_devpd 0 <<
301 <<
302 arm,cs-dev-assoc = <&etm0>; <<
303 }; <<
304 <<
305 funnel@220c0000 { /* cluster0 funnel * 228 funnel@220c0000 { /* cluster0 funnel */
306 compatible = "arm,coresight-dy !! 229 compatible = "arm,coresight-funnel", "arm,primecell";
307 reg = <0 0x220c0000 0 0x1000>; 230 reg = <0 0x220c0000 0 0x1000>;
308 231
309 clocks = <&soc_smc50mhz>; 232 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk"; 233 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0 234 power-domains = <&scpi_devpd 0>;
312 out-ports { !! 235 ports {
313 port { !! 236 #address-cells = <1>;
>> 237 #size-cells = <0>;
>> 238
>> 239 port@0 {
>> 240 reg = <0>;
314 cluster0_funne 241 cluster0_funnel_out_port: endpoint {
315 remote 242 remote-endpoint = <&main_funnel_in_port0>;
316 }; 243 };
317 }; 244 };
318 }; <<
319 245
320 in-ports { !! 246 port@1 {
321 #address-cells = <1>; <<
322 #size-cells = <0>; <<
323 <<
324 port@0 { <<
325 reg = <0>; 247 reg = <0>;
326 cluster0_funne 248 cluster0_funnel_in_port0: endpoint {
>> 249 slave-mode;
327 remote 250 remote-endpoint = <&cluster0_etm0_out_port>;
328 }; 251 };
329 }; 252 };
330 253
331 port@1 { !! 254 port@2 {
332 reg = <1>; 255 reg = <1>;
333 cluster0_funne 256 cluster0_funnel_in_port1: endpoint {
>> 257 slave-mode;
334 remote 258 remote-endpoint = <&cluster0_etm1_out_port>;
335 }; 259 };
336 }; 260 };
337 }; 261 };
338 }; 262 };
339 263
340 cpu_debug1: cpu-debug@22110000 { 264 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp 265 compatible = "arm,coresight-cpu-debug", "arm,primecell";
342 reg = <0x0 0x22110000 0x0 0x10 266 reg = <0x0 0x22110000 0x0 0x1000>;
343 267
344 clocks = <&soc_smc50mhz>; 268 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk"; 269 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0 270 power-domains = <&scpi_devpd 0>;
347 }; 271 };
348 272
349 etm1: etm@22140000 { 273 etm1: etm@22140000 {
350 compatible = "arm,coresight-et 274 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0x22140000 0 0x1000>; 275 reg = <0 0x22140000 0 0x1000>;
352 276
353 clocks = <&soc_smc50mhz>; 277 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk"; 278 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0 279 power-domains = <&scpi_devpd 0>;
356 out-ports { !! 280 port {
357 port { !! 281 cluster0_etm1_out_port: endpoint {
358 cluster0_etm1_ !! 282 remote-endpoint = <&cluster0_funnel_in_port1>;
359 remote <<
360 }; <<
361 }; 283 };
362 }; 284 };
363 }; 285 };
364 286
365 cti1: cti@22120000 { <<
366 compatible = "arm,coresight-ct <<
367 "arm,primecell"; <<
368 reg = <0 0x22120000 0 0x1000>; <<
369 <<
370 clocks = <&soc_smc50mhz>; <<
371 clock-names = "apb_pclk"; <<
372 power-domains = <&scpi_devpd 0 <<
373 <<
374 arm,cs-dev-assoc = <&etm1>; <<
375 }; <<
376 <<
377 cpu_debug2: cpu-debug@23010000 { 287 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp 288 compatible = "arm,coresight-cpu-debug", "arm,primecell";
379 reg = <0x0 0x23010000 0x0 0x10 289 reg = <0x0 0x23010000 0x0 0x1000>;
380 290
381 clocks = <&soc_smc50mhz>; 291 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk"; 292 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0 293 power-domains = <&scpi_devpd 0>;
384 }; 294 };
385 295
386 etm2: etm@23040000 { 296 etm2: etm@23040000 {
387 compatible = "arm,coresight-et 297 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0 0x23040000 0 0x1000>; 298 reg = <0 0x23040000 0 0x1000>;
389 299
390 clocks = <&soc_smc50mhz>; 300 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk"; 301 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0 302 power-domains = <&scpi_devpd 0>;
393 out-ports { !! 303 port {
394 port { !! 304 cluster1_etm0_out_port: endpoint {
395 cluster1_etm0_ !! 305 remote-endpoint = <&cluster1_funnel_in_port0>;
396 remote <<
397 }; <<
398 }; 306 };
399 }; 307 };
400 }; 308 };
401 309
402 cti2: cti@23020000 { <<
403 compatible = "arm,coresight-ct <<
404 "arm,primecell"; <<
405 reg = <0 0x23020000 0 0x1000>; <<
406 <<
407 clocks = <&soc_smc50mhz>; <<
408 clock-names = "apb_pclk"; <<
409 power-domains = <&scpi_devpd 0 <<
410 <<
411 arm,cs-dev-assoc = <&etm2>; <<
412 }; <<
413 <<
414 funnel@230c0000 { /* cluster1 funnel * 310 funnel@230c0000 { /* cluster1 funnel */
415 compatible = "arm,coresight-dy !! 311 compatible = "arm,coresight-funnel", "arm,primecell";
416 reg = <0 0x230c0000 0 0x1000>; 312 reg = <0 0x230c0000 0 0x1000>;
417 313
418 clocks = <&soc_smc50mhz>; 314 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk"; 315 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0 316 power-domains = <&scpi_devpd 0>;
421 out-ports { !! 317 ports {
422 port { !! 318 #address-cells = <1>;
>> 319 #size-cells = <0>;
>> 320
>> 321 port@0 {
>> 322 reg = <0>;
423 cluster1_funne 323 cluster1_funnel_out_port: endpoint {
424 remote 324 remote-endpoint = <&main_funnel_in_port1>;
425 }; 325 };
426 }; 326 };
427 }; <<
428 327
429 in-ports { !! 328 port@1 {
430 #address-cells = <1>; <<
431 #size-cells = <0>; <<
432 <<
433 port@0 { <<
434 reg = <0>; 329 reg = <0>;
435 cluster1_funne 330 cluster1_funnel_in_port0: endpoint {
>> 331 slave-mode;
436 remote 332 remote-endpoint = <&cluster1_etm0_out_port>;
437 }; 333 };
438 }; 334 };
439 335
440 port@1 { !! 336 port@2 {
441 reg = <1>; 337 reg = <1>;
442 cluster1_funne 338 cluster1_funnel_in_port1: endpoint {
>> 339 slave-mode;
443 remote 340 remote-endpoint = <&cluster1_etm1_out_port>;
444 }; 341 };
445 }; 342 };
446 port@2 { !! 343 port@3 {
447 reg = <2>; 344 reg = <2>;
448 cluster1_funne 345 cluster1_funnel_in_port2: endpoint {
>> 346 slave-mode;
449 remote 347 remote-endpoint = <&cluster1_etm2_out_port>;
450 }; 348 };
451 }; 349 };
452 port@3 { !! 350 port@4 {
453 reg = <3>; 351 reg = <3>;
454 cluster1_funne 352 cluster1_funnel_in_port3: endpoint {
>> 353 slave-mode;
455 remote 354 remote-endpoint = <&cluster1_etm3_out_port>;
456 }; 355 };
457 }; 356 };
458 }; 357 };
459 }; 358 };
460 359
461 cpu_debug3: cpu-debug@23110000 { 360 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp 361 compatible = "arm,coresight-cpu-debug", "arm,primecell";
463 reg = <0x0 0x23110000 0x0 0x10 362 reg = <0x0 0x23110000 0x0 0x1000>;
464 363
465 clocks = <&soc_smc50mhz>; 364 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk"; 365 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0 366 power-domains = <&scpi_devpd 0>;
468 }; 367 };
469 368
470 etm3: etm@23140000 { 369 etm3: etm@23140000 {
471 compatible = "arm,coresight-et 370 compatible = "arm,coresight-etm4x", "arm,primecell";
472 reg = <0 0x23140000 0 0x1000>; 371 reg = <0 0x23140000 0 0x1000>;
473 372
474 clocks = <&soc_smc50mhz>; 373 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk"; 374 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0 375 power-domains = <&scpi_devpd 0>;
477 out-ports { !! 376 port {
478 port { !! 377 cluster1_etm1_out_port: endpoint {
479 cluster1_etm1_ !! 378 remote-endpoint = <&cluster1_funnel_in_port1>;
480 remote <<
481 }; <<
482 }; 379 };
483 }; 380 };
484 }; 381 };
485 382
486 cti3: cti@23120000 { <<
487 compatible = "arm,coresight-ct <<
488 "arm,primecell"; <<
489 reg = <0 0x23120000 0 0x1000>; <<
490 <<
491 clocks = <&soc_smc50mhz>; <<
492 clock-names = "apb_pclk"; <<
493 power-domains = <&scpi_devpd 0 <<
494 <<
495 arm,cs-dev-assoc = <&etm3>; <<
496 }; <<
497 <<
498 cpu_debug4: cpu-debug@23210000 { 383 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp 384 compatible = "arm,coresight-cpu-debug", "arm,primecell";
500 reg = <0x0 0x23210000 0x0 0x10 385 reg = <0x0 0x23210000 0x0 0x1000>;
501 386
502 clocks = <&soc_smc50mhz>; 387 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk"; 388 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0 389 power-domains = <&scpi_devpd 0>;
505 }; 390 };
506 391
507 etm4: etm@23240000 { 392 etm4: etm@23240000 {
508 compatible = "arm,coresight-et 393 compatible = "arm,coresight-etm4x", "arm,primecell";
509 reg = <0 0x23240000 0 0x1000>; 394 reg = <0 0x23240000 0 0x1000>;
510 395
511 clocks = <&soc_smc50mhz>; 396 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk"; 397 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0 398 power-domains = <&scpi_devpd 0>;
514 out-ports { !! 399 port {
515 port { !! 400 cluster1_etm2_out_port: endpoint {
516 cluster1_etm2_ !! 401 remote-endpoint = <&cluster1_funnel_in_port2>;
517 remote <<
518 }; <<
519 }; 402 };
520 }; 403 };
521 }; 404 };
522 405
523 cti4: cti@23220000 { <<
524 compatible = "arm,coresight-ct <<
525 "arm,primecell"; <<
526 reg = <0 0x23220000 0 0x1000>; <<
527 <<
528 clocks = <&soc_smc50mhz>; <<
529 clock-names = "apb_pclk"; <<
530 power-domains = <&scpi_devpd 0 <<
531 <<
532 arm,cs-dev-assoc = <&etm4>; <<
533 }; <<
534 <<
535 cpu_debug5: cpu-debug@23310000 { 406 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp 407 compatible = "arm,coresight-cpu-debug", "arm,primecell";
537 reg = <0x0 0x23310000 0x0 0x10 408 reg = <0x0 0x23310000 0x0 0x1000>;
538 409
539 clocks = <&soc_smc50mhz>; 410 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk"; 411 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0 412 power-domains = <&scpi_devpd 0>;
542 }; 413 };
543 414
544 etm5: etm@23340000 { 415 etm5: etm@23340000 {
545 compatible = "arm,coresight-et 416 compatible = "arm,coresight-etm4x", "arm,primecell";
546 reg = <0 0x23340000 0 0x1000>; 417 reg = <0 0x23340000 0 0x1000>;
547 418
548 clocks = <&soc_smc50mhz>; 419 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk"; 420 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0 421 power-domains = <&scpi_devpd 0>;
551 out-ports { !! 422 port {
552 port { !! 423 cluster1_etm3_out_port: endpoint {
553 cluster1_etm3_ !! 424 remote-endpoint = <&cluster1_funnel_in_port3>;
554 remote <<
555 }; <<
556 }; 425 };
557 }; 426 };
558 }; 427 };
559 428
560 cti5: cti@23320000 { !! 429 replicator@20120000 {
561 compatible = "arm,coresight-ct !! 430 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
562 "arm,primecell"; !! 431 reg = <0 0x20120000 0 0x1000>;
563 reg = <0 0x23320000 0 0x1000>; <<
564 <<
565 clocks = <&soc_smc50mhz>; <<
566 clock-names = "apb_pclk"; <<
567 power-domains = <&scpi_devpd 0 <<
568 <<
569 arm,cs-dev-assoc = <&etm5>; <<
570 }; <<
571 <<
572 cti_sys0: cti@20020000 { /* sys_cti_0 <<
573 compatible = "arm,coresight-ct <<
574 reg = <0 0x20020000 0 0x1000>; <<
575 432
576 clocks = <&soc_smc50mhz>; 433 clocks = <&soc_smc50mhz>;
577 clock-names = "apb_pclk"; 434 clock-names = "apb_pclk";
578 power-domains = <&scpi_devpd 0 435 power-domains = <&scpi_devpd 0>;
579 436
580 #address-cells = <1>; !! 437 ports {
581 #size-cells = <0>; !! 438 #address-cells = <1>;
582 !! 439 #size-cells = <0>;
583 trig-conns@0 { <<
584 reg = <0>; <<
585 arm,trig-in-sigs = <2 <<
586 arm,trig-in-types = <S <<
587 arm,trig-out-sigs = <0 <<
588 arm,trig-out-types = < <<
589 arm,cs-dev-assoc = <&e <<
590 }; <<
591 <<
592 trig-conns@1 { <<
593 reg = <1>; <<
594 arm,trig-in-sigs = <0 <<
595 arm,trig-in-types = <S <<
596 arm,trig-out-sigs = <7 <<
597 arm,trig-out-types = < <<
598 arm,cs-dev-assoc = <&e <<
599 }; <<
600 <<
601 trig-conns@2 { <<
602 reg = <2>; <<
603 arm,trig-in-sigs = <4 <<
604 arm,trig-in-types = <S <<
605 STM <<
606 arm,trig-out-sigs = <4 <<
607 arm,trig-out-types = < <<
608 arm,cs-dev-assoc = <&s <<
609 }; <<
610 <<
611 trig-conns@3 { <<
612 reg = <3>; <<
613 arm,trig-out-sigs = <2 <<
614 arm,trig-out-types = < <<
615 arm,cs-dev-assoc = <&t <<
616 }; <<
617 }; <<
618 <<
619 cti_sys1: cti@20110000 { /* sys_cti_1 <<
620 compatible = "arm,coresight-ct <<
621 reg = <0 0x20110000 0 0x1000>; <<
622 440
623 clocks = <&soc_smc50mhz>; !! 441 /* replicator output ports */
624 clock-names = "apb_pclk"; !! 442 port@0 {
625 power-domains = <&scpi_devpd 0 !! 443 reg = <0>;
>> 444 replicator_out_port0: endpoint {
>> 445 remote-endpoint = <&tpiu_in_port>;
>> 446 };
>> 447 };
626 448
627 #address-cells = <1>; !! 449 port@1 {
628 #size-cells = <0>; !! 450 reg = <1>;
>> 451 replicator_out_port1: endpoint {
>> 452 remote-endpoint = <&etr_in_port>;
>> 453 };
>> 454 };
629 455
630 trig-conns@0 { !! 456 /* replicator input port */
631 reg = <0>; !! 457 port@2 {
632 arm,trig-in-sigs = <0> !! 458 reg = <0>;
633 arm,trig-in-types = <G !! 459 replicator_in_port0: endpoint {
634 arm,trig-out-sigs = <0 !! 460 slave-mode;
635 arm,trig-out-types = < !! 461 };
636 arm,trig-conn-name = " !! 462 };
637 }; <<
638 <<
639 trig-conns@1 { <<
640 reg = <1>; <<
641 arm,trig-out-sigs = <2 <<
642 arm,trig-out-types = < <<
643 arm,trig-conn-name = " <<
644 }; <<
645 <<
646 trig-conns@2 { <<
647 reg = <2>; <<
648 arm,trig-out-sigs = <1 <<
649 arm,trig-out-types = < <<
650 arm,trig-conn-name = " <<
651 }; 463 };
652 }; 464 };
653 465
654 gpu: gpu@2d000000 { <<
655 compatible = "arm,juno-mali", <<
656 reg = <0 0x2d000000 0 0x10000> <<
657 interrupts = <GIC_SPI 33 IRQ_T <<
658 <GIC_SPI 34 IRQ_T <<
659 <GIC_SPI 32 IRQ_T <<
660 interrupt-names = "job", "mmu" <<
661 clocks = <&scpi_dvfs 2>; <<
662 power-domains = <&scpi_devpd 1 <<
663 dma-coherent; <<
664 /* The SMMU is only really of <<
665 /* iommus = <&smmu_gpu 0>; */ <<
666 }; <<
667 <<
668 sram: sram@2e000000 { 466 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns 467 compatible = "arm,juno-sram-ns", "mmio-sram";
670 reg = <0x0 0x2e000000 0x0 0x80 468 reg = <0x0 0x2e000000 0x0 0x8000>;
671 469
672 #address-cells = <1>; 470 #address-cells = <1>;
673 #size-cells = <1>; 471 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8 472 ranges = <0 0x0 0x2e000000 0x8000>;
675 473
676 cpu_scp_lpri: scp-sram@0 { !! 474 cpu_scp_lpri: scp-shmem@0 {
677 compatible = "arm,juno 475 compatible = "arm,juno-scp-shmem";
678 reg = <0x0 0x200>; 476 reg = <0x0 0x200>;
679 }; 477 };
680 478
681 cpu_scp_hpri: scp-sram@200 { !! 479 cpu_scp_hpri: scp-shmem@200 {
682 compatible = "arm,juno 480 compatible = "arm,juno-scp-shmem";
683 reg = <0x200 0x200>; 481 reg = <0x200 0x200>;
684 }; 482 };
685 }; 483 };
686 484
687 pcie_ctlr: pcie@40000000 { 485 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie 486 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
689 device_type = "pci"; 487 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000 488 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
691 bus-range = <0 255>; 489 bus-range = <0 255>;
692 linux,pci-domain = <0>; 490 linux,pci-domain = <0>;
693 #address-cells = <3>; 491 #address-cells = <3>;
694 #size-cells = <2>; 492 #size-cells = <2>;
695 dma-coherent; 493 dma-coherent;
696 ranges = <0x01000000 0x00 0x00 494 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
697 <0x02000000 0x00 0x50 495 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
698 <0x42000000 0x40 0x00 496 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
699 /* Standard AXI Translation en <<
700 dma-ranges = <0x02000000 0x0 0 <<
701 <0x43000000 0x8 0 <<
702 #interrupt-cells = <1>; 497 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7> 498 interrupt-map-mask = <0 0 0 7>;
704 interrupt-map = <0 0 0 1 &gic !! 499 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
705 <0 0 0 2 &gic !! 500 <0 0 0 2 &gic 0 0 0 137 4>,
706 <0 0 0 3 &gic !! 501 <0 0 0 3 &gic 0 0 0 138 4>,
707 <0 0 0 4 &gic !! 502 <0 0 0 4 &gic 0 0 0 139 4>;
708 msi-parent = <&v2m_0>; 503 msi-parent = <&v2m_0>;
709 status = "disabled"; 504 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC 505 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
711 iommu-map = <0x0 &smmu_pcie 0x 506 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
712 }; 507 };
713 508
714 scpi { 509 scpi {
715 compatible = "arm,scpi"; 510 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>; 511 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>; 512 shmem = <&cpu_scp_hpri>;
718 513
719 clocks { 514 clocks {
720 compatible = "arm,scpi 515 compatible = "arm,scpi-clocks";
721 516
722 scpi_dvfs: clocks-0 { !! 517 scpi_dvfs: scpi-dvfs {
723 compatible = " 518 compatible = "arm,scpi-dvfs-clocks";
724 #clock-cells = 519 #clock-cells = <1>;
725 clock-indices 520 clock-indices = <0>, <1>, <2>;
726 clock-output-n 521 clock-output-names = "atlclk", "aplclk","gpuclk";
727 }; 522 };
728 scpi_clk: clocks-1 { !! 523 scpi_clk: scpi-clk {
729 compatible = " 524 compatible = "arm,scpi-variable-clocks";
730 #clock-cells = 525 #clock-cells = <1>;
731 clock-indices 526 clock-indices = <3>;
732 clock-output-n 527 clock-output-names = "pxlclk";
733 }; 528 };
734 }; 529 };
735 530
736 scpi_devpd: power-controller { !! 531 scpi_devpd: scpi-power-domains {
737 compatible = "arm,scpi 532 compatible = "arm,scpi-power-domains";
738 num-domains = <2>; 533 num-domains = <2>;
739 #power-domain-cells = 534 #power-domain-cells = <1>;
740 }; 535 };
741 536
742 scpi_sensors0: sensors { 537 scpi_sensors0: sensors {
743 compatible = "arm,scpi 538 compatible = "arm,scpi-sensors";
744 #thermal-sensor-cells 539 #thermal-sensor-cells = <1>;
745 }; 540 };
746 }; 541 };
747 542
748 thermal-zones { 543 thermal-zones {
749 pmic-thermal { !! 544 pmic {
750 polling-delay = <1000> 545 polling-delay = <1000>;
751 polling-delay-passive 546 polling-delay-passive = <100>;
752 thermal-sensors = <&sc 547 thermal-sensors = <&scpi_sensors0 0>;
753 trips { <<
754 pmic_crit0: tr <<
755 temper <<
756 hyster <<
757 type = <<
758 }; <<
759 }; <<
760 }; 548 };
761 549
762 soc-thermal { !! 550 soc {
763 polling-delay = <1000> 551 polling-delay = <1000>;
764 polling-delay-passive 552 polling-delay-passive = <100>;
765 thermal-sensors = <&sc 553 thermal-sensors = <&scpi_sensors0 3>;
766 trips { <<
767 soc_crit0: tri <<
768 temper <<
769 hyster <<
770 type = <<
771 }; <<
772 }; <<
773 }; 554 };
774 555
775 big_cluster_thermal_zone: big- !! 556 big_cluster_thermal_zone: big_cluster {
776 polling-delay = <1000> 557 polling-delay = <1000>;
777 polling-delay-passive 558 polling-delay-passive = <100>;
778 thermal-sensors = <&sc 559 thermal-sensors = <&scpi_sensors0 21>;
779 status = "disabled"; 560 status = "disabled";
780 }; 561 };
781 562
782 little_cluster_thermal_zone: l !! 563 little_cluster_thermal_zone: little_cluster {
783 polling-delay = <1000> 564 polling-delay = <1000>;
784 polling-delay-passive 565 polling-delay-passive = <100>;
785 thermal-sensors = <&sc 566 thermal-sensors = <&scpi_sensors0 22>;
786 status = "disabled"; 567 status = "disabled";
787 }; 568 };
788 569
789 gpu0_thermal_zone: gpu0-therma !! 570 gpu0_thermal_zone: gpu0 {
790 polling-delay = <1000> 571 polling-delay = <1000>;
791 polling-delay-passive 572 polling-delay-passive = <100>;
792 thermal-sensors = <&sc 573 thermal-sensors = <&scpi_sensors0 23>;
793 status = "disabled"; 574 status = "disabled";
794 }; 575 };
795 576
796 gpu1_thermal_zone: gpu1-therma !! 577 gpu1_thermal_zone: gpu1 {
797 polling-delay = <1000> 578 polling-delay = <1000>;
798 polling-delay-passive 579 polling-delay-passive = <100>;
799 thermal-sensors = <&sc 580 thermal-sensors = <&scpi_sensors0 24>;
800 status = "disabled"; 581 status = "disabled";
801 }; 582 };
802 }; 583 };
803 584
804 smmu_dma: iommu@7fb00000 { 585 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a 586 compatible = "arm,mmu-401", "arm,smmu-v1";
806 reg = <0x0 0x7fb00000 0x0 0x10 587 reg = <0x0 0x7fb00000 0x0 0x10000>;
807 interrupts = <GIC_SPI 95 IRQ_T 588 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 95 IRQ_T 589 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
809 #iommu-cells = <1>; 590 #iommu-cells = <1>;
810 #global-interrupts = <1>; 591 #global-interrupts = <1>;
811 dma-coherent; 592 dma-coherent;
>> 593 status = "disabled";
812 }; 594 };
813 595
814 smmu_hdlcd1: iommu@7fb10000 { 596 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a 597 compatible = "arm,mmu-401", "arm,smmu-v1";
816 reg = <0x0 0x7fb10000 0x0 0x10 598 reg = <0x0 0x7fb10000 0x0 0x10000>;
817 interrupts = <GIC_SPI 99 IRQ_T 599 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 99 IRQ_T 600 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
819 #iommu-cells = <1>; 601 #iommu-cells = <1>;
820 #global-interrupts = <1>; 602 #global-interrupts = <1>;
821 }; 603 };
822 604
823 smmu_hdlcd0: iommu@7fb20000 { 605 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a 606 compatible = "arm,mmu-401", "arm,smmu-v1";
825 reg = <0x0 0x7fb20000 0x0 0x10 607 reg = <0x0 0x7fb20000 0x0 0x10000>;
826 interrupts = <GIC_SPI 97 IRQ_T 608 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 97 IRQ_T 609 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
828 #iommu-cells = <1>; 610 #iommu-cells = <1>;
829 #global-interrupts = <1>; 611 #global-interrupts = <1>;
830 }; 612 };
831 613
832 smmu_usb: iommu@7fb30000 { 614 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a 615 compatible = "arm,mmu-401", "arm,smmu-v1";
834 reg = <0x0 0x7fb30000 0x0 0x10 616 reg = <0x0 0x7fb30000 0x0 0x10000>;
835 interrupts = <GIC_SPI 101 IRQ_ 617 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 101 IRQ_ 618 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
837 #iommu-cells = <1>; 619 #iommu-cells = <1>;
838 #global-interrupts = <1>; 620 #global-interrupts = <1>;
839 dma-coherent; 621 dma-coherent;
840 }; 622 };
841 623
842 dma-controller@7ff00000 { !! 624 dma@7ff00000 {
843 compatible = "arm,pl330", "arm 625 compatible = "arm,pl330", "arm,primecell";
844 reg = <0x0 0x7ff00000 0 0x1000 626 reg = <0x0 0x7ff00000 0 0x1000>;
845 #dma-cells = <1>; 627 #dma-cells = <1>;
>> 628 #dma-channels = <8>;
>> 629 #dma-requests = <32>;
846 interrupts = <GIC_SPI 88 IRQ_T 630 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 89 IRQ_T 631 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 90 IRQ_T 632 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 91 IRQ_T 633 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 92 IRQ_T 634 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 108 IRQ_ 635 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 109 IRQ_ 636 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 110 IRQ_ 637 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 111 IRQ_ 638 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 iommus = <&smmu_dma 0>, 639 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>, 640 <&smmu_dma 1>,
857 <&smmu_dma 2>, 641 <&smmu_dma 2>,
858 <&smmu_dma 3>, 642 <&smmu_dma 3>,
859 <&smmu_dma 4>, 643 <&smmu_dma 4>,
860 <&smmu_dma 5>, 644 <&smmu_dma 5>,
861 <&smmu_dma 6>, 645 <&smmu_dma 6>,
862 <&smmu_dma 7>, 646 <&smmu_dma 7>,
863 <&smmu_dma 8>; 647 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>; 648 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk"; 649 clock-names = "apb_pclk";
866 }; 650 };
867 651
868 hdlcd@7ff50000 { 652 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd"; 653 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>; 654 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T 655 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 iommus = <&smmu_hdlcd1 0>; 656 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>; 657 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk"; 658 clock-names = "pxlclk";
875 659
876 port { 660 port {
877 hdlcd1_output: endpoin !! 661 hdlcd1_output: hdlcd1-endpoint {
878 remote-endpoin 662 remote-endpoint = <&tda998x_1_input>;
879 }; 663 };
880 }; 664 };
881 }; 665 };
882 666
883 hdlcd@7ff60000 { 667 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd"; 668 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>; 669 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T 670 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
887 iommus = <&smmu_hdlcd0 0>; 671 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>; 672 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk"; 673 clock-names = "pxlclk";
890 674
891 port { 675 port {
892 hdlcd0_output: endpoin !! 676 hdlcd0_output: hdlcd0-endpoint {
893 remote-endpoin 677 remote-endpoint = <&tda998x_0_input>;
894 }; 678 };
895 }; 679 };
896 }; 680 };
897 681
898 soc_uart0: serial@7ff80000 { !! 682 soc_uart0: uart@7ff80000 {
899 compatible = "arm,pl011", "arm 683 compatible = "arm,pl011", "arm,primecell";
900 reg = <0x0 0x7ff80000 0x0 0x10 684 reg = <0x0 0x7ff80000 0x0 0x1000>;
901 interrupts = <GIC_SPI 83 IRQ_T 685 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&soc_uartclk>, <&soc 686 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
903 clock-names = "uartclk", "apb_ 687 clock-names = "uartclk", "apb_pclk";
904 }; 688 };
905 689
906 i2c@7ffa0000 { 690 i2c@7ffa0000 {
907 compatible = "snps,designware- 691 compatible = "snps,designware-i2c";
908 reg = <0x0 0x7ffa0000 0x0 0x10 692 reg = <0x0 0x7ffa0000 0x0 0x1000>;
909 #address-cells = <1>; 693 #address-cells = <1>;
910 #size-cells = <0>; 694 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_ 695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
912 clock-frequency = <400000>; 696 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>; 697 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>; 698 clocks = <&soc_smc50mhz>;
915 699
916 hdmi-transmitter@70 { 700 hdmi-transmitter@70 {
917 compatible = "nxp,tda9 701 compatible = "nxp,tda998x";
918 reg = <0x70>; 702 reg = <0x70>;
919 port { 703 port {
920 tda998x_0_inpu !! 704 tda998x_0_input: tda998x-0-endpoint {
921 remote 705 remote-endpoint = <&hdlcd0_output>;
922 }; 706 };
923 }; 707 };
924 }; 708 };
925 709
926 hdmi-transmitter@71 { 710 hdmi-transmitter@71 {
927 compatible = "nxp,tda9 711 compatible = "nxp,tda998x";
928 reg = <0x71>; 712 reg = <0x71>;
929 port { 713 port {
930 tda998x_1_inpu !! 714 tda998x_1_input: tda998x-1-endpoint {
931 remote 715 remote-endpoint = <&hdlcd1_output>;
932 }; 716 };
933 }; 717 };
934 }; 718 };
935 }; 719 };
936 720
937 usb@7ffb0000 { !! 721 ohci@7ffb0000 {
938 compatible = "generic-ohci"; 722 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10 723 reg = <0x0 0x7ffb0000 0x0 0x10000>;
940 interrupts = <GIC_SPI 116 IRQ_ 724 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
941 iommus = <&smmu_usb 0>; 725 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>; 726 clocks = <&soc_usb48mhz>;
943 }; 727 };
944 728
945 usb@7ffc0000 { !! 729 ehci@7ffc0000 {
946 compatible = "generic-ehci"; 730 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10 731 reg = <0x0 0x7ffc0000 0x0 0x10000>;
948 interrupts = <GIC_SPI 117 IRQ_ 732 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
949 iommus = <&smmu_usb 0>; 733 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>; 734 clocks = <&soc_usb48mhz>;
951 }; 735 };
952 736
953 memory-controller@7ffd0000 { 737 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm 738 compatible = "arm,pl354", "arm,primecell";
955 reg = <0 0x7ffd0000 0 0x1000>; 739 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T 740 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 87 IRQ_T 741 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&soc_smc50mhz>; 742 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk"; 743 clock-names = "apb_pclk";
960 }; 744 };
961 745
962 memory@80000000 { 746 memory@80000000 {
963 device_type = "memory"; 747 device_type = "memory";
964 /* last 16MB of the first memo 748 /* last 16MB of the first memory area is reserved for secure world use by firmware */
965 reg = <0x00000000 0x80000000 0 749 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
966 <0x00000008 0x80000000 0 750 <0x00000008 0x80000000 0x1 0x80000000>;
967 }; 751 };
968 752
969 bus@8000000 { !! 753 smb@8000000 {
>> 754 compatible = "simple-bus";
>> 755 #address-cells = <2>;
>> 756 #size-cells = <1>;
>> 757 ranges = <0 0 0 0x08000000 0x04000000>,
>> 758 <1 0 0 0x14000000 0x04000000>,
>> 759 <2 0 0 0x18000000 0x04000000>,
>> 760 <3 0 0 0x1c000000 0x04000000>,
>> 761 <4 0 0 0x0c000000 0x04000000>,
>> 762 <5 0 0 0x10000000 0x04000000>;
>> 763
970 #interrupt-cells = <1>; 764 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>; 765 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0 !! 766 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
973 <0 0 1 &gic 0 !! 767 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
974 <0 0 2 &gic 0 !! 768 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 3 &gic 0 !! 769 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 4 &gic 0 !! 770 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 5 &gic 0 !! 771 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
978 <0 0 6 &gic 0 !! 772 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
979 <0 0 7 &gic 0 !! 773 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
980 <0 0 8 &gic 0 !! 774 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
981 <0 0 9 &gic 0 !! 775 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 10 &gic 0 !! 776 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 11 &gic 0 !! 777 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 12 &gic 0 !! 778 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
>> 779
>> 780 /include/ "juno-motherboard.dtsi"
985 }; 781 };
986 782
987 site2: tlx-bus@60000000 { !! 783 site2: tlx@60000000 {
988 compatible = "simple-bus"; 784 compatible = "simple-bus";
989 #address-cells = <1>; 785 #address-cells = <1>;
990 #size-cells = <1>; 786 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100 787 ranges = <0 0 0x60000000 0x10000000>;
992 #interrupt-cells = <1>; 788 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>; 789 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI !! 790 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
995 }; 791 };
996 }; 792 };
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