1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi" 2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi" 3 #include "juno-motherboard.dtsi"
4 4
5 / { 5 / {
6 /* 6 /*
7 * Devices shared by all Juno boards 7 * Devices shared by all Juno boards
8 */ 8 */
>> 9 dma-ranges = <0 0 0 0 0x100 0>;
9 10
10 memtimer: timer@2a810000 { 11 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer- 12 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10 13 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>; 14 clock-frequency = <50000000>;
14 #address-cells = <1>; !! 15 #address-cells = <2>;
15 #size-cells = <1>; !! 16 #size-cells = <2>;
16 ranges = <0 0x0 0x2a820000 0x2 !! 17 ranges;
17 status = "disabled"; 18 status = "disabled";
18 frame@2a830000 { 19 frame@2a830000 {
19 frame-number = <1>; 20 frame-number = <1>;
20 interrupts = <GIC_SPI !! 21 interrupts = <0 60 4>;
21 reg = <0x10000 0x10000 !! 22 reg = <0x0 0x2a830000 0x0 0x10000>;
22 }; 23 };
23 }; 24 };
24 25
25 mailbox: mhu@2b1f0000 { 26 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p 27 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x10 28 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_T 29 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_T !! 30 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 <GIC_SPI 37 IRQ_T !! 31 interrupt-names = "mhu_lpri_rx",
>> 32 "mhu_hpri_rx";
31 #mbox-cells = <1>; 33 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>; 34 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk"; 35 clock-names = "apb_pclk";
34 }; 36 };
35 37
36 smmu_gpu: iommu@2b400000 { <<
37 compatible = "arm,mmu-400", "a <<
38 reg = <0x0 0x2b400000 0x0 0x10 <<
39 interrupts = <GIC_SPI 38 IRQ_T <<
40 <GIC_SPI 38 IRQ_T <<
41 #iommu-cells = <1>; <<
42 #global-interrupts = <1>; <<
43 power-domains = <&scpi_devpd 1 <<
44 dma-coherent; <<
45 status = "disabled"; <<
46 }; <<
47 <<
48 smmu_pcie: iommu@2b500000 { 38 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a 39 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b500000 0x0 0x10 40 reg = <0x0 0x2b500000 0x0 0x10000>;
51 interrupts = <GIC_SPI 40 IRQ_T 41 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 40 IRQ_T 42 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
53 #iommu-cells = <1>; 43 #iommu-cells = <1>;
54 #global-interrupts = <1>; 44 #global-interrupts = <1>;
55 dma-coherent; 45 dma-coherent;
56 status = "disabled"; 46 status = "disabled";
57 }; 47 };
58 48
59 smmu_etr: iommu@2b600000 { 49 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a 50 compatible = "arm,mmu-401", "arm,smmu-v1";
61 reg = <0x0 0x2b600000 0x0 0x10 51 reg = <0x0 0x2b600000 0x0 0x10000>;
62 interrupts = <GIC_SPI 42 IRQ_T 52 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 42 IRQ_T 53 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
64 #iommu-cells = <1>; 54 #iommu-cells = <1>;
65 #global-interrupts = <1>; 55 #global-interrupts = <1>;
66 dma-coherent; 56 dma-coherent;
67 power-domains = <&scpi_devpd 0 57 power-domains = <&scpi_devpd 0>;
68 }; 58 };
69 59
70 gic: interrupt-controller@2c010000 { 60 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a 61 compatible = "arm,gic-400", "arm,cortex-a15-gic";
72 reg = <0x0 0x2c010000 0 0x1000 62 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000 63 <0x0 0x2c02f000 0 0x2000>,
74 <0x0 0x2c04f000 0 0x2000 64 <0x0 0x2c04f000 0 0x2000>,
75 <0x0 0x2c06f000 0 0x2000 65 <0x0 0x2c06f000 0 0x2000>;
76 #address-cells = <1>; !! 66 #address-cells = <2>;
77 #interrupt-cells = <3>; 67 #interrupt-cells = <3>;
78 #size-cells = <1>; !! 68 #size-cells = <2>;
79 interrupt-controller; 69 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C 70 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
81 ranges = <0 0 0x2c1c0000 0x400 !! 71 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
82 72
83 v2m_0: v2m@0 { 73 v2m_0: v2m@0 {
84 compatible = "arm,gic- 74 compatible = "arm,gic-v2m-frame";
85 msi-controller; 75 msi-controller;
86 reg = <0 0x10000>; !! 76 reg = <0 0 0 0x10000>;
87 }; 77 };
88 78
89 v2m@10000 { 79 v2m@10000 {
90 compatible = "arm,gic- 80 compatible = "arm,gic-v2m-frame";
91 msi-controller; 81 msi-controller;
92 reg = <0x10000 0x10000 !! 82 reg = <0 0x10000 0 0x10000>;
93 }; 83 };
94 84
95 v2m@20000 { 85 v2m@20000 {
96 compatible = "arm,gic- 86 compatible = "arm,gic-v2m-frame";
97 msi-controller; 87 msi-controller;
98 reg = <0x20000 0x10000 !! 88 reg = <0 0x20000 0 0x10000>;
99 }; 89 };
100 90
101 v2m@30000 { 91 v2m@30000 {
102 compatible = "arm,gic- 92 compatible = "arm,gic-v2m-frame";
103 msi-controller; 93 msi-controller;
104 reg = <0x30000 0x10000 !! 94 reg = <0 0x30000 0 0x10000>;
105 }; 95 };
106 }; 96 };
107 97
108 timer { 98 timer {
109 compatible = "arm,armv8-timer" 99 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_ 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_ 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_ 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_ 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
114 }; 104 };
115 105
116 /* 106 /*
117 * Juno TRMs specify the size for thes 107 * Juno TRMs specify the size for these coresight components as 64K.
118 * The actual size is just 4K though 6 108 * The actual size is just 4K though 64K is reserved. Access to the
119 * unmapped reserved region results in 109 * unmapped reserved region results in a DECERR response.
120 */ 110 */
121 etf_sys0: etf@20010000 { /* etf0 */ !! 111 etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm 112 compatible = "arm,coresight-tmc", "arm,primecell";
123 reg = <0 0x20010000 0 0x1000>; 113 reg = <0 0x20010000 0 0x1000>;
124 114
125 clocks = <&soc_smc50mhz>; 115 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk"; 116 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0 117 power-domains = <&scpi_devpd 0>;
>> 118 ports {
>> 119 #address-cells = <1>;
>> 120 #size-cells = <0>;
128 121
129 in-ports { !! 122 /* input port */
130 port { !! 123 port@0 {
>> 124 reg = <0>;
131 etf0_in_port: 125 etf0_in_port: endpoint {
>> 126 slave-mode;
132 remote 127 remote-endpoint = <&main_funnel_out_port>;
133 }; 128 };
134 }; 129 };
135 }; <<
136 130
137 out-ports { !! 131 /* output port */
138 port { !! 132 port@1 {
>> 133 reg = <0>;
139 etf0_out_port: 134 etf0_out_port: endpoint {
140 }; 135 };
141 }; 136 };
142 }; 137 };
143 }; 138 };
144 139
145 tpiu_sys: tpiu@20030000 { !! 140 tpiu@20030000 {
146 compatible = "arm,coresight-tp 141 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0 0x20030000 0 0x1000>; 142 reg = <0 0x20030000 0 0x1000>;
148 143
149 clocks = <&soc_smc50mhz>; 144 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk"; 145 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0 146 power-domains = <&scpi_devpd 0>;
152 in-ports { !! 147 port {
153 port { !! 148 tpiu_in_port: endpoint {
154 tpiu_in_port: !! 149 slave-mode;
155 remote !! 150 remote-endpoint = <&replicator_out_port0>;
156 }; <<
157 }; 151 };
158 }; 152 };
159 }; 153 };
160 154
161 /* main funnel on Juno r0, cssys0 funn 155 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
162 main_funnel: funnel@20040000 { 156 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy !! 157 compatible = "arm,coresight-funnel", "arm,primecell";
164 reg = <0 0x20040000 0 0x1000>; 158 reg = <0 0x20040000 0 0x1000>;
165 159
166 clocks = <&soc_smc50mhz>; 160 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk"; 161 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0 162 power-domains = <&scpi_devpd 0>;
>> 163 ports {
>> 164 #address-cells = <1>;
>> 165 #size-cells = <0>;
169 166
170 out-ports { !! 167 /* output port */
171 port { !! 168 port@0 {
>> 169 reg = <0>;
172 main_funnel_ou 170 main_funnel_out_port: endpoint {
173 remote 171 remote-endpoint = <&etf0_in_port>;
174 }; 172 };
175 }; 173 };
176 }; <<
177 174
178 main_funnel_in_ports: in-ports !! 175 /* input ports */
179 #address-cells = <1>; !! 176 port@1 {
180 #size-cells = <0>; <<
181 <<
182 port@0 { <<
183 reg = <0>; 177 reg = <0>;
184 main_funnel_in 178 main_funnel_in_port0: endpoint {
>> 179 slave-mode;
185 remote 180 remote-endpoint = <&cluster0_funnel_out_port>;
186 }; 181 };
187 }; 182 };
188 183
189 port@1 { !! 184 port@2 {
190 reg = <1>; 185 reg = <1>;
191 main_funnel_in 186 main_funnel_in_port1: endpoint {
>> 187 slave-mode;
192 remote 188 remote-endpoint = <&cluster1_funnel_out_port>;
193 }; 189 };
194 }; 190 };
195 }; 191 };
196 }; 192 };
197 193
198 etr_sys: etr@20070000 { !! 194 etr@20070000 {
199 compatible = "arm,coresight-tm 195 compatible = "arm,coresight-tmc", "arm,primecell";
200 reg = <0 0x20070000 0 0x1000>; 196 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>; 197 iommus = <&smmu_etr 0>;
202 198
203 clocks = <&soc_smc50mhz>; 199 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk"; 200 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0 201 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather; !! 202 port {
207 in-ports { !! 203 etr_in_port: endpoint {
208 port { !! 204 slave-mode;
209 etr_in_port: e !! 205 remote-endpoint = <&replicator_out_port1>;
210 remote <<
211 }; <<
212 }; 206 };
213 }; 207 };
214 }; 208 };
215 209
216 stm_sys: stm@20100000 { !! 210 stm@20100000 {
217 compatible = "arm,coresight-st 211 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>, 212 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000 213 <0 0x28000000 0 0x1000000>;
220 reg-names = "stm-base", "stm-s 214 reg-names = "stm-base", "stm-stimulus-base";
221 215
222 clocks = <&soc_smc50mhz>; 216 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk"; 217 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0 218 power-domains = <&scpi_devpd 0>;
225 out-ports { !! 219 port {
226 port { !! 220 stm_out_port: endpoint {
227 stm_out_port: <<
228 }; <<
229 }; <<
230 }; <<
231 }; <<
232 <<
233 replicator@20120000 { <<
234 compatible = "arm,coresight-dy <<
235 reg = <0 0x20120000 0 0x1000>; <<
236 <<
237 clocks = <&soc_smc50mhz>; <<
238 clock-names = "apb_pclk"; <<
239 power-domains = <&scpi_devpd 0 <<
240 <<
241 out-ports { <<
242 #address-cells = <1>; <<
243 #size-cells = <0>; <<
244 <<
245 /* replicator output p <<
246 port@0 { <<
247 reg = <0>; <<
248 replicator_out <<
249 remote <<
250 }; <<
251 }; <<
252 <<
253 port@1 { <<
254 reg = <1>; <<
255 replicator_out <<
256 remote <<
257 }; <<
258 }; <<
259 }; <<
260 in-ports { <<
261 port { <<
262 replicator_in_ <<
263 }; <<
264 }; 221 };
265 }; 222 };
266 }; 223 };
267 224
268 cpu_debug0: cpu-debug@22010000 { 225 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp 226 compatible = "arm,coresight-cpu-debug", "arm,primecell";
270 reg = <0x0 0x22010000 0x0 0x10 227 reg = <0x0 0x22010000 0x0 0x1000>;
271 228
272 clocks = <&soc_smc50mhz>; 229 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk"; 230 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0 231 power-domains = <&scpi_devpd 0>;
275 }; 232 };
276 233
277 etm0: etm@22040000 { 234 etm0: etm@22040000 {
278 compatible = "arm,coresight-et 235 compatible = "arm,coresight-etm4x", "arm,primecell";
279 reg = <0 0x22040000 0 0x1000>; 236 reg = <0 0x22040000 0 0x1000>;
280 237
281 clocks = <&soc_smc50mhz>; 238 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk"; 239 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0 240 power-domains = <&scpi_devpd 0>;
284 out-ports { !! 241 port {
285 port { !! 242 cluster0_etm0_out_port: endpoint {
286 cluster0_etm0_ !! 243 remote-endpoint = <&cluster0_funnel_in_port0>;
287 remote <<
288 }; <<
289 }; 244 };
290 }; 245 };
291 }; 246 };
292 247
293 cti0: cti@22020000 { <<
294 compatible = "arm,coresight-ct <<
295 "arm,primecell"; <<
296 reg = <0 0x22020000 0 0x1000>; <<
297 <<
298 clocks = <&soc_smc50mhz>; <<
299 clock-names = "apb_pclk"; <<
300 power-domains = <&scpi_devpd 0 <<
301 <<
302 arm,cs-dev-assoc = <&etm0>; <<
303 }; <<
304 <<
305 funnel@220c0000 { /* cluster0 funnel * 248 funnel@220c0000 { /* cluster0 funnel */
306 compatible = "arm,coresight-dy !! 249 compatible = "arm,coresight-funnel", "arm,primecell";
307 reg = <0 0x220c0000 0 0x1000>; 250 reg = <0 0x220c0000 0 0x1000>;
308 251
309 clocks = <&soc_smc50mhz>; 252 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk"; 253 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0 254 power-domains = <&scpi_devpd 0>;
312 out-ports { !! 255 ports {
313 port { !! 256 #address-cells = <1>;
>> 257 #size-cells = <0>;
>> 258
>> 259 port@0 {
>> 260 reg = <0>;
314 cluster0_funne 261 cluster0_funnel_out_port: endpoint {
315 remote 262 remote-endpoint = <&main_funnel_in_port0>;
316 }; 263 };
317 }; 264 };
318 }; <<
319 265
320 in-ports { !! 266 port@1 {
321 #address-cells = <1>; <<
322 #size-cells = <0>; <<
323 <<
324 port@0 { <<
325 reg = <0>; 267 reg = <0>;
326 cluster0_funne 268 cluster0_funnel_in_port0: endpoint {
>> 269 slave-mode;
327 remote 270 remote-endpoint = <&cluster0_etm0_out_port>;
328 }; 271 };
329 }; 272 };
330 273
331 port@1 { !! 274 port@2 {
332 reg = <1>; 275 reg = <1>;
333 cluster0_funne 276 cluster0_funnel_in_port1: endpoint {
>> 277 slave-mode;
334 remote 278 remote-endpoint = <&cluster0_etm1_out_port>;
335 }; 279 };
336 }; 280 };
337 }; 281 };
338 }; 282 };
339 283
340 cpu_debug1: cpu-debug@22110000 { 284 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp 285 compatible = "arm,coresight-cpu-debug", "arm,primecell";
342 reg = <0x0 0x22110000 0x0 0x10 286 reg = <0x0 0x22110000 0x0 0x1000>;
343 287
344 clocks = <&soc_smc50mhz>; 288 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk"; 289 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0 290 power-domains = <&scpi_devpd 0>;
347 }; 291 };
348 292
349 etm1: etm@22140000 { 293 etm1: etm@22140000 {
350 compatible = "arm,coresight-et 294 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0x22140000 0 0x1000>; 295 reg = <0 0x22140000 0 0x1000>;
352 296
353 clocks = <&soc_smc50mhz>; 297 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk"; 298 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0 299 power-domains = <&scpi_devpd 0>;
356 out-ports { !! 300 port {
357 port { !! 301 cluster0_etm1_out_port: endpoint {
358 cluster0_etm1_ !! 302 remote-endpoint = <&cluster0_funnel_in_port1>;
359 remote <<
360 }; <<
361 }; 303 };
362 }; 304 };
363 }; 305 };
364 306
365 cti1: cti@22120000 { <<
366 compatible = "arm,coresight-ct <<
367 "arm,primecell"; <<
368 reg = <0 0x22120000 0 0x1000>; <<
369 <<
370 clocks = <&soc_smc50mhz>; <<
371 clock-names = "apb_pclk"; <<
372 power-domains = <&scpi_devpd 0 <<
373 <<
374 arm,cs-dev-assoc = <&etm1>; <<
375 }; <<
376 <<
377 cpu_debug2: cpu-debug@23010000 { 307 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp 308 compatible = "arm,coresight-cpu-debug", "arm,primecell";
379 reg = <0x0 0x23010000 0x0 0x10 309 reg = <0x0 0x23010000 0x0 0x1000>;
380 310
381 clocks = <&soc_smc50mhz>; 311 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk"; 312 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0 313 power-domains = <&scpi_devpd 0>;
384 }; 314 };
385 315
386 etm2: etm@23040000 { 316 etm2: etm@23040000 {
387 compatible = "arm,coresight-et 317 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0 0x23040000 0 0x1000>; 318 reg = <0 0x23040000 0 0x1000>;
389 319
390 clocks = <&soc_smc50mhz>; 320 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk"; 321 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0 322 power-domains = <&scpi_devpd 0>;
393 out-ports { !! 323 port {
394 port { !! 324 cluster1_etm0_out_port: endpoint {
395 cluster1_etm0_ !! 325 remote-endpoint = <&cluster1_funnel_in_port0>;
396 remote <<
397 }; <<
398 }; 326 };
399 }; 327 };
400 }; 328 };
401 329
402 cti2: cti@23020000 { <<
403 compatible = "arm,coresight-ct <<
404 "arm,primecell"; <<
405 reg = <0 0x23020000 0 0x1000>; <<
406 <<
407 clocks = <&soc_smc50mhz>; <<
408 clock-names = "apb_pclk"; <<
409 power-domains = <&scpi_devpd 0 <<
410 <<
411 arm,cs-dev-assoc = <&etm2>; <<
412 }; <<
413 <<
414 funnel@230c0000 { /* cluster1 funnel * 330 funnel@230c0000 { /* cluster1 funnel */
415 compatible = "arm,coresight-dy !! 331 compatible = "arm,coresight-funnel", "arm,primecell";
416 reg = <0 0x230c0000 0 0x1000>; 332 reg = <0 0x230c0000 0 0x1000>;
417 333
418 clocks = <&soc_smc50mhz>; 334 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk"; 335 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0 336 power-domains = <&scpi_devpd 0>;
421 out-ports { !! 337 ports {
422 port { !! 338 #address-cells = <1>;
>> 339 #size-cells = <0>;
>> 340
>> 341 port@0 {
>> 342 reg = <0>;
423 cluster1_funne 343 cluster1_funnel_out_port: endpoint {
424 remote 344 remote-endpoint = <&main_funnel_in_port1>;
425 }; 345 };
426 }; 346 };
427 }; <<
428 347
429 in-ports { !! 348 port@1 {
430 #address-cells = <1>; <<
431 #size-cells = <0>; <<
432 <<
433 port@0 { <<
434 reg = <0>; 349 reg = <0>;
435 cluster1_funne 350 cluster1_funnel_in_port0: endpoint {
>> 351 slave-mode;
436 remote 352 remote-endpoint = <&cluster1_etm0_out_port>;
437 }; 353 };
438 }; 354 };
439 355
440 port@1 { !! 356 port@2 {
441 reg = <1>; 357 reg = <1>;
442 cluster1_funne 358 cluster1_funnel_in_port1: endpoint {
>> 359 slave-mode;
443 remote 360 remote-endpoint = <&cluster1_etm1_out_port>;
444 }; 361 };
445 }; 362 };
446 port@2 { !! 363 port@3 {
447 reg = <2>; 364 reg = <2>;
448 cluster1_funne 365 cluster1_funnel_in_port2: endpoint {
>> 366 slave-mode;
449 remote 367 remote-endpoint = <&cluster1_etm2_out_port>;
450 }; 368 };
451 }; 369 };
452 port@3 { !! 370 port@4 {
453 reg = <3>; 371 reg = <3>;
454 cluster1_funne 372 cluster1_funnel_in_port3: endpoint {
>> 373 slave-mode;
455 remote 374 remote-endpoint = <&cluster1_etm3_out_port>;
456 }; 375 };
457 }; 376 };
458 }; 377 };
459 }; 378 };
460 379
461 cpu_debug3: cpu-debug@23110000 { 380 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp 381 compatible = "arm,coresight-cpu-debug", "arm,primecell";
463 reg = <0x0 0x23110000 0x0 0x10 382 reg = <0x0 0x23110000 0x0 0x1000>;
464 383
465 clocks = <&soc_smc50mhz>; 384 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk"; 385 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0 386 power-domains = <&scpi_devpd 0>;
468 }; 387 };
469 388
470 etm3: etm@23140000 { 389 etm3: etm@23140000 {
471 compatible = "arm,coresight-et 390 compatible = "arm,coresight-etm4x", "arm,primecell";
472 reg = <0 0x23140000 0 0x1000>; 391 reg = <0 0x23140000 0 0x1000>;
473 392
474 clocks = <&soc_smc50mhz>; 393 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk"; 394 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0 395 power-domains = <&scpi_devpd 0>;
477 out-ports { !! 396 port {
478 port { !! 397 cluster1_etm1_out_port: endpoint {
479 cluster1_etm1_ !! 398 remote-endpoint = <&cluster1_funnel_in_port1>;
480 remote <<
481 }; <<
482 }; 399 };
483 }; 400 };
484 }; 401 };
485 402
486 cti3: cti@23120000 { <<
487 compatible = "arm,coresight-ct <<
488 "arm,primecell"; <<
489 reg = <0 0x23120000 0 0x1000>; <<
490 <<
491 clocks = <&soc_smc50mhz>; <<
492 clock-names = "apb_pclk"; <<
493 power-domains = <&scpi_devpd 0 <<
494 <<
495 arm,cs-dev-assoc = <&etm3>; <<
496 }; <<
497 <<
498 cpu_debug4: cpu-debug@23210000 { 403 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp 404 compatible = "arm,coresight-cpu-debug", "arm,primecell";
500 reg = <0x0 0x23210000 0x0 0x10 405 reg = <0x0 0x23210000 0x0 0x1000>;
501 406
502 clocks = <&soc_smc50mhz>; 407 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk"; 408 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0 409 power-domains = <&scpi_devpd 0>;
505 }; 410 };
506 411
507 etm4: etm@23240000 { 412 etm4: etm@23240000 {
508 compatible = "arm,coresight-et 413 compatible = "arm,coresight-etm4x", "arm,primecell";
509 reg = <0 0x23240000 0 0x1000>; 414 reg = <0 0x23240000 0 0x1000>;
510 415
511 clocks = <&soc_smc50mhz>; 416 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk"; 417 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0 418 power-domains = <&scpi_devpd 0>;
514 out-ports { !! 419 port {
515 port { !! 420 cluster1_etm2_out_port: endpoint {
516 cluster1_etm2_ !! 421 remote-endpoint = <&cluster1_funnel_in_port2>;
517 remote <<
518 }; <<
519 }; 422 };
520 }; 423 };
521 }; 424 };
522 425
523 cti4: cti@23220000 { <<
524 compatible = "arm,coresight-ct <<
525 "arm,primecell"; <<
526 reg = <0 0x23220000 0 0x1000>; <<
527 <<
528 clocks = <&soc_smc50mhz>; <<
529 clock-names = "apb_pclk"; <<
530 power-domains = <&scpi_devpd 0 <<
531 <<
532 arm,cs-dev-assoc = <&etm4>; <<
533 }; <<
534 <<
535 cpu_debug5: cpu-debug@23310000 { 426 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp 427 compatible = "arm,coresight-cpu-debug", "arm,primecell";
537 reg = <0x0 0x23310000 0x0 0x10 428 reg = <0x0 0x23310000 0x0 0x1000>;
538 429
539 clocks = <&soc_smc50mhz>; 430 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk"; 431 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0 432 power-domains = <&scpi_devpd 0>;
542 }; 433 };
543 434
544 etm5: etm@23340000 { 435 etm5: etm@23340000 {
545 compatible = "arm,coresight-et 436 compatible = "arm,coresight-etm4x", "arm,primecell";
546 reg = <0 0x23340000 0 0x1000>; 437 reg = <0 0x23340000 0 0x1000>;
547 438
548 clocks = <&soc_smc50mhz>; 439 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk"; 440 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0 441 power-domains = <&scpi_devpd 0>;
551 out-ports { !! 442 port {
552 port { !! 443 cluster1_etm3_out_port: endpoint {
553 cluster1_etm3_ !! 444 remote-endpoint = <&cluster1_funnel_in_port3>;
554 remote <<
555 }; <<
556 }; 445 };
557 }; 446 };
558 }; 447 };
559 448
560 cti5: cti@23320000 { !! 449 replicator@20120000 {
561 compatible = "arm,coresight-ct !! 450 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
562 "arm,primecell"; !! 451 reg = <0 0x20120000 0 0x1000>;
563 reg = <0 0x23320000 0 0x1000>; <<
564 <<
565 clocks = <&soc_smc50mhz>; <<
566 clock-names = "apb_pclk"; <<
567 power-domains = <&scpi_devpd 0 <<
568 <<
569 arm,cs-dev-assoc = <&etm5>; <<
570 }; <<
571 <<
572 cti_sys0: cti@20020000 { /* sys_cti_0 <<
573 compatible = "arm,coresight-ct <<
574 reg = <0 0x20020000 0 0x1000>; <<
575 452
576 clocks = <&soc_smc50mhz>; 453 clocks = <&soc_smc50mhz>;
577 clock-names = "apb_pclk"; 454 clock-names = "apb_pclk";
578 power-domains = <&scpi_devpd 0 455 power-domains = <&scpi_devpd 0>;
579 456
580 #address-cells = <1>; !! 457 ports {
581 #size-cells = <0>; !! 458 #address-cells = <1>;
582 !! 459 #size-cells = <0>;
583 trig-conns@0 { <<
584 reg = <0>; <<
585 arm,trig-in-sigs = <2 <<
586 arm,trig-in-types = <S <<
587 arm,trig-out-sigs = <0 <<
588 arm,trig-out-types = < <<
589 arm,cs-dev-assoc = <&e <<
590 }; <<
591 <<
592 trig-conns@1 { <<
593 reg = <1>; <<
594 arm,trig-in-sigs = <0 <<
595 arm,trig-in-types = <S <<
596 arm,trig-out-sigs = <7 <<
597 arm,trig-out-types = < <<
598 arm,cs-dev-assoc = <&e <<
599 }; <<
600 <<
601 trig-conns@2 { <<
602 reg = <2>; <<
603 arm,trig-in-sigs = <4 <<
604 arm,trig-in-types = <S <<
605 STM <<
606 arm,trig-out-sigs = <4 <<
607 arm,trig-out-types = < <<
608 arm,cs-dev-assoc = <&s <<
609 }; <<
610 <<
611 trig-conns@3 { <<
612 reg = <3>; <<
613 arm,trig-out-sigs = <2 <<
614 arm,trig-out-types = < <<
615 arm,cs-dev-assoc = <&t <<
616 }; <<
617 }; <<
618 <<
619 cti_sys1: cti@20110000 { /* sys_cti_1 <<
620 compatible = "arm,coresight-ct <<
621 reg = <0 0x20110000 0 0x1000>; <<
622 460
623 clocks = <&soc_smc50mhz>; !! 461 /* replicator output ports */
624 clock-names = "apb_pclk"; !! 462 port@0 {
625 power-domains = <&scpi_devpd 0 !! 463 reg = <0>;
>> 464 replicator_out_port0: endpoint {
>> 465 remote-endpoint = <&tpiu_in_port>;
>> 466 };
>> 467 };
626 468
627 #address-cells = <1>; !! 469 port@1 {
628 #size-cells = <0>; !! 470 reg = <1>;
>> 471 replicator_out_port1: endpoint {
>> 472 remote-endpoint = <&etr_in_port>;
>> 473 };
>> 474 };
629 475
630 trig-conns@0 { !! 476 /* replicator input port */
631 reg = <0>; !! 477 port@2 {
632 arm,trig-in-sigs = <0> !! 478 reg = <0>;
633 arm,trig-in-types = <G !! 479 replicator_in_port0: endpoint {
634 arm,trig-out-sigs = <0 !! 480 slave-mode;
635 arm,trig-out-types = < !! 481 };
636 arm,trig-conn-name = " !! 482 };
637 }; <<
638 <<
639 trig-conns@1 { <<
640 reg = <1>; <<
641 arm,trig-out-sigs = <2 <<
642 arm,trig-out-types = < <<
643 arm,trig-conn-name = " <<
644 }; <<
645 <<
646 trig-conns@2 { <<
647 reg = <2>; <<
648 arm,trig-out-sigs = <1 <<
649 arm,trig-out-types = < <<
650 arm,trig-conn-name = " <<
651 }; 483 };
652 }; 484 };
653 485
654 gpu: gpu@2d000000 { <<
655 compatible = "arm,juno-mali", <<
656 reg = <0 0x2d000000 0 0x10000> <<
657 interrupts = <GIC_SPI 33 IRQ_T <<
658 <GIC_SPI 34 IRQ_T <<
659 <GIC_SPI 32 IRQ_T <<
660 interrupt-names = "job", "mmu" <<
661 clocks = <&scpi_dvfs 2>; <<
662 power-domains = <&scpi_devpd 1 <<
663 dma-coherent; <<
664 /* The SMMU is only really of <<
665 /* iommus = <&smmu_gpu 0>; */ <<
666 }; <<
667 <<
668 sram: sram@2e000000 { 486 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns 487 compatible = "arm,juno-sram-ns", "mmio-sram";
670 reg = <0x0 0x2e000000 0x0 0x80 488 reg = <0x0 0x2e000000 0x0 0x8000>;
671 489
672 #address-cells = <1>; 490 #address-cells = <1>;
673 #size-cells = <1>; 491 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8 492 ranges = <0 0x0 0x2e000000 0x8000>;
675 493
676 cpu_scp_lpri: scp-sram@0 { !! 494 cpu_scp_lpri: scp-shmem@0 {
677 compatible = "arm,juno 495 compatible = "arm,juno-scp-shmem";
678 reg = <0x0 0x200>; 496 reg = <0x0 0x200>;
679 }; 497 };
680 498
681 cpu_scp_hpri: scp-sram@200 { !! 499 cpu_scp_hpri: scp-shmem@200 {
682 compatible = "arm,juno 500 compatible = "arm,juno-scp-shmem";
683 reg = <0x200 0x200>; 501 reg = <0x200 0x200>;
684 }; 502 };
685 }; 503 };
686 504
687 pcie_ctlr: pcie@40000000 { 505 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie 506 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
689 device_type = "pci"; 507 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000 508 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
691 bus-range = <0 255>; 509 bus-range = <0 255>;
692 linux,pci-domain = <0>; 510 linux,pci-domain = <0>;
693 #address-cells = <3>; 511 #address-cells = <3>;
694 #size-cells = <2>; 512 #size-cells = <2>;
695 dma-coherent; 513 dma-coherent;
696 ranges = <0x01000000 0x00 0x00 514 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
697 <0x02000000 0x00 0x50 515 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
698 <0x42000000 0x40 0x00 516 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
699 /* Standard AXI Translation en <<
700 dma-ranges = <0x02000000 0x0 0 <<
701 <0x43000000 0x8 0 <<
702 #interrupt-cells = <1>; 517 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7> 518 interrupt-map-mask = <0 0 0 7>;
704 interrupt-map = <0 0 0 1 &gic !! 519 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
705 <0 0 0 2 &gic !! 520 <0 0 0 2 &gic 0 0 0 137 4>,
706 <0 0 0 3 &gic !! 521 <0 0 0 3 &gic 0 0 0 138 4>,
707 <0 0 0 4 &gic !! 522 <0 0 0 4 &gic 0 0 0 139 4>;
708 msi-parent = <&v2m_0>; 523 msi-parent = <&v2m_0>;
709 status = "disabled"; 524 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC 525 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
711 iommu-map = <0x0 &smmu_pcie 0x 526 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
712 }; 527 };
713 528
714 scpi { 529 scpi {
715 compatible = "arm,scpi"; 530 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>; 531 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>; 532 shmem = <&cpu_scp_hpri>;
718 533
719 clocks { 534 clocks {
720 compatible = "arm,scpi 535 compatible = "arm,scpi-clocks";
721 536
722 scpi_dvfs: clocks-0 { !! 537 scpi_dvfs: scpi-dvfs {
723 compatible = " 538 compatible = "arm,scpi-dvfs-clocks";
724 #clock-cells = 539 #clock-cells = <1>;
725 clock-indices 540 clock-indices = <0>, <1>, <2>;
726 clock-output-n 541 clock-output-names = "atlclk", "aplclk","gpuclk";
727 }; 542 };
728 scpi_clk: clocks-1 { !! 543 scpi_clk: scpi-clk {
729 compatible = " 544 compatible = "arm,scpi-variable-clocks";
730 #clock-cells = 545 #clock-cells = <1>;
731 clock-indices 546 clock-indices = <3>;
732 clock-output-n 547 clock-output-names = "pxlclk";
733 }; 548 };
734 }; 549 };
735 550
736 scpi_devpd: power-controller { !! 551 scpi_devpd: scpi-power-domains {
737 compatible = "arm,scpi 552 compatible = "arm,scpi-power-domains";
738 num-domains = <2>; 553 num-domains = <2>;
739 #power-domain-cells = 554 #power-domain-cells = <1>;
740 }; 555 };
741 556
742 scpi_sensors0: sensors { 557 scpi_sensors0: sensors {
743 compatible = "arm,scpi 558 compatible = "arm,scpi-sensors";
744 #thermal-sensor-cells 559 #thermal-sensor-cells = <1>;
745 }; 560 };
746 }; 561 };
747 562
748 thermal-zones { 563 thermal-zones {
749 pmic-thermal { !! 564 pmic {
750 polling-delay = <1000> 565 polling-delay = <1000>;
751 polling-delay-passive 566 polling-delay-passive = <100>;
752 thermal-sensors = <&sc 567 thermal-sensors = <&scpi_sensors0 0>;
753 trips { <<
754 pmic_crit0: tr <<
755 temper <<
756 hyster <<
757 type = <<
758 }; <<
759 }; <<
760 }; 568 };
761 569
762 soc-thermal { !! 570 soc {
763 polling-delay = <1000> 571 polling-delay = <1000>;
764 polling-delay-passive 572 polling-delay-passive = <100>;
765 thermal-sensors = <&sc 573 thermal-sensors = <&scpi_sensors0 3>;
766 trips { <<
767 soc_crit0: tri <<
768 temper <<
769 hyster <<
770 type = <<
771 }; <<
772 }; <<
773 }; 574 };
774 575
775 big_cluster_thermal_zone: big- !! 576 big_cluster_thermal_zone: big-cluster {
776 polling-delay = <1000> 577 polling-delay = <1000>;
777 polling-delay-passive 578 polling-delay-passive = <100>;
778 thermal-sensors = <&sc 579 thermal-sensors = <&scpi_sensors0 21>;
779 status = "disabled"; 580 status = "disabled";
780 }; 581 };
781 582
782 little_cluster_thermal_zone: l !! 583 little_cluster_thermal_zone: little-cluster {
783 polling-delay = <1000> 584 polling-delay = <1000>;
784 polling-delay-passive 585 polling-delay-passive = <100>;
785 thermal-sensors = <&sc 586 thermal-sensors = <&scpi_sensors0 22>;
786 status = "disabled"; 587 status = "disabled";
787 }; 588 };
788 589
789 gpu0_thermal_zone: gpu0-therma !! 590 gpu0_thermal_zone: gpu0 {
790 polling-delay = <1000> 591 polling-delay = <1000>;
791 polling-delay-passive 592 polling-delay-passive = <100>;
792 thermal-sensors = <&sc 593 thermal-sensors = <&scpi_sensors0 23>;
793 status = "disabled"; 594 status = "disabled";
794 }; 595 };
795 596
796 gpu1_thermal_zone: gpu1-therma !! 597 gpu1_thermal_zone: gpu1 {
797 polling-delay = <1000> 598 polling-delay = <1000>;
798 polling-delay-passive 599 polling-delay-passive = <100>;
799 thermal-sensors = <&sc 600 thermal-sensors = <&scpi_sensors0 24>;
800 status = "disabled"; 601 status = "disabled";
801 }; 602 };
802 }; 603 };
803 604
804 smmu_dma: iommu@7fb00000 { 605 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a 606 compatible = "arm,mmu-401", "arm,smmu-v1";
806 reg = <0x0 0x7fb00000 0x0 0x10 607 reg = <0x0 0x7fb00000 0x0 0x10000>;
807 interrupts = <GIC_SPI 95 IRQ_T 608 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 95 IRQ_T 609 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
809 #iommu-cells = <1>; 610 #iommu-cells = <1>;
810 #global-interrupts = <1>; 611 #global-interrupts = <1>;
811 dma-coherent; 612 dma-coherent;
>> 613 status = "disabled";
812 }; 614 };
813 615
814 smmu_hdlcd1: iommu@7fb10000 { 616 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a 617 compatible = "arm,mmu-401", "arm,smmu-v1";
816 reg = <0x0 0x7fb10000 0x0 0x10 618 reg = <0x0 0x7fb10000 0x0 0x10000>;
817 interrupts = <GIC_SPI 99 IRQ_T 619 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 99 IRQ_T 620 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
819 #iommu-cells = <1>; 621 #iommu-cells = <1>;
820 #global-interrupts = <1>; 622 #global-interrupts = <1>;
821 }; 623 };
822 624
823 smmu_hdlcd0: iommu@7fb20000 { 625 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a 626 compatible = "arm,mmu-401", "arm,smmu-v1";
825 reg = <0x0 0x7fb20000 0x0 0x10 627 reg = <0x0 0x7fb20000 0x0 0x10000>;
826 interrupts = <GIC_SPI 97 IRQ_T 628 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 97 IRQ_T 629 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
828 #iommu-cells = <1>; 630 #iommu-cells = <1>;
829 #global-interrupts = <1>; 631 #global-interrupts = <1>;
830 }; 632 };
831 633
832 smmu_usb: iommu@7fb30000 { 634 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a 635 compatible = "arm,mmu-401", "arm,smmu-v1";
834 reg = <0x0 0x7fb30000 0x0 0x10 636 reg = <0x0 0x7fb30000 0x0 0x10000>;
835 interrupts = <GIC_SPI 101 IRQ_ 637 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 101 IRQ_ 638 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
837 #iommu-cells = <1>; 639 #iommu-cells = <1>;
838 #global-interrupts = <1>; 640 #global-interrupts = <1>;
839 dma-coherent; 641 dma-coherent;
840 }; 642 };
841 643
842 dma-controller@7ff00000 { !! 644 dma@7ff00000 {
843 compatible = "arm,pl330", "arm 645 compatible = "arm,pl330", "arm,primecell";
844 reg = <0x0 0x7ff00000 0 0x1000 646 reg = <0x0 0x7ff00000 0 0x1000>;
845 #dma-cells = <1>; 647 #dma-cells = <1>;
>> 648 #dma-channels = <8>;
>> 649 #dma-requests = <32>;
846 interrupts = <GIC_SPI 88 IRQ_T 650 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 89 IRQ_T 651 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 90 IRQ_T 652 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 91 IRQ_T 653 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 92 IRQ_T 654 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 108 IRQ_ 655 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 109 IRQ_ 656 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 110 IRQ_ 657 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 111 IRQ_ 658 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 iommus = <&smmu_dma 0>, 659 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>, 660 <&smmu_dma 1>,
857 <&smmu_dma 2>, 661 <&smmu_dma 2>,
858 <&smmu_dma 3>, 662 <&smmu_dma 3>,
859 <&smmu_dma 4>, 663 <&smmu_dma 4>,
860 <&smmu_dma 5>, 664 <&smmu_dma 5>,
861 <&smmu_dma 6>, 665 <&smmu_dma 6>,
862 <&smmu_dma 7>, 666 <&smmu_dma 7>,
863 <&smmu_dma 8>; 667 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>; 668 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk"; 669 clock-names = "apb_pclk";
866 }; 670 };
867 671
868 hdlcd@7ff50000 { 672 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd"; 673 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>; 674 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T 675 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 iommus = <&smmu_hdlcd1 0>; 676 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>; 677 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk"; 678 clock-names = "pxlclk";
875 679
876 port { 680 port {
877 hdlcd1_output: endpoin 681 hdlcd1_output: endpoint {
878 remote-endpoin 682 remote-endpoint = <&tda998x_1_input>;
879 }; 683 };
880 }; 684 };
881 }; 685 };
882 686
883 hdlcd@7ff60000 { 687 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd"; 688 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>; 689 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T 690 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
887 iommus = <&smmu_hdlcd0 0>; 691 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>; 692 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk"; 693 clock-names = "pxlclk";
890 694
891 port { 695 port {
892 hdlcd0_output: endpoin 696 hdlcd0_output: endpoint {
893 remote-endpoin 697 remote-endpoint = <&tda998x_0_input>;
894 }; 698 };
895 }; 699 };
896 }; 700 };
897 701
898 soc_uart0: serial@7ff80000 { !! 702 soc_uart0: uart@7ff80000 {
899 compatible = "arm,pl011", "arm 703 compatible = "arm,pl011", "arm,primecell";
900 reg = <0x0 0x7ff80000 0x0 0x10 704 reg = <0x0 0x7ff80000 0x0 0x1000>;
901 interrupts = <GIC_SPI 83 IRQ_T 705 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&soc_uartclk>, <&soc 706 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
903 clock-names = "uartclk", "apb_ 707 clock-names = "uartclk", "apb_pclk";
904 }; 708 };
905 709
906 i2c@7ffa0000 { 710 i2c@7ffa0000 {
907 compatible = "snps,designware- 711 compatible = "snps,designware-i2c";
908 reg = <0x0 0x7ffa0000 0x0 0x10 712 reg = <0x0 0x7ffa0000 0x0 0x1000>;
909 #address-cells = <1>; 713 #address-cells = <1>;
910 #size-cells = <0>; 714 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_ 715 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
912 clock-frequency = <400000>; 716 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>; 717 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>; 718 clocks = <&soc_smc50mhz>;
915 719
916 hdmi-transmitter@70 { 720 hdmi-transmitter@70 {
917 compatible = "nxp,tda9 721 compatible = "nxp,tda998x";
918 reg = <0x70>; 722 reg = <0x70>;
919 port { 723 port {
920 tda998x_0_inpu 724 tda998x_0_input: endpoint {
921 remote 725 remote-endpoint = <&hdlcd0_output>;
922 }; 726 };
923 }; 727 };
924 }; 728 };
925 729
926 hdmi-transmitter@71 { 730 hdmi-transmitter@71 {
927 compatible = "nxp,tda9 731 compatible = "nxp,tda998x";
928 reg = <0x71>; 732 reg = <0x71>;
929 port { 733 port {
930 tda998x_1_inpu 734 tda998x_1_input: endpoint {
931 remote 735 remote-endpoint = <&hdlcd1_output>;
932 }; 736 };
933 }; 737 };
934 }; 738 };
935 }; 739 };
936 740
937 usb@7ffb0000 { !! 741 ohci@7ffb0000 {
938 compatible = "generic-ohci"; 742 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10 743 reg = <0x0 0x7ffb0000 0x0 0x10000>;
940 interrupts = <GIC_SPI 116 IRQ_ 744 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
941 iommus = <&smmu_usb 0>; 745 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>; 746 clocks = <&soc_usb48mhz>;
943 }; 747 };
944 748
945 usb@7ffc0000 { !! 749 ehci@7ffc0000 {
946 compatible = "generic-ehci"; 750 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10 751 reg = <0x0 0x7ffc0000 0x0 0x10000>;
948 interrupts = <GIC_SPI 117 IRQ_ 752 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
949 iommus = <&smmu_usb 0>; 753 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>; 754 clocks = <&soc_usb48mhz>;
951 }; 755 };
952 756
953 memory-controller@7ffd0000 { 757 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm 758 compatible = "arm,pl354", "arm,primecell";
955 reg = <0 0x7ffd0000 0 0x1000>; 759 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T 760 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 87 IRQ_T 761 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&soc_smc50mhz>; 762 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk"; 763 clock-names = "apb_pclk";
960 }; 764 };
961 765
962 memory@80000000 { 766 memory@80000000 {
963 device_type = "memory"; 767 device_type = "memory";
964 /* last 16MB of the first memo 768 /* last 16MB of the first memory area is reserved for secure world use by firmware */
965 reg = <0x00000000 0x80000000 0 769 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
966 <0x00000008 0x80000000 0 770 <0x00000008 0x80000000 0x1 0x80000000>;
967 }; 771 };
968 772
969 bus@8000000 { !! 773 smb@8000000 {
>> 774 compatible = "simple-bus";
>> 775 #address-cells = <2>;
>> 776 #size-cells = <1>;
>> 777 ranges = <0 0 0 0x08000000 0x04000000>,
>> 778 <1 0 0 0x14000000 0x04000000>,
>> 779 <2 0 0 0x18000000 0x04000000>,
>> 780 <3 0 0 0x1c000000 0x04000000>,
>> 781 <4 0 0 0x0c000000 0x04000000>,
>> 782 <5 0 0 0x10000000 0x04000000>;
>> 783
970 #interrupt-cells = <1>; 784 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>; 785 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0 !! 786 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
973 <0 0 1 &gic 0 !! 787 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
974 <0 0 2 &gic 0 !! 788 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 3 &gic 0 !! 789 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 4 &gic 0 !! 790 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 5 &gic 0 !! 791 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
978 <0 0 6 &gic 0 !! 792 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
979 <0 0 7 &gic 0 !! 793 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
980 <0 0 8 &gic 0 !! 794 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
981 <0 0 9 &gic 0 !! 795 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 10 &gic 0 !! 796 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 11 &gic 0 !! 797 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 12 &gic 0 !! 798 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
985 }; 799 };
986 800
987 site2: tlx-bus@60000000 { !! 801 site2: tlx@60000000 {
988 compatible = "simple-bus"; 802 compatible = "simple-bus";
989 #address-cells = <1>; 803 #address-cells = <1>;
990 #size-cells = <1>; 804 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100 805 ranges = <0 0 0x60000000 0x10000000>;
992 #interrupt-cells = <1>; 806 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>; 807 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI !! 808 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
995 }; 809 };
996 }; 810 };
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