1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi" 2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi" 3 #include "juno-motherboard.dtsi"
4 4
5 / { 5 / {
6 /* 6 /*
7 * Devices shared by all Juno boards 7 * Devices shared by all Juno boards
8 */ 8 */
9 9
10 memtimer: timer@2a810000 { 10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer- 11 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10 12 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>; 13 clock-frequency = <50000000>;
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 ranges = <0 0x0 0x2a820000 0x2 16 ranges = <0 0x0 0x2a820000 0x20000>;
17 status = "disabled"; 17 status = "disabled";
18 frame@2a830000 { 18 frame@2a830000 {
19 frame-number = <1>; 19 frame-number = <1>;
20 interrupts = <GIC_SPI 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
21 reg = <0x10000 0x10000 21 reg = <0x10000 0x10000>;
22 }; 22 };
23 }; 23 };
24 24
25 mailbox: mhu@2b1f0000 { 25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p 26 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x10 27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_T 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_T !! 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 <GIC_SPI 37 IRQ_T !! 30 interrupt-names = "mhu_lpri_rx",
>> 31 "mhu_hpri_rx";
31 #mbox-cells = <1>; 32 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>; 33 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk"; 34 clock-names = "apb_pclk";
34 }; 35 };
35 36
36 smmu_gpu: iommu@2b400000 { 37 smmu_gpu: iommu@2b400000 {
37 compatible = "arm,mmu-400", "a 38 compatible = "arm,mmu-400", "arm,smmu-v1";
38 reg = <0x0 0x2b400000 0x0 0x10 39 reg = <0x0 0x2b400000 0x0 0x10000>;
39 interrupts = <GIC_SPI 38 IRQ_T 40 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 38 IRQ_T 41 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
41 #iommu-cells = <1>; 42 #iommu-cells = <1>;
42 #global-interrupts = <1>; 43 #global-interrupts = <1>;
43 power-domains = <&scpi_devpd 1 44 power-domains = <&scpi_devpd 1>;
44 dma-coherent; 45 dma-coherent;
45 status = "disabled"; 46 status = "disabled";
46 }; 47 };
47 48
48 smmu_pcie: iommu@2b500000 { 49 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a 50 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b500000 0x0 0x10 51 reg = <0x0 0x2b500000 0x0 0x10000>;
51 interrupts = <GIC_SPI 40 IRQ_T 52 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 40 IRQ_T 53 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
53 #iommu-cells = <1>; 54 #iommu-cells = <1>;
54 #global-interrupts = <1>; 55 #global-interrupts = <1>;
55 dma-coherent; 56 dma-coherent;
56 status = "disabled"; 57 status = "disabled";
57 }; 58 };
58 59
59 smmu_etr: iommu@2b600000 { 60 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a 61 compatible = "arm,mmu-401", "arm,smmu-v1";
61 reg = <0x0 0x2b600000 0x0 0x10 62 reg = <0x0 0x2b600000 0x0 0x10000>;
62 interrupts = <GIC_SPI 42 IRQ_T 63 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 42 IRQ_T 64 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
64 #iommu-cells = <1>; 65 #iommu-cells = <1>;
65 #global-interrupts = <1>; 66 #global-interrupts = <1>;
66 dma-coherent; 67 dma-coherent;
67 power-domains = <&scpi_devpd 0 68 power-domains = <&scpi_devpd 0>;
68 }; 69 };
69 70
70 gic: interrupt-controller@2c010000 { 71 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a 72 compatible = "arm,gic-400", "arm,cortex-a15-gic";
72 reg = <0x0 0x2c010000 0 0x1000 73 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000 74 <0x0 0x2c02f000 0 0x2000>,
74 <0x0 0x2c04f000 0 0x2000 75 <0x0 0x2c04f000 0 0x2000>,
75 <0x0 0x2c06f000 0 0x2000 76 <0x0 0x2c06f000 0 0x2000>;
76 #address-cells = <1>; 77 #address-cells = <1>;
77 #interrupt-cells = <3>; 78 #interrupt-cells = <3>;
78 #size-cells = <1>; 79 #size-cells = <1>;
79 interrupt-controller; 80 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C 81 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
81 ranges = <0 0 0x2c1c0000 0x400 82 ranges = <0 0 0x2c1c0000 0x40000>;
82 83
83 v2m_0: v2m@0 { 84 v2m_0: v2m@0 {
84 compatible = "arm,gic- 85 compatible = "arm,gic-v2m-frame";
85 msi-controller; 86 msi-controller;
86 reg = <0 0x10000>; 87 reg = <0 0x10000>;
87 }; 88 };
88 89
89 v2m@10000 { 90 v2m@10000 {
90 compatible = "arm,gic- 91 compatible = "arm,gic-v2m-frame";
91 msi-controller; 92 msi-controller;
92 reg = <0x10000 0x10000 93 reg = <0x10000 0x10000>;
93 }; 94 };
94 95
95 v2m@20000 { 96 v2m@20000 {
96 compatible = "arm,gic- 97 compatible = "arm,gic-v2m-frame";
97 msi-controller; 98 msi-controller;
98 reg = <0x20000 0x10000 99 reg = <0x20000 0x10000>;
99 }; 100 };
100 101
101 v2m@30000 { 102 v2m@30000 {
102 compatible = "arm,gic- 103 compatible = "arm,gic-v2m-frame";
103 msi-controller; 104 msi-controller;
104 reg = <0x30000 0x10000 105 reg = <0x30000 0x10000>;
105 }; 106 };
106 }; 107 };
107 108
108 timer { 109 timer {
109 compatible = "arm,armv8-timer" 110 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_ 111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_ 112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_ 113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_ 114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
114 }; 115 };
115 116
116 /* 117 /*
117 * Juno TRMs specify the size for thes 118 * Juno TRMs specify the size for these coresight components as 64K.
118 * The actual size is just 4K though 6 119 * The actual size is just 4K though 64K is reserved. Access to the
119 * unmapped reserved region results in 120 * unmapped reserved region results in a DECERR response.
120 */ 121 */
121 etf_sys0: etf@20010000 { /* etf0 */ !! 122 etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm 123 compatible = "arm,coresight-tmc", "arm,primecell";
123 reg = <0 0x20010000 0 0x1000>; 124 reg = <0 0x20010000 0 0x1000>;
124 125
125 clocks = <&soc_smc50mhz>; 126 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk"; 127 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0 128 power-domains = <&scpi_devpd 0>;
128 129
129 in-ports { 130 in-ports {
130 port { 131 port {
131 etf0_in_port: 132 etf0_in_port: endpoint {
132 remote 133 remote-endpoint = <&main_funnel_out_port>;
133 }; 134 };
134 }; 135 };
135 }; 136 };
136 137
137 out-ports { 138 out-ports {
138 port { 139 port {
139 etf0_out_port: 140 etf0_out_port: endpoint {
140 }; 141 };
141 }; 142 };
142 }; 143 };
143 }; 144 };
144 145
145 tpiu_sys: tpiu@20030000 { !! 146 tpiu@20030000 {
146 compatible = "arm,coresight-tp 147 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0 0x20030000 0 0x1000>; 148 reg = <0 0x20030000 0 0x1000>;
148 149
149 clocks = <&soc_smc50mhz>; 150 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk"; 151 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0 152 power-domains = <&scpi_devpd 0>;
152 in-ports { 153 in-ports {
153 port { 154 port {
154 tpiu_in_port: 155 tpiu_in_port: endpoint {
155 remote 156 remote-endpoint = <&replicator_out_port0>;
156 }; 157 };
157 }; 158 };
158 }; 159 };
159 }; 160 };
160 161
161 /* main funnel on Juno r0, cssys0 funn 162 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
162 main_funnel: funnel@20040000 { 163 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy 164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
164 reg = <0 0x20040000 0 0x1000>; 165 reg = <0 0x20040000 0 0x1000>;
165 166
166 clocks = <&soc_smc50mhz>; 167 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk"; 168 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0 169 power-domains = <&scpi_devpd 0>;
169 170
170 out-ports { 171 out-ports {
171 port { 172 port {
172 main_funnel_ou 173 main_funnel_out_port: endpoint {
173 remote 174 remote-endpoint = <&etf0_in_port>;
174 }; 175 };
175 }; 176 };
176 }; 177 };
177 178
178 main_funnel_in_ports: in-ports 179 main_funnel_in_ports: in-ports {
179 #address-cells = <1>; 180 #address-cells = <1>;
180 #size-cells = <0>; 181 #size-cells = <0>;
181 182
182 port@0 { 183 port@0 {
183 reg = <0>; 184 reg = <0>;
184 main_funnel_in 185 main_funnel_in_port0: endpoint {
185 remote 186 remote-endpoint = <&cluster0_funnel_out_port>;
186 }; 187 };
187 }; 188 };
188 189
189 port@1 { 190 port@1 {
190 reg = <1>; 191 reg = <1>;
191 main_funnel_in 192 main_funnel_in_port1: endpoint {
192 remote 193 remote-endpoint = <&cluster1_funnel_out_port>;
193 }; 194 };
194 }; 195 };
195 }; 196 };
196 }; 197 };
197 198
198 etr_sys: etr@20070000 { !! 199 etr@20070000 {
199 compatible = "arm,coresight-tm 200 compatible = "arm,coresight-tmc", "arm,primecell";
200 reg = <0 0x20070000 0 0x1000>; 201 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>; 202 iommus = <&smmu_etr 0>;
202 203
203 clocks = <&soc_smc50mhz>; 204 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk"; 205 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0 206 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather; 207 arm,scatter-gather;
207 in-ports { 208 in-ports {
208 port { 209 port {
209 etr_in_port: e 210 etr_in_port: endpoint {
210 remote 211 remote-endpoint = <&replicator_out_port1>;
211 }; 212 };
212 }; 213 };
213 }; 214 };
214 }; 215 };
215 216
216 stm_sys: stm@20100000 { !! 217 stm@20100000 {
217 compatible = "arm,coresight-st 218 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>, 219 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000 220 <0 0x28000000 0 0x1000000>;
220 reg-names = "stm-base", "stm-s 221 reg-names = "stm-base", "stm-stimulus-base";
221 222
222 clocks = <&soc_smc50mhz>; 223 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk"; 224 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0 225 power-domains = <&scpi_devpd 0>;
225 out-ports { 226 out-ports {
226 port { 227 port {
227 stm_out_port: 228 stm_out_port: endpoint {
228 }; 229 };
229 }; 230 };
230 }; 231 };
231 }; 232 };
232 233
233 replicator@20120000 { 234 replicator@20120000 {
234 compatible = "arm,coresight-dy 235 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
235 reg = <0 0x20120000 0 0x1000>; 236 reg = <0 0x20120000 0 0x1000>;
236 237
237 clocks = <&soc_smc50mhz>; 238 clocks = <&soc_smc50mhz>;
238 clock-names = "apb_pclk"; 239 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0 240 power-domains = <&scpi_devpd 0>;
240 241
241 out-ports { 242 out-ports {
242 #address-cells = <1>; 243 #address-cells = <1>;
243 #size-cells = <0>; 244 #size-cells = <0>;
244 245
245 /* replicator output p 246 /* replicator output ports */
246 port@0 { 247 port@0 {
247 reg = <0>; 248 reg = <0>;
248 replicator_out 249 replicator_out_port0: endpoint {
249 remote 250 remote-endpoint = <&tpiu_in_port>;
250 }; 251 };
251 }; 252 };
252 253
253 port@1 { 254 port@1 {
254 reg = <1>; 255 reg = <1>;
255 replicator_out 256 replicator_out_port1: endpoint {
256 remote 257 remote-endpoint = <&etr_in_port>;
257 }; 258 };
258 }; 259 };
259 }; 260 };
260 in-ports { 261 in-ports {
261 port { 262 port {
262 replicator_in_ 263 replicator_in_port0: endpoint {
263 }; 264 };
264 }; 265 };
265 }; 266 };
266 }; 267 };
267 268
268 cpu_debug0: cpu-debug@22010000 { 269 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp 270 compatible = "arm,coresight-cpu-debug", "arm,primecell";
270 reg = <0x0 0x22010000 0x0 0x10 271 reg = <0x0 0x22010000 0x0 0x1000>;
271 272
272 clocks = <&soc_smc50mhz>; 273 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk"; 274 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0 275 power-domains = <&scpi_devpd 0>;
275 }; 276 };
276 277
277 etm0: etm@22040000 { 278 etm0: etm@22040000 {
278 compatible = "arm,coresight-et 279 compatible = "arm,coresight-etm4x", "arm,primecell";
279 reg = <0 0x22040000 0 0x1000>; 280 reg = <0 0x22040000 0 0x1000>;
280 281
281 clocks = <&soc_smc50mhz>; 282 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk"; 283 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0 284 power-domains = <&scpi_devpd 0>;
284 out-ports { 285 out-ports {
285 port { 286 port {
286 cluster0_etm0_ 287 cluster0_etm0_out_port: endpoint {
287 remote 288 remote-endpoint = <&cluster0_funnel_in_port0>;
288 }; 289 };
289 }; 290 };
290 }; 291 };
291 }; 292 };
292 293
293 cti0: cti@22020000 { <<
294 compatible = "arm,coresight-ct <<
295 "arm,primecell"; <<
296 reg = <0 0x22020000 0 0x1000>; <<
297 <<
298 clocks = <&soc_smc50mhz>; <<
299 clock-names = "apb_pclk"; <<
300 power-domains = <&scpi_devpd 0 <<
301 <<
302 arm,cs-dev-assoc = <&etm0>; <<
303 }; <<
304 <<
305 funnel@220c0000 { /* cluster0 funnel * 294 funnel@220c0000 { /* cluster0 funnel */
306 compatible = "arm,coresight-dy 295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
307 reg = <0 0x220c0000 0 0x1000>; 296 reg = <0 0x220c0000 0 0x1000>;
308 297
309 clocks = <&soc_smc50mhz>; 298 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk"; 299 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0 300 power-domains = <&scpi_devpd 0>;
312 out-ports { 301 out-ports {
313 port { 302 port {
314 cluster0_funne 303 cluster0_funnel_out_port: endpoint {
315 remote 304 remote-endpoint = <&main_funnel_in_port0>;
316 }; 305 };
317 }; 306 };
318 }; 307 };
319 308
320 in-ports { 309 in-ports {
321 #address-cells = <1>; 310 #address-cells = <1>;
322 #size-cells = <0>; 311 #size-cells = <0>;
323 312
324 port@0 { 313 port@0 {
325 reg = <0>; 314 reg = <0>;
326 cluster0_funne 315 cluster0_funnel_in_port0: endpoint {
327 remote 316 remote-endpoint = <&cluster0_etm0_out_port>;
328 }; 317 };
329 }; 318 };
330 319
331 port@1 { 320 port@1 {
332 reg = <1>; 321 reg = <1>;
333 cluster0_funne 322 cluster0_funnel_in_port1: endpoint {
334 remote 323 remote-endpoint = <&cluster0_etm1_out_port>;
335 }; 324 };
336 }; 325 };
337 }; 326 };
338 }; 327 };
339 328
340 cpu_debug1: cpu-debug@22110000 { 329 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp 330 compatible = "arm,coresight-cpu-debug", "arm,primecell";
342 reg = <0x0 0x22110000 0x0 0x10 331 reg = <0x0 0x22110000 0x0 0x1000>;
343 332
344 clocks = <&soc_smc50mhz>; 333 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk"; 334 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0 335 power-domains = <&scpi_devpd 0>;
347 }; 336 };
348 337
349 etm1: etm@22140000 { 338 etm1: etm@22140000 {
350 compatible = "arm,coresight-et 339 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0x22140000 0 0x1000>; 340 reg = <0 0x22140000 0 0x1000>;
352 341
353 clocks = <&soc_smc50mhz>; 342 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk"; 343 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0 344 power-domains = <&scpi_devpd 0>;
356 out-ports { 345 out-ports {
357 port { 346 port {
358 cluster0_etm1_ 347 cluster0_etm1_out_port: endpoint {
359 remote 348 remote-endpoint = <&cluster0_funnel_in_port1>;
360 }; 349 };
361 }; 350 };
362 }; 351 };
363 }; 352 };
364 353
365 cti1: cti@22120000 { <<
366 compatible = "arm,coresight-ct <<
367 "arm,primecell"; <<
368 reg = <0 0x22120000 0 0x1000>; <<
369 <<
370 clocks = <&soc_smc50mhz>; <<
371 clock-names = "apb_pclk"; <<
372 power-domains = <&scpi_devpd 0 <<
373 <<
374 arm,cs-dev-assoc = <&etm1>; <<
375 }; <<
376 <<
377 cpu_debug2: cpu-debug@23010000 { 354 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp 355 compatible = "arm,coresight-cpu-debug", "arm,primecell";
379 reg = <0x0 0x23010000 0x0 0x10 356 reg = <0x0 0x23010000 0x0 0x1000>;
380 357
381 clocks = <&soc_smc50mhz>; 358 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk"; 359 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0 360 power-domains = <&scpi_devpd 0>;
384 }; 361 };
385 362
386 etm2: etm@23040000 { 363 etm2: etm@23040000 {
387 compatible = "arm,coresight-et 364 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0 0x23040000 0 0x1000>; 365 reg = <0 0x23040000 0 0x1000>;
389 366
390 clocks = <&soc_smc50mhz>; 367 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk"; 368 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0 369 power-domains = <&scpi_devpd 0>;
393 out-ports { 370 out-ports {
394 port { 371 port {
395 cluster1_etm0_ 372 cluster1_etm0_out_port: endpoint {
396 remote 373 remote-endpoint = <&cluster1_funnel_in_port0>;
397 }; 374 };
398 }; 375 };
399 }; 376 };
400 }; 377 };
401 378
402 cti2: cti@23020000 { <<
403 compatible = "arm,coresight-ct <<
404 "arm,primecell"; <<
405 reg = <0 0x23020000 0 0x1000>; <<
406 <<
407 clocks = <&soc_smc50mhz>; <<
408 clock-names = "apb_pclk"; <<
409 power-domains = <&scpi_devpd 0 <<
410 <<
411 arm,cs-dev-assoc = <&etm2>; <<
412 }; <<
413 <<
414 funnel@230c0000 { /* cluster1 funnel * 379 funnel@230c0000 { /* cluster1 funnel */
415 compatible = "arm,coresight-dy 380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
416 reg = <0 0x230c0000 0 0x1000>; 381 reg = <0 0x230c0000 0 0x1000>;
417 382
418 clocks = <&soc_smc50mhz>; 383 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk"; 384 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0 385 power-domains = <&scpi_devpd 0>;
421 out-ports { 386 out-ports {
422 port { 387 port {
423 cluster1_funne 388 cluster1_funnel_out_port: endpoint {
424 remote 389 remote-endpoint = <&main_funnel_in_port1>;
425 }; 390 };
426 }; 391 };
427 }; 392 };
428 393
429 in-ports { 394 in-ports {
430 #address-cells = <1>; 395 #address-cells = <1>;
431 #size-cells = <0>; 396 #size-cells = <0>;
432 397
433 port@0 { 398 port@0 {
434 reg = <0>; 399 reg = <0>;
435 cluster1_funne 400 cluster1_funnel_in_port0: endpoint {
436 remote 401 remote-endpoint = <&cluster1_etm0_out_port>;
437 }; 402 };
438 }; 403 };
439 404
440 port@1 { 405 port@1 {
441 reg = <1>; 406 reg = <1>;
442 cluster1_funne 407 cluster1_funnel_in_port1: endpoint {
443 remote 408 remote-endpoint = <&cluster1_etm1_out_port>;
444 }; 409 };
445 }; 410 };
446 port@2 { 411 port@2 {
447 reg = <2>; 412 reg = <2>;
448 cluster1_funne 413 cluster1_funnel_in_port2: endpoint {
449 remote 414 remote-endpoint = <&cluster1_etm2_out_port>;
450 }; 415 };
451 }; 416 };
452 port@3 { 417 port@3 {
453 reg = <3>; 418 reg = <3>;
454 cluster1_funne 419 cluster1_funnel_in_port3: endpoint {
455 remote 420 remote-endpoint = <&cluster1_etm3_out_port>;
456 }; 421 };
457 }; 422 };
458 }; 423 };
459 }; 424 };
460 425
461 cpu_debug3: cpu-debug@23110000 { 426 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp 427 compatible = "arm,coresight-cpu-debug", "arm,primecell";
463 reg = <0x0 0x23110000 0x0 0x10 428 reg = <0x0 0x23110000 0x0 0x1000>;
464 429
465 clocks = <&soc_smc50mhz>; 430 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk"; 431 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0 432 power-domains = <&scpi_devpd 0>;
468 }; 433 };
469 434
470 etm3: etm@23140000 { 435 etm3: etm@23140000 {
471 compatible = "arm,coresight-et 436 compatible = "arm,coresight-etm4x", "arm,primecell";
472 reg = <0 0x23140000 0 0x1000>; 437 reg = <0 0x23140000 0 0x1000>;
473 438
474 clocks = <&soc_smc50mhz>; 439 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk"; 440 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0 441 power-domains = <&scpi_devpd 0>;
477 out-ports { 442 out-ports {
478 port { 443 port {
479 cluster1_etm1_ 444 cluster1_etm1_out_port: endpoint {
480 remote 445 remote-endpoint = <&cluster1_funnel_in_port1>;
481 }; 446 };
482 }; 447 };
483 }; 448 };
484 }; 449 };
485 450
486 cti3: cti@23120000 { <<
487 compatible = "arm,coresight-ct <<
488 "arm,primecell"; <<
489 reg = <0 0x23120000 0 0x1000>; <<
490 <<
491 clocks = <&soc_smc50mhz>; <<
492 clock-names = "apb_pclk"; <<
493 power-domains = <&scpi_devpd 0 <<
494 <<
495 arm,cs-dev-assoc = <&etm3>; <<
496 }; <<
497 <<
498 cpu_debug4: cpu-debug@23210000 { 451 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp 452 compatible = "arm,coresight-cpu-debug", "arm,primecell";
500 reg = <0x0 0x23210000 0x0 0x10 453 reg = <0x0 0x23210000 0x0 0x1000>;
501 454
502 clocks = <&soc_smc50mhz>; 455 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk"; 456 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0 457 power-domains = <&scpi_devpd 0>;
505 }; 458 };
506 459
507 etm4: etm@23240000 { 460 etm4: etm@23240000 {
508 compatible = "arm,coresight-et 461 compatible = "arm,coresight-etm4x", "arm,primecell";
509 reg = <0 0x23240000 0 0x1000>; 462 reg = <0 0x23240000 0 0x1000>;
510 463
511 clocks = <&soc_smc50mhz>; 464 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk"; 465 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0 466 power-domains = <&scpi_devpd 0>;
514 out-ports { 467 out-ports {
515 port { 468 port {
516 cluster1_etm2_ 469 cluster1_etm2_out_port: endpoint {
517 remote 470 remote-endpoint = <&cluster1_funnel_in_port2>;
518 }; 471 };
519 }; 472 };
520 }; 473 };
521 }; 474 };
522 475
523 cti4: cti@23220000 { <<
524 compatible = "arm,coresight-ct <<
525 "arm,primecell"; <<
526 reg = <0 0x23220000 0 0x1000>; <<
527 <<
528 clocks = <&soc_smc50mhz>; <<
529 clock-names = "apb_pclk"; <<
530 power-domains = <&scpi_devpd 0 <<
531 <<
532 arm,cs-dev-assoc = <&etm4>; <<
533 }; <<
534 <<
535 cpu_debug5: cpu-debug@23310000 { 476 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp 477 compatible = "arm,coresight-cpu-debug", "arm,primecell";
537 reg = <0x0 0x23310000 0x0 0x10 478 reg = <0x0 0x23310000 0x0 0x1000>;
538 479
539 clocks = <&soc_smc50mhz>; 480 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk"; 481 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0 482 power-domains = <&scpi_devpd 0>;
542 }; 483 };
543 484
544 etm5: etm@23340000 { 485 etm5: etm@23340000 {
545 compatible = "arm,coresight-et 486 compatible = "arm,coresight-etm4x", "arm,primecell";
546 reg = <0 0x23340000 0 0x1000>; 487 reg = <0 0x23340000 0 0x1000>;
547 488
548 clocks = <&soc_smc50mhz>; 489 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk"; 490 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0 491 power-domains = <&scpi_devpd 0>;
551 out-ports { 492 out-ports {
552 port { 493 port {
553 cluster1_etm3_ 494 cluster1_etm3_out_port: endpoint {
554 remote 495 remote-endpoint = <&cluster1_funnel_in_port3>;
555 }; 496 };
556 }; 497 };
557 }; 498 };
558 }; 499 };
559 500
560 cti5: cti@23320000 { <<
561 compatible = "arm,coresight-ct <<
562 "arm,primecell"; <<
563 reg = <0 0x23320000 0 0x1000>; <<
564 <<
565 clocks = <&soc_smc50mhz>; <<
566 clock-names = "apb_pclk"; <<
567 power-domains = <&scpi_devpd 0 <<
568 <<
569 arm,cs-dev-assoc = <&etm5>; <<
570 }; <<
571 <<
572 cti_sys0: cti@20020000 { /* sys_cti_0 <<
573 compatible = "arm,coresight-ct <<
574 reg = <0 0x20020000 0 0x1000>; <<
575 <<
576 clocks = <&soc_smc50mhz>; <<
577 clock-names = "apb_pclk"; <<
578 power-domains = <&scpi_devpd 0 <<
579 <<
580 #address-cells = <1>; <<
581 #size-cells = <0>; <<
582 <<
583 trig-conns@0 { <<
584 reg = <0>; <<
585 arm,trig-in-sigs = <2 <<
586 arm,trig-in-types = <S <<
587 arm,trig-out-sigs = <0 <<
588 arm,trig-out-types = < <<
589 arm,cs-dev-assoc = <&e <<
590 }; <<
591 <<
592 trig-conns@1 { <<
593 reg = <1>; <<
594 arm,trig-in-sigs = <0 <<
595 arm,trig-in-types = <S <<
596 arm,trig-out-sigs = <7 <<
597 arm,trig-out-types = < <<
598 arm,cs-dev-assoc = <&e <<
599 }; <<
600 <<
601 trig-conns@2 { <<
602 reg = <2>; <<
603 arm,trig-in-sigs = <4 <<
604 arm,trig-in-types = <S <<
605 STM <<
606 arm,trig-out-sigs = <4 <<
607 arm,trig-out-types = < <<
608 arm,cs-dev-assoc = <&s <<
609 }; <<
610 <<
611 trig-conns@3 { <<
612 reg = <3>; <<
613 arm,trig-out-sigs = <2 <<
614 arm,trig-out-types = < <<
615 arm,cs-dev-assoc = <&t <<
616 }; <<
617 }; <<
618 <<
619 cti_sys1: cti@20110000 { /* sys_cti_1 <<
620 compatible = "arm,coresight-ct <<
621 reg = <0 0x20110000 0 0x1000>; <<
622 <<
623 clocks = <&soc_smc50mhz>; <<
624 clock-names = "apb_pclk"; <<
625 power-domains = <&scpi_devpd 0 <<
626 <<
627 #address-cells = <1>; <<
628 #size-cells = <0>; <<
629 <<
630 trig-conns@0 { <<
631 reg = <0>; <<
632 arm,trig-in-sigs = <0> <<
633 arm,trig-in-types = <G <<
634 arm,trig-out-sigs = <0 <<
635 arm,trig-out-types = < <<
636 arm,trig-conn-name = " <<
637 }; <<
638 <<
639 trig-conns@1 { <<
640 reg = <1>; <<
641 arm,trig-out-sigs = <2 <<
642 arm,trig-out-types = < <<
643 arm,trig-conn-name = " <<
644 }; <<
645 <<
646 trig-conns@2 { <<
647 reg = <2>; <<
648 arm,trig-out-sigs = <1 <<
649 arm,trig-out-types = < <<
650 arm,trig-conn-name = " <<
651 }; <<
652 }; <<
653 <<
654 gpu: gpu@2d000000 { 501 gpu: gpu@2d000000 {
655 compatible = "arm,juno-mali", 502 compatible = "arm,juno-mali", "arm,mali-t624";
656 reg = <0 0x2d000000 0 0x10000> 503 reg = <0 0x2d000000 0 0x10000>;
657 interrupts = <GIC_SPI 33 IRQ_T 504 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 34 IRQ_T 505 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 32 IRQ_T 506 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "job", "mmu" 507 interrupt-names = "job", "mmu", "gpu";
661 clocks = <&scpi_dvfs 2>; 508 clocks = <&scpi_dvfs 2>;
662 power-domains = <&scpi_devpd 1 509 power-domains = <&scpi_devpd 1>;
663 dma-coherent; 510 dma-coherent;
664 /* The SMMU is only really of 511 /* The SMMU is only really of interest to bare-metal hypervisors */
665 /* iommus = <&smmu_gpu 0>; */ 512 /* iommus = <&smmu_gpu 0>; */
>> 513 status = "disabled";
666 }; 514 };
667 515
668 sram: sram@2e000000 { 516 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns 517 compatible = "arm,juno-sram-ns", "mmio-sram";
670 reg = <0x0 0x2e000000 0x0 0x80 518 reg = <0x0 0x2e000000 0x0 0x8000>;
671 519
672 #address-cells = <1>; 520 #address-cells = <1>;
673 #size-cells = <1>; 521 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8 522 ranges = <0 0x0 0x2e000000 0x8000>;
675 523
676 cpu_scp_lpri: scp-sram@0 { 524 cpu_scp_lpri: scp-sram@0 {
677 compatible = "arm,juno 525 compatible = "arm,juno-scp-shmem";
678 reg = <0x0 0x200>; 526 reg = <0x0 0x200>;
679 }; 527 };
680 528
681 cpu_scp_hpri: scp-sram@200 { 529 cpu_scp_hpri: scp-sram@200 {
682 compatible = "arm,juno 530 compatible = "arm,juno-scp-shmem";
683 reg = <0x200 0x200>; 531 reg = <0x200 0x200>;
684 }; 532 };
685 }; 533 };
686 534
687 pcie_ctlr: pcie@40000000 { 535 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie 536 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
689 device_type = "pci"; 537 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000 538 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
691 bus-range = <0 255>; 539 bus-range = <0 255>;
692 linux,pci-domain = <0>; 540 linux,pci-domain = <0>;
693 #address-cells = <3>; 541 #address-cells = <3>;
694 #size-cells = <2>; 542 #size-cells = <2>;
695 dma-coherent; 543 dma-coherent;
696 ranges = <0x01000000 0x00 0x00 544 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
697 <0x02000000 0x00 0x50 545 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
698 <0x42000000 0x40 0x00 546 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
699 /* Standard AXI Translation en <<
700 dma-ranges = <0x02000000 0x0 0 <<
701 <0x43000000 0x8 0 <<
702 #interrupt-cells = <1>; 547 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7> 548 interrupt-map-mask = <0 0 0 7>;
704 interrupt-map = <0 0 0 1 &gic 549 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 0 2 &gic 550 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 0 3 &gic 551 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
707 <0 0 0 4 &gic 552 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
708 msi-parent = <&v2m_0>; 553 msi-parent = <&v2m_0>;
709 status = "disabled"; 554 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC 555 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
711 iommu-map = <0x0 &smmu_pcie 0x 556 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
712 }; 557 };
713 558
714 scpi { 559 scpi {
715 compatible = "arm,scpi"; 560 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>; 561 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>; 562 shmem = <&cpu_scp_hpri>;
718 563
719 clocks { 564 clocks {
720 compatible = "arm,scpi 565 compatible = "arm,scpi-clocks";
721 566
722 scpi_dvfs: clocks-0 { 567 scpi_dvfs: clocks-0 {
723 compatible = " 568 compatible = "arm,scpi-dvfs-clocks";
724 #clock-cells = 569 #clock-cells = <1>;
725 clock-indices 570 clock-indices = <0>, <1>, <2>;
726 clock-output-n 571 clock-output-names = "atlclk", "aplclk","gpuclk";
727 }; 572 };
728 scpi_clk: clocks-1 { 573 scpi_clk: clocks-1 {
729 compatible = " 574 compatible = "arm,scpi-variable-clocks";
730 #clock-cells = 575 #clock-cells = <1>;
731 clock-indices 576 clock-indices = <3>;
732 clock-output-n 577 clock-output-names = "pxlclk";
733 }; 578 };
734 }; 579 };
735 580
736 scpi_devpd: power-controller { 581 scpi_devpd: power-controller {
737 compatible = "arm,scpi 582 compatible = "arm,scpi-power-domains";
738 num-domains = <2>; 583 num-domains = <2>;
739 #power-domain-cells = 584 #power-domain-cells = <1>;
740 }; 585 };
741 586
742 scpi_sensors0: sensors { 587 scpi_sensors0: sensors {
743 compatible = "arm,scpi 588 compatible = "arm,scpi-sensors";
744 #thermal-sensor-cells 589 #thermal-sensor-cells = <1>;
745 }; 590 };
746 }; 591 };
747 592
748 thermal-zones { 593 thermal-zones {
749 pmic-thermal { !! 594 pmic {
750 polling-delay = <1000> 595 polling-delay = <1000>;
751 polling-delay-passive 596 polling-delay-passive = <100>;
752 thermal-sensors = <&sc 597 thermal-sensors = <&scpi_sensors0 0>;
753 trips { 598 trips {
754 pmic_crit0: tr 599 pmic_crit0: trip0 {
755 temper 600 temperature = <90000>;
756 hyster 601 hysteresis = <2000>;
757 type = 602 type = "critical";
758 }; 603 };
759 }; 604 };
760 }; 605 };
761 606
762 soc-thermal { !! 607 soc {
763 polling-delay = <1000> 608 polling-delay = <1000>;
764 polling-delay-passive 609 polling-delay-passive = <100>;
765 thermal-sensors = <&sc 610 thermal-sensors = <&scpi_sensors0 3>;
766 trips { 611 trips {
767 soc_crit0: tri 612 soc_crit0: trip0 {
768 temper 613 temperature = <80000>;
769 hyster 614 hysteresis = <2000>;
770 type = 615 type = "critical";
771 }; 616 };
772 }; 617 };
773 }; 618 };
774 619
775 big_cluster_thermal_zone: big- !! 620 big_cluster_thermal_zone: big-cluster {
776 polling-delay = <1000> 621 polling-delay = <1000>;
777 polling-delay-passive 622 polling-delay-passive = <100>;
778 thermal-sensors = <&sc 623 thermal-sensors = <&scpi_sensors0 21>;
779 status = "disabled"; 624 status = "disabled";
780 }; 625 };
781 626
782 little_cluster_thermal_zone: l !! 627 little_cluster_thermal_zone: little-cluster {
783 polling-delay = <1000> 628 polling-delay = <1000>;
784 polling-delay-passive 629 polling-delay-passive = <100>;
785 thermal-sensors = <&sc 630 thermal-sensors = <&scpi_sensors0 22>;
786 status = "disabled"; 631 status = "disabled";
787 }; 632 };
788 633
789 gpu0_thermal_zone: gpu0-therma !! 634 gpu0_thermal_zone: gpu0 {
790 polling-delay = <1000> 635 polling-delay = <1000>;
791 polling-delay-passive 636 polling-delay-passive = <100>;
792 thermal-sensors = <&sc 637 thermal-sensors = <&scpi_sensors0 23>;
793 status = "disabled"; 638 status = "disabled";
794 }; 639 };
795 640
796 gpu1_thermal_zone: gpu1-therma !! 641 gpu1_thermal_zone: gpu1 {
797 polling-delay = <1000> 642 polling-delay = <1000>;
798 polling-delay-passive 643 polling-delay-passive = <100>;
799 thermal-sensors = <&sc 644 thermal-sensors = <&scpi_sensors0 24>;
800 status = "disabled"; 645 status = "disabled";
801 }; 646 };
802 }; 647 };
803 648
804 smmu_dma: iommu@7fb00000 { 649 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a 650 compatible = "arm,mmu-401", "arm,smmu-v1";
806 reg = <0x0 0x7fb00000 0x0 0x10 651 reg = <0x0 0x7fb00000 0x0 0x10000>;
807 interrupts = <GIC_SPI 95 IRQ_T 652 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 95 IRQ_T 653 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
809 #iommu-cells = <1>; 654 #iommu-cells = <1>;
810 #global-interrupts = <1>; 655 #global-interrupts = <1>;
811 dma-coherent; 656 dma-coherent;
>> 657 status = "disabled";
812 }; 658 };
813 659
814 smmu_hdlcd1: iommu@7fb10000 { 660 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a 661 compatible = "arm,mmu-401", "arm,smmu-v1";
816 reg = <0x0 0x7fb10000 0x0 0x10 662 reg = <0x0 0x7fb10000 0x0 0x10000>;
817 interrupts = <GIC_SPI 99 IRQ_T 663 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 99 IRQ_T 664 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
819 #iommu-cells = <1>; 665 #iommu-cells = <1>;
820 #global-interrupts = <1>; 666 #global-interrupts = <1>;
821 }; 667 };
822 668
823 smmu_hdlcd0: iommu@7fb20000 { 669 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a 670 compatible = "arm,mmu-401", "arm,smmu-v1";
825 reg = <0x0 0x7fb20000 0x0 0x10 671 reg = <0x0 0x7fb20000 0x0 0x10000>;
826 interrupts = <GIC_SPI 97 IRQ_T 672 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 97 IRQ_T 673 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
828 #iommu-cells = <1>; 674 #iommu-cells = <1>;
829 #global-interrupts = <1>; 675 #global-interrupts = <1>;
830 }; 676 };
831 677
832 smmu_usb: iommu@7fb30000 { 678 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a 679 compatible = "arm,mmu-401", "arm,smmu-v1";
834 reg = <0x0 0x7fb30000 0x0 0x10 680 reg = <0x0 0x7fb30000 0x0 0x10000>;
835 interrupts = <GIC_SPI 101 IRQ_ 681 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 101 IRQ_ 682 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
837 #iommu-cells = <1>; 683 #iommu-cells = <1>;
838 #global-interrupts = <1>; 684 #global-interrupts = <1>;
839 dma-coherent; 685 dma-coherent;
840 }; 686 };
841 687
842 dma-controller@7ff00000 { !! 688 dma@7ff00000 {
843 compatible = "arm,pl330", "arm 689 compatible = "arm,pl330", "arm,primecell";
844 reg = <0x0 0x7ff00000 0 0x1000 690 reg = <0x0 0x7ff00000 0 0x1000>;
845 #dma-cells = <1>; 691 #dma-cells = <1>;
>> 692 #dma-channels = <8>;
>> 693 #dma-requests = <32>;
846 interrupts = <GIC_SPI 88 IRQ_T 694 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 89 IRQ_T 695 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 90 IRQ_T 696 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 91 IRQ_T 697 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 92 IRQ_T 698 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 108 IRQ_ 699 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 109 IRQ_ 700 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 110 IRQ_ 701 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 111 IRQ_ 702 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 iommus = <&smmu_dma 0>, 703 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>, 704 <&smmu_dma 1>,
857 <&smmu_dma 2>, 705 <&smmu_dma 2>,
858 <&smmu_dma 3>, 706 <&smmu_dma 3>,
859 <&smmu_dma 4>, 707 <&smmu_dma 4>,
860 <&smmu_dma 5>, 708 <&smmu_dma 5>,
861 <&smmu_dma 6>, 709 <&smmu_dma 6>,
862 <&smmu_dma 7>, 710 <&smmu_dma 7>,
863 <&smmu_dma 8>; 711 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>; 712 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk"; 713 clock-names = "apb_pclk";
866 }; 714 };
867 715
868 hdlcd@7ff50000 { 716 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd"; 717 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>; 718 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T 719 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 iommus = <&smmu_hdlcd1 0>; 720 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>; 721 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk"; 722 clock-names = "pxlclk";
875 723
876 port { 724 port {
877 hdlcd1_output: endpoin 725 hdlcd1_output: endpoint {
878 remote-endpoin 726 remote-endpoint = <&tda998x_1_input>;
879 }; 727 };
880 }; 728 };
881 }; 729 };
882 730
883 hdlcd@7ff60000 { 731 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd"; 732 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>; 733 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T 734 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
887 iommus = <&smmu_hdlcd0 0>; 735 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>; 736 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk"; 737 clock-names = "pxlclk";
890 738
891 port { 739 port {
892 hdlcd0_output: endpoin 740 hdlcd0_output: endpoint {
893 remote-endpoin 741 remote-endpoint = <&tda998x_0_input>;
894 }; 742 };
895 }; 743 };
896 }; 744 };
897 745
898 soc_uart0: serial@7ff80000 { 746 soc_uart0: serial@7ff80000 {
899 compatible = "arm,pl011", "arm 747 compatible = "arm,pl011", "arm,primecell";
900 reg = <0x0 0x7ff80000 0x0 0x10 748 reg = <0x0 0x7ff80000 0x0 0x1000>;
901 interrupts = <GIC_SPI 83 IRQ_T 749 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&soc_uartclk>, <&soc 750 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
903 clock-names = "uartclk", "apb_ 751 clock-names = "uartclk", "apb_pclk";
904 }; 752 };
905 753
906 i2c@7ffa0000 { 754 i2c@7ffa0000 {
907 compatible = "snps,designware- 755 compatible = "snps,designware-i2c";
908 reg = <0x0 0x7ffa0000 0x0 0x10 756 reg = <0x0 0x7ffa0000 0x0 0x1000>;
909 #address-cells = <1>; 757 #address-cells = <1>;
910 #size-cells = <0>; 758 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_ 759 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
912 clock-frequency = <400000>; 760 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>; 761 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>; 762 clocks = <&soc_smc50mhz>;
915 763
916 hdmi-transmitter@70 { 764 hdmi-transmitter@70 {
917 compatible = "nxp,tda9 765 compatible = "nxp,tda998x";
918 reg = <0x70>; 766 reg = <0x70>;
919 port { 767 port {
920 tda998x_0_inpu 768 tda998x_0_input: endpoint {
921 remote 769 remote-endpoint = <&hdlcd0_output>;
922 }; 770 };
923 }; 771 };
924 }; 772 };
925 773
926 hdmi-transmitter@71 { 774 hdmi-transmitter@71 {
927 compatible = "nxp,tda9 775 compatible = "nxp,tda998x";
928 reg = <0x71>; 776 reg = <0x71>;
929 port { 777 port {
930 tda998x_1_inpu 778 tda998x_1_input: endpoint {
931 remote 779 remote-endpoint = <&hdlcd1_output>;
932 }; 780 };
933 }; 781 };
934 }; 782 };
935 }; 783 };
936 784
937 usb@7ffb0000 { 785 usb@7ffb0000 {
938 compatible = "generic-ohci"; 786 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10 787 reg = <0x0 0x7ffb0000 0x0 0x10000>;
940 interrupts = <GIC_SPI 116 IRQ_ 788 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
941 iommus = <&smmu_usb 0>; 789 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>; 790 clocks = <&soc_usb48mhz>;
943 }; 791 };
944 792
945 usb@7ffc0000 { 793 usb@7ffc0000 {
946 compatible = "generic-ehci"; 794 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10 795 reg = <0x0 0x7ffc0000 0x0 0x10000>;
948 interrupts = <GIC_SPI 117 IRQ_ 796 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
949 iommus = <&smmu_usb 0>; 797 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>; 798 clocks = <&soc_usb48mhz>;
951 }; 799 };
952 800
953 memory-controller@7ffd0000 { 801 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm 802 compatible = "arm,pl354", "arm,primecell";
955 reg = <0 0x7ffd0000 0 0x1000>; 803 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T 804 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 87 IRQ_T 805 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&soc_smc50mhz>; 806 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk"; 807 clock-names = "apb_pclk";
960 }; 808 };
961 809
962 memory@80000000 { 810 memory@80000000 {
963 device_type = "memory"; 811 device_type = "memory";
964 /* last 16MB of the first memo 812 /* last 16MB of the first memory area is reserved for secure world use by firmware */
965 reg = <0x00000000 0x80000000 0 813 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
966 <0x00000008 0x80000000 0 814 <0x00000008 0x80000000 0x1 0x80000000>;
967 }; 815 };
968 816
969 bus@8000000 { 817 bus@8000000 {
>> 818 compatible = "simple-bus";
>> 819 #address-cells = <2>;
>> 820 #size-cells = <1>;
>> 821 ranges = <0 0 0 0x08000000 0x04000000>,
>> 822 <1 0 0 0x14000000 0x04000000>,
>> 823 <2 0 0 0x18000000 0x04000000>,
>> 824 <3 0 0 0x1c000000 0x04000000>,
>> 825 <4 0 0 0x0c000000 0x04000000>,
>> 826 <5 0 0 0x10000000 0x04000000>;
>> 827
970 #interrupt-cells = <1>; 828 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>; 829 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0 830 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
973 <0 0 1 &gic 0 831 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
974 <0 0 2 &gic 0 832 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 3 &gic 0 833 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 4 &gic 0 834 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 5 &gic 0 835 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
978 <0 0 6 &gic 0 836 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
979 <0 0 7 &gic 0 837 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
980 <0 0 8 &gic 0 838 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
981 <0 0 9 &gic 0 839 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 10 &gic 0 840 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 11 &gic 0 841 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 12 &gic 0 842 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
985 }; 843 };
986 844
987 site2: tlx-bus@60000000 { 845 site2: tlx-bus@60000000 {
988 compatible = "simple-bus"; 846 compatible = "simple-bus";
989 #address-cells = <1>; 847 #address-cells = <1>;
990 #size-cells = <1>; 848 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100 849 ranges = <0 0 0x60000000 0x10000000>;
992 #interrupt-cells = <1>; 850 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>; 851 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI 852 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
995 }; 853 };
996 }; 854 };
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