1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi" 2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi" 3 #include "juno-motherboard.dtsi"
4 4
5 / { 5 / {
6 /* 6 /*
7 * Devices shared by all Juno boards 7 * Devices shared by all Juno boards
8 */ 8 */
9 9
10 memtimer: timer@2a810000 { 10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer- 11 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10 12 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>; 13 clock-frequency = <50000000>;
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 ranges = <0 0x0 0x2a820000 0x2 16 ranges = <0 0x0 0x2a820000 0x20000>;
17 status = "disabled"; 17 status = "disabled";
18 frame@2a830000 { 18 frame@2a830000 {
19 frame-number = <1>; 19 frame-number = <1>;
20 interrupts = <GIC_SPI 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
21 reg = <0x10000 0x10000 21 reg = <0x10000 0x10000>;
22 }; 22 };
23 }; 23 };
24 24
25 mailbox: mhu@2b1f0000 { 25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p 26 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x10 27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_T 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_T !! 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 <GIC_SPI 37 IRQ_T <<
31 #mbox-cells = <1>; 30 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>; 31 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk"; 32 clock-names = "apb_pclk";
34 }; 33 };
35 34
36 smmu_gpu: iommu@2b400000 { 35 smmu_gpu: iommu@2b400000 {
37 compatible = "arm,mmu-400", "a 36 compatible = "arm,mmu-400", "arm,smmu-v1";
38 reg = <0x0 0x2b400000 0x0 0x10 37 reg = <0x0 0x2b400000 0x0 0x10000>;
39 interrupts = <GIC_SPI 38 IRQ_T 38 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 38 IRQ_T 39 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
41 #iommu-cells = <1>; 40 #iommu-cells = <1>;
42 #global-interrupts = <1>; 41 #global-interrupts = <1>;
43 power-domains = <&scpi_devpd 1 42 power-domains = <&scpi_devpd 1>;
44 dma-coherent; 43 dma-coherent;
45 status = "disabled"; 44 status = "disabled";
46 }; 45 };
47 46
48 smmu_pcie: iommu@2b500000 { 47 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a 48 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b500000 0x0 0x10 49 reg = <0x0 0x2b500000 0x0 0x10000>;
51 interrupts = <GIC_SPI 40 IRQ_T 50 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 40 IRQ_T 51 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
53 #iommu-cells = <1>; 52 #iommu-cells = <1>;
54 #global-interrupts = <1>; 53 #global-interrupts = <1>;
55 dma-coherent; 54 dma-coherent;
56 status = "disabled"; 55 status = "disabled";
57 }; 56 };
58 57
59 smmu_etr: iommu@2b600000 { 58 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a 59 compatible = "arm,mmu-401", "arm,smmu-v1";
61 reg = <0x0 0x2b600000 0x0 0x10 60 reg = <0x0 0x2b600000 0x0 0x10000>;
62 interrupts = <GIC_SPI 42 IRQ_T 61 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 42 IRQ_T 62 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
64 #iommu-cells = <1>; 63 #iommu-cells = <1>;
65 #global-interrupts = <1>; 64 #global-interrupts = <1>;
66 dma-coherent; 65 dma-coherent;
67 power-domains = <&scpi_devpd 0 66 power-domains = <&scpi_devpd 0>;
68 }; 67 };
69 68
70 gic: interrupt-controller@2c010000 { 69 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a 70 compatible = "arm,gic-400", "arm,cortex-a15-gic";
72 reg = <0x0 0x2c010000 0 0x1000 71 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000 72 <0x0 0x2c02f000 0 0x2000>,
74 <0x0 0x2c04f000 0 0x2000 73 <0x0 0x2c04f000 0 0x2000>,
75 <0x0 0x2c06f000 0 0x2000 74 <0x0 0x2c06f000 0 0x2000>;
76 #address-cells = <1>; 75 #address-cells = <1>;
77 #interrupt-cells = <3>; 76 #interrupt-cells = <3>;
78 #size-cells = <1>; 77 #size-cells = <1>;
79 interrupt-controller; 78 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C 79 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
81 ranges = <0 0 0x2c1c0000 0x400 80 ranges = <0 0 0x2c1c0000 0x40000>;
82 81
83 v2m_0: v2m@0 { 82 v2m_0: v2m@0 {
84 compatible = "arm,gic- 83 compatible = "arm,gic-v2m-frame";
85 msi-controller; 84 msi-controller;
86 reg = <0 0x10000>; 85 reg = <0 0x10000>;
87 }; 86 };
88 87
89 v2m@10000 { 88 v2m@10000 {
90 compatible = "arm,gic- 89 compatible = "arm,gic-v2m-frame";
91 msi-controller; 90 msi-controller;
92 reg = <0x10000 0x10000 91 reg = <0x10000 0x10000>;
93 }; 92 };
94 93
95 v2m@20000 { 94 v2m@20000 {
96 compatible = "arm,gic- 95 compatible = "arm,gic-v2m-frame";
97 msi-controller; 96 msi-controller;
98 reg = <0x20000 0x10000 97 reg = <0x20000 0x10000>;
99 }; 98 };
100 99
101 v2m@30000 { 100 v2m@30000 {
102 compatible = "arm,gic- 101 compatible = "arm,gic-v2m-frame";
103 msi-controller; 102 msi-controller;
104 reg = <0x30000 0x10000 103 reg = <0x30000 0x10000>;
105 }; 104 };
106 }; 105 };
107 106
108 timer { 107 timer {
109 compatible = "arm,armv8-timer" 108 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_ 109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_ 110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_ 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_ 112 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
114 }; 113 };
115 114
116 /* 115 /*
117 * Juno TRMs specify the size for thes 116 * Juno TRMs specify the size for these coresight components as 64K.
118 * The actual size is just 4K though 6 117 * The actual size is just 4K though 64K is reserved. Access to the
119 * unmapped reserved region results in 118 * unmapped reserved region results in a DECERR response.
120 */ 119 */
121 etf_sys0: etf@20010000 { /* etf0 */ !! 120 etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm 121 compatible = "arm,coresight-tmc", "arm,primecell";
123 reg = <0 0x20010000 0 0x1000>; 122 reg = <0 0x20010000 0 0x1000>;
124 123
125 clocks = <&soc_smc50mhz>; 124 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk"; 125 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0 126 power-domains = <&scpi_devpd 0>;
128 127
129 in-ports { 128 in-ports {
130 port { 129 port {
131 etf0_in_port: 130 etf0_in_port: endpoint {
132 remote 131 remote-endpoint = <&main_funnel_out_port>;
133 }; 132 };
134 }; 133 };
135 }; 134 };
136 135
137 out-ports { 136 out-ports {
138 port { 137 port {
139 etf0_out_port: 138 etf0_out_port: endpoint {
140 }; 139 };
141 }; 140 };
142 }; 141 };
143 }; 142 };
144 143
145 tpiu_sys: tpiu@20030000 { !! 144 tpiu@20030000 {
146 compatible = "arm,coresight-tp 145 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0 0x20030000 0 0x1000>; 146 reg = <0 0x20030000 0 0x1000>;
148 147
149 clocks = <&soc_smc50mhz>; 148 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk"; 149 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0 150 power-domains = <&scpi_devpd 0>;
152 in-ports { 151 in-ports {
153 port { 152 port {
154 tpiu_in_port: 153 tpiu_in_port: endpoint {
155 remote 154 remote-endpoint = <&replicator_out_port0>;
156 }; 155 };
157 }; 156 };
158 }; 157 };
159 }; 158 };
160 159
161 /* main funnel on Juno r0, cssys0 funn 160 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
162 main_funnel: funnel@20040000 { 161 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy 162 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
164 reg = <0 0x20040000 0 0x1000>; 163 reg = <0 0x20040000 0 0x1000>;
165 164
166 clocks = <&soc_smc50mhz>; 165 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk"; 166 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0 167 power-domains = <&scpi_devpd 0>;
169 168
170 out-ports { 169 out-ports {
171 port { 170 port {
172 main_funnel_ou 171 main_funnel_out_port: endpoint {
173 remote 172 remote-endpoint = <&etf0_in_port>;
174 }; 173 };
175 }; 174 };
176 }; 175 };
177 176
178 main_funnel_in_ports: in-ports 177 main_funnel_in_ports: in-ports {
179 #address-cells = <1>; 178 #address-cells = <1>;
180 #size-cells = <0>; 179 #size-cells = <0>;
181 180
182 port@0 { 181 port@0 {
183 reg = <0>; 182 reg = <0>;
184 main_funnel_in 183 main_funnel_in_port0: endpoint {
185 remote 184 remote-endpoint = <&cluster0_funnel_out_port>;
186 }; 185 };
187 }; 186 };
188 187
189 port@1 { 188 port@1 {
190 reg = <1>; 189 reg = <1>;
191 main_funnel_in 190 main_funnel_in_port1: endpoint {
192 remote 191 remote-endpoint = <&cluster1_funnel_out_port>;
193 }; 192 };
194 }; 193 };
195 }; 194 };
196 }; 195 };
197 196
198 etr_sys: etr@20070000 { !! 197 etr@20070000 {
199 compatible = "arm,coresight-tm 198 compatible = "arm,coresight-tmc", "arm,primecell";
200 reg = <0 0x20070000 0 0x1000>; 199 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>; 200 iommus = <&smmu_etr 0>;
202 201
203 clocks = <&soc_smc50mhz>; 202 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk"; 203 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0 204 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather; 205 arm,scatter-gather;
207 in-ports { 206 in-ports {
208 port { 207 port {
209 etr_in_port: e 208 etr_in_port: endpoint {
210 remote 209 remote-endpoint = <&replicator_out_port1>;
211 }; 210 };
212 }; 211 };
213 }; 212 };
214 }; 213 };
215 214
216 stm_sys: stm@20100000 { !! 215 stm@20100000 {
217 compatible = "arm,coresight-st 216 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>, 217 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000 218 <0 0x28000000 0 0x1000000>;
220 reg-names = "stm-base", "stm-s 219 reg-names = "stm-base", "stm-stimulus-base";
221 220
222 clocks = <&soc_smc50mhz>; 221 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk"; 222 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0 223 power-domains = <&scpi_devpd 0>;
225 out-ports { 224 out-ports {
226 port { 225 port {
227 stm_out_port: 226 stm_out_port: endpoint {
228 }; 227 };
229 }; 228 };
230 }; 229 };
231 }; 230 };
232 231
233 replicator@20120000 { 232 replicator@20120000 {
234 compatible = "arm,coresight-dy 233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
235 reg = <0 0x20120000 0 0x1000>; 234 reg = <0 0x20120000 0 0x1000>;
236 235
237 clocks = <&soc_smc50mhz>; 236 clocks = <&soc_smc50mhz>;
238 clock-names = "apb_pclk"; 237 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0 238 power-domains = <&scpi_devpd 0>;
240 239
241 out-ports { 240 out-ports {
242 #address-cells = <1>; 241 #address-cells = <1>;
243 #size-cells = <0>; 242 #size-cells = <0>;
244 243
245 /* replicator output p 244 /* replicator output ports */
246 port@0 { 245 port@0 {
247 reg = <0>; 246 reg = <0>;
248 replicator_out 247 replicator_out_port0: endpoint {
249 remote 248 remote-endpoint = <&tpiu_in_port>;
250 }; 249 };
251 }; 250 };
252 251
253 port@1 { 252 port@1 {
254 reg = <1>; 253 reg = <1>;
255 replicator_out 254 replicator_out_port1: endpoint {
256 remote 255 remote-endpoint = <&etr_in_port>;
257 }; 256 };
258 }; 257 };
259 }; 258 };
260 in-ports { 259 in-ports {
261 port { 260 port {
262 replicator_in_ 261 replicator_in_port0: endpoint {
263 }; 262 };
264 }; 263 };
265 }; 264 };
266 }; 265 };
267 266
268 cpu_debug0: cpu-debug@22010000 { 267 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp 268 compatible = "arm,coresight-cpu-debug", "arm,primecell";
270 reg = <0x0 0x22010000 0x0 0x10 269 reg = <0x0 0x22010000 0x0 0x1000>;
271 270
272 clocks = <&soc_smc50mhz>; 271 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk"; 272 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0 273 power-domains = <&scpi_devpd 0>;
275 }; 274 };
276 275
277 etm0: etm@22040000 { 276 etm0: etm@22040000 {
278 compatible = "arm,coresight-et 277 compatible = "arm,coresight-etm4x", "arm,primecell";
279 reg = <0 0x22040000 0 0x1000>; 278 reg = <0 0x22040000 0 0x1000>;
280 279
281 clocks = <&soc_smc50mhz>; 280 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk"; 281 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0 282 power-domains = <&scpi_devpd 0>;
284 out-ports { 283 out-ports {
285 port { 284 port {
286 cluster0_etm0_ 285 cluster0_etm0_out_port: endpoint {
287 remote 286 remote-endpoint = <&cluster0_funnel_in_port0>;
288 }; 287 };
289 }; 288 };
290 }; 289 };
291 }; 290 };
292 291
293 cti0: cti@22020000 { <<
294 compatible = "arm,coresight-ct <<
295 "arm,primecell"; <<
296 reg = <0 0x22020000 0 0x1000>; <<
297 <<
298 clocks = <&soc_smc50mhz>; <<
299 clock-names = "apb_pclk"; <<
300 power-domains = <&scpi_devpd 0 <<
301 <<
302 arm,cs-dev-assoc = <&etm0>; <<
303 }; <<
304 <<
305 funnel@220c0000 { /* cluster0 funnel * 292 funnel@220c0000 { /* cluster0 funnel */
306 compatible = "arm,coresight-dy 293 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
307 reg = <0 0x220c0000 0 0x1000>; 294 reg = <0 0x220c0000 0 0x1000>;
308 295
309 clocks = <&soc_smc50mhz>; 296 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk"; 297 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0 298 power-domains = <&scpi_devpd 0>;
312 out-ports { 299 out-ports {
313 port { 300 port {
314 cluster0_funne 301 cluster0_funnel_out_port: endpoint {
315 remote 302 remote-endpoint = <&main_funnel_in_port0>;
316 }; 303 };
317 }; 304 };
318 }; 305 };
319 306
320 in-ports { 307 in-ports {
321 #address-cells = <1>; 308 #address-cells = <1>;
322 #size-cells = <0>; 309 #size-cells = <0>;
323 310
324 port@0 { 311 port@0 {
325 reg = <0>; 312 reg = <0>;
326 cluster0_funne 313 cluster0_funnel_in_port0: endpoint {
327 remote 314 remote-endpoint = <&cluster0_etm0_out_port>;
328 }; 315 };
329 }; 316 };
330 317
331 port@1 { 318 port@1 {
332 reg = <1>; 319 reg = <1>;
333 cluster0_funne 320 cluster0_funnel_in_port1: endpoint {
334 remote 321 remote-endpoint = <&cluster0_etm1_out_port>;
335 }; 322 };
336 }; 323 };
337 }; 324 };
338 }; 325 };
339 326
340 cpu_debug1: cpu-debug@22110000 { 327 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp 328 compatible = "arm,coresight-cpu-debug", "arm,primecell";
342 reg = <0x0 0x22110000 0x0 0x10 329 reg = <0x0 0x22110000 0x0 0x1000>;
343 330
344 clocks = <&soc_smc50mhz>; 331 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk"; 332 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0 333 power-domains = <&scpi_devpd 0>;
347 }; 334 };
348 335
349 etm1: etm@22140000 { 336 etm1: etm@22140000 {
350 compatible = "arm,coresight-et 337 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0x22140000 0 0x1000>; 338 reg = <0 0x22140000 0 0x1000>;
352 339
353 clocks = <&soc_smc50mhz>; 340 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk"; 341 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0 342 power-domains = <&scpi_devpd 0>;
356 out-ports { 343 out-ports {
357 port { 344 port {
358 cluster0_etm1_ 345 cluster0_etm1_out_port: endpoint {
359 remote 346 remote-endpoint = <&cluster0_funnel_in_port1>;
360 }; 347 };
361 }; 348 };
362 }; 349 };
363 }; 350 };
364 351
365 cti1: cti@22120000 { <<
366 compatible = "arm,coresight-ct <<
367 "arm,primecell"; <<
368 reg = <0 0x22120000 0 0x1000>; <<
369 <<
370 clocks = <&soc_smc50mhz>; <<
371 clock-names = "apb_pclk"; <<
372 power-domains = <&scpi_devpd 0 <<
373 <<
374 arm,cs-dev-assoc = <&etm1>; <<
375 }; <<
376 <<
377 cpu_debug2: cpu-debug@23010000 { 352 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp 353 compatible = "arm,coresight-cpu-debug", "arm,primecell";
379 reg = <0x0 0x23010000 0x0 0x10 354 reg = <0x0 0x23010000 0x0 0x1000>;
380 355
381 clocks = <&soc_smc50mhz>; 356 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk"; 357 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0 358 power-domains = <&scpi_devpd 0>;
384 }; 359 };
385 360
386 etm2: etm@23040000 { 361 etm2: etm@23040000 {
387 compatible = "arm,coresight-et 362 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0 0x23040000 0 0x1000>; 363 reg = <0 0x23040000 0 0x1000>;
389 364
390 clocks = <&soc_smc50mhz>; 365 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk"; 366 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0 367 power-domains = <&scpi_devpd 0>;
393 out-ports { 368 out-ports {
394 port { 369 port {
395 cluster1_etm0_ 370 cluster1_etm0_out_port: endpoint {
396 remote 371 remote-endpoint = <&cluster1_funnel_in_port0>;
397 }; 372 };
398 }; 373 };
399 }; 374 };
400 }; 375 };
401 376
402 cti2: cti@23020000 { <<
403 compatible = "arm,coresight-ct <<
404 "arm,primecell"; <<
405 reg = <0 0x23020000 0 0x1000>; <<
406 <<
407 clocks = <&soc_smc50mhz>; <<
408 clock-names = "apb_pclk"; <<
409 power-domains = <&scpi_devpd 0 <<
410 <<
411 arm,cs-dev-assoc = <&etm2>; <<
412 }; <<
413 <<
414 funnel@230c0000 { /* cluster1 funnel * 377 funnel@230c0000 { /* cluster1 funnel */
415 compatible = "arm,coresight-dy 378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
416 reg = <0 0x230c0000 0 0x1000>; 379 reg = <0 0x230c0000 0 0x1000>;
417 380
418 clocks = <&soc_smc50mhz>; 381 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk"; 382 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0 383 power-domains = <&scpi_devpd 0>;
421 out-ports { 384 out-ports {
422 port { 385 port {
423 cluster1_funne 386 cluster1_funnel_out_port: endpoint {
424 remote 387 remote-endpoint = <&main_funnel_in_port1>;
425 }; 388 };
426 }; 389 };
427 }; 390 };
428 391
429 in-ports { 392 in-ports {
430 #address-cells = <1>; 393 #address-cells = <1>;
431 #size-cells = <0>; 394 #size-cells = <0>;
432 395
433 port@0 { 396 port@0 {
434 reg = <0>; 397 reg = <0>;
435 cluster1_funne 398 cluster1_funnel_in_port0: endpoint {
436 remote 399 remote-endpoint = <&cluster1_etm0_out_port>;
437 }; 400 };
438 }; 401 };
439 402
440 port@1 { 403 port@1 {
441 reg = <1>; 404 reg = <1>;
442 cluster1_funne 405 cluster1_funnel_in_port1: endpoint {
443 remote 406 remote-endpoint = <&cluster1_etm1_out_port>;
444 }; 407 };
445 }; 408 };
446 port@2 { 409 port@2 {
447 reg = <2>; 410 reg = <2>;
448 cluster1_funne 411 cluster1_funnel_in_port2: endpoint {
449 remote 412 remote-endpoint = <&cluster1_etm2_out_port>;
450 }; 413 };
451 }; 414 };
452 port@3 { 415 port@3 {
453 reg = <3>; 416 reg = <3>;
454 cluster1_funne 417 cluster1_funnel_in_port3: endpoint {
455 remote 418 remote-endpoint = <&cluster1_etm3_out_port>;
456 }; 419 };
457 }; 420 };
458 }; 421 };
459 }; 422 };
460 423
461 cpu_debug3: cpu-debug@23110000 { 424 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp 425 compatible = "arm,coresight-cpu-debug", "arm,primecell";
463 reg = <0x0 0x23110000 0x0 0x10 426 reg = <0x0 0x23110000 0x0 0x1000>;
464 427
465 clocks = <&soc_smc50mhz>; 428 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk"; 429 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0 430 power-domains = <&scpi_devpd 0>;
468 }; 431 };
469 432
470 etm3: etm@23140000 { 433 etm3: etm@23140000 {
471 compatible = "arm,coresight-et 434 compatible = "arm,coresight-etm4x", "arm,primecell";
472 reg = <0 0x23140000 0 0x1000>; 435 reg = <0 0x23140000 0 0x1000>;
473 436
474 clocks = <&soc_smc50mhz>; 437 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk"; 438 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0 439 power-domains = <&scpi_devpd 0>;
477 out-ports { 440 out-ports {
478 port { 441 port {
479 cluster1_etm1_ 442 cluster1_etm1_out_port: endpoint {
480 remote 443 remote-endpoint = <&cluster1_funnel_in_port1>;
481 }; 444 };
482 }; 445 };
483 }; 446 };
484 }; 447 };
485 448
486 cti3: cti@23120000 { <<
487 compatible = "arm,coresight-ct <<
488 "arm,primecell"; <<
489 reg = <0 0x23120000 0 0x1000>; <<
490 <<
491 clocks = <&soc_smc50mhz>; <<
492 clock-names = "apb_pclk"; <<
493 power-domains = <&scpi_devpd 0 <<
494 <<
495 arm,cs-dev-assoc = <&etm3>; <<
496 }; <<
497 <<
498 cpu_debug4: cpu-debug@23210000 { 449 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp 450 compatible = "arm,coresight-cpu-debug", "arm,primecell";
500 reg = <0x0 0x23210000 0x0 0x10 451 reg = <0x0 0x23210000 0x0 0x1000>;
501 452
502 clocks = <&soc_smc50mhz>; 453 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk"; 454 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0 455 power-domains = <&scpi_devpd 0>;
505 }; 456 };
506 457
507 etm4: etm@23240000 { 458 etm4: etm@23240000 {
508 compatible = "arm,coresight-et 459 compatible = "arm,coresight-etm4x", "arm,primecell";
509 reg = <0 0x23240000 0 0x1000>; 460 reg = <0 0x23240000 0 0x1000>;
510 461
511 clocks = <&soc_smc50mhz>; 462 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk"; 463 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0 464 power-domains = <&scpi_devpd 0>;
514 out-ports { 465 out-ports {
515 port { 466 port {
516 cluster1_etm2_ 467 cluster1_etm2_out_port: endpoint {
517 remote 468 remote-endpoint = <&cluster1_funnel_in_port2>;
518 }; 469 };
519 }; 470 };
520 }; 471 };
521 }; 472 };
522 473
523 cti4: cti@23220000 { <<
524 compatible = "arm,coresight-ct <<
525 "arm,primecell"; <<
526 reg = <0 0x23220000 0 0x1000>; <<
527 <<
528 clocks = <&soc_smc50mhz>; <<
529 clock-names = "apb_pclk"; <<
530 power-domains = <&scpi_devpd 0 <<
531 <<
532 arm,cs-dev-assoc = <&etm4>; <<
533 }; <<
534 <<
535 cpu_debug5: cpu-debug@23310000 { 474 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp 475 compatible = "arm,coresight-cpu-debug", "arm,primecell";
537 reg = <0x0 0x23310000 0x0 0x10 476 reg = <0x0 0x23310000 0x0 0x1000>;
538 477
539 clocks = <&soc_smc50mhz>; 478 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk"; 479 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0 480 power-domains = <&scpi_devpd 0>;
542 }; 481 };
543 482
544 etm5: etm@23340000 { 483 etm5: etm@23340000 {
545 compatible = "arm,coresight-et 484 compatible = "arm,coresight-etm4x", "arm,primecell";
546 reg = <0 0x23340000 0 0x1000>; 485 reg = <0 0x23340000 0 0x1000>;
547 486
548 clocks = <&soc_smc50mhz>; 487 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk"; 488 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0 489 power-domains = <&scpi_devpd 0>;
551 out-ports { 490 out-ports {
552 port { 491 port {
553 cluster1_etm3_ 492 cluster1_etm3_out_port: endpoint {
554 remote 493 remote-endpoint = <&cluster1_funnel_in_port3>;
555 }; 494 };
556 }; 495 };
557 }; 496 };
558 }; 497 };
559 498
560 cti5: cti@23320000 { <<
561 compatible = "arm,coresight-ct <<
562 "arm,primecell"; <<
563 reg = <0 0x23320000 0 0x1000>; <<
564 <<
565 clocks = <&soc_smc50mhz>; <<
566 clock-names = "apb_pclk"; <<
567 power-domains = <&scpi_devpd 0 <<
568 <<
569 arm,cs-dev-assoc = <&etm5>; <<
570 }; <<
571 <<
572 cti_sys0: cti@20020000 { /* sys_cti_0 <<
573 compatible = "arm,coresight-ct <<
574 reg = <0 0x20020000 0 0x1000>; <<
575 <<
576 clocks = <&soc_smc50mhz>; <<
577 clock-names = "apb_pclk"; <<
578 power-domains = <&scpi_devpd 0 <<
579 <<
580 #address-cells = <1>; <<
581 #size-cells = <0>; <<
582 <<
583 trig-conns@0 { <<
584 reg = <0>; <<
585 arm,trig-in-sigs = <2 <<
586 arm,trig-in-types = <S <<
587 arm,trig-out-sigs = <0 <<
588 arm,trig-out-types = < <<
589 arm,cs-dev-assoc = <&e <<
590 }; <<
591 <<
592 trig-conns@1 { <<
593 reg = <1>; <<
594 arm,trig-in-sigs = <0 <<
595 arm,trig-in-types = <S <<
596 arm,trig-out-sigs = <7 <<
597 arm,trig-out-types = < <<
598 arm,cs-dev-assoc = <&e <<
599 }; <<
600 <<
601 trig-conns@2 { <<
602 reg = <2>; <<
603 arm,trig-in-sigs = <4 <<
604 arm,trig-in-types = <S <<
605 STM <<
606 arm,trig-out-sigs = <4 <<
607 arm,trig-out-types = < <<
608 arm,cs-dev-assoc = <&s <<
609 }; <<
610 <<
611 trig-conns@3 { <<
612 reg = <3>; <<
613 arm,trig-out-sigs = <2 <<
614 arm,trig-out-types = < <<
615 arm,cs-dev-assoc = <&t <<
616 }; <<
617 }; <<
618 <<
619 cti_sys1: cti@20110000 { /* sys_cti_1 <<
620 compatible = "arm,coresight-ct <<
621 reg = <0 0x20110000 0 0x1000>; <<
622 <<
623 clocks = <&soc_smc50mhz>; <<
624 clock-names = "apb_pclk"; <<
625 power-domains = <&scpi_devpd 0 <<
626 <<
627 #address-cells = <1>; <<
628 #size-cells = <0>; <<
629 <<
630 trig-conns@0 { <<
631 reg = <0>; <<
632 arm,trig-in-sigs = <0> <<
633 arm,trig-in-types = <G <<
634 arm,trig-out-sigs = <0 <<
635 arm,trig-out-types = < <<
636 arm,trig-conn-name = " <<
637 }; <<
638 <<
639 trig-conns@1 { <<
640 reg = <1>; <<
641 arm,trig-out-sigs = <2 <<
642 arm,trig-out-types = < <<
643 arm,trig-conn-name = " <<
644 }; <<
645 <<
646 trig-conns@2 { <<
647 reg = <2>; <<
648 arm,trig-out-sigs = <1 <<
649 arm,trig-out-types = < <<
650 arm,trig-conn-name = " <<
651 }; <<
652 }; <<
653 <<
654 gpu: gpu@2d000000 { 499 gpu: gpu@2d000000 {
655 compatible = "arm,juno-mali", 500 compatible = "arm,juno-mali", "arm,mali-t624";
656 reg = <0 0x2d000000 0 0x10000> 501 reg = <0 0x2d000000 0 0x10000>;
657 interrupts = <GIC_SPI 33 IRQ_T 502 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 34 IRQ_T 503 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 32 IRQ_T 504 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "job", "mmu" 505 interrupt-names = "job", "mmu", "gpu";
661 clocks = <&scpi_dvfs 2>; 506 clocks = <&scpi_dvfs 2>;
662 power-domains = <&scpi_devpd 1 507 power-domains = <&scpi_devpd 1>;
663 dma-coherent; 508 dma-coherent;
664 /* The SMMU is only really of 509 /* The SMMU is only really of interest to bare-metal hypervisors */
665 /* iommus = <&smmu_gpu 0>; */ 510 /* iommus = <&smmu_gpu 0>; */
>> 511 status = "disabled";
666 }; 512 };
667 513
668 sram: sram@2e000000 { 514 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns 515 compatible = "arm,juno-sram-ns", "mmio-sram";
670 reg = <0x0 0x2e000000 0x0 0x80 516 reg = <0x0 0x2e000000 0x0 0x8000>;
671 517
672 #address-cells = <1>; 518 #address-cells = <1>;
673 #size-cells = <1>; 519 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8 520 ranges = <0 0x0 0x2e000000 0x8000>;
675 521
676 cpu_scp_lpri: scp-sram@0 { 522 cpu_scp_lpri: scp-sram@0 {
677 compatible = "arm,juno 523 compatible = "arm,juno-scp-shmem";
678 reg = <0x0 0x200>; 524 reg = <0x0 0x200>;
679 }; 525 };
680 526
681 cpu_scp_hpri: scp-sram@200 { 527 cpu_scp_hpri: scp-sram@200 {
682 compatible = "arm,juno 528 compatible = "arm,juno-scp-shmem";
683 reg = <0x200 0x200>; 529 reg = <0x200 0x200>;
684 }; 530 };
685 }; 531 };
686 532
687 pcie_ctlr: pcie@40000000 { 533 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie 534 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
689 device_type = "pci"; 535 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000 536 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
691 bus-range = <0 255>; 537 bus-range = <0 255>;
692 linux,pci-domain = <0>; 538 linux,pci-domain = <0>;
693 #address-cells = <3>; 539 #address-cells = <3>;
694 #size-cells = <2>; 540 #size-cells = <2>;
695 dma-coherent; 541 dma-coherent;
696 ranges = <0x01000000 0x00 0x00 542 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
697 <0x02000000 0x00 0x50 543 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
698 <0x42000000 0x40 0x00 544 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
699 /* Standard AXI Translation en 545 /* Standard AXI Translation entries as programmed by EDK2 */
700 dma-ranges = <0x02000000 0x0 0 546 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
701 <0x43000000 0x8 0 547 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
702 #interrupt-cells = <1>; 548 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7> 549 interrupt-map-mask = <0 0 0 7>;
704 interrupt-map = <0 0 0 1 &gic 550 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 0 2 &gic 551 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 0 3 &gic 552 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
707 <0 0 0 4 &gic 553 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
708 msi-parent = <&v2m_0>; 554 msi-parent = <&v2m_0>;
709 status = "disabled"; 555 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC 556 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
711 iommu-map = <0x0 &smmu_pcie 0x 557 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
712 }; 558 };
713 559
714 scpi { 560 scpi {
715 compatible = "arm,scpi"; 561 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>; 562 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>; 563 shmem = <&cpu_scp_hpri>;
718 564
719 clocks { 565 clocks {
720 compatible = "arm,scpi 566 compatible = "arm,scpi-clocks";
721 567
722 scpi_dvfs: clocks-0 { 568 scpi_dvfs: clocks-0 {
723 compatible = " 569 compatible = "arm,scpi-dvfs-clocks";
724 #clock-cells = 570 #clock-cells = <1>;
725 clock-indices 571 clock-indices = <0>, <1>, <2>;
726 clock-output-n 572 clock-output-names = "atlclk", "aplclk","gpuclk";
727 }; 573 };
728 scpi_clk: clocks-1 { 574 scpi_clk: clocks-1 {
729 compatible = " 575 compatible = "arm,scpi-variable-clocks";
730 #clock-cells = 576 #clock-cells = <1>;
731 clock-indices 577 clock-indices = <3>;
732 clock-output-n 578 clock-output-names = "pxlclk";
733 }; 579 };
734 }; 580 };
735 581
736 scpi_devpd: power-controller { 582 scpi_devpd: power-controller {
737 compatible = "arm,scpi 583 compatible = "arm,scpi-power-domains";
738 num-domains = <2>; 584 num-domains = <2>;
739 #power-domain-cells = 585 #power-domain-cells = <1>;
740 }; 586 };
741 587
742 scpi_sensors0: sensors { 588 scpi_sensors0: sensors {
743 compatible = "arm,scpi 589 compatible = "arm,scpi-sensors";
744 #thermal-sensor-cells 590 #thermal-sensor-cells = <1>;
745 }; 591 };
746 }; 592 };
747 593
748 thermal-zones { 594 thermal-zones {
749 pmic-thermal { !! 595 pmic {
750 polling-delay = <1000> 596 polling-delay = <1000>;
751 polling-delay-passive 597 polling-delay-passive = <100>;
752 thermal-sensors = <&sc 598 thermal-sensors = <&scpi_sensors0 0>;
753 trips { <<
754 pmic_crit0: tr <<
755 temper <<
756 hyster <<
757 type = <<
758 }; <<
759 }; <<
760 }; 599 };
761 600
762 soc-thermal { !! 601 soc {
763 polling-delay = <1000> 602 polling-delay = <1000>;
764 polling-delay-passive 603 polling-delay-passive = <100>;
765 thermal-sensors = <&sc 604 thermal-sensors = <&scpi_sensors0 3>;
766 trips { <<
767 soc_crit0: tri <<
768 temper <<
769 hyster <<
770 type = <<
771 }; <<
772 }; <<
773 }; 605 };
774 606
775 big_cluster_thermal_zone: big- !! 607 big_cluster_thermal_zone: big-cluster {
776 polling-delay = <1000> 608 polling-delay = <1000>;
777 polling-delay-passive 609 polling-delay-passive = <100>;
778 thermal-sensors = <&sc 610 thermal-sensors = <&scpi_sensors0 21>;
779 status = "disabled"; 611 status = "disabled";
780 }; 612 };
781 613
782 little_cluster_thermal_zone: l !! 614 little_cluster_thermal_zone: little-cluster {
783 polling-delay = <1000> 615 polling-delay = <1000>;
784 polling-delay-passive 616 polling-delay-passive = <100>;
785 thermal-sensors = <&sc 617 thermal-sensors = <&scpi_sensors0 22>;
786 status = "disabled"; 618 status = "disabled";
787 }; 619 };
788 620
789 gpu0_thermal_zone: gpu0-therma !! 621 gpu0_thermal_zone: gpu0 {
790 polling-delay = <1000> 622 polling-delay = <1000>;
791 polling-delay-passive 623 polling-delay-passive = <100>;
792 thermal-sensors = <&sc 624 thermal-sensors = <&scpi_sensors0 23>;
793 status = "disabled"; 625 status = "disabled";
794 }; 626 };
795 627
796 gpu1_thermal_zone: gpu1-therma !! 628 gpu1_thermal_zone: gpu1 {
797 polling-delay = <1000> 629 polling-delay = <1000>;
798 polling-delay-passive 630 polling-delay-passive = <100>;
799 thermal-sensors = <&sc 631 thermal-sensors = <&scpi_sensors0 24>;
800 status = "disabled"; 632 status = "disabled";
801 }; 633 };
802 }; 634 };
803 635
804 smmu_dma: iommu@7fb00000 { 636 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a 637 compatible = "arm,mmu-401", "arm,smmu-v1";
806 reg = <0x0 0x7fb00000 0x0 0x10 638 reg = <0x0 0x7fb00000 0x0 0x10000>;
807 interrupts = <GIC_SPI 95 IRQ_T 639 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 95 IRQ_T 640 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
809 #iommu-cells = <1>; 641 #iommu-cells = <1>;
810 #global-interrupts = <1>; 642 #global-interrupts = <1>;
811 dma-coherent; 643 dma-coherent;
812 }; 644 };
813 645
814 smmu_hdlcd1: iommu@7fb10000 { 646 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a 647 compatible = "arm,mmu-401", "arm,smmu-v1";
816 reg = <0x0 0x7fb10000 0x0 0x10 648 reg = <0x0 0x7fb10000 0x0 0x10000>;
817 interrupts = <GIC_SPI 99 IRQ_T 649 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 99 IRQ_T 650 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
819 #iommu-cells = <1>; 651 #iommu-cells = <1>;
820 #global-interrupts = <1>; 652 #global-interrupts = <1>;
821 }; 653 };
822 654
823 smmu_hdlcd0: iommu@7fb20000 { 655 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a 656 compatible = "arm,mmu-401", "arm,smmu-v1";
825 reg = <0x0 0x7fb20000 0x0 0x10 657 reg = <0x0 0x7fb20000 0x0 0x10000>;
826 interrupts = <GIC_SPI 97 IRQ_T 658 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 97 IRQ_T 659 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
828 #iommu-cells = <1>; 660 #iommu-cells = <1>;
829 #global-interrupts = <1>; 661 #global-interrupts = <1>;
830 }; 662 };
831 663
832 smmu_usb: iommu@7fb30000 { 664 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a 665 compatible = "arm,mmu-401", "arm,smmu-v1";
834 reg = <0x0 0x7fb30000 0x0 0x10 666 reg = <0x0 0x7fb30000 0x0 0x10000>;
835 interrupts = <GIC_SPI 101 IRQ_ 667 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 101 IRQ_ 668 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
837 #iommu-cells = <1>; 669 #iommu-cells = <1>;
838 #global-interrupts = <1>; 670 #global-interrupts = <1>;
839 dma-coherent; 671 dma-coherent;
840 }; 672 };
841 673
842 dma-controller@7ff00000 { !! 674 dma@7ff00000 {
843 compatible = "arm,pl330", "arm 675 compatible = "arm,pl330", "arm,primecell";
844 reg = <0x0 0x7ff00000 0 0x1000 676 reg = <0x0 0x7ff00000 0 0x1000>;
845 #dma-cells = <1>; 677 #dma-cells = <1>;
>> 678 #dma-channels = <8>;
>> 679 #dma-requests = <32>;
846 interrupts = <GIC_SPI 88 IRQ_T 680 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 89 IRQ_T 681 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 90 IRQ_T 682 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 91 IRQ_T 683 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 92 IRQ_T 684 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 108 IRQ_ 685 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 109 IRQ_ 686 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 110 IRQ_ 687 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 111 IRQ_ 688 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 iommus = <&smmu_dma 0>, 689 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>, 690 <&smmu_dma 1>,
857 <&smmu_dma 2>, 691 <&smmu_dma 2>,
858 <&smmu_dma 3>, 692 <&smmu_dma 3>,
859 <&smmu_dma 4>, 693 <&smmu_dma 4>,
860 <&smmu_dma 5>, 694 <&smmu_dma 5>,
861 <&smmu_dma 6>, 695 <&smmu_dma 6>,
862 <&smmu_dma 7>, 696 <&smmu_dma 7>,
863 <&smmu_dma 8>; 697 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>; 698 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk"; 699 clock-names = "apb_pclk";
866 }; 700 };
867 701
868 hdlcd@7ff50000 { 702 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd"; 703 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>; 704 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T 705 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 iommus = <&smmu_hdlcd1 0>; 706 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>; 707 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk"; 708 clock-names = "pxlclk";
875 709
876 port { 710 port {
877 hdlcd1_output: endpoin 711 hdlcd1_output: endpoint {
878 remote-endpoin 712 remote-endpoint = <&tda998x_1_input>;
879 }; 713 };
880 }; 714 };
881 }; 715 };
882 716
883 hdlcd@7ff60000 { 717 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd"; 718 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>; 719 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T 720 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
887 iommus = <&smmu_hdlcd0 0>; 721 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>; 722 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk"; 723 clock-names = "pxlclk";
890 724
891 port { 725 port {
892 hdlcd0_output: endpoin 726 hdlcd0_output: endpoint {
893 remote-endpoin 727 remote-endpoint = <&tda998x_0_input>;
894 }; 728 };
895 }; 729 };
896 }; 730 };
897 731
898 soc_uart0: serial@7ff80000 { 732 soc_uart0: serial@7ff80000 {
899 compatible = "arm,pl011", "arm 733 compatible = "arm,pl011", "arm,primecell";
900 reg = <0x0 0x7ff80000 0x0 0x10 734 reg = <0x0 0x7ff80000 0x0 0x1000>;
901 interrupts = <GIC_SPI 83 IRQ_T 735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&soc_uartclk>, <&soc 736 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
903 clock-names = "uartclk", "apb_ 737 clock-names = "uartclk", "apb_pclk";
904 }; 738 };
905 739
906 i2c@7ffa0000 { 740 i2c@7ffa0000 {
907 compatible = "snps,designware- 741 compatible = "snps,designware-i2c";
908 reg = <0x0 0x7ffa0000 0x0 0x10 742 reg = <0x0 0x7ffa0000 0x0 0x1000>;
909 #address-cells = <1>; 743 #address-cells = <1>;
910 #size-cells = <0>; 744 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_ 745 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
912 clock-frequency = <400000>; 746 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>; 747 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>; 748 clocks = <&soc_smc50mhz>;
915 749
916 hdmi-transmitter@70 { 750 hdmi-transmitter@70 {
917 compatible = "nxp,tda9 751 compatible = "nxp,tda998x";
918 reg = <0x70>; 752 reg = <0x70>;
919 port { 753 port {
920 tda998x_0_inpu 754 tda998x_0_input: endpoint {
921 remote 755 remote-endpoint = <&hdlcd0_output>;
922 }; 756 };
923 }; 757 };
924 }; 758 };
925 759
926 hdmi-transmitter@71 { 760 hdmi-transmitter@71 {
927 compatible = "nxp,tda9 761 compatible = "nxp,tda998x";
928 reg = <0x71>; 762 reg = <0x71>;
929 port { 763 port {
930 tda998x_1_inpu 764 tda998x_1_input: endpoint {
931 remote 765 remote-endpoint = <&hdlcd1_output>;
932 }; 766 };
933 }; 767 };
934 }; 768 };
935 }; 769 };
936 770
937 usb@7ffb0000 { 771 usb@7ffb0000 {
938 compatible = "generic-ohci"; 772 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10 773 reg = <0x0 0x7ffb0000 0x0 0x10000>;
940 interrupts = <GIC_SPI 116 IRQ_ 774 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
941 iommus = <&smmu_usb 0>; 775 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>; 776 clocks = <&soc_usb48mhz>;
943 }; 777 };
944 778
945 usb@7ffc0000 { 779 usb@7ffc0000 {
946 compatible = "generic-ehci"; 780 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10 781 reg = <0x0 0x7ffc0000 0x0 0x10000>;
948 interrupts = <GIC_SPI 117 IRQ_ 782 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
949 iommus = <&smmu_usb 0>; 783 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>; 784 clocks = <&soc_usb48mhz>;
951 }; 785 };
952 786
953 memory-controller@7ffd0000 { 787 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm 788 compatible = "arm,pl354", "arm,primecell";
955 reg = <0 0x7ffd0000 0 0x1000>; 789 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T 790 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 87 IRQ_T 791 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&soc_smc50mhz>; 792 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk"; 793 clock-names = "apb_pclk";
960 }; 794 };
961 795
962 memory@80000000 { 796 memory@80000000 {
963 device_type = "memory"; 797 device_type = "memory";
964 /* last 16MB of the first memo 798 /* last 16MB of the first memory area is reserved for secure world use by firmware */
965 reg = <0x00000000 0x80000000 0 799 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
966 <0x00000008 0x80000000 0 800 <0x00000008 0x80000000 0x1 0x80000000>;
967 }; 801 };
968 802
969 bus@8000000 { 803 bus@8000000 {
970 #interrupt-cells = <1>; 804 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>; 805 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0 806 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
973 <0 0 1 &gic 0 807 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
974 <0 0 2 &gic 0 808 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 3 &gic 0 809 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 4 &gic 0 810 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 5 &gic 0 811 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
978 <0 0 6 &gic 0 812 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
979 <0 0 7 &gic 0 813 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
980 <0 0 8 &gic 0 814 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
981 <0 0 9 &gic 0 815 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 10 &gic 0 816 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 11 &gic 0 817 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 12 &gic 0 818 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
985 }; 819 };
986 820
987 site2: tlx-bus@60000000 { 821 site2: tlx-bus@60000000 {
988 compatible = "simple-bus"; 822 compatible = "simple-bus";
989 #address-cells = <1>; 823 #address-cells = <1>;
990 #size-cells = <1>; 824 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100 825 ranges = <0 0 0x60000000 0x10000000>;
992 #interrupt-cells = <1>; 826 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>; 827 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI 828 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
995 }; 829 };
996 }; 830 };
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