1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi" 2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi" 3 #include "juno-motherboard.dtsi"
4 4
5 / { 5 / {
6 /* 6 /*
7 * Devices shared by all Juno boards 7 * Devices shared by all Juno boards
8 */ 8 */
>> 9 dma-ranges = <0 0 0 0 0x100 0>;
9 10
10 memtimer: timer@2a810000 { 11 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer- 12 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10 13 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>; 14 clock-frequency = <50000000>;
14 #address-cells = <1>; !! 15 #address-cells = <2>;
15 #size-cells = <1>; !! 16 #size-cells = <2>;
16 ranges = <0 0x0 0x2a820000 0x2 !! 17 ranges;
17 status = "disabled"; 18 status = "disabled";
18 frame@2a830000 { 19 frame@2a830000 {
19 frame-number = <1>; 20 frame-number = <1>;
20 interrupts = <GIC_SPI 21 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
21 reg = <0x10000 0x10000 !! 22 reg = <0x0 0x2a830000 0x0 0x10000>;
22 }; 23 };
23 }; 24 };
24 25
25 mailbox: mhu@2b1f0000 { 26 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p 27 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x10 28 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_T 29 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_T !! 30 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 <GIC_SPI 37 IRQ_T !! 31 interrupt-names = "mhu_lpri_rx",
>> 32 "mhu_hpri_rx";
31 #mbox-cells = <1>; 33 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>; 34 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk"; 35 clock-names = "apb_pclk";
34 }; 36 };
35 37
36 smmu_gpu: iommu@2b400000 { <<
37 compatible = "arm,mmu-400", "a <<
38 reg = <0x0 0x2b400000 0x0 0x10 <<
39 interrupts = <GIC_SPI 38 IRQ_T <<
40 <GIC_SPI 38 IRQ_T <<
41 #iommu-cells = <1>; <<
42 #global-interrupts = <1>; <<
43 power-domains = <&scpi_devpd 1 <<
44 dma-coherent; <<
45 status = "disabled"; <<
46 }; <<
47 <<
48 smmu_pcie: iommu@2b500000 { 38 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a 39 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b500000 0x0 0x10 40 reg = <0x0 0x2b500000 0x0 0x10000>;
51 interrupts = <GIC_SPI 40 IRQ_T 41 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 40 IRQ_T 42 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
53 #iommu-cells = <1>; 43 #iommu-cells = <1>;
54 #global-interrupts = <1>; 44 #global-interrupts = <1>;
55 dma-coherent; 45 dma-coherent;
56 status = "disabled"; 46 status = "disabled";
57 }; 47 };
58 48
59 smmu_etr: iommu@2b600000 { 49 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a 50 compatible = "arm,mmu-401", "arm,smmu-v1";
61 reg = <0x0 0x2b600000 0x0 0x10 51 reg = <0x0 0x2b600000 0x0 0x10000>;
62 interrupts = <GIC_SPI 42 IRQ_T 52 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 42 IRQ_T 53 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
64 #iommu-cells = <1>; 54 #iommu-cells = <1>;
65 #global-interrupts = <1>; 55 #global-interrupts = <1>;
66 dma-coherent; 56 dma-coherent;
67 power-domains = <&scpi_devpd 0 57 power-domains = <&scpi_devpd 0>;
68 }; 58 };
69 59
70 gic: interrupt-controller@2c010000 { 60 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a 61 compatible = "arm,gic-400", "arm,cortex-a15-gic";
72 reg = <0x0 0x2c010000 0 0x1000 62 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000 63 <0x0 0x2c02f000 0 0x2000>,
74 <0x0 0x2c04f000 0 0x2000 64 <0x0 0x2c04f000 0 0x2000>,
75 <0x0 0x2c06f000 0 0x2000 65 <0x0 0x2c06f000 0 0x2000>;
76 #address-cells = <1>; !! 66 #address-cells = <2>;
77 #interrupt-cells = <3>; 67 #interrupt-cells = <3>;
78 #size-cells = <1>; !! 68 #size-cells = <2>;
79 interrupt-controller; 69 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C 70 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
81 ranges = <0 0 0x2c1c0000 0x400 !! 71 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
82 72
83 v2m_0: v2m@0 { 73 v2m_0: v2m@0 {
84 compatible = "arm,gic- 74 compatible = "arm,gic-v2m-frame";
85 msi-controller; 75 msi-controller;
86 reg = <0 0x10000>; !! 76 reg = <0 0 0 0x10000>;
87 }; 77 };
88 78
89 v2m@10000 { 79 v2m@10000 {
90 compatible = "arm,gic- 80 compatible = "arm,gic-v2m-frame";
91 msi-controller; 81 msi-controller;
92 reg = <0x10000 0x10000 !! 82 reg = <0 0x10000 0 0x10000>;
93 }; 83 };
94 84
95 v2m@20000 { 85 v2m@20000 {
96 compatible = "arm,gic- 86 compatible = "arm,gic-v2m-frame";
97 msi-controller; 87 msi-controller;
98 reg = <0x20000 0x10000 !! 88 reg = <0 0x20000 0 0x10000>;
99 }; 89 };
100 90
101 v2m@30000 { 91 v2m@30000 {
102 compatible = "arm,gic- 92 compatible = "arm,gic-v2m-frame";
103 msi-controller; 93 msi-controller;
104 reg = <0x30000 0x10000 !! 94 reg = <0 0x30000 0 0x10000>;
105 }; 95 };
106 }; 96 };
107 97
108 timer { 98 timer {
109 compatible = "arm,armv8-timer" 99 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_ 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_ 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_ 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_ 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
114 }; 104 };
115 105
116 /* 106 /*
117 * Juno TRMs specify the size for thes 107 * Juno TRMs specify the size for these coresight components as 64K.
118 * The actual size is just 4K though 6 108 * The actual size is just 4K though 64K is reserved. Access to the
119 * unmapped reserved region results in 109 * unmapped reserved region results in a DECERR response.
120 */ 110 */
121 etf_sys0: etf@20010000 { /* etf0 */ !! 111 etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm 112 compatible = "arm,coresight-tmc", "arm,primecell";
123 reg = <0 0x20010000 0 0x1000>; 113 reg = <0 0x20010000 0 0x1000>;
124 114
125 clocks = <&soc_smc50mhz>; 115 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk"; 116 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0 117 power-domains = <&scpi_devpd 0>;
128 118
129 in-ports { 119 in-ports {
130 port { 120 port {
131 etf0_in_port: 121 etf0_in_port: endpoint {
132 remote 122 remote-endpoint = <&main_funnel_out_port>;
133 }; 123 };
134 }; 124 };
135 }; 125 };
136 126
137 out-ports { 127 out-ports {
138 port { 128 port {
139 etf0_out_port: 129 etf0_out_port: endpoint {
140 }; 130 };
141 }; 131 };
142 }; 132 };
143 }; 133 };
144 134
145 tpiu_sys: tpiu@20030000 { !! 135 tpiu@20030000 {
146 compatible = "arm,coresight-tp 136 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0 0x20030000 0 0x1000>; 137 reg = <0 0x20030000 0 0x1000>;
148 138
149 clocks = <&soc_smc50mhz>; 139 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk"; 140 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0 141 power-domains = <&scpi_devpd 0>;
152 in-ports { 142 in-ports {
153 port { 143 port {
154 tpiu_in_port: 144 tpiu_in_port: endpoint {
155 remote 145 remote-endpoint = <&replicator_out_port0>;
156 }; 146 };
157 }; 147 };
158 }; 148 };
159 }; 149 };
160 150
161 /* main funnel on Juno r0, cssys0 funn 151 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
162 main_funnel: funnel@20040000 { 152 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy 153 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
164 reg = <0 0x20040000 0 0x1000>; 154 reg = <0 0x20040000 0 0x1000>;
165 155
166 clocks = <&soc_smc50mhz>; 156 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk"; 157 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0 158 power-domains = <&scpi_devpd 0>;
169 159
170 out-ports { 160 out-ports {
171 port { 161 port {
172 main_funnel_ou 162 main_funnel_out_port: endpoint {
173 remote 163 remote-endpoint = <&etf0_in_port>;
174 }; 164 };
175 }; 165 };
176 }; 166 };
177 167
178 main_funnel_in_ports: in-ports 168 main_funnel_in_ports: in-ports {
179 #address-cells = <1>; 169 #address-cells = <1>;
180 #size-cells = <0>; 170 #size-cells = <0>;
181 171
182 port@0 { 172 port@0 {
183 reg = <0>; 173 reg = <0>;
184 main_funnel_in 174 main_funnel_in_port0: endpoint {
185 remote 175 remote-endpoint = <&cluster0_funnel_out_port>;
186 }; 176 };
187 }; 177 };
188 178
189 port@1 { 179 port@1 {
190 reg = <1>; 180 reg = <1>;
191 main_funnel_in 181 main_funnel_in_port1: endpoint {
192 remote 182 remote-endpoint = <&cluster1_funnel_out_port>;
193 }; 183 };
194 }; 184 };
195 }; 185 };
196 }; 186 };
197 187
198 etr_sys: etr@20070000 { !! 188 etr@20070000 {
199 compatible = "arm,coresight-tm 189 compatible = "arm,coresight-tmc", "arm,primecell";
200 reg = <0 0x20070000 0 0x1000>; 190 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>; 191 iommus = <&smmu_etr 0>;
202 192
203 clocks = <&soc_smc50mhz>; 193 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk"; 194 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0 195 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather; 196 arm,scatter-gather;
207 in-ports { 197 in-ports {
208 port { 198 port {
209 etr_in_port: e 199 etr_in_port: endpoint {
210 remote 200 remote-endpoint = <&replicator_out_port1>;
211 }; 201 };
212 }; 202 };
213 }; 203 };
214 }; 204 };
215 205
216 stm_sys: stm@20100000 { !! 206 stm@20100000 {
217 compatible = "arm,coresight-st 207 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>, 208 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000 209 <0 0x28000000 0 0x1000000>;
220 reg-names = "stm-base", "stm-s 210 reg-names = "stm-base", "stm-stimulus-base";
221 211
222 clocks = <&soc_smc50mhz>; 212 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk"; 213 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0 214 power-domains = <&scpi_devpd 0>;
225 out-ports { 215 out-ports {
226 port { 216 port {
227 stm_out_port: 217 stm_out_port: endpoint {
228 }; 218 };
229 }; 219 };
230 }; 220 };
231 }; 221 };
232 222
233 replicator@20120000 { 223 replicator@20120000 {
234 compatible = "arm,coresight-dy 224 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
235 reg = <0 0x20120000 0 0x1000>; 225 reg = <0 0x20120000 0 0x1000>;
236 226
237 clocks = <&soc_smc50mhz>; 227 clocks = <&soc_smc50mhz>;
238 clock-names = "apb_pclk"; 228 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0 229 power-domains = <&scpi_devpd 0>;
240 230
241 out-ports { 231 out-ports {
242 #address-cells = <1>; 232 #address-cells = <1>;
243 #size-cells = <0>; 233 #size-cells = <0>;
244 234
245 /* replicator output p 235 /* replicator output ports */
246 port@0 { 236 port@0 {
247 reg = <0>; 237 reg = <0>;
248 replicator_out 238 replicator_out_port0: endpoint {
249 remote 239 remote-endpoint = <&tpiu_in_port>;
250 }; 240 };
251 }; 241 };
252 242
253 port@1 { 243 port@1 {
254 reg = <1>; 244 reg = <1>;
255 replicator_out 245 replicator_out_port1: endpoint {
256 remote 246 remote-endpoint = <&etr_in_port>;
257 }; 247 };
258 }; 248 };
259 }; 249 };
260 in-ports { 250 in-ports {
261 port { 251 port {
262 replicator_in_ 252 replicator_in_port0: endpoint {
263 }; 253 };
264 }; 254 };
265 }; 255 };
266 }; 256 };
267 257
268 cpu_debug0: cpu-debug@22010000 { 258 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp 259 compatible = "arm,coresight-cpu-debug", "arm,primecell";
270 reg = <0x0 0x22010000 0x0 0x10 260 reg = <0x0 0x22010000 0x0 0x1000>;
271 261
272 clocks = <&soc_smc50mhz>; 262 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk"; 263 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0 264 power-domains = <&scpi_devpd 0>;
275 }; 265 };
276 266
277 etm0: etm@22040000 { 267 etm0: etm@22040000 {
278 compatible = "arm,coresight-et 268 compatible = "arm,coresight-etm4x", "arm,primecell";
279 reg = <0 0x22040000 0 0x1000>; 269 reg = <0 0x22040000 0 0x1000>;
280 270
281 clocks = <&soc_smc50mhz>; 271 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk"; 272 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0 273 power-domains = <&scpi_devpd 0>;
284 out-ports { 274 out-ports {
285 port { 275 port {
286 cluster0_etm0_ 276 cluster0_etm0_out_port: endpoint {
287 remote 277 remote-endpoint = <&cluster0_funnel_in_port0>;
288 }; 278 };
289 }; 279 };
290 }; 280 };
291 }; 281 };
292 282
293 cti0: cti@22020000 { <<
294 compatible = "arm,coresight-ct <<
295 "arm,primecell"; <<
296 reg = <0 0x22020000 0 0x1000>; <<
297 <<
298 clocks = <&soc_smc50mhz>; <<
299 clock-names = "apb_pclk"; <<
300 power-domains = <&scpi_devpd 0 <<
301 <<
302 arm,cs-dev-assoc = <&etm0>; <<
303 }; <<
304 <<
305 funnel@220c0000 { /* cluster0 funnel * 283 funnel@220c0000 { /* cluster0 funnel */
306 compatible = "arm,coresight-dy 284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
307 reg = <0 0x220c0000 0 0x1000>; 285 reg = <0 0x220c0000 0 0x1000>;
308 286
309 clocks = <&soc_smc50mhz>; 287 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk"; 288 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0 289 power-domains = <&scpi_devpd 0>;
312 out-ports { 290 out-ports {
313 port { 291 port {
314 cluster0_funne 292 cluster0_funnel_out_port: endpoint {
315 remote 293 remote-endpoint = <&main_funnel_in_port0>;
316 }; 294 };
317 }; 295 };
318 }; 296 };
319 297
320 in-ports { 298 in-ports {
321 #address-cells = <1>; 299 #address-cells = <1>;
322 #size-cells = <0>; 300 #size-cells = <0>;
323 301
324 port@0 { 302 port@0 {
325 reg = <0>; 303 reg = <0>;
326 cluster0_funne 304 cluster0_funnel_in_port0: endpoint {
327 remote 305 remote-endpoint = <&cluster0_etm0_out_port>;
328 }; 306 };
329 }; 307 };
330 308
331 port@1 { 309 port@1 {
332 reg = <1>; 310 reg = <1>;
333 cluster0_funne 311 cluster0_funnel_in_port1: endpoint {
334 remote 312 remote-endpoint = <&cluster0_etm1_out_port>;
335 }; 313 };
336 }; 314 };
337 }; 315 };
338 }; 316 };
339 317
340 cpu_debug1: cpu-debug@22110000 { 318 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp 319 compatible = "arm,coresight-cpu-debug", "arm,primecell";
342 reg = <0x0 0x22110000 0x0 0x10 320 reg = <0x0 0x22110000 0x0 0x1000>;
343 321
344 clocks = <&soc_smc50mhz>; 322 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk"; 323 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0 324 power-domains = <&scpi_devpd 0>;
347 }; 325 };
348 326
349 etm1: etm@22140000 { 327 etm1: etm@22140000 {
350 compatible = "arm,coresight-et 328 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0x22140000 0 0x1000>; 329 reg = <0 0x22140000 0 0x1000>;
352 330
353 clocks = <&soc_smc50mhz>; 331 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk"; 332 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0 333 power-domains = <&scpi_devpd 0>;
356 out-ports { 334 out-ports {
357 port { 335 port {
358 cluster0_etm1_ 336 cluster0_etm1_out_port: endpoint {
359 remote 337 remote-endpoint = <&cluster0_funnel_in_port1>;
360 }; 338 };
361 }; 339 };
362 }; 340 };
363 }; 341 };
364 342
365 cti1: cti@22120000 { <<
366 compatible = "arm,coresight-ct <<
367 "arm,primecell"; <<
368 reg = <0 0x22120000 0 0x1000>; <<
369 <<
370 clocks = <&soc_smc50mhz>; <<
371 clock-names = "apb_pclk"; <<
372 power-domains = <&scpi_devpd 0 <<
373 <<
374 arm,cs-dev-assoc = <&etm1>; <<
375 }; <<
376 <<
377 cpu_debug2: cpu-debug@23010000 { 343 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp 344 compatible = "arm,coresight-cpu-debug", "arm,primecell";
379 reg = <0x0 0x23010000 0x0 0x10 345 reg = <0x0 0x23010000 0x0 0x1000>;
380 346
381 clocks = <&soc_smc50mhz>; 347 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk"; 348 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0 349 power-domains = <&scpi_devpd 0>;
384 }; 350 };
385 351
386 etm2: etm@23040000 { 352 etm2: etm@23040000 {
387 compatible = "arm,coresight-et 353 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0 0x23040000 0 0x1000>; 354 reg = <0 0x23040000 0 0x1000>;
389 355
390 clocks = <&soc_smc50mhz>; 356 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk"; 357 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0 358 power-domains = <&scpi_devpd 0>;
393 out-ports { 359 out-ports {
394 port { 360 port {
395 cluster1_etm0_ 361 cluster1_etm0_out_port: endpoint {
396 remote 362 remote-endpoint = <&cluster1_funnel_in_port0>;
397 }; 363 };
398 }; 364 };
399 }; 365 };
400 }; 366 };
401 367
402 cti2: cti@23020000 { <<
403 compatible = "arm,coresight-ct <<
404 "arm,primecell"; <<
405 reg = <0 0x23020000 0 0x1000>; <<
406 <<
407 clocks = <&soc_smc50mhz>; <<
408 clock-names = "apb_pclk"; <<
409 power-domains = <&scpi_devpd 0 <<
410 <<
411 arm,cs-dev-assoc = <&etm2>; <<
412 }; <<
413 <<
414 funnel@230c0000 { /* cluster1 funnel * 368 funnel@230c0000 { /* cluster1 funnel */
415 compatible = "arm,coresight-dy 369 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
416 reg = <0 0x230c0000 0 0x1000>; 370 reg = <0 0x230c0000 0 0x1000>;
417 371
418 clocks = <&soc_smc50mhz>; 372 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk"; 373 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0 374 power-domains = <&scpi_devpd 0>;
421 out-ports { 375 out-ports {
422 port { 376 port {
423 cluster1_funne 377 cluster1_funnel_out_port: endpoint {
424 remote 378 remote-endpoint = <&main_funnel_in_port1>;
425 }; 379 };
426 }; 380 };
427 }; 381 };
428 382
429 in-ports { 383 in-ports {
430 #address-cells = <1>; 384 #address-cells = <1>;
431 #size-cells = <0>; 385 #size-cells = <0>;
432 386
433 port@0 { 387 port@0 {
434 reg = <0>; 388 reg = <0>;
435 cluster1_funne 389 cluster1_funnel_in_port0: endpoint {
436 remote 390 remote-endpoint = <&cluster1_etm0_out_port>;
437 }; 391 };
438 }; 392 };
439 393
440 port@1 { 394 port@1 {
441 reg = <1>; 395 reg = <1>;
442 cluster1_funne 396 cluster1_funnel_in_port1: endpoint {
443 remote 397 remote-endpoint = <&cluster1_etm1_out_port>;
444 }; 398 };
445 }; 399 };
446 port@2 { 400 port@2 {
447 reg = <2>; 401 reg = <2>;
448 cluster1_funne 402 cluster1_funnel_in_port2: endpoint {
449 remote 403 remote-endpoint = <&cluster1_etm2_out_port>;
450 }; 404 };
451 }; 405 };
452 port@3 { 406 port@3 {
453 reg = <3>; 407 reg = <3>;
454 cluster1_funne 408 cluster1_funnel_in_port3: endpoint {
455 remote 409 remote-endpoint = <&cluster1_etm3_out_port>;
456 }; 410 };
457 }; 411 };
458 }; 412 };
459 }; 413 };
460 414
461 cpu_debug3: cpu-debug@23110000 { 415 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp 416 compatible = "arm,coresight-cpu-debug", "arm,primecell";
463 reg = <0x0 0x23110000 0x0 0x10 417 reg = <0x0 0x23110000 0x0 0x1000>;
464 418
465 clocks = <&soc_smc50mhz>; 419 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk"; 420 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0 421 power-domains = <&scpi_devpd 0>;
468 }; 422 };
469 423
470 etm3: etm@23140000 { 424 etm3: etm@23140000 {
471 compatible = "arm,coresight-et 425 compatible = "arm,coresight-etm4x", "arm,primecell";
472 reg = <0 0x23140000 0 0x1000>; 426 reg = <0 0x23140000 0 0x1000>;
473 427
474 clocks = <&soc_smc50mhz>; 428 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk"; 429 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0 430 power-domains = <&scpi_devpd 0>;
477 out-ports { 431 out-ports {
478 port { 432 port {
479 cluster1_etm1_ 433 cluster1_etm1_out_port: endpoint {
480 remote 434 remote-endpoint = <&cluster1_funnel_in_port1>;
481 }; 435 };
482 }; 436 };
483 }; 437 };
484 }; 438 };
485 439
486 cti3: cti@23120000 { <<
487 compatible = "arm,coresight-ct <<
488 "arm,primecell"; <<
489 reg = <0 0x23120000 0 0x1000>; <<
490 <<
491 clocks = <&soc_smc50mhz>; <<
492 clock-names = "apb_pclk"; <<
493 power-domains = <&scpi_devpd 0 <<
494 <<
495 arm,cs-dev-assoc = <&etm3>; <<
496 }; <<
497 <<
498 cpu_debug4: cpu-debug@23210000 { 440 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp 441 compatible = "arm,coresight-cpu-debug", "arm,primecell";
500 reg = <0x0 0x23210000 0x0 0x10 442 reg = <0x0 0x23210000 0x0 0x1000>;
501 443
502 clocks = <&soc_smc50mhz>; 444 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk"; 445 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0 446 power-domains = <&scpi_devpd 0>;
505 }; 447 };
506 448
507 etm4: etm@23240000 { 449 etm4: etm@23240000 {
508 compatible = "arm,coresight-et 450 compatible = "arm,coresight-etm4x", "arm,primecell";
509 reg = <0 0x23240000 0 0x1000>; 451 reg = <0 0x23240000 0 0x1000>;
510 452
511 clocks = <&soc_smc50mhz>; 453 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk"; 454 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0 455 power-domains = <&scpi_devpd 0>;
514 out-ports { 456 out-ports {
515 port { 457 port {
516 cluster1_etm2_ 458 cluster1_etm2_out_port: endpoint {
517 remote 459 remote-endpoint = <&cluster1_funnel_in_port2>;
518 }; 460 };
519 }; 461 };
520 }; 462 };
521 }; 463 };
522 464
523 cti4: cti@23220000 { <<
524 compatible = "arm,coresight-ct <<
525 "arm,primecell"; <<
526 reg = <0 0x23220000 0 0x1000>; <<
527 <<
528 clocks = <&soc_smc50mhz>; <<
529 clock-names = "apb_pclk"; <<
530 power-domains = <&scpi_devpd 0 <<
531 <<
532 arm,cs-dev-assoc = <&etm4>; <<
533 }; <<
534 <<
535 cpu_debug5: cpu-debug@23310000 { 465 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp 466 compatible = "arm,coresight-cpu-debug", "arm,primecell";
537 reg = <0x0 0x23310000 0x0 0x10 467 reg = <0x0 0x23310000 0x0 0x1000>;
538 468
539 clocks = <&soc_smc50mhz>; 469 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk"; 470 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0 471 power-domains = <&scpi_devpd 0>;
542 }; 472 };
543 473
544 etm5: etm@23340000 { 474 etm5: etm@23340000 {
545 compatible = "arm,coresight-et 475 compatible = "arm,coresight-etm4x", "arm,primecell";
546 reg = <0 0x23340000 0 0x1000>; 476 reg = <0 0x23340000 0 0x1000>;
547 477
548 clocks = <&soc_smc50mhz>; 478 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk"; 479 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0 480 power-domains = <&scpi_devpd 0>;
551 out-ports { 481 out-ports {
552 port { 482 port {
553 cluster1_etm3_ 483 cluster1_etm3_out_port: endpoint {
554 remote 484 remote-endpoint = <&cluster1_funnel_in_port3>;
555 }; 485 };
556 }; 486 };
557 }; 487 };
558 }; 488 };
559 489
560 cti5: cti@23320000 { <<
561 compatible = "arm,coresight-ct <<
562 "arm,primecell"; <<
563 reg = <0 0x23320000 0 0x1000>; <<
564 <<
565 clocks = <&soc_smc50mhz>; <<
566 clock-names = "apb_pclk"; <<
567 power-domains = <&scpi_devpd 0 <<
568 <<
569 arm,cs-dev-assoc = <&etm5>; <<
570 }; <<
571 <<
572 cti_sys0: cti@20020000 { /* sys_cti_0 <<
573 compatible = "arm,coresight-ct <<
574 reg = <0 0x20020000 0 0x1000>; <<
575 <<
576 clocks = <&soc_smc50mhz>; <<
577 clock-names = "apb_pclk"; <<
578 power-domains = <&scpi_devpd 0 <<
579 <<
580 #address-cells = <1>; <<
581 #size-cells = <0>; <<
582 <<
583 trig-conns@0 { <<
584 reg = <0>; <<
585 arm,trig-in-sigs = <2 <<
586 arm,trig-in-types = <S <<
587 arm,trig-out-sigs = <0 <<
588 arm,trig-out-types = < <<
589 arm,cs-dev-assoc = <&e <<
590 }; <<
591 <<
592 trig-conns@1 { <<
593 reg = <1>; <<
594 arm,trig-in-sigs = <0 <<
595 arm,trig-in-types = <S <<
596 arm,trig-out-sigs = <7 <<
597 arm,trig-out-types = < <<
598 arm,cs-dev-assoc = <&e <<
599 }; <<
600 <<
601 trig-conns@2 { <<
602 reg = <2>; <<
603 arm,trig-in-sigs = <4 <<
604 arm,trig-in-types = <S <<
605 STM <<
606 arm,trig-out-sigs = <4 <<
607 arm,trig-out-types = < <<
608 arm,cs-dev-assoc = <&s <<
609 }; <<
610 <<
611 trig-conns@3 { <<
612 reg = <3>; <<
613 arm,trig-out-sigs = <2 <<
614 arm,trig-out-types = < <<
615 arm,cs-dev-assoc = <&t <<
616 }; <<
617 }; <<
618 <<
619 cti_sys1: cti@20110000 { /* sys_cti_1 <<
620 compatible = "arm,coresight-ct <<
621 reg = <0 0x20110000 0 0x1000>; <<
622 <<
623 clocks = <&soc_smc50mhz>; <<
624 clock-names = "apb_pclk"; <<
625 power-domains = <&scpi_devpd 0 <<
626 <<
627 #address-cells = <1>; <<
628 #size-cells = <0>; <<
629 <<
630 trig-conns@0 { <<
631 reg = <0>; <<
632 arm,trig-in-sigs = <0> <<
633 arm,trig-in-types = <G <<
634 arm,trig-out-sigs = <0 <<
635 arm,trig-out-types = < <<
636 arm,trig-conn-name = " <<
637 }; <<
638 <<
639 trig-conns@1 { <<
640 reg = <1>; <<
641 arm,trig-out-sigs = <2 <<
642 arm,trig-out-types = < <<
643 arm,trig-conn-name = " <<
644 }; <<
645 <<
646 trig-conns@2 { <<
647 reg = <2>; <<
648 arm,trig-out-sigs = <1 <<
649 arm,trig-out-types = < <<
650 arm,trig-conn-name = " <<
651 }; <<
652 }; <<
653 <<
654 gpu: gpu@2d000000 { <<
655 compatible = "arm,juno-mali", <<
656 reg = <0 0x2d000000 0 0x10000> <<
657 interrupts = <GIC_SPI 33 IRQ_T <<
658 <GIC_SPI 34 IRQ_T <<
659 <GIC_SPI 32 IRQ_T <<
660 interrupt-names = "job", "mmu" <<
661 clocks = <&scpi_dvfs 2>; <<
662 power-domains = <&scpi_devpd 1 <<
663 dma-coherent; <<
664 /* The SMMU is only really of <<
665 /* iommus = <&smmu_gpu 0>; */ <<
666 }; <<
667 <<
668 sram: sram@2e000000 { 490 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns 491 compatible = "arm,juno-sram-ns", "mmio-sram";
670 reg = <0x0 0x2e000000 0x0 0x80 492 reg = <0x0 0x2e000000 0x0 0x8000>;
671 493
672 #address-cells = <1>; 494 #address-cells = <1>;
673 #size-cells = <1>; 495 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8 496 ranges = <0 0x0 0x2e000000 0x8000>;
675 497
676 cpu_scp_lpri: scp-sram@0 { !! 498 cpu_scp_lpri: scp-shmem@0 {
677 compatible = "arm,juno 499 compatible = "arm,juno-scp-shmem";
678 reg = <0x0 0x200>; 500 reg = <0x0 0x200>;
679 }; 501 };
680 502
681 cpu_scp_hpri: scp-sram@200 { !! 503 cpu_scp_hpri: scp-shmem@200 {
682 compatible = "arm,juno 504 compatible = "arm,juno-scp-shmem";
683 reg = <0x200 0x200>; 505 reg = <0x200 0x200>;
684 }; 506 };
685 }; 507 };
686 508
687 pcie_ctlr: pcie@40000000 { 509 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie 510 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
689 device_type = "pci"; 511 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000 512 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
691 bus-range = <0 255>; 513 bus-range = <0 255>;
692 linux,pci-domain = <0>; 514 linux,pci-domain = <0>;
693 #address-cells = <3>; 515 #address-cells = <3>;
694 #size-cells = <2>; 516 #size-cells = <2>;
695 dma-coherent; 517 dma-coherent;
696 ranges = <0x01000000 0x00 0x00 518 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
697 <0x02000000 0x00 0x50 519 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
698 <0x42000000 0x40 0x00 520 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
699 /* Standard AXI Translation en <<
700 dma-ranges = <0x02000000 0x0 0 <<
701 <0x43000000 0x8 0 <<
702 #interrupt-cells = <1>; 521 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7> 522 interrupt-map-mask = <0 0 0 7>;
704 interrupt-map = <0 0 0 1 &gic !! 523 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 0 2 &gic !! 524 <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 0 3 &gic !! 525 <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
707 <0 0 0 4 &gic !! 526 <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
708 msi-parent = <&v2m_0>; 527 msi-parent = <&v2m_0>;
709 status = "disabled"; 528 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC 529 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
711 iommu-map = <0x0 &smmu_pcie 0x 530 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
712 }; 531 };
713 532
714 scpi { 533 scpi {
715 compatible = "arm,scpi"; 534 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>; 535 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>; 536 shmem = <&cpu_scp_hpri>;
718 537
719 clocks { 538 clocks {
720 compatible = "arm,scpi 539 compatible = "arm,scpi-clocks";
721 540
722 scpi_dvfs: clocks-0 { !! 541 scpi_dvfs: scpi-dvfs {
723 compatible = " 542 compatible = "arm,scpi-dvfs-clocks";
724 #clock-cells = 543 #clock-cells = <1>;
725 clock-indices 544 clock-indices = <0>, <1>, <2>;
726 clock-output-n 545 clock-output-names = "atlclk", "aplclk","gpuclk";
727 }; 546 };
728 scpi_clk: clocks-1 { !! 547 scpi_clk: scpi-clk {
729 compatible = " 548 compatible = "arm,scpi-variable-clocks";
730 #clock-cells = 549 #clock-cells = <1>;
731 clock-indices 550 clock-indices = <3>;
732 clock-output-n 551 clock-output-names = "pxlclk";
733 }; 552 };
734 }; 553 };
735 554
736 scpi_devpd: power-controller { !! 555 scpi_devpd: scpi-power-domains {
737 compatible = "arm,scpi 556 compatible = "arm,scpi-power-domains";
738 num-domains = <2>; 557 num-domains = <2>;
739 #power-domain-cells = 558 #power-domain-cells = <1>;
740 }; 559 };
741 560
742 scpi_sensors0: sensors { 561 scpi_sensors0: sensors {
743 compatible = "arm,scpi 562 compatible = "arm,scpi-sensors";
744 #thermal-sensor-cells 563 #thermal-sensor-cells = <1>;
745 }; 564 };
746 }; 565 };
747 566
748 thermal-zones { 567 thermal-zones {
749 pmic-thermal { !! 568 pmic {
750 polling-delay = <1000> 569 polling-delay = <1000>;
751 polling-delay-passive 570 polling-delay-passive = <100>;
752 thermal-sensors = <&sc 571 thermal-sensors = <&scpi_sensors0 0>;
753 trips { <<
754 pmic_crit0: tr <<
755 temper <<
756 hyster <<
757 type = <<
758 }; <<
759 }; <<
760 }; 572 };
761 573
762 soc-thermal { !! 574 soc {
763 polling-delay = <1000> 575 polling-delay = <1000>;
764 polling-delay-passive 576 polling-delay-passive = <100>;
765 thermal-sensors = <&sc 577 thermal-sensors = <&scpi_sensors0 3>;
766 trips { <<
767 soc_crit0: tri <<
768 temper <<
769 hyster <<
770 type = <<
771 }; <<
772 }; <<
773 }; 578 };
774 579
775 big_cluster_thermal_zone: big- !! 580 big_cluster_thermal_zone: big-cluster {
776 polling-delay = <1000> 581 polling-delay = <1000>;
777 polling-delay-passive 582 polling-delay-passive = <100>;
778 thermal-sensors = <&sc 583 thermal-sensors = <&scpi_sensors0 21>;
779 status = "disabled"; 584 status = "disabled";
780 }; 585 };
781 586
782 little_cluster_thermal_zone: l !! 587 little_cluster_thermal_zone: little-cluster {
783 polling-delay = <1000> 588 polling-delay = <1000>;
784 polling-delay-passive 589 polling-delay-passive = <100>;
785 thermal-sensors = <&sc 590 thermal-sensors = <&scpi_sensors0 22>;
786 status = "disabled"; 591 status = "disabled";
787 }; 592 };
788 593
789 gpu0_thermal_zone: gpu0-therma !! 594 gpu0_thermal_zone: gpu0 {
790 polling-delay = <1000> 595 polling-delay = <1000>;
791 polling-delay-passive 596 polling-delay-passive = <100>;
792 thermal-sensors = <&sc 597 thermal-sensors = <&scpi_sensors0 23>;
793 status = "disabled"; 598 status = "disabled";
794 }; 599 };
795 600
796 gpu1_thermal_zone: gpu1-therma !! 601 gpu1_thermal_zone: gpu1 {
797 polling-delay = <1000> 602 polling-delay = <1000>;
798 polling-delay-passive 603 polling-delay-passive = <100>;
799 thermal-sensors = <&sc 604 thermal-sensors = <&scpi_sensors0 24>;
800 status = "disabled"; 605 status = "disabled";
801 }; 606 };
802 }; 607 };
803 608
804 smmu_dma: iommu@7fb00000 { 609 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a 610 compatible = "arm,mmu-401", "arm,smmu-v1";
806 reg = <0x0 0x7fb00000 0x0 0x10 611 reg = <0x0 0x7fb00000 0x0 0x10000>;
807 interrupts = <GIC_SPI 95 IRQ_T 612 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 95 IRQ_T 613 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
809 #iommu-cells = <1>; 614 #iommu-cells = <1>;
810 #global-interrupts = <1>; 615 #global-interrupts = <1>;
811 dma-coherent; 616 dma-coherent;
>> 617 status = "disabled";
812 }; 618 };
813 619
814 smmu_hdlcd1: iommu@7fb10000 { 620 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a 621 compatible = "arm,mmu-401", "arm,smmu-v1";
816 reg = <0x0 0x7fb10000 0x0 0x10 622 reg = <0x0 0x7fb10000 0x0 0x10000>;
817 interrupts = <GIC_SPI 99 IRQ_T 623 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 99 IRQ_T 624 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
819 #iommu-cells = <1>; 625 #iommu-cells = <1>;
820 #global-interrupts = <1>; 626 #global-interrupts = <1>;
821 }; 627 };
822 628
823 smmu_hdlcd0: iommu@7fb20000 { 629 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a 630 compatible = "arm,mmu-401", "arm,smmu-v1";
825 reg = <0x0 0x7fb20000 0x0 0x10 631 reg = <0x0 0x7fb20000 0x0 0x10000>;
826 interrupts = <GIC_SPI 97 IRQ_T 632 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 97 IRQ_T 633 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
828 #iommu-cells = <1>; 634 #iommu-cells = <1>;
829 #global-interrupts = <1>; 635 #global-interrupts = <1>;
830 }; 636 };
831 637
832 smmu_usb: iommu@7fb30000 { 638 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a 639 compatible = "arm,mmu-401", "arm,smmu-v1";
834 reg = <0x0 0x7fb30000 0x0 0x10 640 reg = <0x0 0x7fb30000 0x0 0x10000>;
835 interrupts = <GIC_SPI 101 IRQ_ 641 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 101 IRQ_ 642 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
837 #iommu-cells = <1>; 643 #iommu-cells = <1>;
838 #global-interrupts = <1>; 644 #global-interrupts = <1>;
839 dma-coherent; 645 dma-coherent;
840 }; 646 };
841 647
842 dma-controller@7ff00000 { !! 648 dma@7ff00000 {
843 compatible = "arm,pl330", "arm 649 compatible = "arm,pl330", "arm,primecell";
844 reg = <0x0 0x7ff00000 0 0x1000 650 reg = <0x0 0x7ff00000 0 0x1000>;
845 #dma-cells = <1>; 651 #dma-cells = <1>;
>> 652 #dma-channels = <8>;
>> 653 #dma-requests = <32>;
846 interrupts = <GIC_SPI 88 IRQ_T 654 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 89 IRQ_T 655 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 90 IRQ_T 656 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 91 IRQ_T 657 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 92 IRQ_T 658 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 108 IRQ_ 659 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 109 IRQ_ 660 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 110 IRQ_ 661 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 111 IRQ_ 662 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 iommus = <&smmu_dma 0>, 663 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>, 664 <&smmu_dma 1>,
857 <&smmu_dma 2>, 665 <&smmu_dma 2>,
858 <&smmu_dma 3>, 666 <&smmu_dma 3>,
859 <&smmu_dma 4>, 667 <&smmu_dma 4>,
860 <&smmu_dma 5>, 668 <&smmu_dma 5>,
861 <&smmu_dma 6>, 669 <&smmu_dma 6>,
862 <&smmu_dma 7>, 670 <&smmu_dma 7>,
863 <&smmu_dma 8>; 671 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>; 672 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk"; 673 clock-names = "apb_pclk";
866 }; 674 };
867 675
868 hdlcd@7ff50000 { 676 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd"; 677 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>; 678 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T 679 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 iommus = <&smmu_hdlcd1 0>; 680 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>; 681 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk"; 682 clock-names = "pxlclk";
875 683
876 port { 684 port {
877 hdlcd1_output: endpoin 685 hdlcd1_output: endpoint {
878 remote-endpoin 686 remote-endpoint = <&tda998x_1_input>;
879 }; 687 };
880 }; 688 };
881 }; 689 };
882 690
883 hdlcd@7ff60000 { 691 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd"; 692 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>; 693 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T 694 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
887 iommus = <&smmu_hdlcd0 0>; 695 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>; 696 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk"; 697 clock-names = "pxlclk";
890 698
891 port { 699 port {
892 hdlcd0_output: endpoin 700 hdlcd0_output: endpoint {
893 remote-endpoin 701 remote-endpoint = <&tda998x_0_input>;
894 }; 702 };
895 }; 703 };
896 }; 704 };
897 705
898 soc_uart0: serial@7ff80000 { !! 706 soc_uart0: uart@7ff80000 {
899 compatible = "arm,pl011", "arm 707 compatible = "arm,pl011", "arm,primecell";
900 reg = <0x0 0x7ff80000 0x0 0x10 708 reg = <0x0 0x7ff80000 0x0 0x1000>;
901 interrupts = <GIC_SPI 83 IRQ_T 709 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&soc_uartclk>, <&soc 710 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
903 clock-names = "uartclk", "apb_ 711 clock-names = "uartclk", "apb_pclk";
904 }; 712 };
905 713
906 i2c@7ffa0000 { 714 i2c@7ffa0000 {
907 compatible = "snps,designware- 715 compatible = "snps,designware-i2c";
908 reg = <0x0 0x7ffa0000 0x0 0x10 716 reg = <0x0 0x7ffa0000 0x0 0x1000>;
909 #address-cells = <1>; 717 #address-cells = <1>;
910 #size-cells = <0>; 718 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_ 719 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
912 clock-frequency = <400000>; 720 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>; 721 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>; 722 clocks = <&soc_smc50mhz>;
915 723
916 hdmi-transmitter@70 { 724 hdmi-transmitter@70 {
917 compatible = "nxp,tda9 725 compatible = "nxp,tda998x";
918 reg = <0x70>; 726 reg = <0x70>;
919 port { 727 port {
920 tda998x_0_inpu 728 tda998x_0_input: endpoint {
921 remote 729 remote-endpoint = <&hdlcd0_output>;
922 }; 730 };
923 }; 731 };
924 }; 732 };
925 733
926 hdmi-transmitter@71 { 734 hdmi-transmitter@71 {
927 compatible = "nxp,tda9 735 compatible = "nxp,tda998x";
928 reg = <0x71>; 736 reg = <0x71>;
929 port { 737 port {
930 tda998x_1_inpu 738 tda998x_1_input: endpoint {
931 remote 739 remote-endpoint = <&hdlcd1_output>;
932 }; 740 };
933 }; 741 };
934 }; 742 };
935 }; 743 };
936 744
937 usb@7ffb0000 { !! 745 ohci@7ffb0000 {
938 compatible = "generic-ohci"; 746 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10 747 reg = <0x0 0x7ffb0000 0x0 0x10000>;
940 interrupts = <GIC_SPI 116 IRQ_ 748 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
941 iommus = <&smmu_usb 0>; 749 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>; 750 clocks = <&soc_usb48mhz>;
943 }; 751 };
944 752
945 usb@7ffc0000 { !! 753 ehci@7ffc0000 {
946 compatible = "generic-ehci"; 754 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10 755 reg = <0x0 0x7ffc0000 0x0 0x10000>;
948 interrupts = <GIC_SPI 117 IRQ_ 756 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
949 iommus = <&smmu_usb 0>; 757 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>; 758 clocks = <&soc_usb48mhz>;
951 }; 759 };
952 760
953 memory-controller@7ffd0000 { 761 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm 762 compatible = "arm,pl354", "arm,primecell";
955 reg = <0 0x7ffd0000 0 0x1000>; 763 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T 764 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 87 IRQ_T 765 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&soc_smc50mhz>; 766 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk"; 767 clock-names = "apb_pclk";
960 }; 768 };
961 769
962 memory@80000000 { 770 memory@80000000 {
963 device_type = "memory"; 771 device_type = "memory";
964 /* last 16MB of the first memo 772 /* last 16MB of the first memory area is reserved for secure world use by firmware */
965 reg = <0x00000000 0x80000000 0 773 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
966 <0x00000008 0x80000000 0 774 <0x00000008 0x80000000 0x1 0x80000000>;
967 }; 775 };
968 776
969 bus@8000000 { !! 777 smb@8000000 {
>> 778 compatible = "simple-bus";
>> 779 #address-cells = <2>;
>> 780 #size-cells = <1>;
>> 781 ranges = <0 0 0 0x08000000 0x04000000>,
>> 782 <1 0 0 0x14000000 0x04000000>,
>> 783 <2 0 0 0x18000000 0x04000000>,
>> 784 <3 0 0 0x1c000000 0x04000000>,
>> 785 <4 0 0 0x0c000000 0x04000000>,
>> 786 <5 0 0 0x10000000 0x04000000>;
>> 787
970 #interrupt-cells = <1>; 788 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>; 789 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0 !! 790 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
973 <0 0 1 &gic 0 !! 791 <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
974 <0 0 2 &gic 0 !! 792 <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 3 &gic 0 !! 793 <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 4 &gic 0 !! 794 <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 5 &gic 0 !! 795 <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
978 <0 0 6 &gic 0 !! 796 <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
979 <0 0 7 &gic 0 !! 797 <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
980 <0 0 8 &gic 0 !! 798 <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
981 <0 0 9 &gic 0 !! 799 <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 10 &gic 0 !! 800 <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 11 &gic 0 !! 801 <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 12 &gic 0 !! 802 <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
985 }; 803 };
986 804
987 site2: tlx-bus@60000000 { !! 805 site2: tlx@60000000 {
988 compatible = "simple-bus"; 806 compatible = "simple-bus";
989 #address-cells = <1>; 807 #address-cells = <1>;
990 #size-cells = <1>; 808 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100 809 ranges = <0 0 0x60000000 0x10000000>;
992 #interrupt-cells = <1>; 810 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>; 811 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI !! 812 interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
995 }; 813 };
996 }; 814 };
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