1 /* 1 /*
2 * ARM Ltd. Juno Platform 2 * ARM Ltd. Juno Platform
3 * 3 *
4 * Copyright (c) 2015 ARM Ltd. 4 * Copyright (c) 2015 ARM Ltd.
5 * 5 *
6 * This file is licensed under a dual GPLv2 or 6 * This file is licensed under a dual GPLv2 or BSD license.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h> <<
13 #include "juno-base.dtsi" 12 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi" 13 #include "juno-cs-r1r2.dtsi"
15 14
16 / { 15 / {
17 model = "ARM Juno development board (r 16 model = "ARM Juno development board (r2)";
18 compatible = "arm,juno-r2", "arm,juno" 17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
20 #address-cells = <2>; 19 #address-cells = <2>;
21 #size-cells = <2>; 20 #size-cells = <2>;
22 21
23 aliases { 22 aliases {
24 serial0 = &soc_uart0; 23 serial0 = &soc_uart0;
25 }; 24 };
26 25
27 chosen { 26 chosen {
28 stdout-path = "serial0:115200n 27 stdout-path = "serial0:115200n8";
29 }; 28 };
30 29
31 psci { 30 psci {
32 compatible = "arm,psci-0.2"; 31 compatible = "arm,psci-0.2";
33 method = "smc"; 32 method = "smc";
34 }; 33 };
35 34
36 cpus { 35 cpus {
37 #address-cells = <2>; 36 #address-cells = <2>;
38 #size-cells = <0>; 37 #size-cells = <0>;
39 38
40 cpu-map { 39 cpu-map {
41 cluster0 { 40 cluster0 {
42 core0 { 41 core0 {
43 cpu = 42 cpu = <&A72_0>;
44 }; 43 };
45 core1 { 44 core1 {
46 cpu = 45 cpu = <&A72_1>;
47 }; 46 };
48 }; 47 };
49 48
50 cluster1 { 49 cluster1 {
51 core0 { 50 core0 {
52 cpu = 51 cpu = <&A53_0>;
53 }; 52 };
54 core1 { 53 core1 {
55 cpu = 54 cpu = <&A53_1>;
56 }; 55 };
57 core2 { 56 core2 {
58 cpu = 57 cpu = <&A53_2>;
59 }; 58 };
60 core3 { 59 core3 {
61 cpu = 60 cpu = <&A53_3>;
62 }; 61 };
63 }; 62 };
64 }; 63 };
65 64
66 idle-states { 65 idle-states {
67 entry-method = "psci"; !! 66 entry-method = "arm,psci";
68 67
69 CPU_SLEEP_0: cpu-sleep 68 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = " 69 compatible = "arm,idle-state";
71 arm,psci-suspe 70 arm,psci-suspend-param = <0x0010000>;
72 local-timer-st 71 local-timer-stop;
73 entry-latency- 72 entry-latency-us = <300>;
74 exit-latency-u 73 exit-latency-us = <1200>;
75 min-residency- 74 min-residency-us = <2000>;
76 }; 75 };
77 76
78 CLUSTER_SLEEP_0: clust 77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = " 78 compatible = "arm,idle-state";
80 arm,psci-suspe 79 arm,psci-suspend-param = <0x1010000>;
81 local-timer-st 80 local-timer-stop;
82 entry-latency- 81 entry-latency-us = <400>;
83 exit-latency-u 82 exit-latency-us = <1200>;
84 min-residency- 83 min-residency-us = <2500>;
85 }; 84 };
86 }; 85 };
87 86
88 A72_0: cpu@0 { 87 A72_0: cpu@0 {
89 compatible = "arm,cort !! 88 compatible = "arm,cortex-a72","arm,armv8";
90 reg = <0x0 0x0>; 89 reg = <0x0 0x0>;
91 device_type = "cpu"; 90 device_type = "cpu";
92 enable-method = "psci" 91 enable-method = "psci";
93 i-cache-size = <0xc000 92 i-cache-size = <0xc000>;
94 i-cache-line-size = <6 93 i-cache-line-size = <64>;
95 i-cache-sets = <256>; 94 i-cache-sets = <256>;
96 d-cache-size = <0x8000 95 d-cache-size = <0x8000>;
97 d-cache-line-size = <6 96 d-cache-line-size = <64>;
98 d-cache-sets = <256>; 97 d-cache-sets = <256>;
99 next-level-cache = <&A 98 next-level-cache = <&A72_L2>;
100 clocks = <&scpi_dvfs 0 99 clocks = <&scpi_dvfs 0>;
101 cpu-idle-states = <&CP 100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = < 101 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici <<
104 }; 102 };
105 103
106 A72_1: cpu@1 { 104 A72_1: cpu@1 {
107 compatible = "arm,cort !! 105 compatible = "arm,cortex-a72","arm,armv8";
108 reg = <0x0 0x1>; 106 reg = <0x0 0x1>;
109 device_type = "cpu"; 107 device_type = "cpu";
110 enable-method = "psci" 108 enable-method = "psci";
111 i-cache-size = <0xc000 109 i-cache-size = <0xc000>;
112 i-cache-line-size = <6 110 i-cache-line-size = <64>;
113 i-cache-sets = <256>; 111 i-cache-sets = <256>;
114 d-cache-size = <0x8000 112 d-cache-size = <0x8000>;
115 d-cache-line-size = <6 113 d-cache-line-size = <64>;
116 d-cache-sets = <256>; 114 d-cache-sets = <256>;
117 next-level-cache = <&A 115 next-level-cache = <&A72_L2>;
118 clocks = <&scpi_dvfs 0 116 clocks = <&scpi_dvfs 0>;
119 cpu-idle-states = <&CP 117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <1024>;
121 dynamic-power-coeffici <<
122 }; 119 };
123 120
124 A53_0: cpu@100 { 121 A53_0: cpu@100 {
125 compatible = "arm,cort !! 122 compatible = "arm,cortex-a53","arm,armv8";
126 reg = <0x0 0x100>; 123 reg = <0x0 0x100>;
127 device_type = "cpu"; 124 device_type = "cpu";
128 enable-method = "psci" 125 enable-method = "psci";
129 i-cache-size = <0x8000 126 i-cache-size = <0x8000>;
130 i-cache-line-size = <6 127 i-cache-line-size = <64>;
131 i-cache-sets = <256>; 128 i-cache-sets = <256>;
132 d-cache-size = <0x8000 129 d-cache-size = <0x8000>;
133 d-cache-line-size = <6 130 d-cache-line-size = <64>;
134 d-cache-sets = <128>; 131 d-cache-sets = <128>;
135 next-level-cache = <&A 132 next-level-cache = <&A53_L2>;
136 clocks = <&scpi_dvfs 1 133 clocks = <&scpi_dvfs 1>;
137 cpu-idle-states = <&CP 134 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 capacity-dmips-mhz = < 135 capacity-dmips-mhz = <485>;
139 dynamic-power-coeffici <<
140 }; 136 };
141 137
142 A53_1: cpu@101 { 138 A53_1: cpu@101 {
143 compatible = "arm,cort !! 139 compatible = "arm,cortex-a53","arm,armv8";
144 reg = <0x0 0x101>; 140 reg = <0x0 0x101>;
145 device_type = "cpu"; 141 device_type = "cpu";
146 enable-method = "psci" 142 enable-method = "psci";
147 i-cache-size = <0x8000 143 i-cache-size = <0x8000>;
148 i-cache-line-size = <6 144 i-cache-line-size = <64>;
149 i-cache-sets = <256>; 145 i-cache-sets = <256>;
150 d-cache-size = <0x8000 146 d-cache-size = <0x8000>;
151 d-cache-line-size = <6 147 d-cache-line-size = <64>;
152 d-cache-sets = <128>; 148 d-cache-sets = <128>;
153 next-level-cache = <&A 149 next-level-cache = <&A53_L2>;
154 clocks = <&scpi_dvfs 1 150 clocks = <&scpi_dvfs 1>;
155 cpu-idle-states = <&CP 151 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 capacity-dmips-mhz = < 152 capacity-dmips-mhz = <485>;
157 dynamic-power-coeffici <<
158 }; 153 };
159 154
160 A53_2: cpu@102 { 155 A53_2: cpu@102 {
161 compatible = "arm,cort !! 156 compatible = "arm,cortex-a53","arm,armv8";
162 reg = <0x0 0x102>; 157 reg = <0x0 0x102>;
163 device_type = "cpu"; 158 device_type = "cpu";
164 enable-method = "psci" 159 enable-method = "psci";
165 i-cache-size = <0x8000 160 i-cache-size = <0x8000>;
166 i-cache-line-size = <6 161 i-cache-line-size = <64>;
167 i-cache-sets = <256>; 162 i-cache-sets = <256>;
168 d-cache-size = <0x8000 163 d-cache-size = <0x8000>;
169 d-cache-line-size = <6 164 d-cache-line-size = <64>;
170 d-cache-sets = <128>; 165 d-cache-sets = <128>;
171 next-level-cache = <&A 166 next-level-cache = <&A53_L2>;
172 clocks = <&scpi_dvfs 1 167 clocks = <&scpi_dvfs 1>;
173 cpu-idle-states = <&CP 168 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174 capacity-dmips-mhz = < 169 capacity-dmips-mhz = <485>;
175 dynamic-power-coeffici <<
176 }; 170 };
177 171
178 A53_3: cpu@103 { 172 A53_3: cpu@103 {
179 compatible = "arm,cort !! 173 compatible = "arm,cortex-a53","arm,armv8";
180 reg = <0x0 0x103>; 174 reg = <0x0 0x103>;
181 device_type = "cpu"; 175 device_type = "cpu";
182 enable-method = "psci" 176 enable-method = "psci";
183 i-cache-size = <0x8000 177 i-cache-size = <0x8000>;
184 i-cache-line-size = <6 178 i-cache-line-size = <64>;
185 i-cache-sets = <256>; 179 i-cache-sets = <256>;
186 d-cache-size = <0x8000 180 d-cache-size = <0x8000>;
187 d-cache-line-size = <6 181 d-cache-line-size = <64>;
188 d-cache-sets = <128>; 182 d-cache-sets = <128>;
189 next-level-cache = <&A 183 next-level-cache = <&A53_L2>;
190 clocks = <&scpi_dvfs 1 184 clocks = <&scpi_dvfs 1>;
191 cpu-idle-states = <&CP 185 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192 capacity-dmips-mhz = < 186 capacity-dmips-mhz = <485>;
193 dynamic-power-coeffici <<
194 }; 187 };
195 188
196 A72_L2: l2-cache0 { 189 A72_L2: l2-cache0 {
197 compatible = "cache"; 190 compatible = "cache";
198 cache-unified; <<
199 cache-size = <0x200000 191 cache-size = <0x200000>;
200 cache-line-size = <64> 192 cache-line-size = <64>;
201 cache-sets = <2048>; 193 cache-sets = <2048>;
202 cache-level = <2>; <<
203 }; 194 };
204 195
205 A53_L2: l2-cache1 { 196 A53_L2: l2-cache1 {
206 compatible = "cache"; 197 compatible = "cache";
207 cache-unified; <<
208 cache-size = <0x100000 198 cache-size = <0x100000>;
209 cache-line-size = <64> 199 cache-line-size = <64>;
210 cache-sets = <1024>; 200 cache-sets = <1024>;
211 cache-level = <2>; <<
212 }; 201 };
213 }; 202 };
214 203
215 pmu-a72 { 204 pmu-a72 {
216 compatible = "arm,cortex-a72-p 205 compatible = "arm,cortex-a72-pmu";
217 interrupts = <GIC_SPI 02 IRQ_T 206 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 06 IRQ_T 207 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-affinity = <&A72_0>, 208 interrupt-affinity = <&A72_0>,
220 <&A72_1>; 209 <&A72_1>;
221 }; 210 };
222 211
223 pmu-a53 { 212 pmu-a53 {
224 compatible = "arm,cortex-a53-p 213 compatible = "arm,cortex-a53-pmu";
225 interrupts = <GIC_SPI 18 IRQ_T 214 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 22 IRQ_T 215 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 26 IRQ_T 216 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 30 IRQ_T 217 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-affinity = <&A53_0>, 218 interrupt-affinity = <&A53_0>,
230 <&A53_1>, 219 <&A53_1>,
231 <&A53_2>, 220 <&A53_2>,
232 <&A53_3>; 221 <&A53_3>;
233 }; 222 };
234 }; 223 };
235 224
236 &memtimer { 225 &memtimer {
237 status = "okay"; 226 status = "okay";
238 }; 227 };
239 228
240 &pcie_ctlr { 229 &pcie_ctlr {
241 status = "okay"; 230 status = "okay";
242 }; 231 };
243 232
244 &smmu_pcie { <<
245 status = "okay"; <<
246 }; <<
247 <<
248 &etm0 { 233 &etm0 {
249 cpu = <&A72_0>; 234 cpu = <&A72_0>;
250 }; 235 };
251 236
252 &etm1 { 237 &etm1 {
253 cpu = <&A72_1>; 238 cpu = <&A72_1>;
254 }; 239 };
255 240
256 &etm2 { 241 &etm2 {
257 cpu = <&A53_0>; 242 cpu = <&A53_0>;
258 }; 243 };
259 244
260 &etm3 { 245 &etm3 {
261 cpu = <&A53_1>; 246 cpu = <&A53_1>;
262 }; 247 };
263 248
264 &etm4 { 249 &etm4 {
265 cpu = <&A53_2>; 250 cpu = <&A53_2>;
266 }; 251 };
267 252
268 &etm5 { 253 &etm5 {
269 cpu = <&A53_3>; 254 cpu = <&A53_3>;
270 }; 255 };
271 256
272 &big_cluster_thermal_zone { 257 &big_cluster_thermal_zone {
273 status = "okay"; 258 status = "okay";
274 }; 259 };
275 260
276 &little_cluster_thermal_zone { 261 &little_cluster_thermal_zone {
277 status = "okay"; 262 status = "okay";
278 }; 263 };
279 264
280 &gpu0_thermal_zone { 265 &gpu0_thermal_zone {
281 status = "okay"; 266 status = "okay";
282 }; 267 };
283 268
284 &gpu1_thermal_zone { 269 &gpu1_thermal_zone {
285 status = "okay"; 270 status = "okay";
286 }; 271 };
287 272
288 &etf0_out_port { 273 &etf0_out_port {
289 remote-endpoint = <&csys2_funnel_in_po 274 remote-endpoint = <&csys2_funnel_in_port0>;
290 }; 275 };
291 276
292 &replicator_in_port0 { 277 &replicator_in_port0 {
293 remote-endpoint = <&csys2_funnel_out_p 278 remote-endpoint = <&csys2_funnel_out_port>;
294 }; 279 };
295 280
296 &csys1_funnel_in_port0 { 281 &csys1_funnel_in_port0 {
297 remote-endpoint = <&stm_out_port>; 282 remote-endpoint = <&stm_out_port>;
298 }; 283 };
299 284
300 &stm_out_port { 285 &stm_out_port {
301 remote-endpoint = <&csys1_funnel_in_po 286 remote-endpoint = <&csys1_funnel_in_port0>;
302 }; 287 };
303 288
304 &cpu_debug0 { 289 &cpu_debug0 {
305 cpu = <&A72_0>; 290 cpu = <&A72_0>;
306 }; 291 };
307 292
308 &cpu_debug1 { 293 &cpu_debug1 {
309 cpu = <&A72_1>; 294 cpu = <&A72_1>;
310 }; 295 };
311 296
312 &cpu_debug2 { 297 &cpu_debug2 {
313 cpu = <&A53_0>; 298 cpu = <&A53_0>;
314 }; 299 };
315 300
316 &cpu_debug3 { 301 &cpu_debug3 {
317 cpu = <&A53_1>; 302 cpu = <&A53_1>;
318 }; 303 };
319 304
320 &cpu_debug4 { 305 &cpu_debug4 {
321 cpu = <&A53_2>; 306 cpu = <&A53_2>;
322 }; 307 };
323 308
324 &cpu_debug5 { 309 &cpu_debug5 {
325 cpu = <&A53_3>; <<
326 }; <<
327 <<
328 &cti0 { <<
329 cpu = <&A72_0>; <<
330 }; <<
331 <<
332 &cti1 { <<
333 cpu = <&A72_1>; <<
334 }; <<
335 <<
336 &cti2 { <<
337 cpu = <&A53_0>; <<
338 }; <<
339 <<
340 &cti3 { <<
341 cpu = <&A53_1>; <<
342 }; <<
343 <<
344 &cti4 { <<
345 cpu = <&A53_2>; <<
346 }; <<
347 <<
348 &cti5 { <<
349 cpu = <&A53_3>; 310 cpu = <&A53_3>;
350 }; 311 };
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