1 /* 1 /*
2 * ARM Ltd. Juno Platform 2 * ARM Ltd. Juno Platform
3 * 3 *
4 * Copyright (c) 2015 ARM Ltd. 4 * Copyright (c) 2015 ARM Ltd.
5 * 5 *
6 * This file is licensed under a dual GPLv2 or 6 * This file is licensed under a dual GPLv2 or BSD license.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h> <<
13 #include "juno-base.dtsi" 12 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi" 13 #include "juno-cs-r1r2.dtsi"
15 14
16 / { 15 / {
17 model = "ARM Juno development board (r 16 model = "ARM Juno development board (r2)";
18 compatible = "arm,juno-r2", "arm,juno" 17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
20 #address-cells = <2>; 19 #address-cells = <2>;
21 #size-cells = <2>; 20 #size-cells = <2>;
22 21
23 aliases { 22 aliases {
24 serial0 = &soc_uart0; 23 serial0 = &soc_uart0;
25 }; 24 };
26 25
27 chosen { 26 chosen {
28 stdout-path = "serial0:115200n 27 stdout-path = "serial0:115200n8";
29 }; 28 };
30 29
31 psci { 30 psci {
32 compatible = "arm,psci-0.2"; 31 compatible = "arm,psci-0.2";
33 method = "smc"; 32 method = "smc";
34 }; 33 };
35 34
36 cpus { 35 cpus {
37 #address-cells = <2>; 36 #address-cells = <2>;
38 #size-cells = <0>; 37 #size-cells = <0>;
39 38
40 cpu-map { 39 cpu-map {
41 cluster0 { 40 cluster0 {
42 core0 { 41 core0 {
43 cpu = 42 cpu = <&A72_0>;
44 }; 43 };
45 core1 { 44 core1 {
46 cpu = 45 cpu = <&A72_1>;
47 }; 46 };
48 }; 47 };
49 48
50 cluster1 { 49 cluster1 {
51 core0 { 50 core0 {
52 cpu = 51 cpu = <&A53_0>;
53 }; 52 };
54 core1 { 53 core1 {
55 cpu = 54 cpu = <&A53_1>;
56 }; 55 };
57 core2 { 56 core2 {
58 cpu = 57 cpu = <&A53_2>;
59 }; 58 };
60 core3 { 59 core3 {
61 cpu = 60 cpu = <&A53_3>;
62 }; 61 };
63 }; 62 };
64 }; 63 };
65 64
66 idle-states { 65 idle-states {
67 entry-method = "psci"; 66 entry-method = "psci";
68 67
69 CPU_SLEEP_0: cpu-sleep 68 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = " 69 compatible = "arm,idle-state";
71 arm,psci-suspe 70 arm,psci-suspend-param = <0x0010000>;
72 local-timer-st 71 local-timer-stop;
73 entry-latency- 72 entry-latency-us = <300>;
74 exit-latency-u 73 exit-latency-us = <1200>;
75 min-residency- 74 min-residency-us = <2000>;
76 }; 75 };
77 76
78 CLUSTER_SLEEP_0: clust 77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = " 78 compatible = "arm,idle-state";
80 arm,psci-suspe 79 arm,psci-suspend-param = <0x1010000>;
81 local-timer-st 80 local-timer-stop;
82 entry-latency- 81 entry-latency-us = <400>;
83 exit-latency-u 82 exit-latency-us = <1200>;
84 min-residency- 83 min-residency-us = <2500>;
85 }; 84 };
86 }; 85 };
87 86
88 A72_0: cpu@0 { 87 A72_0: cpu@0 {
89 compatible = "arm,cort 88 compatible = "arm,cortex-a72";
90 reg = <0x0 0x0>; 89 reg = <0x0 0x0>;
91 device_type = "cpu"; 90 device_type = "cpu";
92 enable-method = "psci" 91 enable-method = "psci";
93 i-cache-size = <0xc000 92 i-cache-size = <0xc000>;
94 i-cache-line-size = <6 93 i-cache-line-size = <64>;
95 i-cache-sets = <256>; 94 i-cache-sets = <256>;
96 d-cache-size = <0x8000 95 d-cache-size = <0x8000>;
97 d-cache-line-size = <6 96 d-cache-line-size = <64>;
98 d-cache-sets = <256>; 97 d-cache-sets = <256>;
99 next-level-cache = <&A 98 next-level-cache = <&A72_L2>;
100 clocks = <&scpi_dvfs 0 99 clocks = <&scpi_dvfs 0>;
101 cpu-idle-states = <&CP 100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = < 101 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 102 dynamic-power-coefficient = <450>;
104 }; 103 };
105 104
106 A72_1: cpu@1 { 105 A72_1: cpu@1 {
107 compatible = "arm,cort 106 compatible = "arm,cortex-a72";
108 reg = <0x0 0x1>; 107 reg = <0x0 0x1>;
109 device_type = "cpu"; 108 device_type = "cpu";
110 enable-method = "psci" 109 enable-method = "psci";
111 i-cache-size = <0xc000 110 i-cache-size = <0xc000>;
112 i-cache-line-size = <6 111 i-cache-line-size = <64>;
113 i-cache-sets = <256>; 112 i-cache-sets = <256>;
114 d-cache-size = <0x8000 113 d-cache-size = <0x8000>;
115 d-cache-line-size = <6 114 d-cache-line-size = <64>;
116 d-cache-sets = <256>; 115 d-cache-sets = <256>;
117 next-level-cache = <&A 116 next-level-cache = <&A72_L2>;
118 clocks = <&scpi_dvfs 0 117 clocks = <&scpi_dvfs 0>;
119 cpu-idle-states = <&CP 118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 capacity-dmips-mhz = < 119 capacity-dmips-mhz = <1024>;
121 dynamic-power-coeffici 120 dynamic-power-coefficient = <450>;
122 }; 121 };
123 122
124 A53_0: cpu@100 { 123 A53_0: cpu@100 {
125 compatible = "arm,cort 124 compatible = "arm,cortex-a53";
126 reg = <0x0 0x100>; 125 reg = <0x0 0x100>;
127 device_type = "cpu"; 126 device_type = "cpu";
128 enable-method = "psci" 127 enable-method = "psci";
129 i-cache-size = <0x8000 128 i-cache-size = <0x8000>;
130 i-cache-line-size = <6 129 i-cache-line-size = <64>;
131 i-cache-sets = <256>; 130 i-cache-sets = <256>;
132 d-cache-size = <0x8000 131 d-cache-size = <0x8000>;
133 d-cache-line-size = <6 132 d-cache-line-size = <64>;
134 d-cache-sets = <128>; 133 d-cache-sets = <128>;
135 next-level-cache = <&A 134 next-level-cache = <&A53_L2>;
136 clocks = <&scpi_dvfs 1 135 clocks = <&scpi_dvfs 1>;
137 cpu-idle-states = <&CP 136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 capacity-dmips-mhz = < 137 capacity-dmips-mhz = <485>;
139 dynamic-power-coeffici 138 dynamic-power-coefficient = <140>;
140 }; 139 };
141 140
142 A53_1: cpu@101 { 141 A53_1: cpu@101 {
143 compatible = "arm,cort 142 compatible = "arm,cortex-a53";
144 reg = <0x0 0x101>; 143 reg = <0x0 0x101>;
145 device_type = "cpu"; 144 device_type = "cpu";
146 enable-method = "psci" 145 enable-method = "psci";
147 i-cache-size = <0x8000 146 i-cache-size = <0x8000>;
148 i-cache-line-size = <6 147 i-cache-line-size = <64>;
149 i-cache-sets = <256>; 148 i-cache-sets = <256>;
150 d-cache-size = <0x8000 149 d-cache-size = <0x8000>;
151 d-cache-line-size = <6 150 d-cache-line-size = <64>;
152 d-cache-sets = <128>; 151 d-cache-sets = <128>;
153 next-level-cache = <&A 152 next-level-cache = <&A53_L2>;
154 clocks = <&scpi_dvfs 1 153 clocks = <&scpi_dvfs 1>;
155 cpu-idle-states = <&CP 154 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 capacity-dmips-mhz = < 155 capacity-dmips-mhz = <485>;
157 dynamic-power-coeffici 156 dynamic-power-coefficient = <140>;
158 }; 157 };
159 158
160 A53_2: cpu@102 { 159 A53_2: cpu@102 {
161 compatible = "arm,cort 160 compatible = "arm,cortex-a53";
162 reg = <0x0 0x102>; 161 reg = <0x0 0x102>;
163 device_type = "cpu"; 162 device_type = "cpu";
164 enable-method = "psci" 163 enable-method = "psci";
165 i-cache-size = <0x8000 164 i-cache-size = <0x8000>;
166 i-cache-line-size = <6 165 i-cache-line-size = <64>;
167 i-cache-sets = <256>; 166 i-cache-sets = <256>;
168 d-cache-size = <0x8000 167 d-cache-size = <0x8000>;
169 d-cache-line-size = <6 168 d-cache-line-size = <64>;
170 d-cache-sets = <128>; 169 d-cache-sets = <128>;
171 next-level-cache = <&A 170 next-level-cache = <&A53_L2>;
172 clocks = <&scpi_dvfs 1 171 clocks = <&scpi_dvfs 1>;
173 cpu-idle-states = <&CP 172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174 capacity-dmips-mhz = < 173 capacity-dmips-mhz = <485>;
175 dynamic-power-coeffici 174 dynamic-power-coefficient = <140>;
176 }; 175 };
177 176
178 A53_3: cpu@103 { 177 A53_3: cpu@103 {
179 compatible = "arm,cort 178 compatible = "arm,cortex-a53";
180 reg = <0x0 0x103>; 179 reg = <0x0 0x103>;
181 device_type = "cpu"; 180 device_type = "cpu";
182 enable-method = "psci" 181 enable-method = "psci";
183 i-cache-size = <0x8000 182 i-cache-size = <0x8000>;
184 i-cache-line-size = <6 183 i-cache-line-size = <64>;
185 i-cache-sets = <256>; 184 i-cache-sets = <256>;
186 d-cache-size = <0x8000 185 d-cache-size = <0x8000>;
187 d-cache-line-size = <6 186 d-cache-line-size = <64>;
188 d-cache-sets = <128>; 187 d-cache-sets = <128>;
189 next-level-cache = <&A 188 next-level-cache = <&A53_L2>;
190 clocks = <&scpi_dvfs 1 189 clocks = <&scpi_dvfs 1>;
191 cpu-idle-states = <&CP 190 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192 capacity-dmips-mhz = < 191 capacity-dmips-mhz = <485>;
193 dynamic-power-coeffici 192 dynamic-power-coefficient = <140>;
194 }; 193 };
195 194
196 A72_L2: l2-cache0 { 195 A72_L2: l2-cache0 {
197 compatible = "cache"; 196 compatible = "cache";
198 cache-unified; <<
199 cache-size = <0x200000 197 cache-size = <0x200000>;
200 cache-line-size = <64> 198 cache-line-size = <64>;
201 cache-sets = <2048>; 199 cache-sets = <2048>;
202 cache-level = <2>; <<
203 }; 200 };
204 201
205 A53_L2: l2-cache1 { 202 A53_L2: l2-cache1 {
206 compatible = "cache"; 203 compatible = "cache";
207 cache-unified; <<
208 cache-size = <0x100000 204 cache-size = <0x100000>;
209 cache-line-size = <64> 205 cache-line-size = <64>;
210 cache-sets = <1024>; 206 cache-sets = <1024>;
211 cache-level = <2>; <<
212 }; 207 };
213 }; 208 };
214 209
215 pmu-a72 { 210 pmu-a72 {
216 compatible = "arm,cortex-a72-p 211 compatible = "arm,cortex-a72-pmu";
217 interrupts = <GIC_SPI 02 IRQ_T 212 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 06 IRQ_T 213 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-affinity = <&A72_0>, 214 interrupt-affinity = <&A72_0>,
220 <&A72_1>; 215 <&A72_1>;
221 }; 216 };
222 217
223 pmu-a53 { 218 pmu-a53 {
224 compatible = "arm,cortex-a53-p 219 compatible = "arm,cortex-a53-pmu";
225 interrupts = <GIC_SPI 18 IRQ_T 220 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 22 IRQ_T 221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 26 IRQ_T 222 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 30 IRQ_T 223 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-affinity = <&A53_0>, 224 interrupt-affinity = <&A53_0>,
230 <&A53_1>, 225 <&A53_1>,
231 <&A53_2>, 226 <&A53_2>,
232 <&A53_3>; 227 <&A53_3>;
233 }; 228 };
234 }; 229 };
235 230
236 &memtimer { 231 &memtimer {
237 status = "okay"; 232 status = "okay";
238 }; 233 };
239 234
240 &pcie_ctlr { 235 &pcie_ctlr {
241 status = "okay"; 236 status = "okay";
242 }; 237 };
243 238
244 &smmu_pcie { 239 &smmu_pcie {
245 status = "okay"; 240 status = "okay";
246 }; 241 };
247 242
248 &etm0 { 243 &etm0 {
249 cpu = <&A72_0>; 244 cpu = <&A72_0>;
250 }; 245 };
251 246
252 &etm1 { 247 &etm1 {
253 cpu = <&A72_1>; 248 cpu = <&A72_1>;
254 }; 249 };
255 250
256 &etm2 { 251 &etm2 {
257 cpu = <&A53_0>; 252 cpu = <&A53_0>;
258 }; 253 };
259 254
260 &etm3 { 255 &etm3 {
261 cpu = <&A53_1>; 256 cpu = <&A53_1>;
262 }; 257 };
263 258
264 &etm4 { 259 &etm4 {
265 cpu = <&A53_2>; 260 cpu = <&A53_2>;
266 }; 261 };
267 262
268 &etm5 { 263 &etm5 {
269 cpu = <&A53_3>; 264 cpu = <&A53_3>;
270 }; 265 };
271 266
272 &big_cluster_thermal_zone { 267 &big_cluster_thermal_zone {
273 status = "okay"; 268 status = "okay";
274 }; 269 };
275 270
276 &little_cluster_thermal_zone { 271 &little_cluster_thermal_zone {
277 status = "okay"; 272 status = "okay";
278 }; 273 };
279 274
280 &gpu0_thermal_zone { 275 &gpu0_thermal_zone {
281 status = "okay"; 276 status = "okay";
282 }; 277 };
283 278
284 &gpu1_thermal_zone { 279 &gpu1_thermal_zone {
285 status = "okay"; 280 status = "okay";
286 }; 281 };
287 282
288 &etf0_out_port { 283 &etf0_out_port {
289 remote-endpoint = <&csys2_funnel_in_po 284 remote-endpoint = <&csys2_funnel_in_port0>;
290 }; 285 };
291 286
292 &replicator_in_port0 { 287 &replicator_in_port0 {
293 remote-endpoint = <&csys2_funnel_out_p 288 remote-endpoint = <&csys2_funnel_out_port>;
294 }; 289 };
295 290
296 &csys1_funnel_in_port0 { 291 &csys1_funnel_in_port0 {
297 remote-endpoint = <&stm_out_port>; 292 remote-endpoint = <&stm_out_port>;
298 }; 293 };
299 294
300 &stm_out_port { 295 &stm_out_port {
301 remote-endpoint = <&csys1_funnel_in_po 296 remote-endpoint = <&csys1_funnel_in_port0>;
302 }; 297 };
303 298
304 &cpu_debug0 { 299 &cpu_debug0 {
305 cpu = <&A72_0>; 300 cpu = <&A72_0>;
306 }; 301 };
307 302
308 &cpu_debug1 { 303 &cpu_debug1 {
309 cpu = <&A72_1>; 304 cpu = <&A72_1>;
310 }; 305 };
311 306
312 &cpu_debug2 { 307 &cpu_debug2 {
313 cpu = <&A53_0>; 308 cpu = <&A53_0>;
314 }; 309 };
315 310
316 &cpu_debug3 { 311 &cpu_debug3 {
317 cpu = <&A53_1>; 312 cpu = <&A53_1>;
318 }; 313 };
319 314
320 &cpu_debug4 { 315 &cpu_debug4 {
321 cpu = <&A53_2>; 316 cpu = <&A53_2>;
322 }; 317 };
323 318
324 &cpu_debug5 { 319 &cpu_debug5 {
325 cpu = <&A53_3>; <<
326 }; <<
327 <<
328 &cti0 { <<
329 cpu = <&A72_0>; <<
330 }; <<
331 <<
332 &cti1 { <<
333 cpu = <&A72_1>; <<
334 }; <<
335 <<
336 &cti2 { <<
337 cpu = <&A53_0>; <<
338 }; <<
339 <<
340 &cti3 { <<
341 cpu = <&A53_1>; <<
342 }; <<
343 <<
344 &cti4 { <<
345 cpu = <&A53_2>; <<
346 }; <<
347 <<
348 &cti5 { <<
349 cpu = <&A53_3>; 320 cpu = <&A53_3>;
350 }; 321 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.