1 /* 1 /*
2 * ARM Ltd. Juno Platform 2 * ARM Ltd. Juno Platform
3 * 3 *
4 * Copyright (c) 2015 ARM Ltd. 4 * Copyright (c) 2015 ARM Ltd.
5 * 5 *
6 * This file is licensed under a dual GPLv2 or 6 * This file is licensed under a dual GPLv2 or BSD license.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi" 13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi" 14 #include "juno-cs-r1r2.dtsi"
15 15
16 / { 16 / {
17 model = "ARM Juno development board (r 17 model = "ARM Juno development board (r2)";
18 compatible = "arm,juno-r2", "arm,juno" 18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 aliases { 23 aliases {
24 serial0 = &soc_uart0; 24 serial0 = &soc_uart0;
25 }; 25 };
26 26
27 chosen { 27 chosen {
28 stdout-path = "serial0:115200n 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 psci { 31 psci {
32 compatible = "arm,psci-0.2"; 32 compatible = "arm,psci-0.2";
33 method = "smc"; 33 method = "smc";
34 }; 34 };
35 35
36 cpus { 36 cpus {
37 #address-cells = <2>; 37 #address-cells = <2>;
38 #size-cells = <0>; 38 #size-cells = <0>;
39 39
40 cpu-map { 40 cpu-map {
41 cluster0 { 41 cluster0 {
42 core0 { 42 core0 {
43 cpu = 43 cpu = <&A72_0>;
44 }; 44 };
45 core1 { 45 core1 {
46 cpu = 46 cpu = <&A72_1>;
47 }; 47 };
48 }; 48 };
49 49
50 cluster1 { 50 cluster1 {
51 core0 { 51 core0 {
52 cpu = 52 cpu = <&A53_0>;
53 }; 53 };
54 core1 { 54 core1 {
55 cpu = 55 cpu = <&A53_1>;
56 }; 56 };
57 core2 { 57 core2 {
58 cpu = 58 cpu = <&A53_2>;
59 }; 59 };
60 core3 { 60 core3 {
61 cpu = 61 cpu = <&A53_3>;
62 }; 62 };
63 }; 63 };
64 }; 64 };
65 65
66 idle-states { 66 idle-states {
67 entry-method = "psci"; 67 entry-method = "psci";
68 68
69 CPU_SLEEP_0: cpu-sleep 69 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = " 70 compatible = "arm,idle-state";
71 arm,psci-suspe 71 arm,psci-suspend-param = <0x0010000>;
72 local-timer-st 72 local-timer-stop;
73 entry-latency- 73 entry-latency-us = <300>;
74 exit-latency-u 74 exit-latency-us = <1200>;
75 min-residency- 75 min-residency-us = <2000>;
76 }; 76 };
77 77
78 CLUSTER_SLEEP_0: clust 78 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = " 79 compatible = "arm,idle-state";
80 arm,psci-suspe 80 arm,psci-suspend-param = <0x1010000>;
81 local-timer-st 81 local-timer-stop;
82 entry-latency- 82 entry-latency-us = <400>;
83 exit-latency-u 83 exit-latency-us = <1200>;
84 min-residency- 84 min-residency-us = <2500>;
85 }; 85 };
86 }; 86 };
87 87
88 A72_0: cpu@0 { 88 A72_0: cpu@0 {
89 compatible = "arm,cort 89 compatible = "arm,cortex-a72";
90 reg = <0x0 0x0>; 90 reg = <0x0 0x0>;
91 device_type = "cpu"; 91 device_type = "cpu";
92 enable-method = "psci" 92 enable-method = "psci";
93 i-cache-size = <0xc000 93 i-cache-size = <0xc000>;
94 i-cache-line-size = <6 94 i-cache-line-size = <64>;
95 i-cache-sets = <256>; 95 i-cache-sets = <256>;
96 d-cache-size = <0x8000 96 d-cache-size = <0x8000>;
97 d-cache-line-size = <6 97 d-cache-line-size = <64>;
98 d-cache-sets = <256>; 98 d-cache-sets = <256>;
99 next-level-cache = <&A 99 next-level-cache = <&A72_L2>;
100 clocks = <&scpi_dvfs 0 100 clocks = <&scpi_dvfs 0>;
101 cpu-idle-states = <&CP 101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = < 102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 103 dynamic-power-coefficient = <450>;
104 }; 104 };
105 105
106 A72_1: cpu@1 { 106 A72_1: cpu@1 {
107 compatible = "arm,cort 107 compatible = "arm,cortex-a72";
108 reg = <0x0 0x1>; 108 reg = <0x0 0x1>;
109 device_type = "cpu"; 109 device_type = "cpu";
110 enable-method = "psci" 110 enable-method = "psci";
111 i-cache-size = <0xc000 111 i-cache-size = <0xc000>;
112 i-cache-line-size = <6 112 i-cache-line-size = <64>;
113 i-cache-sets = <256>; 113 i-cache-sets = <256>;
114 d-cache-size = <0x8000 114 d-cache-size = <0x8000>;
115 d-cache-line-size = <6 115 d-cache-line-size = <64>;
116 d-cache-sets = <256>; 116 d-cache-sets = <256>;
117 next-level-cache = <&A 117 next-level-cache = <&A72_L2>;
118 clocks = <&scpi_dvfs 0 118 clocks = <&scpi_dvfs 0>;
119 cpu-idle-states = <&CP 119 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 capacity-dmips-mhz = < 120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coeffici 121 dynamic-power-coefficient = <450>;
122 }; 122 };
123 123
124 A53_0: cpu@100 { 124 A53_0: cpu@100 {
125 compatible = "arm,cort 125 compatible = "arm,cortex-a53";
126 reg = <0x0 0x100>; 126 reg = <0x0 0x100>;
127 device_type = "cpu"; 127 device_type = "cpu";
128 enable-method = "psci" 128 enable-method = "psci";
129 i-cache-size = <0x8000 129 i-cache-size = <0x8000>;
130 i-cache-line-size = <6 130 i-cache-line-size = <64>;
131 i-cache-sets = <256>; 131 i-cache-sets = <256>;
132 d-cache-size = <0x8000 132 d-cache-size = <0x8000>;
133 d-cache-line-size = <6 133 d-cache-line-size = <64>;
134 d-cache-sets = <128>; 134 d-cache-sets = <128>;
135 next-level-cache = <&A 135 next-level-cache = <&A53_L2>;
136 clocks = <&scpi_dvfs 1 136 clocks = <&scpi_dvfs 1>;
137 cpu-idle-states = <&CP 137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 capacity-dmips-mhz = < 138 capacity-dmips-mhz = <485>;
139 dynamic-power-coeffici 139 dynamic-power-coefficient = <140>;
140 }; 140 };
141 141
142 A53_1: cpu@101 { 142 A53_1: cpu@101 {
143 compatible = "arm,cort 143 compatible = "arm,cortex-a53";
144 reg = <0x0 0x101>; 144 reg = <0x0 0x101>;
145 device_type = "cpu"; 145 device_type = "cpu";
146 enable-method = "psci" 146 enable-method = "psci";
147 i-cache-size = <0x8000 147 i-cache-size = <0x8000>;
148 i-cache-line-size = <6 148 i-cache-line-size = <64>;
149 i-cache-sets = <256>; 149 i-cache-sets = <256>;
150 d-cache-size = <0x8000 150 d-cache-size = <0x8000>;
151 d-cache-line-size = <6 151 d-cache-line-size = <64>;
152 d-cache-sets = <128>; 152 d-cache-sets = <128>;
153 next-level-cache = <&A 153 next-level-cache = <&A53_L2>;
154 clocks = <&scpi_dvfs 1 154 clocks = <&scpi_dvfs 1>;
155 cpu-idle-states = <&CP 155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <485>;
157 dynamic-power-coeffici 157 dynamic-power-coefficient = <140>;
158 }; 158 };
159 159
160 A53_2: cpu@102 { 160 A53_2: cpu@102 {
161 compatible = "arm,cort 161 compatible = "arm,cortex-a53";
162 reg = <0x0 0x102>; 162 reg = <0x0 0x102>;
163 device_type = "cpu"; 163 device_type = "cpu";
164 enable-method = "psci" 164 enable-method = "psci";
165 i-cache-size = <0x8000 165 i-cache-size = <0x8000>;
166 i-cache-line-size = <6 166 i-cache-line-size = <64>;
167 i-cache-sets = <256>; 167 i-cache-sets = <256>;
168 d-cache-size = <0x8000 168 d-cache-size = <0x8000>;
169 d-cache-line-size = <6 169 d-cache-line-size = <64>;
170 d-cache-sets = <128>; 170 d-cache-sets = <128>;
171 next-level-cache = <&A 171 next-level-cache = <&A53_L2>;
172 clocks = <&scpi_dvfs 1 172 clocks = <&scpi_dvfs 1>;
173 cpu-idle-states = <&CP 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174 capacity-dmips-mhz = < 174 capacity-dmips-mhz = <485>;
175 dynamic-power-coeffici 175 dynamic-power-coefficient = <140>;
176 }; 176 };
177 177
178 A53_3: cpu@103 { 178 A53_3: cpu@103 {
179 compatible = "arm,cort 179 compatible = "arm,cortex-a53";
180 reg = <0x0 0x103>; 180 reg = <0x0 0x103>;
181 device_type = "cpu"; 181 device_type = "cpu";
182 enable-method = "psci" 182 enable-method = "psci";
183 i-cache-size = <0x8000 183 i-cache-size = <0x8000>;
184 i-cache-line-size = <6 184 i-cache-line-size = <64>;
185 i-cache-sets = <256>; 185 i-cache-sets = <256>;
186 d-cache-size = <0x8000 186 d-cache-size = <0x8000>;
187 d-cache-line-size = <6 187 d-cache-line-size = <64>;
188 d-cache-sets = <128>; 188 d-cache-sets = <128>;
189 next-level-cache = <&A 189 next-level-cache = <&A53_L2>;
190 clocks = <&scpi_dvfs 1 190 clocks = <&scpi_dvfs 1>;
191 cpu-idle-states = <&CP 191 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192 capacity-dmips-mhz = < 192 capacity-dmips-mhz = <485>;
193 dynamic-power-coeffici 193 dynamic-power-coefficient = <140>;
194 }; 194 };
195 195
196 A72_L2: l2-cache0 { 196 A72_L2: l2-cache0 {
197 compatible = "cache"; 197 compatible = "cache";
198 cache-unified; <<
199 cache-size = <0x200000 198 cache-size = <0x200000>;
200 cache-line-size = <64> 199 cache-line-size = <64>;
201 cache-sets = <2048>; 200 cache-sets = <2048>;
202 cache-level = <2>; 201 cache-level = <2>;
203 }; 202 };
204 203
205 A53_L2: l2-cache1 { 204 A53_L2: l2-cache1 {
206 compatible = "cache"; 205 compatible = "cache";
207 cache-unified; <<
208 cache-size = <0x100000 206 cache-size = <0x100000>;
209 cache-line-size = <64> 207 cache-line-size = <64>;
210 cache-sets = <1024>; 208 cache-sets = <1024>;
211 cache-level = <2>; 209 cache-level = <2>;
212 }; 210 };
213 }; 211 };
214 212
215 pmu-a72 { 213 pmu-a72 {
216 compatible = "arm,cortex-a72-p 214 compatible = "arm,cortex-a72-pmu";
217 interrupts = <GIC_SPI 02 IRQ_T 215 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 06 IRQ_T 216 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-affinity = <&A72_0>, 217 interrupt-affinity = <&A72_0>,
220 <&A72_1>; 218 <&A72_1>;
221 }; 219 };
222 220
223 pmu-a53 { 221 pmu-a53 {
224 compatible = "arm,cortex-a53-p 222 compatible = "arm,cortex-a53-pmu";
225 interrupts = <GIC_SPI 18 IRQ_T 223 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 22 IRQ_T 224 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 26 IRQ_T 225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 30 IRQ_T 226 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-affinity = <&A53_0>, 227 interrupt-affinity = <&A53_0>,
230 <&A53_1>, 228 <&A53_1>,
231 <&A53_2>, 229 <&A53_2>,
232 <&A53_3>; 230 <&A53_3>;
233 }; 231 };
234 }; 232 };
235 233
236 &memtimer { 234 &memtimer {
237 status = "okay"; 235 status = "okay";
238 }; 236 };
239 237
240 &pcie_ctlr { 238 &pcie_ctlr {
241 status = "okay"; 239 status = "okay";
242 }; 240 };
243 241
244 &smmu_pcie { 242 &smmu_pcie {
245 status = "okay"; 243 status = "okay";
246 }; 244 };
247 245
248 &etm0 { 246 &etm0 {
249 cpu = <&A72_0>; 247 cpu = <&A72_0>;
250 }; 248 };
251 249
252 &etm1 { 250 &etm1 {
253 cpu = <&A72_1>; 251 cpu = <&A72_1>;
254 }; 252 };
255 253
256 &etm2 { 254 &etm2 {
257 cpu = <&A53_0>; 255 cpu = <&A53_0>;
258 }; 256 };
259 257
260 &etm3 { 258 &etm3 {
261 cpu = <&A53_1>; 259 cpu = <&A53_1>;
262 }; 260 };
263 261
264 &etm4 { 262 &etm4 {
265 cpu = <&A53_2>; 263 cpu = <&A53_2>;
266 }; 264 };
267 265
268 &etm5 { 266 &etm5 {
269 cpu = <&A53_3>; 267 cpu = <&A53_3>;
270 }; 268 };
271 269
272 &big_cluster_thermal_zone { 270 &big_cluster_thermal_zone {
273 status = "okay"; 271 status = "okay";
274 }; 272 };
275 273
276 &little_cluster_thermal_zone { 274 &little_cluster_thermal_zone {
277 status = "okay"; 275 status = "okay";
278 }; 276 };
279 277
280 &gpu0_thermal_zone { 278 &gpu0_thermal_zone {
281 status = "okay"; 279 status = "okay";
282 }; 280 };
283 281
284 &gpu1_thermal_zone { 282 &gpu1_thermal_zone {
285 status = "okay"; 283 status = "okay";
286 }; 284 };
287 285
288 &etf0_out_port { 286 &etf0_out_port {
289 remote-endpoint = <&csys2_funnel_in_po 287 remote-endpoint = <&csys2_funnel_in_port0>;
290 }; 288 };
291 289
292 &replicator_in_port0 { 290 &replicator_in_port0 {
293 remote-endpoint = <&csys2_funnel_out_p 291 remote-endpoint = <&csys2_funnel_out_port>;
294 }; 292 };
295 293
296 &csys1_funnel_in_port0 { 294 &csys1_funnel_in_port0 {
297 remote-endpoint = <&stm_out_port>; 295 remote-endpoint = <&stm_out_port>;
298 }; 296 };
299 297
300 &stm_out_port { 298 &stm_out_port {
301 remote-endpoint = <&csys1_funnel_in_po 299 remote-endpoint = <&csys1_funnel_in_port0>;
302 }; 300 };
303 301
304 &cpu_debug0 { 302 &cpu_debug0 {
305 cpu = <&A72_0>; 303 cpu = <&A72_0>;
306 }; 304 };
307 305
308 &cpu_debug1 { 306 &cpu_debug1 {
309 cpu = <&A72_1>; 307 cpu = <&A72_1>;
310 }; 308 };
311 309
312 &cpu_debug2 { 310 &cpu_debug2 {
313 cpu = <&A53_0>; 311 cpu = <&A53_0>;
314 }; 312 };
315 313
316 &cpu_debug3 { 314 &cpu_debug3 {
317 cpu = <&A53_1>; 315 cpu = <&A53_1>;
318 }; 316 };
319 317
320 &cpu_debug4 { 318 &cpu_debug4 {
321 cpu = <&A53_2>; 319 cpu = <&A53_2>;
322 }; 320 };
323 321
324 &cpu_debug5 { 322 &cpu_debug5 {
325 cpu = <&A53_3>; 323 cpu = <&A53_3>;
326 }; 324 };
327 325
328 &cti0 { 326 &cti0 {
329 cpu = <&A72_0>; 327 cpu = <&A72_0>;
330 }; 328 };
331 329
332 &cti1 { 330 &cti1 {
333 cpu = <&A72_1>; 331 cpu = <&A72_1>;
334 }; 332 };
335 333
336 &cti2 { 334 &cti2 {
337 cpu = <&A53_0>; 335 cpu = <&A53_0>;
338 }; 336 };
339 337
340 &cti3 { 338 &cti3 {
341 cpu = <&A53_1>; 339 cpu = <&A53_1>;
342 }; 340 };
343 341
344 &cti4 { 342 &cti4 {
345 cpu = <&A53_2>; 343 cpu = <&A53_2>;
346 }; 344 };
347 345
348 &cti5 { 346 &cti5 {
349 cpu = <&A53_3>; 347 cpu = <&A53_3>;
350 }; 348 };
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