1 / { 1 / {
2 etf@20010000 { 2 etf@20010000 {
3 power-domains = <&scmi_devpd 8 3 power-domains = <&scmi_devpd 8>;
4 }; 4 };
5 5
6 tpiu@20030000 { 6 tpiu@20030000 {
7 power-domains = <&scmi_devpd 8 7 power-domains = <&scmi_devpd 8>;
8 }; 8 };
9 9
10 funnel@20040000 { 10 funnel@20040000 {
11 power-domains = <&scmi_devpd 8 11 power-domains = <&scmi_devpd 8>;
12 }; 12 };
13 13
14 etr@20070000 { 14 etr@20070000 {
15 power-domains = <&scmi_devpd 8 15 power-domains = <&scmi_devpd 8>;
16 }; 16 };
17 17
18 stm@20100000 { 18 stm@20100000 {
19 power-domains = <&scmi_devpd 8 19 power-domains = <&scmi_devpd 8>;
20 }; 20 };
21 21
22 replicator@20120000 { 22 replicator@20120000 {
23 power-domains = <&scmi_devpd 8 23 power-domains = <&scmi_devpd 8>;
24 }; 24 };
25 25
26 funnel@220c0000 { 26 funnel@220c0000 {
27 power-domains = <&scmi_devpd 8 27 power-domains = <&scmi_devpd 8>;
28 }; 28 };
29 29
30 funnel@230c0000 { 30 funnel@230c0000 {
31 power-domains = <&scmi_devpd 8 31 power-domains = <&scmi_devpd 8>;
32 }; 32 };
33 33
34 hdlcd@7ff50000 { 34 hdlcd@7ff50000 {
35 clocks = <&scmi_clk 3>; 35 clocks = <&scmi_clk 3>;
36 }; 36 };
37 37
38 hdlcd@7ff60000 { 38 hdlcd@7ff60000 {
39 clocks = <&scmi_clk 3>; 39 clocks = <&scmi_clk 3>;
40 }; 40 };
41 41
42 /delete-node/ scpi; 42 /delete-node/ scpi;
43 43
44 firmware { 44 firmware {
45 scmi { 45 scmi {
46 compatible = "arm,scmi 46 compatible = "arm,scmi";
47 mbox-names = "tx", "rx 47 mbox-names = "tx", "rx";
48 mboxes = <&mailbox 0 0 48 mboxes = <&mailbox 0 0 &mailbox 0 1>;
49 shmem = <&cpu_scp_lpri 49 shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 scmi_devpd: protocol@1 53 scmi_devpd: protocol@11 {
54 reg = <0x11>; 54 reg = <0x11>;
55 #power-domain- 55 #power-domain-cells = <1>;
56 }; 56 };
57 57
58 scmi_dvfs: protocol@13 58 scmi_dvfs: protocol@13 {
59 reg = <0x13>; 59 reg = <0x13>;
60 #clock-cells = 60 #clock-cells = <1>;
61 mbox-names = " 61 mbox-names = "tx", "rx";
62 mboxes = <&mai 62 mboxes = <&mailbox 1 0 &mailbox 1 1>;
63 shmem = <&cpu_ 63 shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
64 }; 64 };
65 65
66 scmi_clk: protocol@14 66 scmi_clk: protocol@14 {
67 reg = <0x14>; 67 reg = <0x14>;
68 #clock-cells = 68 #clock-cells = <1>;
69 }; 69 };
70 70
71 scmi_sensors0: protoco 71 scmi_sensors0: protocol@15 {
72 reg = <0x15>; 72 reg = <0x15>;
73 #thermal-senso 73 #thermal-sensor-cells = <1>;
74 }; 74 };
75 }; 75 };
76 }; 76 };
77 77
78 thermal-zones { 78 thermal-zones {
79 pmic-thermal { !! 79 pmic {
80 thermal-sensors = <&sc 80 thermal-sensors = <&scmi_sensors0 0>;
81 }; 81 };
82 82
83 soc-thermal { !! 83 soc {
84 thermal-sensors = <&sc 84 thermal-sensors = <&scmi_sensors0 3>;
85 }; 85 };
86 86
87 big-cl-thermal { !! 87 big-cluster {
88 thermal-sensors = <&sc 88 thermal-sensors = <&scmi_sensors0 21>;
89 }; 89 };
90 90
91 little-cl-thermal { !! 91 little-cluster {
92 thermal-sensors = <&sc 92 thermal-sensors = <&scmi_sensors0 22>;
93 }; 93 };
94 94
95 gpu0-thermal { !! 95 gpu0 {
96 thermal-sensors = <&sc 96 thermal-sensors = <&scmi_sensors0 23>;
97 }; 97 };
98 98
99 gpu1-thermal { !! 99 gpu1 {
100 thermal-sensors = <&sc 100 thermal-sensors = <&scmi_sensors0 24>;
101 }; 101 };
102 }; 102 };
103 103
104 }; 104 };
105 105
106 &A53_0 { 106 &A53_0 {
107 clocks = <&scmi_dvfs 1>; 107 clocks = <&scmi_dvfs 1>;
108 }; 108 };
109 &A53_1 { 109 &A53_1 {
110 clocks = <&scmi_dvfs 1>; 110 clocks = <&scmi_dvfs 1>;
111 }; 111 };
112 &A53_2 { 112 &A53_2 {
113 clocks = <&scmi_dvfs 1>; 113 clocks = <&scmi_dvfs 1>;
114 }; 114 };
115 &A53_3 { 115 &A53_3 {
116 clocks = <&scmi_dvfs 1>; 116 clocks = <&scmi_dvfs 1>;
117 }; 117 };
118 118
119 &cpu_debug0 { 119 &cpu_debug0 {
120 power-domains = <&scmi_devpd 8>; 120 power-domains = <&scmi_devpd 8>;
121 }; 121 };
122 &cpu_debug1 { 122 &cpu_debug1 {
123 power-domains = <&scmi_devpd 8>; 123 power-domains = <&scmi_devpd 8>;
124 }; 124 };
125 &cpu_debug2 { 125 &cpu_debug2 {
126 power-domains = <&scmi_devpd 8>; 126 power-domains = <&scmi_devpd 8>;
127 }; 127 };
128 &cpu_debug3 { 128 &cpu_debug3 {
129 power-domains = <&scmi_devpd 8>; 129 power-domains = <&scmi_devpd 8>;
130 }; 130 };
131 &cpu_debug4 { 131 &cpu_debug4 {
132 power-domains = <&scmi_devpd 8>; 132 power-domains = <&scmi_devpd 8>;
133 }; 133 };
134 &cpu_debug5 { 134 &cpu_debug5 {
135 power-domains = <&scmi_devpd 8>; 135 power-domains = <&scmi_devpd 8>;
136 }; 136 };
137 137
138 &etm0 { 138 &etm0 {
139 power-domains = <&scmi_devpd 8>; 139 power-domains = <&scmi_devpd 8>;
140 }; 140 };
141 &etm1 { 141 &etm1 {
142 power-domains = <&scmi_devpd 8>; 142 power-domains = <&scmi_devpd 8>;
143 }; 143 };
144 &etm2 { 144 &etm2 {
145 power-domains = <&scmi_devpd 8>; 145 power-domains = <&scmi_devpd 8>;
146 }; 146 };
147 &etm3 { 147 &etm3 {
148 power-domains = <&scmi_devpd 8>; 148 power-domains = <&scmi_devpd 8>;
149 }; 149 };
150 &etm4 { 150 &etm4 {
151 power-domains = <&scmi_devpd 8>; 151 power-domains = <&scmi_devpd 8>;
152 }; 152 };
153 &etm5 { 153 &etm5 {
154 power-domains = <&scmi_devpd 8>; 154 power-domains = <&scmi_devpd 8>;
155 }; 155 };
156 156
157 &cti0 { <<
158 power-domains = <&scmi_devpd 8>; <<
159 }; <<
160 &cti1 { <<
161 power-domains = <&scmi_devpd 8>; <<
162 }; <<
163 &cti2 { <<
164 power-domains = <&scmi_devpd 8>; <<
165 }; <<
166 &cti3 { <<
167 power-domains = <&scmi_devpd 8>; <<
168 }; <<
169 &cti4 { <<
170 power-domains = <&scmi_devpd 8>; <<
171 }; <<
172 &cti5 { <<
173 power-domains = <&scmi_devpd 8>; <<
174 }; <<
175 &cti_sys0 { <<
176 power-domains = <&scmi_devpd 8>; <<
177 }; <<
178 &cti_sys1 { <<
179 power-domains = <&scmi_devpd 8>; <<
180 }; <<
181 <<
182 &gpu { 157 &gpu {
183 clocks = <&scmi_dvfs 2>; 158 clocks = <&scmi_dvfs 2>;
184 power-domains = <&scmi_devpd 9>; 159 power-domains = <&scmi_devpd 9>;
185 }; 160 };
186 161
187 &mailbox { 162 &mailbox {
188 compatible = "arm,mhu-doorbell", "arm, 163 compatible = "arm,mhu-doorbell", "arm,primecell";
189 #mbox-cells = <2>; 164 #mbox-cells = <2>;
>> 165 mbox-name = "ARM-MHU";
190 }; 166 };
191 167
192 &smmu_etr { 168 &smmu_etr {
193 power-domains = <&scmi_devpd 8>; 169 power-domains = <&scmi_devpd 8>;
194 }; 170 };
195 171
196 &smmu_gpu { 172 &smmu_gpu {
197 power-domains = <&scmi_devpd 9>; 173 power-domains = <&scmi_devpd 9>;
198 }; 174 };
199 175
200 &sram { 176 &sram {
201 /delete-node/ scp-sram@0; 177 /delete-node/ scp-sram@0;
202 /delete-node/ scp-sram@200; 178 /delete-node/ scp-sram@200;
203 179
204 cpu_scp_lpri0: scp-sram@0 { 180 cpu_scp_lpri0: scp-sram@0 {
205 compatible = "arm,scmi-shmem"; 181 compatible = "arm,scmi-shmem";
206 reg = <0x0 0x80>; 182 reg = <0x0 0x80>;
207 }; 183 };
208 184
209 cpu_scp_lpri1: scp-sram@80 { 185 cpu_scp_lpri1: scp-sram@80 {
210 compatible = "arm,scmi-shmem"; 186 compatible = "arm,scmi-shmem";
211 reg = <0x80 0x80>; 187 reg = <0x80 0x80>;
212 }; 188 };
213 189
214 cpu_scp_hpri0: scp-sram@100 { 190 cpu_scp_hpri0: scp-sram@100 {
215 compatible = "arm,scmi-shmem"; 191 compatible = "arm,scmi-shmem";
216 reg = <0x100 0x80>; 192 reg = <0x100 0x80>;
217 }; 193 };
218 194
219 cpu_scp_hpri1: scp-sram@180 { 195 cpu_scp_hpri1: scp-sram@180 {
220 compatible = "arm,scmi-shmem"; 196 compatible = "arm,scmi-shmem";
221 reg = <0x180 0x80>; 197 reg = <0x180 0x80>;
222 }; 198 };
223 }; 199 };
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