1 /* 1 /*
2 * ARM Ltd. Juno Platform 2 * ARM Ltd. Juno Platform
3 * 3 *
4 * Copyright (c) 2013-2014 ARM Ltd. 4 * Copyright (c) 2013-2014 ARM Ltd.
5 * 5 *
6 * This file is licensed under a dual GPLv2 or 6 * This file is licensed under a dual GPLv2 or BSD license.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h> <<
13 #include "juno-base.dtsi" 12 #include "juno-base.dtsi"
14 13
15 / { 14 / {
16 model = "ARM Juno development board (r 15 model = "ARM Juno development board (r0)";
17 compatible = "arm,juno", "arm,vexpress 16 compatible = "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
19 #address-cells = <2>; 18 #address-cells = <2>;
20 #size-cells = <2>; 19 #size-cells = <2>;
21 20
22 aliases { 21 aliases {
23 serial0 = &soc_uart0; 22 serial0 = &soc_uart0;
24 }; 23 };
25 24
26 chosen { 25 chosen {
27 stdout-path = "serial0:115200n 26 stdout-path = "serial0:115200n8";
28 }; 27 };
29 28
30 psci { 29 psci {
31 compatible = "arm,psci-0.2"; 30 compatible = "arm,psci-0.2";
32 method = "smc"; 31 method = "smc";
33 }; 32 };
34 33
35 cpus { 34 cpus {
36 #address-cells = <2>; 35 #address-cells = <2>;
37 #size-cells = <0>; 36 #size-cells = <0>;
38 37
39 cpu-map { 38 cpu-map {
40 cluster0 { 39 cluster0 {
41 core0 { 40 core0 {
42 cpu = 41 cpu = <&A57_0>;
43 }; 42 };
44 core1 { 43 core1 {
45 cpu = 44 cpu = <&A57_1>;
46 }; 45 };
47 }; 46 };
48 47
49 cluster1 { 48 cluster1 {
50 core0 { 49 core0 {
51 cpu = 50 cpu = <&A53_0>;
52 }; 51 };
53 core1 { 52 core1 {
54 cpu = 53 cpu = <&A53_1>;
55 }; 54 };
56 core2 { 55 core2 {
57 cpu = 56 cpu = <&A53_2>;
58 }; 57 };
59 core3 { 58 core3 {
60 cpu = 59 cpu = <&A53_3>;
61 }; 60 };
62 }; 61 };
63 }; 62 };
64 63
65 idle-states { 64 idle-states {
66 entry-method = "psci"; 65 entry-method = "psci";
67 66
68 CPU_SLEEP_0: cpu-sleep 67 CPU_SLEEP_0: cpu-sleep-0 {
69 compatible = " 68 compatible = "arm,idle-state";
70 arm,psci-suspe 69 arm,psci-suspend-param = <0x0010000>;
71 local-timer-st 70 local-timer-stop;
72 entry-latency- 71 entry-latency-us = <300>;
73 exit-latency-u 72 exit-latency-us = <1200>;
74 min-residency- 73 min-residency-us = <2000>;
75 }; 74 };
76 75
77 CLUSTER_SLEEP_0: clust 76 CLUSTER_SLEEP_0: cluster-sleep-0 {
78 compatible = " 77 compatible = "arm,idle-state";
79 arm,psci-suspe 78 arm,psci-suspend-param = <0x1010000>;
80 local-timer-st 79 local-timer-stop;
81 entry-latency- 80 entry-latency-us = <400>;
82 exit-latency-u 81 exit-latency-us = <1200>;
83 min-residency- 82 min-residency-us = <2500>;
84 }; 83 };
85 }; 84 };
86 85
87 A57_0: cpu@0 { 86 A57_0: cpu@0 {
88 compatible = "arm,cort !! 87 compatible = "arm,cortex-a57","arm,armv8";
89 reg = <0x0 0x0>; 88 reg = <0x0 0x0>;
90 device_type = "cpu"; 89 device_type = "cpu";
91 enable-method = "psci" 90 enable-method = "psci";
92 i-cache-size = <0xc000 91 i-cache-size = <0xc000>;
93 i-cache-line-size = <6 92 i-cache-line-size = <64>;
94 i-cache-sets = <256>; 93 i-cache-sets = <256>;
95 d-cache-size = <0x8000 94 d-cache-size = <0x8000>;
96 d-cache-line-size = <6 95 d-cache-line-size = <64>;
97 d-cache-sets = <256>; 96 d-cache-sets = <256>;
98 next-level-cache = <&A 97 next-level-cache = <&A57_L2>;
99 clocks = <&scpi_dvfs 0 98 clocks = <&scpi_dvfs 0>;
100 cpu-idle-states = <&CP 99 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
101 capacity-dmips-mhz = < 100 capacity-dmips-mhz = <1024>;
102 dynamic-power-coeffici <<
103 }; 101 };
104 102
105 A57_1: cpu@1 { 103 A57_1: cpu@1 {
106 compatible = "arm,cort !! 104 compatible = "arm,cortex-a57","arm,armv8";
107 reg = <0x0 0x1>; 105 reg = <0x0 0x1>;
108 device_type = "cpu"; 106 device_type = "cpu";
109 enable-method = "psci" 107 enable-method = "psci";
110 i-cache-size = <0xc000 108 i-cache-size = <0xc000>;
111 i-cache-line-size = <6 109 i-cache-line-size = <64>;
112 i-cache-sets = <256>; 110 i-cache-sets = <256>;
113 d-cache-size = <0x8000 111 d-cache-size = <0x8000>;
114 d-cache-line-size = <6 112 d-cache-line-size = <64>;
115 d-cache-sets = <256>; 113 d-cache-sets = <256>;
116 next-level-cache = <&A 114 next-level-cache = <&A57_L2>;
117 clocks = <&scpi_dvfs 0 115 clocks = <&scpi_dvfs 0>;
118 cpu-idle-states = <&CP 116 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119 capacity-dmips-mhz = < 117 capacity-dmips-mhz = <1024>;
120 dynamic-power-coeffici <<
121 }; 118 };
122 119
123 A53_0: cpu@100 { 120 A53_0: cpu@100 {
124 compatible = "arm,cort !! 121 compatible = "arm,cortex-a53","arm,armv8";
125 reg = <0x0 0x100>; 122 reg = <0x0 0x100>;
126 device_type = "cpu"; 123 device_type = "cpu";
127 enable-method = "psci" 124 enable-method = "psci";
128 i-cache-size = <0x8000 125 i-cache-size = <0x8000>;
129 i-cache-line-size = <6 126 i-cache-line-size = <64>;
130 i-cache-sets = <256>; 127 i-cache-sets = <256>;
131 d-cache-size = <0x8000 128 d-cache-size = <0x8000>;
132 d-cache-line-size = <6 129 d-cache-line-size = <64>;
133 d-cache-sets = <128>; 130 d-cache-sets = <128>;
134 next-level-cache = <&A 131 next-level-cache = <&A53_L2>;
135 clocks = <&scpi_dvfs 1 132 clocks = <&scpi_dvfs 1>;
136 cpu-idle-states = <&CP 133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = < 134 capacity-dmips-mhz = <578>;
138 dynamic-power-coeffici <<
139 }; 135 };
140 136
141 A53_1: cpu@101 { 137 A53_1: cpu@101 {
142 compatible = "arm,cort !! 138 compatible = "arm,cortex-a53","arm,armv8";
143 reg = <0x0 0x101>; 139 reg = <0x0 0x101>;
144 device_type = "cpu"; 140 device_type = "cpu";
145 enable-method = "psci" 141 enable-method = "psci";
146 i-cache-size = <0x8000 142 i-cache-size = <0x8000>;
147 i-cache-line-size = <6 143 i-cache-line-size = <64>;
148 i-cache-sets = <256>; 144 i-cache-sets = <256>;
149 d-cache-size = <0x8000 145 d-cache-size = <0x8000>;
150 d-cache-line-size = <6 146 d-cache-line-size = <64>;
151 d-cache-sets = <128>; 147 d-cache-sets = <128>;
152 next-level-cache = <&A 148 next-level-cache = <&A53_L2>;
153 clocks = <&scpi_dvfs 1 149 clocks = <&scpi_dvfs 1>;
154 cpu-idle-states = <&CP 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
155 capacity-dmips-mhz = < 151 capacity-dmips-mhz = <578>;
156 dynamic-power-coeffici <<
157 }; 152 };
158 153
159 A53_2: cpu@102 { 154 A53_2: cpu@102 {
160 compatible = "arm,cort !! 155 compatible = "arm,cortex-a53","arm,armv8";
161 reg = <0x0 0x102>; 156 reg = <0x0 0x102>;
162 device_type = "cpu"; 157 device_type = "cpu";
163 enable-method = "psci" 158 enable-method = "psci";
164 i-cache-size = <0x8000 159 i-cache-size = <0x8000>;
165 i-cache-line-size = <6 160 i-cache-line-size = <64>;
166 i-cache-sets = <256>; 161 i-cache-sets = <256>;
167 d-cache-size = <0x8000 162 d-cache-size = <0x8000>;
168 d-cache-line-size = <6 163 d-cache-line-size = <64>;
169 d-cache-sets = <128>; 164 d-cache-sets = <128>;
170 next-level-cache = <&A 165 next-level-cache = <&A53_L2>;
171 clocks = <&scpi_dvfs 1 166 clocks = <&scpi_dvfs 1>;
172 cpu-idle-states = <&CP 167 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <578>;
174 dynamic-power-coeffici <<
175 }; 169 };
176 170
177 A53_3: cpu@103 { 171 A53_3: cpu@103 {
178 compatible = "arm,cort !! 172 compatible = "arm,cortex-a53","arm,armv8";
179 reg = <0x0 0x103>; 173 reg = <0x0 0x103>;
180 device_type = "cpu"; 174 device_type = "cpu";
181 enable-method = "psci" 175 enable-method = "psci";
182 i-cache-size = <0x8000 176 i-cache-size = <0x8000>;
183 i-cache-line-size = <6 177 i-cache-line-size = <64>;
184 i-cache-sets = <256>; 178 i-cache-sets = <256>;
185 d-cache-size = <0x8000 179 d-cache-size = <0x8000>;
186 d-cache-line-size = <6 180 d-cache-line-size = <64>;
187 d-cache-sets = <128>; 181 d-cache-sets = <128>;
188 next-level-cache = <&A 182 next-level-cache = <&A53_L2>;
189 clocks = <&scpi_dvfs 1 183 clocks = <&scpi_dvfs 1>;
190 cpu-idle-states = <&CP 184 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
191 capacity-dmips-mhz = < 185 capacity-dmips-mhz = <578>;
192 dynamic-power-coeffici <<
193 }; 186 };
194 187
195 A57_L2: l2-cache0 { 188 A57_L2: l2-cache0 {
196 compatible = "cache"; 189 compatible = "cache";
197 cache-unified; <<
198 cache-size = <0x200000 190 cache-size = <0x200000>;
199 cache-line-size = <64> 191 cache-line-size = <64>;
200 cache-sets = <2048>; 192 cache-sets = <2048>;
201 cache-level = <2>; <<
202 }; 193 };
203 194
204 A53_L2: l2-cache1 { 195 A53_L2: l2-cache1 {
205 compatible = "cache"; 196 compatible = "cache";
206 cache-unified; <<
207 cache-size = <0x100000 197 cache-size = <0x100000>;
208 cache-line-size = <64> 198 cache-line-size = <64>;
209 cache-sets = <1024>; 199 cache-sets = <1024>;
210 cache-level = <2>; <<
211 }; 200 };
212 }; 201 };
213 202
214 pmu-a57 { 203 pmu-a57 {
215 compatible = "arm,cortex-a57-p 204 compatible = "arm,cortex-a57-pmu";
216 interrupts = <GIC_SPI 02 IRQ_T 205 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 06 IRQ_T 206 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-affinity = <&A57_0>, 207 interrupt-affinity = <&A57_0>,
219 <&A57_1>; 208 <&A57_1>;
220 }; 209 };
221 210
222 pmu-a53 { 211 pmu-a53 {
223 compatible = "arm,cortex-a53-p 212 compatible = "arm,cortex-a53-pmu";
224 interrupts = <GIC_SPI 18 IRQ_T 213 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 22 IRQ_T 214 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 26 IRQ_T 215 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 30 IRQ_T 216 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
228 interrupt-affinity = <&A53_0>, 217 interrupt-affinity = <&A53_0>,
229 <&A53_1>, 218 <&A53_1>,
230 <&A53_2>, 219 <&A53_2>,
231 <&A53_3>; 220 <&A53_3>;
232 }; 221 };
233 }; 222 };
234 223
235 &etm0 { 224 &etm0 {
236 cpu = <&A57_0>; 225 cpu = <&A57_0>;
237 }; 226 };
238 227
239 &etm1 { 228 &etm1 {
240 cpu = <&A57_1>; 229 cpu = <&A57_1>;
241 }; 230 };
242 231
243 &etm2 { 232 &etm2 {
244 cpu = <&A53_0>; 233 cpu = <&A53_0>;
245 }; 234 };
246 235
247 &etm3 { 236 &etm3 {
248 cpu = <&A53_1>; 237 cpu = <&A53_1>;
249 }; 238 };
250 239
251 &etm4 { 240 &etm4 {
252 cpu = <&A53_2>; 241 cpu = <&A53_2>;
253 }; 242 };
254 243
255 &etm5 { 244 &etm5 {
256 cpu = <&A53_3>; 245 cpu = <&A53_3>;
257 }; 246 };
258 247
259 &etf0_out_port { 248 &etf0_out_port {
260 remote-endpoint = <&replicator_in_port 249 remote-endpoint = <&replicator_in_port0>;
261 }; 250 };
262 251
263 &replicator_in_port0 { 252 &replicator_in_port0 {
264 remote-endpoint = <&etf0_out_port>; 253 remote-endpoint = <&etf0_out_port>;
265 }; 254 };
266 255
267 &stm_out_port { 256 &stm_out_port {
268 remote-endpoint = <&main_funnel_in_por 257 remote-endpoint = <&main_funnel_in_port2>;
269 }; 258 };
270 259
271 &main_funnel_in_ports { 260 &main_funnel_in_ports {
272 port@2 { 261 port@2 {
273 reg = <2>; 262 reg = <2>;
274 main_funnel_in_port2: endpoint 263 main_funnel_in_port2: endpoint {
275 remote-endpoint = <&st 264 remote-endpoint = <&stm_out_port>;
276 }; 265 };
277 }; 266 };
278 }; 267 };
279 268
280 &cpu_debug0 { 269 &cpu_debug0 {
281 cpu = <&A57_0>; 270 cpu = <&A57_0>;
282 }; 271 };
283 272
284 &cpu_debug1 { 273 &cpu_debug1 {
285 cpu = <&A57_1>; 274 cpu = <&A57_1>;
286 }; 275 };
287 276
288 &cpu_debug2 { 277 &cpu_debug2 {
289 cpu = <&A53_0>; 278 cpu = <&A53_0>;
290 }; 279 };
291 280
292 &cpu_debug3 { 281 &cpu_debug3 {
293 cpu = <&A53_1>; 282 cpu = <&A53_1>;
294 }; 283 };
295 284
296 &cpu_debug4 { 285 &cpu_debug4 {
297 cpu = <&A53_2>; 286 cpu = <&A53_2>;
298 }; 287 };
299 288
300 &cpu_debug5 { 289 &cpu_debug5 {
301 cpu = <&A53_3>; <<
302 }; <<
303 <<
304 &cti0 { <<
305 cpu = <&A57_0>; <<
306 }; <<
307 <<
308 &cti1 { <<
309 cpu = <&A57_1>; <<
310 }; <<
311 <<
312 &cti2 { <<
313 cpu = <&A53_0>; <<
314 }; <<
315 <<
316 &cti3 { <<
317 cpu = <&A53_1>; <<
318 }; <<
319 <<
320 &cti4 { <<
321 cpu = <&A53_2>; <<
322 }; <<
323 <<
324 &cti5 { <<
325 cpu = <&A53_3>; 290 cpu = <&A53_3>;
326 }; 291 };
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