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Linux/scripts/dtc/include-prefixes/arm64/arm/juno.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/arm/juno.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/arm/juno.dts (Version linux-6.10.14)


  1 /*                                                  1 /*
  2  * ARM Ltd. Juno Platform                           2  * ARM Ltd. Juno Platform
  3  *                                                  3  *
  4  * Copyright (c) 2013-2014 ARM Ltd.                 4  * Copyright (c) 2013-2014 ARM Ltd.
  5  *                                                  5  *
  6  * This file is licensed under a dual GPLv2 or      6  * This file is licensed under a dual GPLv2 or BSD license.
  7  */                                                 7  */
  8                                                     8 
  9 /dts-v1/;                                           9 /dts-v1/;
 10                                                    10 
 11 #include <dt-bindings/interrupt-controller/arm     11 #include <dt-bindings/interrupt-controller/arm-gic.h>
 12 #include <dt-bindings/arm/coresight-cti-dt.h>      12 #include <dt-bindings/arm/coresight-cti-dt.h>
 13 #include "juno-base.dtsi"                          13 #include "juno-base.dtsi"
 14                                                    14 
 15 / {                                                15 / {
 16         model = "ARM Juno development board (r     16         model = "ARM Juno development board (r0)";
 17         compatible = "arm,juno", "arm,vexpress     17         compatible = "arm,juno", "arm,vexpress";
 18         interrupt-parent = <&gic>;                 18         interrupt-parent = <&gic>;
 19         #address-cells = <2>;                      19         #address-cells = <2>;
 20         #size-cells = <2>;                         20         #size-cells = <2>;
 21                                                    21 
 22         aliases {                                  22         aliases {
 23                 serial0 = &soc_uart0;              23                 serial0 = &soc_uart0;
 24         };                                         24         };
 25                                                    25 
 26         chosen {                                   26         chosen {
 27                 stdout-path = "serial0:115200n     27                 stdout-path = "serial0:115200n8";
 28         };                                         28         };
 29                                                    29 
 30         psci {                                     30         psci {
 31                 compatible = "arm,psci-0.2";       31                 compatible = "arm,psci-0.2";
 32                 method = "smc";                    32                 method = "smc";
 33         };                                         33         };
 34                                                    34 
 35         cpus {                                     35         cpus {
 36                 #address-cells = <2>;              36                 #address-cells = <2>;
 37                 #size-cells = <0>;                 37                 #size-cells = <0>;
 38                                                    38 
 39                 cpu-map {                          39                 cpu-map {
 40                         cluster0 {                 40                         cluster0 {
 41                                 core0 {            41                                 core0 {
 42                                         cpu =      42                                         cpu = <&A57_0>;
 43                                 };                 43                                 };
 44                                 core1 {            44                                 core1 {
 45                                         cpu =      45                                         cpu = <&A57_1>;
 46                                 };                 46                                 };
 47                         };                         47                         };
 48                                                    48 
 49                         cluster1 {                 49                         cluster1 {
 50                                 core0 {            50                                 core0 {
 51                                         cpu =      51                                         cpu = <&A53_0>;
 52                                 };                 52                                 };
 53                                 core1 {            53                                 core1 {
 54                                         cpu =      54                                         cpu = <&A53_1>;
 55                                 };                 55                                 };
 56                                 core2 {            56                                 core2 {
 57                                         cpu =      57                                         cpu = <&A53_2>;
 58                                 };                 58                                 };
 59                                 core3 {            59                                 core3 {
 60                                         cpu =      60                                         cpu = <&A53_3>;
 61                                 };                 61                                 };
 62                         };                         62                         };
 63                 };                                 63                 };
 64                                                    64 
 65                 idle-states {                      65                 idle-states {
 66                         entry-method = "psci";     66                         entry-method = "psci";
 67                                                    67 
 68                         CPU_SLEEP_0: cpu-sleep     68                         CPU_SLEEP_0: cpu-sleep-0 {
 69                                 compatible = "     69                                 compatible = "arm,idle-state";
 70                                 arm,psci-suspe     70                                 arm,psci-suspend-param = <0x0010000>;
 71                                 local-timer-st     71                                 local-timer-stop;
 72                                 entry-latency-     72                                 entry-latency-us = <300>;
 73                                 exit-latency-u     73                                 exit-latency-us = <1200>;
 74                                 min-residency-     74                                 min-residency-us = <2000>;
 75                         };                         75                         };
 76                                                    76 
 77                         CLUSTER_SLEEP_0: clust     77                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 78                                 compatible = "     78                                 compatible = "arm,idle-state";
 79                                 arm,psci-suspe     79                                 arm,psci-suspend-param = <0x1010000>;
 80                                 local-timer-st     80                                 local-timer-stop;
 81                                 entry-latency-     81                                 entry-latency-us = <400>;
 82                                 exit-latency-u     82                                 exit-latency-us = <1200>;
 83                                 min-residency-     83                                 min-residency-us = <2500>;
 84                         };                         84                         };
 85                 };                                 85                 };
 86                                                    86 
 87                 A57_0: cpu@0 {                     87                 A57_0: cpu@0 {
 88                         compatible = "arm,cort     88                         compatible = "arm,cortex-a57";
 89                         reg = <0x0 0x0>;           89                         reg = <0x0 0x0>;
 90                         device_type = "cpu";       90                         device_type = "cpu";
 91                         enable-method = "psci"     91                         enable-method = "psci";
 92                         i-cache-size = <0xc000     92                         i-cache-size = <0xc000>;
 93                         i-cache-line-size = <6     93                         i-cache-line-size = <64>;
 94                         i-cache-sets = <256>;      94                         i-cache-sets = <256>;
 95                         d-cache-size = <0x8000     95                         d-cache-size = <0x8000>;
 96                         d-cache-line-size = <6     96                         d-cache-line-size = <64>;
 97                         d-cache-sets = <256>;      97                         d-cache-sets = <256>;
 98                         next-level-cache = <&A     98                         next-level-cache = <&A57_L2>;
 99                         clocks = <&scpi_dvfs 0     99                         clocks = <&scpi_dvfs 0>;
100                         cpu-idle-states = <&CP    100                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
101                         capacity-dmips-mhz = <    101                         capacity-dmips-mhz = <1024>;
102                         dynamic-power-coeffici    102                         dynamic-power-coefficient = <530>;
103                 };                                103                 };
104                                                   104 
105                 A57_1: cpu@1 {                    105                 A57_1: cpu@1 {
106                         compatible = "arm,cort    106                         compatible = "arm,cortex-a57";
107                         reg = <0x0 0x1>;          107                         reg = <0x0 0x1>;
108                         device_type = "cpu";      108                         device_type = "cpu";
109                         enable-method = "psci"    109                         enable-method = "psci";
110                         i-cache-size = <0xc000    110                         i-cache-size = <0xc000>;
111                         i-cache-line-size = <6    111                         i-cache-line-size = <64>;
112                         i-cache-sets = <256>;     112                         i-cache-sets = <256>;
113                         d-cache-size = <0x8000    113                         d-cache-size = <0x8000>;
114                         d-cache-line-size = <6    114                         d-cache-line-size = <64>;
115                         d-cache-sets = <256>;     115                         d-cache-sets = <256>;
116                         next-level-cache = <&A    116                         next-level-cache = <&A57_L2>;
117                         clocks = <&scpi_dvfs 0    117                         clocks = <&scpi_dvfs 0>;
118                         cpu-idle-states = <&CP    118                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119                         capacity-dmips-mhz = <    119                         capacity-dmips-mhz = <1024>;
120                         dynamic-power-coeffici    120                         dynamic-power-coefficient = <530>;
121                 };                                121                 };
122                                                   122 
123                 A53_0: cpu@100 {                  123                 A53_0: cpu@100 {
124                         compatible = "arm,cort    124                         compatible = "arm,cortex-a53";
125                         reg = <0x0 0x100>;        125                         reg = <0x0 0x100>;
126                         device_type = "cpu";      126                         device_type = "cpu";
127                         enable-method = "psci"    127                         enable-method = "psci";
128                         i-cache-size = <0x8000    128                         i-cache-size = <0x8000>;
129                         i-cache-line-size = <6    129                         i-cache-line-size = <64>;
130                         i-cache-sets = <256>;     130                         i-cache-sets = <256>;
131                         d-cache-size = <0x8000    131                         d-cache-size = <0x8000>;
132                         d-cache-line-size = <6    132                         d-cache-line-size = <64>;
133                         d-cache-sets = <128>;     133                         d-cache-sets = <128>;
134                         next-level-cache = <&A    134                         next-level-cache = <&A53_L2>;
135                         clocks = <&scpi_dvfs 1    135                         clocks = <&scpi_dvfs 1>;
136                         cpu-idle-states = <&CP    136                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137                         capacity-dmips-mhz = <    137                         capacity-dmips-mhz = <578>;
138                         dynamic-power-coeffici    138                         dynamic-power-coefficient = <140>;
139                 };                                139                 };
140                                                   140 
141                 A53_1: cpu@101 {                  141                 A53_1: cpu@101 {
142                         compatible = "arm,cort    142                         compatible = "arm,cortex-a53";
143                         reg = <0x0 0x101>;        143                         reg = <0x0 0x101>;
144                         device_type = "cpu";      144                         device_type = "cpu";
145                         enable-method = "psci"    145                         enable-method = "psci";
146                         i-cache-size = <0x8000    146                         i-cache-size = <0x8000>;
147                         i-cache-line-size = <6    147                         i-cache-line-size = <64>;
148                         i-cache-sets = <256>;     148                         i-cache-sets = <256>;
149                         d-cache-size = <0x8000    149                         d-cache-size = <0x8000>;
150                         d-cache-line-size = <6    150                         d-cache-line-size = <64>;
151                         d-cache-sets = <128>;     151                         d-cache-sets = <128>;
152                         next-level-cache = <&A    152                         next-level-cache = <&A53_L2>;
153                         clocks = <&scpi_dvfs 1    153                         clocks = <&scpi_dvfs 1>;
154                         cpu-idle-states = <&CP    154                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
155                         capacity-dmips-mhz = <    155                         capacity-dmips-mhz = <578>;
156                         dynamic-power-coeffici    156                         dynamic-power-coefficient = <140>;
157                 };                                157                 };
158                                                   158 
159                 A53_2: cpu@102 {                  159                 A53_2: cpu@102 {
160                         compatible = "arm,cort    160                         compatible = "arm,cortex-a53";
161                         reg = <0x0 0x102>;        161                         reg = <0x0 0x102>;
162                         device_type = "cpu";      162                         device_type = "cpu";
163                         enable-method = "psci"    163                         enable-method = "psci";
164                         i-cache-size = <0x8000    164                         i-cache-size = <0x8000>;
165                         i-cache-line-size = <6    165                         i-cache-line-size = <64>;
166                         i-cache-sets = <256>;     166                         i-cache-sets = <256>;
167                         d-cache-size = <0x8000    167                         d-cache-size = <0x8000>;
168                         d-cache-line-size = <6    168                         d-cache-line-size = <64>;
169                         d-cache-sets = <128>;     169                         d-cache-sets = <128>;
170                         next-level-cache = <&A    170                         next-level-cache = <&A53_L2>;
171                         clocks = <&scpi_dvfs 1    171                         clocks = <&scpi_dvfs 1>;
172                         cpu-idle-states = <&CP    172                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173                         capacity-dmips-mhz = <    173                         capacity-dmips-mhz = <578>;
174                         dynamic-power-coeffici    174                         dynamic-power-coefficient = <140>;
175                 };                                175                 };
176                                                   176 
177                 A53_3: cpu@103 {                  177                 A53_3: cpu@103 {
178                         compatible = "arm,cort    178                         compatible = "arm,cortex-a53";
179                         reg = <0x0 0x103>;        179                         reg = <0x0 0x103>;
180                         device_type = "cpu";      180                         device_type = "cpu";
181                         enable-method = "psci"    181                         enable-method = "psci";
182                         i-cache-size = <0x8000    182                         i-cache-size = <0x8000>;
183                         i-cache-line-size = <6    183                         i-cache-line-size = <64>;
184                         i-cache-sets = <256>;     184                         i-cache-sets = <256>;
185                         d-cache-size = <0x8000    185                         d-cache-size = <0x8000>;
186                         d-cache-line-size = <6    186                         d-cache-line-size = <64>;
187                         d-cache-sets = <128>;     187                         d-cache-sets = <128>;
188                         next-level-cache = <&A    188                         next-level-cache = <&A53_L2>;
189                         clocks = <&scpi_dvfs 1    189                         clocks = <&scpi_dvfs 1>;
190                         cpu-idle-states = <&CP    190                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
191                         capacity-dmips-mhz = <    191                         capacity-dmips-mhz = <578>;
192                         dynamic-power-coeffici    192                         dynamic-power-coefficient = <140>;
193                 };                                193                 };
194                                                   194 
195                 A57_L2: l2-cache0 {               195                 A57_L2: l2-cache0 {
196                         compatible = "cache";     196                         compatible = "cache";
197                         cache-unified;            197                         cache-unified;
198                         cache-size = <0x200000    198                         cache-size = <0x200000>;
199                         cache-line-size = <64>    199                         cache-line-size = <64>;
200                         cache-sets = <2048>;      200                         cache-sets = <2048>;
201                         cache-level = <2>;        201                         cache-level = <2>;
202                 };                                202                 };
203                                                   203 
204                 A53_L2: l2-cache1 {               204                 A53_L2: l2-cache1 {
205                         compatible = "cache";     205                         compatible = "cache";
206                         cache-unified;            206                         cache-unified;
207                         cache-size = <0x100000    207                         cache-size = <0x100000>;
208                         cache-line-size = <64>    208                         cache-line-size = <64>;
209                         cache-sets = <1024>;      209                         cache-sets = <1024>;
210                         cache-level = <2>;        210                         cache-level = <2>;
211                 };                                211                 };
212         };                                        212         };
213                                                   213 
214         pmu-a57 {                                 214         pmu-a57 {
215                 compatible = "arm,cortex-a57-p    215                 compatible = "arm,cortex-a57-pmu";
216                 interrupts = <GIC_SPI 02 IRQ_T    216                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
217                              <GIC_SPI 06 IRQ_T    217                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
218                 interrupt-affinity = <&A57_0>,    218                 interrupt-affinity = <&A57_0>,
219                                      <&A57_1>;    219                                      <&A57_1>;
220         };                                        220         };
221                                                   221 
222         pmu-a53 {                                 222         pmu-a53 {
223                 compatible = "arm,cortex-a53-p    223                 compatible = "arm,cortex-a53-pmu";
224                 interrupts = <GIC_SPI 18 IRQ_T    224                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
225                              <GIC_SPI 22 IRQ_T    225                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
226                              <GIC_SPI 26 IRQ_T    226                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
227                              <GIC_SPI 30 IRQ_T    227                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
228                 interrupt-affinity = <&A53_0>,    228                 interrupt-affinity = <&A53_0>,
229                                      <&A53_1>,    229                                      <&A53_1>,
230                                      <&A53_2>,    230                                      <&A53_2>,
231                                      <&A53_3>;    231                                      <&A53_3>;
232         };                                        232         };
233 };                                                233 };
234                                                   234 
235 &etm0 {                                           235 &etm0 {
236         cpu = <&A57_0>;                           236         cpu = <&A57_0>;
237 };                                                237 };
238                                                   238 
239 &etm1 {                                           239 &etm1 {
240         cpu = <&A57_1>;                           240         cpu = <&A57_1>;
241 };                                                241 };
242                                                   242 
243 &etm2 {                                           243 &etm2 {
244         cpu = <&A53_0>;                           244         cpu = <&A53_0>;
245 };                                                245 };
246                                                   246 
247 &etm3 {                                           247 &etm3 {
248         cpu = <&A53_1>;                           248         cpu = <&A53_1>;
249 };                                                249 };
250                                                   250 
251 &etm4 {                                           251 &etm4 {
252         cpu = <&A53_2>;                           252         cpu = <&A53_2>;
253 };                                                253 };
254                                                   254 
255 &etm5 {                                           255 &etm5 {
256         cpu = <&A53_3>;                           256         cpu = <&A53_3>;
257 };                                                257 };
258                                                   258 
259 &etf0_out_port {                                  259 &etf0_out_port {
260         remote-endpoint = <&replicator_in_port    260         remote-endpoint = <&replicator_in_port0>;
261 };                                                261 };
262                                                   262 
263 &replicator_in_port0 {                            263 &replicator_in_port0 {
264         remote-endpoint = <&etf0_out_port>;       264         remote-endpoint = <&etf0_out_port>;
265 };                                                265 };
266                                                   266 
267 &stm_out_port {                                   267 &stm_out_port {
268         remote-endpoint = <&main_funnel_in_por    268         remote-endpoint = <&main_funnel_in_port2>;
269 };                                                269 };
270                                                   270 
271 &main_funnel_in_ports {                           271 &main_funnel_in_ports {
272         port@2 {                                  272         port@2 {
273                 reg = <2>;                        273                 reg = <2>;
274                 main_funnel_in_port2: endpoint    274                 main_funnel_in_port2: endpoint {
275                         remote-endpoint = <&st    275                         remote-endpoint = <&stm_out_port>;
276                 };                                276                 };
277         };                                        277         };
278 };                                                278 };
279                                                   279 
280 &cpu_debug0 {                                     280 &cpu_debug0 {
281         cpu = <&A57_0>;                           281         cpu = <&A57_0>;
282 };                                                282 };
283                                                   283 
284 &cpu_debug1 {                                     284 &cpu_debug1 {
285         cpu = <&A57_1>;                           285         cpu = <&A57_1>;
286 };                                                286 };
287                                                   287 
288 &cpu_debug2 {                                     288 &cpu_debug2 {
289         cpu = <&A53_0>;                           289         cpu = <&A53_0>;
290 };                                                290 };
291                                                   291 
292 &cpu_debug3 {                                     292 &cpu_debug3 {
293         cpu = <&A53_1>;                           293         cpu = <&A53_1>;
294 };                                                294 };
295                                                   295 
296 &cpu_debug4 {                                     296 &cpu_debug4 {
297         cpu = <&A53_2>;                           297         cpu = <&A53_2>;
298 };                                                298 };
299                                                   299 
300 &cpu_debug5 {                                     300 &cpu_debug5 {
301         cpu = <&A53_3>;                           301         cpu = <&A53_3>;
302 };                                                302 };
303                                                   303 
304 &cti0 {                                           304 &cti0 {
305         cpu = <&A57_0>;                           305         cpu = <&A57_0>;
306 };                                                306 };
307                                                   307 
308 &cti1 {                                           308 &cti1 {
309         cpu = <&A57_1>;                           309         cpu = <&A57_1>;
310 };                                                310 };
311                                                   311 
312 &cti2 {                                           312 &cti2 {
313         cpu = <&A53_0>;                           313         cpu = <&A53_0>;
314 };                                                314 };
315                                                   315 
316 &cti3 {                                           316 &cti3 {
317         cpu = <&A53_1>;                           317         cpu = <&A53_1>;
318 };                                                318 };
319                                                   319 
320 &cti4 {                                           320 &cti4 {
321         cpu = <&A53_2>;                           321         cpu = <&A53_2>;
322 };                                                322 };
323                                                   323 
324 &cti5 {                                           324 &cti5 {
325         cpu = <&A53_3>;                           325         cpu = <&A53_3>;
326 };                                                326 };
                                                      

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