1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 Linaro Ltd. 3 * Copyright (c) 2019 Linaro Ltd.
4 * Author: Manivannan Sadhasivam <manivannan.sa 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/bm1880-clock.h> <<
8 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-res 8 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
10 9
11 / { 10 / {
12 compatible = "bitmain,bm1880"; 11 compatible = "bitmain,bm1880";
13 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
14 #address-cells = <2>; 13 #address-cells = <2>;
15 #size-cells = <2>; 14 #size-cells = <2>;
16 15
17 cpus { 16 cpus {
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <0>; 18 #size-cells = <0>;
20 19
21 cpu0: cpu@0 { 20 cpu0: cpu@0 {
22 device_type = "cpu"; 21 device_type = "cpu";
23 compatible = "arm,cort 22 compatible = "arm,cortex-a53";
24 reg = <0x0>; 23 reg = <0x0>;
25 enable-method = "psci" 24 enable-method = "psci";
26 }; 25 };
27 26
28 cpu1: cpu@1 { 27 cpu1: cpu@1 {
29 device_type = "cpu"; 28 device_type = "cpu";
30 compatible = "arm,cort 29 compatible = "arm,cortex-a53";
31 reg = <0x1>; 30 reg = <0x1>;
32 enable-method = "psci" 31 enable-method = "psci";
33 }; 32 };
34 }; 33 };
35 34
36 reserved-memory { 35 reserved-memory {
37 #address-cells = <2>; 36 #address-cells = <2>;
38 #size-cells = <2>; 37 #size-cells = <2>;
39 ranges; 38 ranges;
40 39
41 secmon@100000000 { 40 secmon@100000000 {
42 reg = <0x1 0x00000000 41 reg = <0x1 0x00000000 0x0 0x20000>;
43 no-map; 42 no-map;
44 }; 43 };
45 44
46 jpu@130000000 { 45 jpu@130000000 {
47 reg = <0x1 0x30000000 46 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
48 no-map; 47 no-map;
49 }; 48 };
50 49
51 vpu@138000000 { 50 vpu@138000000 {
52 reg = <0x1 0x38000000 51 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
53 no-map; 52 no-map;
54 }; 53 };
55 }; 54 };
56 55
57 psci { 56 psci {
58 compatible = "arm,psci-0.2"; 57 compatible = "arm,psci-0.2";
59 method = "smc"; 58 method = "smc";
60 }; 59 };
61 60
62 timer { 61 timer {
63 compatible = "arm,armv8-timer" 62 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 13 IRQ_T 63 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
65 <GIC_PPI 14 IRQ_T 64 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
66 <GIC_PPI 11 IRQ_T 65 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
67 <GIC_PPI 10 IRQ_T 66 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
68 }; 67 };
69 68
70 osc: osc { <<
71 compatible = "fixed-clock"; <<
72 clock-frequency = <25000000>; <<
73 #clock-cells = <0>; <<
74 }; <<
75 <<
76 soc { 69 soc {
77 compatible = "simple-bus"; 70 compatible = "simple-bus";
78 #address-cells = <2>; 71 #address-cells = <2>;
79 #size-cells = <2>; 72 #size-cells = <2>;
80 ranges; 73 ranges;
81 74
82 gic: interrupt-controller@5000 75 gic: interrupt-controller@50001000 {
83 compatible = "arm,gic- 76 compatible = "arm,gic-400";
84 reg = <0x0 0x50001000 77 reg = <0x0 0x50001000 0x0 0x1000>,
85 <0x0 0x50002000 78 <0x0 0x50002000 0x0 0x2000>;
86 interrupts = <GIC_PPI 79 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
87 interrupt-controller; 80 interrupt-controller;
88 #interrupt-cells = <3> 81 #interrupt-cells = <3>;
89 }; 82 };
90 83
91 sctrl: system-controller@50010 84 sctrl: system-controller@50010000 {
92 compatible = "bitmain, 85 compatible = "bitmain,bm1880-sctrl", "syscon",
93 "simple-m 86 "simple-mfd";
94 reg = <0x0 0x50010000 87 reg = <0x0 0x50010000 0x0 0x1000>;
95 #address-cells = <1>; 88 #address-cells = <1>;
96 #size-cells = <1>; 89 #size-cells = <1>;
97 ranges = <0x0 0x0 0x50 90 ranges = <0x0 0x0 0x50010000 0x1000>;
98 91
99 pinctrl: pinctrl@400 { 92 pinctrl: pinctrl@400 {
100 compatible = " 93 compatible = "bitmain,bm1880-pinctrl";
101 reg = <0x400 0 94 reg = <0x400 0x120>;
102 }; 95 };
103 96
104 clk: clock-controller@ <<
105 compatible = " <<
106 reg = <0xe8 0x <<
107 reg-names = "p <<
108 clocks = <&osc <<
109 clock-names = <<
110 #clock-cells = <<
111 }; <<
112 <<
113 rst: reset-controller@ 97 rst: reset-controller@c00 {
114 compatible = " 98 compatible = "bitmain,bm1880-reset";
115 reg = <0xc00 0 99 reg = <0xc00 0x8>;
116 #reset-cells = 100 #reset-cells = <1>;
117 }; 101 };
118 }; 102 };
119 103
120 gpio0: gpio@50027000 { 104 gpio0: gpio@50027000 {
121 #address-cells = <1>; 105 #address-cells = <1>;
122 #size-cells = <0>; 106 #size-cells = <0>;
123 compatible = "snps,dw- 107 compatible = "snps,dw-apb-gpio";
124 reg = <0x0 0x50027000 108 reg = <0x0 0x50027000 0x0 0x400>;
125 109
126 porta: gpio-controller 110 porta: gpio-controller@0 {
127 compatible = " 111 compatible = "snps,dw-apb-gpio-port";
128 gpio-controlle 112 gpio-controller;
129 #gpio-cells = 113 #gpio-cells = <2>;
130 ngpios = <32>; !! 114 snps,nr-gpios = <32>;
131 reg = <0>; 115 reg = <0>;
132 interrupt-cont 116 interrupt-controller;
133 #interrupt-cel 117 #interrupt-cells = <2>;
134 interrupts = < 118 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
135 }; 119 };
136 }; 120 };
137 121
138 gpio1: gpio@50027400 { 122 gpio1: gpio@50027400 {
139 #address-cells = <1>; 123 #address-cells = <1>;
140 #size-cells = <0>; 124 #size-cells = <0>;
141 compatible = "snps,dw- 125 compatible = "snps,dw-apb-gpio";
142 reg = <0x0 0x50027400 126 reg = <0x0 0x50027400 0x0 0x400>;
143 127
144 portb: gpio-controller 128 portb: gpio-controller@0 {
145 compatible = " 129 compatible = "snps,dw-apb-gpio-port";
146 gpio-controlle 130 gpio-controller;
147 #gpio-cells = 131 #gpio-cells = <2>;
148 ngpios = <32>; !! 132 snps,nr-gpios = <32>;
149 reg = <0>; 133 reg = <0>;
150 interrupt-cont 134 interrupt-controller;
151 #interrupt-cel 135 #interrupt-cells = <2>;
152 interrupts = < 136 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
153 }; 137 };
154 }; 138 };
155 139
156 gpio2: gpio@50027800 { 140 gpio2: gpio@50027800 {
157 #address-cells = <1>; 141 #address-cells = <1>;
158 #size-cells = <0>; 142 #size-cells = <0>;
159 compatible = "snps,dw- 143 compatible = "snps,dw-apb-gpio";
160 reg = <0x0 0x50027800 144 reg = <0x0 0x50027800 0x0 0x400>;
161 145
162 portc: gpio-controller 146 portc: gpio-controller@0 {
163 compatible = " 147 compatible = "snps,dw-apb-gpio-port";
164 gpio-controlle 148 gpio-controller;
165 #gpio-cells = 149 #gpio-cells = <2>;
166 ngpios = <8>; !! 150 snps,nr-gpios = <8>;
167 reg = <0>; 151 reg = <0>;
168 interrupt-cont 152 interrupt-controller;
169 #interrupt-cel 153 #interrupt-cells = <2>;
170 interrupts = < 154 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
171 }; 155 };
172 }; 156 };
173 157
174 uart0: serial@58018000 { 158 uart0: serial@58018000 {
175 compatible = "snps,dw- 159 compatible = "snps,dw-apb-uart";
176 reg = <0x0 0x58018000 160 reg = <0x0 0x58018000 0x0 0x2000>;
177 clocks = <&clk BM1880_ <<
178 <&clk BM1880_ <<
179 clock-names = "baudclk <<
180 interrupts = <GIC_SPI 161 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
181 reg-shift = <2>; 162 reg-shift = <2>;
182 reg-io-width = <4>; 163 reg-io-width = <4>;
183 resets = <&rst BM1880_ 164 resets = <&rst BM1880_RST_UART0_1_CLK>;
184 status = "disabled"; 165 status = "disabled";
185 }; 166 };
186 167
187 uart1: serial@5801a000 { !! 168 uart1: serial@5801A000 {
188 compatible = "snps,dw- 169 compatible = "snps,dw-apb-uart";
189 reg = <0x0 0x5801a000 170 reg = <0x0 0x5801a000 0x0 0x2000>;
190 clocks = <&clk BM1880_ <<
191 <&clk BM1880_ <<
192 clock-names = "baudclk <<
193 interrupts = <GIC_SPI 171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
194 reg-shift = <2>; 172 reg-shift = <2>;
195 reg-io-width = <4>; 173 reg-io-width = <4>;
196 resets = <&rst BM1880_ 174 resets = <&rst BM1880_RST_UART0_1_ACLK>;
197 status = "disabled"; 175 status = "disabled";
198 }; 176 };
199 177
200 uart2: serial@5801c000 { !! 178 uart2: serial@5801C000 {
201 compatible = "snps,dw- 179 compatible = "snps,dw-apb-uart";
202 reg = <0x0 0x5801c000 180 reg = <0x0 0x5801c000 0x0 0x2000>;
203 clocks = <&clk BM1880_ <<
204 <&clk BM1880_ <<
205 clock-names = "baudclk <<
206 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
207 reg-shift = <2>; 182 reg-shift = <2>;
208 reg-io-width = <4>; 183 reg-io-width = <4>;
209 resets = <&rst BM1880_ 184 resets = <&rst BM1880_RST_UART2_3_CLK>;
210 status = "disabled"; 185 status = "disabled";
211 }; 186 };
212 187
213 uart3: serial@5801e000 { !! 188 uart3: serial@5801E000 {
214 compatible = "snps,dw- 189 compatible = "snps,dw-apb-uart";
215 reg = <0x0 0x5801e000 190 reg = <0x0 0x5801e000 0x0 0x2000>;
216 clocks = <&clk BM1880_ <<
217 <&clk BM1880_ <<
218 clock-names = "baudclk <<
219 interrupts = <GIC_SPI 191 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
220 reg-shift = <2>; 192 reg-shift = <2>;
221 reg-io-width = <4>; 193 reg-io-width = <4>;
222 resets = <&rst BM1880_ 194 resets = <&rst BM1880_RST_UART2_3_ACLK>;
223 status = "disabled"; 195 status = "disabled";
224 }; 196 };
225 }; 197 };
226 }; 198 };
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