1 /* 1 /*
2 * BSD LICENSE 2 * BSD LICENSE
3 * 3 *
4 * Copyright(c) 2016-2017 Broadcom. All righ 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binar 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 9 *
10 * * Redistributions of source code must re 10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and th 11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must re 12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and th 13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materia 14 * the documentation and/or other materials provided with the
15 * distribution. 15 * distribution.
16 * * Neither the name of Broadcom nor the n 16 * * Neither the name of Broadcom nor the names of its
17 * contributors may be used to endorse or 17 * contributors may be used to endorse or promote products derived
18 * from this software without specific pr 18 * from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE P 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33 #include <dt-bindings/clock/bcm-sr.h> 33 #include <dt-bindings/clock/bcm-sr.h>
34 34
35 osc: oscillator { 35 osc: oscillator {
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 compatible = "fixed-cl 37 compatible = "fixed-clock";
38 clock-frequency = <500 38 clock-frequency = <50000000>;
39 }; 39 };
40 40
41 crmu_ref25m: crmu_ref25m { 41 crmu_ref25m: crmu_ref25m {
42 #clock-cells = <0>; 42 #clock-cells = <0>;
43 compatible = "fixed-fa 43 compatible = "fixed-factor-clock";
44 clocks = <&osc>; 44 clocks = <&osc>;
45 clock-div = <2>; 45 clock-div = <2>;
46 clock-mult = <1>; 46 clock-mult = <1>;
47 }; 47 };
48 48
49 genpll0: genpll0@1d104 { 49 genpll0: genpll0@1d104 {
50 #clock-cells = <1>; 50 #clock-cells = <1>;
51 compatible = "brcm,sr- 51 compatible = "brcm,sr-genpll0";
52 reg = <0x0001d104 0x32 52 reg = <0x0001d104 0x32>,
53 <0x0001c854 0x4> 53 <0x0001c854 0x4>;
54 clocks = <&osc>; 54 clocks = <&osc>;
55 clock-output-names = " 55 clock-output-names = "genpll0", "clk_125m", "clk_scr",
56 " 56 "clk_250", "clk_pcie_axi",
57 " 57 "clk_paxc_axi_x2",
58 " 58 "clk_paxc_axi";
59 }; 59 };
60 60
61 genpll2: genpll2@1d1ac { 61 genpll2: genpll2@1d1ac {
62 #clock-cells = <1>; 62 #clock-cells = <1>;
63 compatible = "brcm,sr- 63 compatible = "brcm,sr-genpll2";
64 reg = <0x0001d1ac 0x32 64 reg = <0x0001d1ac 0x32>,
65 <0x0001c854 0x4> 65 <0x0001c854 0x4>;
66 clocks = <&osc>; 66 clocks = <&osc>;
67 clock-output-names = " 67 clock-output-names = "genpll2", "clk_nic",
68 " 68 "clk_ts_500_ref", "clk_125_nitro",
69 " 69 "clk_chimp", "clk_nic_flash",
70 " 70 "clk_fs";
71 }; 71 };
72 72
73 genpll3: genpll3@1d1e0 { 73 genpll3: genpll3@1d1e0 {
74 #clock-cells = <1>; 74 #clock-cells = <1>;
75 compatible = "brcm,sr- 75 compatible = "brcm,sr-genpll3";
76 reg = <0x0001d1e0 0x32 76 reg = <0x0001d1e0 0x32>,
77 <0x0001c854 0x4> 77 <0x0001c854 0x4>;
78 clocks = <&osc>; 78 clocks = <&osc>;
79 clock-output-names = " 79 clock-output-names = "genpll3", "clk_hsls",
80 " 80 "clk_sdio";
81 }; 81 };
82 82
83 genpll4: genpll4@1d214 { 83 genpll4: genpll4@1d214 {
84 #clock-cells = <1>; 84 #clock-cells = <1>;
85 compatible = "brcm,sr- 85 compatible = "brcm,sr-genpll4";
86 reg = <0x0001d214 0x32 86 reg = <0x0001d214 0x32>,
87 <0x0001c854 0x4> 87 <0x0001c854 0x4>;
88 clocks = <&osc>; 88 clocks = <&osc>;
89 clock-output-names = " 89 clock-output-names = "genpll4", "clk_ccn",
90 " 90 "clk_tpiu_pll", "clk_noc",
91 " 91 "clk_chclk_fs4",
92 " 92 "clk_bridge_fscpu";
93 }; 93 };
94 94
95 genpll5: genpll5@1d248 { 95 genpll5: genpll5@1d248 {
96 #clock-cells = <1>; 96 #clock-cells = <1>;
97 compatible = "brcm,sr- 97 compatible = "brcm,sr-genpll5";
98 reg = <0x0001d248 0x32 98 reg = <0x0001d248 0x32>,
99 <0x0001c870 0x4> 99 <0x0001c870 0x4>;
100 clocks = <&osc>; 100 clocks = <&osc>;
101 clock-output-names = " 101 clock-output-names = "genpll5", "clk_fs4_hf",
102 " 102 "clk_crypto_ae", "clk_raid_ae";
103 }; 103 };
104 104
105 lcpll0: lcpll0@1d0c4 { 105 lcpll0: lcpll0@1d0c4 {
106 #clock-cells = <1>; 106 #clock-cells = <1>;
107 compatible = "brcm,sr- 107 compatible = "brcm,sr-lcpll0";
108 reg = <0x0001d0c4 0x3c 108 reg = <0x0001d0c4 0x3c>,
109 <0x0001c870 0x4> 109 <0x0001c870 0x4>;
110 clocks = <&osc>; 110 clocks = <&osc>;
111 clock-output-names = " 111 clock-output-names = "lcpll0", "clk_sata_refp",
112 " 112 "clk_sata_refn", "clk_sata_350",
113 " 113 "clk_sata_500";
114 }; 114 };
115 115
116 lcpll1: lcpll1@1d138 { 116 lcpll1: lcpll1@1d138 {
117 #clock-cells = <1>; 117 #clock-cells = <1>;
118 compatible = "brcm,sr- 118 compatible = "brcm,sr-lcpll1";
119 reg = <0x0001d138 0x3c 119 reg = <0x0001d138 0x3c>,
120 <0x0001c870 0x4> 120 <0x0001c870 0x4>;
121 clocks = <&osc>; 121 clocks = <&osc>;
122 clock-output-names = " 122 clock-output-names = "lcpll1", "clk_wan",
123 " 123 "clk_usb_ref",
124 " 124 "clk_crmu_ts";
125 }; 125 };
126 126
127 hsls_clk: hsls_clk { 127 hsls_clk: hsls_clk {
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 compatible = "fixed-fa 129 compatible = "fixed-factor-clock";
130 clocks = <&genpll3 1>; 130 clocks = <&genpll3 1>;
131 clock-div = <1>; 131 clock-div = <1>;
132 clock-mult = <1>; 132 clock-mult = <1>;
133 }; 133 };
134 134
135 hsls_div2_clk: hsls_div2_clk { 135 hsls_div2_clk: hsls_div2_clk {
136 #clock-cells = <0>; 136 #clock-cells = <0>;
137 compatible = "fixed-fa 137 compatible = "fixed-factor-clock";
138 clocks = <&genpll3 BCM 138 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
139 clock-div = <2>; 139 clock-div = <2>;
140 clock-mult = <1>; 140 clock-mult = <1>;
141 141
142 }; 142 };
143 143
144 hsls_div4_clk: hsls_div4_clk { 144 hsls_div4_clk: hsls_div4_clk {
145 #clock-cells = <0>; 145 #clock-cells = <0>;
146 compatible = "fixed-fa 146 compatible = "fixed-factor-clock";
147 clocks = <&genpll3 BCM 147 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
148 clock-div = <4>; 148 clock-div = <4>;
149 clock-mult = <1>; 149 clock-mult = <1>;
150 }; 150 };
151 151
152 hsls_25m_clk: hsls_25m_clk { 152 hsls_25m_clk: hsls_25m_clk {
153 #clock-cells = <0>; 153 #clock-cells = <0>;
154 compatible = "fixed-fa 154 compatible = "fixed-factor-clock";
155 clocks = <&crmu_ref25m 155 clocks = <&crmu_ref25m>;
156 clock-div = <1>; 156 clock-div = <1>;
157 clock-mult = <1>; 157 clock-mult = <1>;
158 }; 158 };
159 159
160 hsls_25m_div2_clk: hsls_25m_di 160 hsls_25m_div2_clk: hsls_25m_div2_clk {
161 #clock-cells = <0>; 161 #clock-cells = <0>;
162 compatible = "fixed-fa 162 compatible = "fixed-factor-clock";
163 clocks = <&hsls_25m_cl 163 clocks = <&hsls_25m_clk>;
164 clock-div = <2>; 164 clock-div = <2>;
165 clock-mult = <1>; 165 clock-mult = <1>;
166 }; 166 };
167 167
168 sdio0_clk: sdio0_clk { 168 sdio0_clk: sdio0_clk {
169 #clock-cells = <0>; 169 #clock-cells = <0>;
170 compatible = "fixed-fa 170 compatible = "fixed-factor-clock";
171 clocks = <&genpll3 BCM 171 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
172 clock-div = <1>; 172 clock-div = <1>;
173 clock-mult = <1>; 173 clock-mult = <1>;
174 }; 174 };
175 175
176 sdio1_clk: sdio1_clk { 176 sdio1_clk: sdio1_clk {
177 #clock-cells = <0>; 177 #clock-cells = <0>;
178 compatible = "fixed-fa 178 compatible = "fixed-factor-clock";
179 clocks = <&genpll3 BCM 179 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
180 clock-div = <1>; 180 clock-div = <1>;
181 clock-mult = <1>; 181 clock-mult = <1>;
182 }; 182 };
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