1 /* 1 /*
2 * BSD LICENSE 2 * BSD LICENSE
3 * 3 *
4 * Copyright(c) 2016-2017 Broadcom. All righ 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binar 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 9 *
10 * * Redistributions of source code must re 10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and th 11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must re 12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and th 13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materia 14 * the documentation and/or other materials provided with the
15 * distribution. 15 * distribution.
16 * * Neither the name of Broadcom nor the n 16 * * Neither the name of Broadcom nor the names of its
17 * contributors may be used to endorse or 17 * contributors may be used to endorse or promote products derived
18 * from this software without specific pr 18 * from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE P 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33 #include <dt-bindings/pinctrl/brcm,pinctrl-sti 33 #include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
34 34
35 pinconf: pinconf@140000 { 35 pinconf: pinconf@140000 {
36 compatible = "pinconf- 36 compatible = "pinconf-single";
37 reg = <0x00140000 0x25 37 reg = <0x00140000 0x250>;
38 pinctrl-single,registe 38 pinctrl-single,register-width = <32>;
39 39
40 /* pinconf functions * 40 /* pinconf functions */
41 }; 41 };
42 42
43 pinmux: pinmux@14029c { 43 pinmux: pinmux@14029c {
44 compatible = "pinctrl- 44 compatible = "pinctrl-single";
45 reg = <0x0014029c 0x26 45 reg = <0x0014029c 0x26c>;
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 pinctrl-single,registe 48 pinctrl-single,register-width = <32>;
49 pinctrl-single,functio 49 pinctrl-single,function-mask = <0xf>;
50 pinctrl-single,gpio-ra 50 pinctrl-single,gpio-range = <
51 &range 0 91 M 51 &range 0 91 MODE_GPIO
52 &range 95 60 M 52 &range 95 60 MODE_GPIO
53 >; 53 >;
54 range: gpio-range { 54 range: gpio-range {
55 #pinctrl-singl 55 #pinctrl-single,gpio-range-cells = <3>;
56 }; 56 };
57 57
58 /* pinctrl functions * 58 /* pinctrl functions */
59 tsio_pins: gpio-14-pin 59 tsio_pins: gpio-14-pins {
60 pinctrl-single 60 pinctrl-single,pins = <
61 0x038 61 0x038 MODE_NITRO /* tsio_0 */
62 0x03c 62 0x03c MODE_NITRO /* tsio_1 */
63 >; 63 >;
64 }; 64 };
65 65
66 nor_pins: pnor-adv-n-p 66 nor_pins: pnor-adv-n-pins {
67 pinctrl-single 67 pinctrl-single,pins = <
68 0x0ac 68 0x0ac MODE_PNOR /* nand_ce1_n */
69 0x0b0 69 0x0b0 MODE_PNOR /* nand_ce0_n */
70 0x0b4 70 0x0b4 MODE_PNOR /* nand_we_n */
71 0x0b8 71 0x0b8 MODE_PNOR /* nand_wp_n */
72 0x0bc 72 0x0bc MODE_PNOR /* nand_re_n */
73 0x0c0 73 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
74 0x0c4 74 0x0c4 MODE_PNOR /* nand_io0_0 */
75 0x0c8 75 0x0c8 MODE_PNOR /* nand_io1_0 */
76 0x0cc 76 0x0cc MODE_PNOR /* nand_io2_0 */
77 0x0d0 77 0x0d0 MODE_PNOR /* nand_io3_0 */
78 0x0d4 78 0x0d4 MODE_PNOR /* nand_io4_0 */
79 0x0d8 79 0x0d8 MODE_PNOR /* nand_io5_0 */
80 0x0dc 80 0x0dc MODE_PNOR /* nand_io6_0 */
81 0x0e0 81 0x0e0 MODE_PNOR /* nand_io7_0 */
82 0x0e4 82 0x0e4 MODE_PNOR /* nand_io8_0 */
83 0x0e8 83 0x0e8 MODE_PNOR /* nand_io9_0 */
84 0x0ec 84 0x0ec MODE_PNOR /* nand_io10_0 */
85 0x0f0 85 0x0f0 MODE_PNOR /* nand_io11_0 */
86 0x0f4 86 0x0f4 MODE_PNOR /* nand_io12_0 */
87 0x0f8 87 0x0f8 MODE_PNOR /* nand_io13_0 */
88 0x0fc 88 0x0fc MODE_PNOR /* nand_io14_0 */
89 0x100 89 0x100 MODE_PNOR /* nand_io15_0 */
90 0x104 90 0x104 MODE_PNOR /* nand_ale_0 */
91 0x108 91 0x108 MODE_PNOR /* nand_cle_0 */
92 0x040 92 0x040 MODE_PNOR /* pnor_adv_n */
93 0x044 93 0x044 MODE_PNOR /* pnor_baa_n */
94 0x048 94 0x048 MODE_PNOR /* pnor_bls_0_n */
95 0x04c 95 0x04c MODE_PNOR /* pnor_bls_1_n */
96 0x050 96 0x050 MODE_PNOR /* pnor_cre */
97 0x054 97 0x054 MODE_PNOR /* pnor_cs_2_n */
98 0x058 98 0x058 MODE_PNOR /* pnor_cs_1_n */
99 0x05c 99 0x05c MODE_PNOR /* pnor_cs_0_n */
100 0x060 100 0x060 MODE_PNOR /* pnor_we_n */
101 0x064 101 0x064 MODE_PNOR /* pnor_oe_n */
102 0x068 102 0x068 MODE_PNOR /* pnor_intr */
103 0x06c 103 0x06c MODE_PNOR /* pnor_dat_0 */
104 0x070 104 0x070 MODE_PNOR /* pnor_dat_1 */
105 0x074 105 0x074 MODE_PNOR /* pnor_dat_2 */
106 0x078 106 0x078 MODE_PNOR /* pnor_dat_3 */
107 0x07c 107 0x07c MODE_PNOR /* pnor_dat_4 */
108 0x080 108 0x080 MODE_PNOR /* pnor_dat_5 */
109 0x084 109 0x084 MODE_PNOR /* pnor_dat_6 */
110 0x088 110 0x088 MODE_PNOR /* pnor_dat_7 */
111 0x08c 111 0x08c MODE_PNOR /* pnor_dat_8 */
112 0x090 112 0x090 MODE_PNOR /* pnor_dat_9 */
113 0x094 113 0x094 MODE_PNOR /* pnor_dat_10 */
114 0x098 114 0x098 MODE_PNOR /* pnor_dat_11 */
115 0x09c 115 0x09c MODE_PNOR /* pnor_dat_12 */
116 0x0a0 116 0x0a0 MODE_PNOR /* pnor_dat_13 */
117 0x0a4 117 0x0a4 MODE_PNOR /* pnor_dat_14 */
118 0x0a8 118 0x0a8 MODE_PNOR /* pnor_dat_15 */
119 >; 119 >;
120 }; 120 };
121 121
122 nand_pins: nand-ce1-n- 122 nand_pins: nand-ce1-n-pins {
123 pinctrl-single 123 pinctrl-single,pins = <
124 0x0ac 124 0x0ac MODE_NAND /* nand_ce1_n */
125 0x0b0 125 0x0b0 MODE_NAND /* nand_ce0_n */
126 0x0b4 126 0x0b4 MODE_NAND /* nand_we_n */
127 0x0b8 127 0x0b8 MODE_NAND /* nand_wp_n */
128 0x0bc 128 0x0bc MODE_NAND /* nand_re_n */
129 0x0c0 129 0x0c0 MODE_NAND /* nand_rdy_bsy_n */
130 0x0c4 130 0x0c4 MODE_NAND /* nand_io0_0 */
131 0x0c8 131 0x0c8 MODE_NAND /* nand_io1_0 */
132 0x0cc 132 0x0cc MODE_NAND /* nand_io2_0 */
133 0x0d0 133 0x0d0 MODE_NAND /* nand_io3_0 */
134 0x0d4 134 0x0d4 MODE_NAND /* nand_io4_0 */
135 0x0d8 135 0x0d8 MODE_NAND /* nand_io5_0 */
136 0x0dc 136 0x0dc MODE_NAND /* nand_io6_0 */
137 0x0e0 137 0x0e0 MODE_NAND /* nand_io7_0 */
138 0x0e4 138 0x0e4 MODE_NAND /* nand_io8_0 */
139 0x0e8 139 0x0e8 MODE_NAND /* nand_io9_0 */
140 0x0ec 140 0x0ec MODE_NAND /* nand_io10_0 */
141 0x0f0 141 0x0f0 MODE_NAND /* nand_io11_0 */
142 0x0f4 142 0x0f4 MODE_NAND /* nand_io12_0 */
143 0x0f8 143 0x0f8 MODE_NAND /* nand_io13_0 */
144 0x0fc 144 0x0fc MODE_NAND /* nand_io14_0 */
145 0x100 145 0x100 MODE_NAND /* nand_io15_0 */
146 0x104 146 0x104 MODE_NAND /* nand_ale_0 */
147 0x108 147 0x108 MODE_NAND /* nand_cle_0 */
148 >; 148 >;
149 }; 149 };
150 150
151 pwm0_pins: pwm-0-pins 151 pwm0_pins: pwm-0-pins {
152 pinctrl-single 152 pinctrl-single,pins = <
153 0x10c 153 0x10c MODE_NITRO
154 >; 154 >;
155 }; 155 };
156 156
157 pwm1_pins: pwm-1-pins 157 pwm1_pins: pwm-1-pins {
158 pinctrl-single 158 pinctrl-single,pins = <
159 0x110 159 0x110 MODE_NITRO
160 >; 160 >;
161 }; 161 };
162 162
163 pwm2_pins: pwm-2-pins 163 pwm2_pins: pwm-2-pins {
164 pinctrl-single 164 pinctrl-single,pins = <
165 0x114 165 0x114 MODE_NITRO
166 >; 166 >;
167 }; 167 };
168 168
169 pwm3_pins: pwm-3-pins 169 pwm3_pins: pwm-3-pins {
170 pinctrl-single 170 pinctrl-single,pins = <
171 0x118 171 0x118 MODE_NITRO
172 >; 172 >;
173 }; 173 };
174 174
175 dbu_rxd_pins: uart1-si 175 dbu_rxd_pins: uart1-sin-nitro-pins {
176 pinctrl-single 176 pinctrl-single,pins = <
177 0x11c 177 0x11c MODE_NITRO /* dbu_rxd */
178 0x120 178 0x120 MODE_NITRO /* dbu_txd */
179 >; 179 >;
180 }; 180 };
181 181
182 uart1_pins: uart1-sin- 182 uart1_pins: uart1-sin-nand-pins {
183 pinctrl-single 183 pinctrl-single,pins = <
184 0x11c 184 0x11c MODE_NAND /* uart1_sin */
185 0x120 185 0x120 MODE_NAND /* uart1_out */
186 >; 186 >;
187 }; 187 };
188 188
189 uart2_pins: uart2-sin- 189 uart2_pins: uart2-sin-pins {
190 pinctrl-single 190 pinctrl-single,pins = <
191 0x124 191 0x124 MODE_NITRO /* uart2_sin */
192 0x128 192 0x128 MODE_NITRO /* uart2_out */
193 >; 193 >;
194 }; 194 };
195 195
196 uart3_pins: uart3-sin- 196 uart3_pins: uart3-sin-pins {
197 pinctrl-single 197 pinctrl-single,pins = <
198 0x12c 198 0x12c MODE_NITRO /* uart3_sin */
199 0x130 199 0x130 MODE_NITRO /* uart3_out */
200 >; 200 >;
201 }; 201 };
202 202
203 i2s_pins: i2s-bitclk-p 203 i2s_pins: i2s-bitclk-pins {
204 pinctrl-single 204 pinctrl-single,pins = <
205 0x134 205 0x134 MODE_NITRO /* i2s_bitclk */
206 0x138 206 0x138 MODE_NITRO /* i2s_sdout */
207 0x13c 207 0x13c MODE_NITRO /* i2s_sdin */
208 0x140 208 0x140 MODE_NITRO /* i2s_ws */
209 0x144 209 0x144 MODE_NITRO /* i2s_mclk */
210 0x148 210 0x148 MODE_NITRO /* i2s_spdif_out */
211 >; 211 >;
212 }; 212 };
213 213
214 qspi_pins: qspi-hold-n 214 qspi_pins: qspi-hold-n-pins {
215 pinctrl-single 215 pinctrl-single,pins = <
216 0x14c 216 0x14c MODE_NAND /* qspi_hold_n */
217 0x150 217 0x150 MODE_NAND /* qspi_wp_n */
218 0x154 218 0x154 MODE_NAND /* qspi_sck */
219 0x158 219 0x158 MODE_NAND /* qspi_cs_n */
220 0x15c 220 0x15c MODE_NAND /* qspi_mosi */
221 0x160 221 0x160 MODE_NAND /* qspi_miso */
222 >; 222 >;
223 }; 223 };
224 224
225 mdio_pins: ext-mdio-pi 225 mdio_pins: ext-mdio-pins {
226 pinctrl-single 226 pinctrl-single,pins = <
227 0x164 227 0x164 MODE_NITRO /* ext_mdio */
228 0x168 228 0x168 MODE_NITRO /* ext_mdc */
229 >; 229 >;
230 }; 230 };
231 231
232 i2c0_pins: i2c0-sda-pi 232 i2c0_pins: i2c0-sda-pins {
233 pinctrl-single 233 pinctrl-single,pins = <
234 0x16c 234 0x16c MODE_NITRO /* i2c0_sda */
235 0x170 235 0x170 MODE_NITRO /* i2c0_scl */
236 >; 236 >;
237 }; 237 };
238 238
239 i2c1_pins: i2c1-sda-pi 239 i2c1_pins: i2c1-sda-pins {
240 pinctrl-single 240 pinctrl-single,pins = <
241 0x174 241 0x174 MODE_NITRO /* i2c1_sda */
242 0x178 242 0x178 MODE_NITRO /* i2c1_scl */
243 >; 243 >;
244 }; 244 };
245 245
246 sdio0_pins: sdio0-cd-l 246 sdio0_pins: sdio0-cd-l-pins {
247 pinctrl-single 247 pinctrl-single,pins = <
248 0x17c 248 0x17c MODE_NITRO /* sdio0_cd_l */
249 0x180 249 0x180 MODE_NITRO /* sdio0_clk_sdcard */
250 0x184 250 0x184 MODE_NITRO /* sdio0_data0 */
251 0x188 251 0x188 MODE_NITRO /* sdio0_data1 */
252 0x18c 252 0x18c MODE_NITRO /* sdio0_data2 */
253 0x190 253 0x190 MODE_NITRO /* sdio0_data3 */
254 0x194 254 0x194 MODE_NITRO /* sdio0_data4 */
255 0x198 255 0x198 MODE_NITRO /* sdio0_data5 */
256 0x19c 256 0x19c MODE_NITRO /* sdio0_data6 */
257 0x1a0 257 0x1a0 MODE_NITRO /* sdio0_data7 */
258 0x1a4 258 0x1a4 MODE_NITRO /* sdio0_cmd */
259 0x1a8 259 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
260 0x1ac 260 0x1ac MODE_NITRO /* sdio0_led_on */
261 0x1b0 261 0x1b0 MODE_NITRO /* sdio0_wp */
262 >; 262 >;
263 }; 263 };
264 264
265 sdio1_pins: sdio1-cd-l 265 sdio1_pins: sdio1-cd-l-pins {
266 pinctrl-single 266 pinctrl-single,pins = <
267 0x1b4 267 0x1b4 MODE_NITRO /* sdio1_cd_l */
268 0x1b8 268 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
269 0x1bc 269 0x1bc MODE_NITRO /* sdio1_data0 */
270 0x1c0 270 0x1c0 MODE_NITRO /* sdio1_data1 */
271 0x1c4 271 0x1c4 MODE_NITRO /* sdio1_data2 */
272 0x1c8 272 0x1c8 MODE_NITRO /* sdio1_data3 */
273 0x1cc 273 0x1cc MODE_NITRO /* sdio1_data4 */
274 0x1d0 274 0x1d0 MODE_NITRO /* sdio1_data5 */
275 0x1d4 275 0x1d4 MODE_NITRO /* sdio1_data6 */
276 0x1d8 276 0x1d8 MODE_NITRO /* sdio1_data7 */
277 0x1dc 277 0x1dc MODE_NITRO /* sdio1_cmd */
278 0x1e0 278 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
279 0x1e4 279 0x1e4 MODE_NITRO /* sdio1_led_on */
280 0x1e8 280 0x1e8 MODE_NITRO /* sdio1_wp */
281 >; 281 >;
282 }; 282 };
283 283
284 spi0_pins: spi0-sck-na 284 spi0_pins: spi0-sck-nand-pins {
285 pinctrl-single 285 pinctrl-single,pins = <
286 0x1ec 286 0x1ec MODE_NITRO /* spi0_sck */
287 0x1f0 287 0x1f0 MODE_NITRO /* spi0_rxd */
288 0x1f4 288 0x1f4 MODE_NITRO /* spi0_fss */
289 0x1f8 289 0x1f8 MODE_NITRO /* spi0_txd */
290 >; 290 >;
291 }; 291 };
292 292
293 spi1_pins: spi1-sck-na 293 spi1_pins: spi1-sck-nand-pins {
294 pinctrl-single 294 pinctrl-single,pins = <
295 0x1fc 295 0x1fc MODE_NITRO /* spi1_sck */
296 0x200 296 0x200 MODE_NITRO /* spi1_rxd */
297 0x204 297 0x204 MODE_NITRO /* spi1_fss */
298 0x208 298 0x208 MODE_NITRO /* spi1_txd */
299 >; 299 >;
300 }; 300 };
301 301
302 nuart_pins: uart0-sin- 302 nuart_pins: uart0-sin-nitro-pins {
303 pinctrl-single 303 pinctrl-single,pins = <
304 0x20c 304 0x20c MODE_NITRO /* nuart_rxd */
305 0x210 305 0x210 MODE_NITRO /* nuart_txd */
306 >; 306 >;
307 }; 307 };
308 308
309 uart0_pins: uart0-sin- 309 uart0_pins: uart0-sin-nand-pins {
310 pinctrl-single 310 pinctrl-single,pins = <
311 0x20c 311 0x20c MODE_NAND /* uart0_sin */
312 0x210 312 0x210 MODE_NAND /* uart0_out */
313 0x214 313 0x214 MODE_NAND /* uart0_rts */
314 0x218 314 0x218 MODE_NAND /* uart0_cts */
315 0x21c 315 0x21c MODE_NAND /* uart0_dtr */
316 0x220 316 0x220 MODE_NAND /* uart0_dcd */
317 0x224 317 0x224 MODE_NAND /* uart0_dsr */
318 0x228 318 0x228 MODE_NAND /* uart0_ri */
319 >; 319 >;
320 }; 320 };
321 321
322 drdu2_pins: drdu2-over 322 drdu2_pins: drdu2-overcurrent-pins {
323 pinctrl-single 323 pinctrl-single,pins = <
324 0x22c 324 0x22c MODE_NITRO /* drdu2_overcurrent */
325 0x230 325 0x230 MODE_NITRO /* drdu2_vbus_ppc */
326 0x234 326 0x234 MODE_NITRO /* drdu2_vbus_present */
327 0x238 327 0x238 MODE_NITRO /* drdu2_id */
328 >; 328 >;
329 }; 329 };
330 330
331 drdu3_pins: drdu3-over 331 drdu3_pins: drdu3-overcurrent-pins {
332 pinctrl-single 332 pinctrl-single,pins = <
333 0x23c 333 0x23c MODE_NITRO /* drdu3_overcurrent */
334 0x240 334 0x240 MODE_NITRO /* drdu3_vbus_ppc */
335 0x244 335 0x244 MODE_NITRO /* drdu3_vbus_present */
336 0x248 336 0x248 MODE_NITRO /* drdu3_id */
337 >; 337 >;
338 }; 338 };
339 339
340 usb3h_pins: usb3h-over 340 usb3h_pins: usb3h-overcurrent-pins {
341 pinctrl-single 341 pinctrl-single,pins = <
342 0x24c 342 0x24c MODE_NITRO /* usb3h_overcurrent */
343 0x250 343 0x250 MODE_NITRO /* usb3h_vbus_ppc */
344 >; 344 >;
345 }; 345 };
346 }; 346 };
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