1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung Exynos5433 TM2 board device tree so
4 *
5 * Copyright (c) 2016 Samsung Electronics Co.,
6 *
7 * Common device tree source file for Samsung'
8 * which are based on Samsung Exynos5433 SoC.
9 */
10
11 /dts-v1/;
12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq
17 #include <dt-bindings/sound/samsung-i2s.h>
18
19 / {
20 aliases {
21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0;
25 mmc2 = &mshc_2;
26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0;
37 serial1 = &serial_1;
38 serial2 = &serial_2;
39 serial3 = &serial_3;
40 spi0 = &spi_0;
41 spi1 = &spi_1;
42 spi2 = &spi_2;
43 spi3 = &spi_3;
44 spi4 = &spi_4;
45 };
46
47 chosen {
48 stdout-path = &serial_1;
49 };
50
51 memory@20000000 {
52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0
54 };
55
56 gpio-keys {
57 compatible = "gpio-keys";
58
59 power-key {
60 gpios = <&gpa2 7 GPIO_
61 linux,code = <KEY_POWE
62 label = "power key";
63 debounce-interval = <1
64 };
65
66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_
68 linux,code = <KEY_VOLU
69 label = "volume-up key
70 debounce-interval = <1
71 };
72
73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_
75 linux,code = <KEY_VOLU
76 label = "volume-down k
77 debounce-interval = <1
78 };
79
80 homepage-key {
81 gpios = <&gpa0 3 GPIO_
82 linux,code = <KEY_MENU
83 label = "homepage key"
84 debounce-interval = <1
85 };
86 };
87
88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI
91 scl-gpios = <&gpd0 0 GPIO_ACTI
92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 max98504: amplifier@31 {
97 compatible = "maxim,ma
98 reg = <0x31>;
99
100 DIOVDD-supply = <&ldo3
101 DVDD-supply = <&ldo3_r
102 PVDD-supply = <&vph_pw
103 };
104 };
105
106 vph_pwr_regulator: regulator-vph-pwr {
107 compatible = "regulator-fixed"
108 regulator-name = "VPH_PWR";
109 regulator-min-microvolt = <420
110 regulator-max-microvolt = <420
111 };
112
113 irda_regulator: regulator-irda {
114 compatible = "regulator-fixed"
115 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI
117 regulator-name = "irda_regulat
118 };
119
120 sound {
121 compatible = "samsung,tm2-audi
122 audio-codec = <&wm5110>, <&hdm
123 i2s-controller = <&i2s0 0>, <&
124 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO
126 model = "wm5110";
127 audio-routing = /* Headphone *
128 "HP", "HPOUT1L
129 "HP", "HPOUT1R
130
131 /* Speaker */
132 "SPK", "SPKOUT
133 "SPKOUT", "HPO
134 "SPKOUT", "HPO
135
136 /* Receiver */
137 "RCV", "HPOUT3
138 "RCV", "HPOUT3
139 };
140 };
141
142 &adc {
143 vdd-supply = <&ldo3_reg>;
144 status = "okay";
145
146 thermistor-ap {
147 compatible = "murata,ncp03wf10
148 pullup-uv = <1800000>;
149 pullup-ohm = <100000>;
150 pulldown-ohm = <0>;
151 io-channels = <&adc 0>;
152 };
153
154 thermistor-battery {
155 compatible = "murata,ncp03wf10
156 pullup-uv = <1800000>;
157 pullup-ohm = <100000>;
158 pulldown-ohm = <0>;
159 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>;
161 };
162
163 thermistor-charger {
164 compatible = "murata,ncp03wf10
165 pullup-uv = <1800000>;
166 pullup-ohm = <100000>;
167 pulldown-ohm = <0>;
168 io-channels = <&adc 2>;
169 };
170 };
171
172 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene
174 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>;
176 status = "okay";
177 };
178
179 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>;
181 status = "okay";
182 };
183
184 &bus_gscl {
185 devfreq = <&bus_g2d_400>;
186 status = "okay";
187 };
188
189 &bus_hevc {
190 devfreq = <&bus_g2d_400>;
191 status = "okay";
192 };
193
194 &bus_jpeg {
195 devfreq = <&bus_g2d_400>;
196 status = "okay";
197 };
198
199 &bus_mfc {
200 devfreq = <&bus_g2d_400>;
201 status = "okay";
202 };
203
204 &bus_mscl {
205 devfreq = <&bus_g2d_400>;
206 status = "okay";
207 };
208
209 &bus_noc0 {
210 devfreq = <&bus_g2d_400>;
211 status = "okay";
212 };
213
214 &bus_noc1 {
215 devfreq = <&bus_g2d_400>;
216 status = "okay";
217 };
218
219 &bus_noc2 {
220 devfreq = <&bus_g2d_400>;
221 status = "okay";
222 };
223
224 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC
228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1
232 <&cmu_top CLK_MOUT_SCLK_SPDIF>
233
234 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR
241 <&cmu_top CLK_DIV_SCLK_AUDIO0>
242 <&cmu_top CLK_DIV_SCLK_AUDIO1>
243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>;
245
246 assigned-clock-parents = <&cmu_top CLK
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE
249 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE
252 <&cmu_top CLK_MOUT_AUD_PLL_USE
253 <&cmu_top CLK_SCLK_AUDIO0>;
254
255 assigned-clock-rates = <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276
257 <2048001>, <24576001>, <196608
258 <24576001>, <98304001>, <20480
259 };
260
261 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S
263 <&cmu_top CLK_MOUT_SCLK_USBHOS
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB
270 <&cmu_top CLK_DIV_SCLK_USBDRD3
271 <&cmu_top CLK_DIV_SCLK_USBHOST
272 assigned-clock-parents = <&cmu_top CLK
273 <&cmu_top CLK_MOUT_BUS_PLL_USE
274 <&cmu_top CLK_SCLK_USBDRD30_FS
275 <&cmu_top CLK_SCLK_USBHOST30_F
276 <&cmu_fsys CLK_PHYCLK_USBDRD30
277 <&cmu_fsys CLK_PHYCLK_USBHOST3
278 <&cmu_fsys CLK_PHYCLK_USBDRD30
279 <&cmu_fsys CLK_PHYCLK_USBHOST3
280 assigned-clock-rates = <0>, <0>, <0>,
281 <66700000>, <66
282 };
283
284 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_
286 <&cmu_gscl CLK_MOUT_
287 assigned-clock-parents = <&cmu_top CLK
288 <&cmu_top CLK
289 };
290
291 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A
293 assigned-clock-parents = <&cmu_top CLK
294 };
295
296 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S
298 assigned-clock-parents = <&cmu_mif CLK
299 assigned-clock-rates = <0>, <333000000
300 };
301
302 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_
304 <&cmu_mscl CLK_MOUT_
305 <&cmu_mscl CLK_MOUT_
306 <&cmu_top CLK_MOUT_S
307 assigned-clock-parents = <&cmu_top CLK
308 <&cmu_top CLK
309 <&cmu_mscl CL
310 <&cmu_top CLK
311 };
312
313 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A
315 assigned-clock-rates = <196608001>;
316 };
317
318 &cpu0 {
319 cpu-supply = <&buck3_reg>;
320 };
321
322 &cpu4 {
323 cpu-supply = <&buck2_reg>;
324 };
325
326 &decon {
327 status = "okay";
328 };
329
330 &decon_tv {
331 status = "okay";
332
333 ports {
334 #address-cells = <1>;
335 #size-cells = <0>;
336
337 port@0 {
338 reg = <0>;
339 tv_to_hdmi: endpoint {
340 remote-endpoin
341 };
342 };
343 };
344 };
345
346 &dsi {
347 status = "okay";
348 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200
351 samsung,esc-clock-frequency = <1600000
352 samsung,pll-clock-frequency = <2400000
353 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>;
355 };
356
357 &gpu {
358 mali-supply = <&buck6_reg>;
359 status = "okay";
360 };
361
362 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>
364 status = "okay";
365 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>;
368
369 ports {
370 #address-cells = <1>;
371 #size-cells = <0>;
372
373 port@0 {
374 reg = <0>;
375 hdmi_to_tv: endpoint {
376 remote-endpoin
377 };
378 };
379
380 port@1 {
381 reg = <1>;
382 hdmi_to_mhl: endpoint
383 remote-endpoin
384 };
385 };
386 };
387 };
388
389 &hsi2c_0 {
390 status = "okay";
391 clock-frequency = <2500000>;
392
393 pmic@66 {
394 compatible = "samsung,s2mps13-
395 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL
397 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground;
399 wakeup-source;
400
401 s2mps13_osc: clocks {
402 compatible = "samsung,
403 #clock-cells = <1>;
404 clock-output-names = "
405 "s2mps13_bt";
406 };
407
408 regulators {
409 ldo1_reg: LDO1 {
410 regulator-name
411 regulator-min-
412 regulator-max-
413 regulator-alwa
414 };
415
416 ldo2_reg: LDO2 {
417 regulator-name
418 regulator-min-
419 regulator-max-
420 regulator-alwa
421 regulator-stat
422 regula
423 };
424 };
425
426 ldo3_reg: LDO3 {
427 regulator-name
428 regulator-min-
429 regulator-max-
430 regulator-alwa
431 };
432
433 ldo4_reg: LDO4 {
434 regulator-name
435 regulator-min-
436 regulator-max-
437 regulator-alwa
438 regulator-stat
439 regula
440 };
441 };
442
443 ldo5_reg: LDO5 {
444 regulator-name
445 regulator-min-
446 regulator-max-
447 regulator-alwa
448 regulator-stat
449 regula
450 };
451 };
452
453 ldo6_reg: LDO6 {
454 regulator-name
455 regulator-min-
456 regulator-max-
457 regulator-stat
458 regula
459 };
460 };
461
462 ldo7_reg: LDO7 {
463 regulator-name
464 regulator-min-
465 regulator-max-
466 regulator-alwa
467 regulator-stat
468 regula
469 };
470 };
471
472 ldo8_reg: LDO8 {
473 regulator-name
474 regulator-min-
475 regulator-max-
476 regulator-alwa
477 regulator-stat
478 regula
479 };
480 };
481
482 ldo9_reg: LDO9 {
483 regulator-name
484 regulator-min-
485 regulator-max-
486 regulator-alwa
487 regulator-stat
488 regula
489 };
490 };
491
492 ldo10_reg: LDO10 {
493 regulator-name
494 regulator-min-
495 regulator-max-
496 regulator-stat
497 regula
498 };
499 };
500
501 ldo11_reg: LDO11 {
502 regulator-name
503 regulator-min-
504 regulator-max-
505 regulator-alwa
506 regulator-stat
507 regula
508 };
509 };
510
511 ldo12_reg: LDO12 {
512 regulator-name
513 regulator-min-
514 regulator-max-
515 regulator-alwa
516 };
517
518 ldo13_reg: LDO13 {
519 regulator-name
520 regulator-min-
521 regulator-max-
522 regulator-alwa
523 regulator-stat
524 regula
525 };
526 };
527
528 ldo14_reg: LDO14 {
529 regulator-name
530 regulator-min-
531 regulator-max-
532 regulator-alwa
533 regulator-stat
534 regula
535 };
536 };
537
538 ldo15_reg: LDO15 {
539 regulator-name
540 regulator-min-
541 regulator-max-
542 regulator-alwa
543 regulator-stat
544 regula
545 };
546 };
547
548 ldo16_reg: LDO16 {
549 regulator-name
550 regulator-min-
551 regulator-max-
552 regulator-alwa
553 };
554
555 ldo17_reg: LDO17 {
556 regulator-name
557 regulator-min-
558 regulator-max-
559 };
560
561 ldo18_reg: LDO18 {
562 regulator-name
563 regulator-min-
564 regulator-max-
565 };
566
567 ldo19_reg: LDO19 {
568 regulator-name
569 regulator-min-
570 regulator-max-
571 regulator-alwa
572 };
573
574 ldo20_reg: LDO20 {
575 regulator-name
576 regulator-min-
577 regulator-max-
578 regulator-alwa
579 };
580
581 ldo21_reg: LDO21 {
582 regulator-name
583 regulator-min-
584 regulator-max-
585 };
586
587 ldo22_reg: LDO22 {
588 regulator-name
589 regulator-min-
590 regulator-max-
591 };
592
593 ldo23_reg: LDO23 {
594 regulator-name
595 regulator-min-
596 regulator-max-
597 };
598
599 ldo24_reg: LDO24 {
600 regulator-name
601 regulator-min-
602 regulator-max-
603 };
604
605 ldo25_reg: LDO25 {
606 regulator-name
607 regulator-min-
608 regulator-max-
609 };
610
611 ldo26_reg: LDO26 {
612 regulator-name
613 regulator-min-
614 regulator-max-
615 };
616
617 ldo27_reg: LDO27 {
618 regulator-name
619 regulator-min-
620 regulator-max-
621 };
622
623 ldo28_reg: LDO28 {
624 regulator-name
625 regulator-min-
626 regulator-max-
627 };
628
629 ldo29_reg: LDO29 {
630 regulator-name
631 regulator-min-
632 regulator-max-
633 };
634
635 ldo30_reg: LDO30 {
636 regulator-name
637 regulator-min-
638 regulator-max-
639 };
640
641 ldo31_reg: LDO31 {
642 /*
643 * LDO31 diffe
644 * its definit
645 */
646 };
647
648 ldo32_reg: LDO32 {
649 regulator-name
650 regulator-min-
651 regulator-max-
652 };
653
654 ldo33_reg: LDO33 {
655 regulator-name
656 regulator-min-
657 regulator-max-
658 regulator-ramp
659 };
660
661 ldo34_reg: LDO34 {
662 regulator-name
663 regulator-min-
664 regulator-max-
665 };
666
667 ldo35_reg: LDO35 {
668 regulator-name
669 regulator-min-
670 regulator-max-
671 };
672
673 ldo36_reg: LDO36 {
674 regulator-name
675 regulator-min-
676 regulator-max-
677 };
678
679 ldo37_reg: LDO37 {
680 regulator-name
681 regulator-min-
682 regulator-max-
683 };
684
685 ldo38_reg: LDO38 {
686 /*
687 * LDO38 diffe
688 * its definit
689 */
690 };
691
692 ldo39_reg: LDO39 {
693 regulator-name
694 regulator-min-
695 regulator-max-
696 };
697
698 ldo40_reg: LDO40 {
699 regulator-name
700 regulator-min-
701 regulator-max-
702 };
703
704 buck1_reg: BUCK1 {
705 regulator-name
706 regulator-min-
707 regulator-max-
708 regulator-alwa
709 regulator-stat
710 regula
711 };
712 };
713
714 buck2_reg: BUCK2 {
715 regulator-name
716 regulator-min-
717 regulator-max-
718 regulator-alwa
719 regulator-stat
720 regula
721 };
722 };
723
724 buck3_reg: BUCK3 {
725 regulator-name
726 regulator-min-
727 regulator-max-
728 regulator-alwa
729 regulator-stat
730 regula
731 };
732 };
733
734 buck4_reg: BUCK4 {
735 regulator-name
736 regulator-min-
737 regulator-max-
738 regulator-alwa
739 regulator-stat
740 regula
741 };
742 };
743
744 buck5_reg: BUCK5 {
745 regulator-name
746 regulator-min-
747 regulator-max-
748 regulator-alwa
749 regulator-stat
750 regula
751 };
752 };
753
754 buck6_reg: BUCK6 {
755 regulator-name
756 regulator-min-
757 regulator-max-
758 regulator-alwa
759 regulator-stat
760 regula
761 };
762 };
763
764 buck7_reg: BUCK7 {
765 regulator-name
766 regulator-min-
767 regulator-max-
768 regulator-alwa
769 };
770
771 buck8_reg: BUCK8 {
772 regulator-name
773 regulator-min-
774 regulator-max-
775 regulator-alwa
776 };
777
778 buck9_reg: BUCK9 {
779 regulator-name
780 regulator-min-
781 regulator-max-
782 regulator-alwa
783 };
784
785 buck10_reg: BUCK10 {
786 regulator-name
787 regulator-min-
788 regulator-max-
789 regulator-alwa
790 };
791 };
792 };
793 };
794
795 &hsi2c_4 {
796 status = "okay";
797
798 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5-
800 reg = <0x27>;
801 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_
803 en-gpios = <&gpf1 4 GPIO_ACTIV
804 wake-gpios = <&gpj0 2 GPIO_ACT
805 };
806 };
807
808 &hsi2c_5 {
809 status = "okay";
810
811 stmfts: touchscreen@49 {
812 compatible = "st,stmfts";
813 reg = <0x49>;
814 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL
816 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>;
818 };
819 };
820
821 &hsi2c_7 {
822 status = "okay";
823 clock-frequency = <1000000>;
824
825 bridge@39 {
826 reg = <0x39>;
827 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL
832 reset-gpios = <&gpv7 0 GPIO_AC
833 clocks = <&pmu_system_controll
834 clock-names = "xtal";
835
836 ports {
837 #address-cells = <1>;
838 #size-cells = <0>;
839
840 port@0 {
841 reg = <0>;
842 mhl_to_hdmi: e
843 remote
844 };
845 };
846
847 port@1 {
848 reg = <1>;
849 mhl_to_musb_co
850 remote
851 };
852 };
853 };
854 };
855 };
856
857 &hsi2c_8 {
858 status = "okay";
859
860 pmic@66 {
861 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_
864 reg = <0x66>;
865
866 muic: extcon {
867 compatible = "maxim,ma
868
869 musb_con: connector {
870 compatible = "
871 "
872 label = "micro
873 type = "micro"
874
875 ports {
876 #addre
877 #size-
878
879 port@0
880
881
882
883
884
885
886
887
888 };
889
890 port@3
891
892
893
894
895 };
896 };
897 };
898
899 ports {
900 port {
901 muic_t
902
903 };
904 };
905 };
906 };
907
908 regulators {
909 compatible = "maxim,ma
910 safeout1_reg: SAFEOUT1
911 regulator-name
912 regulator-min-
913 regulator-max-
914 };
915
916 safeout2_reg: SAFEOUT2
917 regulator-name
918 regulator-min-
919 regulator-max-
920 };
921
922 charger_reg: CHARGER {
923 regulator-name
924 regulator-min-
925 regulator-max-
926 };
927 };
928
929 haptic: motor-driver {
930 compatible = "maxim,ma
931 haptic-supply = <&ldo3
932 pwms = <&pwm 0 33670 0
933 };
934 };
935 };
936
937 &hsi2c_11 {
938 status = "okay";
939 };
940
941 &i2s0 {
942 status = "okay";
943 };
944
945 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_
947 assigned-clock-parents = <&cmu_peric C
948 status = "okay";
949 };
950
951 &mshc_0 {
952 status = "okay";
953 mmc-ddr-1_8v;
954 mmc-hs200-1_8v;
955 mmc-hs400-1_8v;
956 cap-mmc-highspeed;
957 non-removable;
958 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr
967 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M
970 assigned-clock-rates = <800000000>;
971 };
972
973 &mshc_2 {
974 status = "okay";
975 cap-sd-highspeed;
976 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu
985 bus-width = <4>;
986 };
987
988 &pcie {
989 status = "okay";
990 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_
995 <&cmu_top CLK_MOUT_S
996 assigned-clock-parents = <&cmu_top CLK
997 <&cmu_top CLK
998 assigned-clock-rates = <0>, <100000000
999 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI
1001 };
1002
1003 &pcie_phy {
1004 status = "okay";
1005 };
1006
1007 &ppmu_d0_general {
1008 status = "okay";
1009 events {
1010 ppmu_event0_d0_general: ppmu-
1011 event-name = "ppmu-ev
1012 };
1013 };
1014 };
1015
1016 &ppmu_d1_general {
1017 status = "okay";
1018 events {
1019 ppmu_event0_d1_general: ppmu-
1020 event-name = "ppmu-eve
1021 };
1022 };
1023 };
1024
1025 &pinctrl_alive {
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>;
1028
1029 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1
1031 PIN_IN(gpa0-1, NONE, FAST_SR1
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1
1033 PIN_IN(gpa0-3, NONE, FAST_SR1
1034 PIN_IN(gpa0-4, NONE, FAST_SR1
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1
1036 PIN_IN(gpa0-6, NONE, FAST_SR1
1037 PIN_IN(gpa0-7, NONE, FAST_SR1
1038
1039 PIN_IN(gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1
1044 PIN_IN(gpa1-5, NONE, FAST_SR1
1045 PIN_IN(gpa1-6, NONE, FAST_SR1
1046 PIN_IN(gpa1-7, NONE, FAST_SR1
1047
1048 PIN_IN(gpa2-0, NONE, FAST_SR1
1049 PIN_IN(gpa2-1, NONE, FAST_SR1
1050 PIN_IN(gpa2-2, NONE, FAST_SR1
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1
1052 PIN_IN(gpa2-4, NONE, FAST_SR1
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1
1055 PIN_IN(gpa2-7, NONE, FAST_SR1
1056
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1
1059 PIN_IN(gpa3-2, NONE, FAST_SR1
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1
1061 PIN_IN(gpa3-4, NONE, FAST_SR1
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1
1065
1066 PIN_IN(gpf1-0, NONE, FAST_SR1
1067 PIN_IN(gpf1-1, NONE, FAST_SR1
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1
1069 PIN_IN(gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1
1073
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1
1078
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1
1081 PIN_IN(gpf3-2, NONE, FAST_SR1
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1
1083
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1
1092
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1
1097 PIN_OT(gpf5-4, NONE, FAST_SR1
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1
1101 };
1102
1103 te_irq: te-irq-pins {
1104 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO
1106 };
1107 };
1108
1109 &pinctrl_cpif {
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>;
1112
1113 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1
1116 };
1117 };
1118
1119 &pinctrl_ese {
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>;
1122
1123 pcie_wlanen: pcie-wlanen-pins {
1124 samsung,pins = "gpj2-0";
1125 samsung,pin-function = <EXYNO
1126 samsung,pin-pud = <EXYNOS_PIN
1127 samsung,pin-drv = <EXYNOS5433
1128 };
1129
1130 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1
1133 };
1134 };
1135
1136 &pinctrl_fsys {
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>;
1139
1140 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1
1145 PIN_IN(gpr3-7, NONE, FAST_SR1
1146 };
1147 };
1148
1149 &pinctrl_imem {
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>;
1152
1153 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1
1157 PIN_IN(gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1
1159 PIN_IN(gpf0-5, NONE, FAST_SR1
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1
1161 PIN_IN(gpf0-7, UP, FAST_SR1);
1162 };
1163 };
1164
1165 &pinctrl_nfc {
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>;
1168
1169 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1
1171 };
1172 };
1173
1174 &pinctrl_peric {
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>;
1177
1178 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1
1181 PIN_IN(gpv7-2, NONE, FAST_SR1
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1
1185
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1
1187
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1
1191
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1
1193
1194 PIN_IN(gpc3-4, NONE, FAST_SR1
1195 PIN_IN(gpc3-5, NONE, FAST_SR1
1196 PIN_IN(gpc3-6, NONE, FAST_SR1
1197 PIN_IN(gpc3-7, NONE, FAST_SR1
1198
1199 PIN_OT(gpg0-0, NONE, FAST_SR1
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1
1201
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1
1203
1204 PIN_IN(gpd4-0, NONE, FAST_SR1
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1
1209
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1
1211
1212 PIN_IN(gpd8-1, UP, FAST_SR1);
1213
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1
1219
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1
1222
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1
1226 };
1227 };
1228
1229 &pinctrl_touch {
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>;
1232
1233 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1
1235 };
1236 };
1237
1238 &pwm {
1239 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default";
1241 status = "okay";
1242 };
1243
1244 &mic {
1245 status = "okay";
1246 };
1247
1248 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro
1250 assigned-clock-parents = <&xxti>;
1251 };
1252
1253 &serial_1 {
1254 status = "okay";
1255 };
1256
1257 &serial_3 {
1258 status = "okay";
1259
1260 bluetooth {
1261 compatible = "brcm,bcm43438-b
1262 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI
1264 device-wakeup-gpios = <&gpr3
1265 host-wakeup-gpios = <&gpa2 2
1266 clocks = <&s2mps13_osc S2MPS1
1267 clock-names = "extclk";
1268 };
1269 };
1270
1271 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>
1273 status = "okay";
1274
1275 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110";
1277 reg = <0x0>;
1278 spi-max-frequency = <20000000
1279 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE
1281 clocks = <&pmu_system_control
1282 <&s2mps13_osc S2MPS11
1283 clock-names = "mclk1", "mclk2
1284
1285 gpio-controller;
1286 #gpio-cells = <2>;
1287 interrupt-controller;
1288 #interrupt-cells = <2>;
1289
1290 wlf,micd-detect-debounce = <3
1291 wlf,micd-bias-start-time = <0
1292 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>;
1294 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>;
1299
1300 wlf,reset = <&gpc0 7 GPIO_ACT
1301 wlf,ldoena = <&gpf0 0 GPIO_AC
1302
1303 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re
1310 SPKVDDR-supply = <&vph_pwr_re
1311
1312 controller-data {
1313 samsung,spi-feedback-
1314 };
1315 };
1316 };
1317
1318 &spi_3 {
1319 status = "okay";
1320 no-cs-readback;
1321
1322 irled@0 {
1323 compatible = "ir-spi-led";
1324 reg = <0x0>;
1325 spi-max-frequency = <5000000>
1326 power-supply = <&irda_regulat
1327 duty-cycle = /bits/ 8 <60>;
1328 led-active-low;
1329
1330 controller-data {
1331 samsung,spi-feedback-
1332 };
1333 };
1334 };
1335
1336 &timer {
1337 clock-frequency = <24000000>;
1338 };
1339
1340 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>;
1342 status = "okay";
1343 };
1344
1345 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>;
1347 status = "okay";
1348 };
1349
1350 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>;
1352 status = "okay";
1353 };
1354
1355 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>;
1358 status = "okay";
1359 };
1360
1361 &usbdrd_dwc3 {
1362 dr_mode = "otg";
1363 };
1364
1365 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>;
1367 status = "okay";
1368
1369 port {
1370 usb_to_muic: endpoint {
1371 remote-endpoint = <&m
1372 };
1373 };
1374 };
1375
1376 &xxti {
1377 clock-frequency = <24000000>;
1378 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.