1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so !! 3 * SAMSUNG Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> <<
18 17
19 / { 18 / {
20 aliases { 19 aliases {
21 gsc0 = &gsc_0; 20 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 21 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 22 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; <<
25 mmc2 = &mshc_2; <<
26 pinctrl0 = &pinctrl_alive; 23 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 24 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 25 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 26 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 27 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 28 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 29 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 30 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 31 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 32 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 33 serial0 = &serial_0;
37 serial1 = &serial_1; 34 serial1 = &serial_1;
38 serial2 = &serial_2; 35 serial2 = &serial_2;
39 serial3 = &serial_3; 36 serial3 = &serial_3;
40 spi0 = &spi_0; 37 spi0 = &spi_0;
41 spi1 = &spi_1; 38 spi1 = &spi_1;
42 spi2 = &spi_2; 39 spi2 = &spi_2;
43 spi3 = &spi_3; 40 spi3 = &spi_3;
44 spi4 = &spi_4; 41 spi4 = &spi_4;
>> 42 mshc0 = &mshc_0;
>> 43 mshc2 = &mshc_2;
45 }; 44 };
46 45
47 chosen { 46 chosen {
48 stdout-path = &serial_1; 47 stdout-path = &serial_1;
49 }; 48 };
50 49
51 memory@20000000 { 50 memory@20000000 {
52 device_type = "memory"; 51 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 52 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 53 };
55 54
56 gpio-keys { 55 gpio-keys {
57 compatible = "gpio-keys"; 56 compatible = "gpio-keys";
58 57
59 power-key { 58 power-key {
60 gpios = <&gpa2 7 GPIO_ 59 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 60 linux,code = <KEY_POWER>;
62 label = "power key"; 61 label = "power key";
63 debounce-interval = <1 62 debounce-interval = <10>;
64 }; 63 };
65 64
66 volume-up-key { 65 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 66 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 67 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 68 label = "volume-up key";
70 debounce-interval = <1 69 debounce-interval = <10>;
71 }; 70 };
72 71
73 volume-down-key { 72 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 73 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 74 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 75 label = "volume-down key";
77 debounce-interval = <1 76 debounce-interval = <10>;
78 }; 77 };
79 78
80 homepage-key { 79 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 80 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 81 linux,code = <KEY_MENU>;
83 label = "homepage key" 82 label = "homepage key";
84 debounce-interval = <1 83 debounce-interval = <10>;
85 }; 84 };
86 }; 85 };
87 86
88 i2c_max98504: i2c-gpio-0 { 87 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 88 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI !! 89 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
91 scl-gpios = <&gpd0 0 GPIO_ACTI !! 90 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
92 i2c-gpio,delay-us = <2>; 91 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 92 #address-cells = <1>;
94 #size-cells = <0>; 93 #size-cells = <0>;
>> 94 status = "okay";
95 95
96 max98504: amplifier@31 { !! 96 max98504: max98504@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 !! 99 maxim,rx-path = <1>;
100 DIOVDD-supply = <&ldo3 !! 100 maxim,tx-path = <1>;
101 DVDD-supply = <&ldo3_r !! 101 maxim,tx-channel-mask = <3>;
102 PVDD-supply = <&vph_pw !! 102 maxim,tx-channel-source = <2>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { !! 106 irda_regulator: irda-regulator {
107 compatible = "regulator-fixed" <<
108 regulator-name = "VPH_PWR"; <<
109 regulator-min-microvolt = <420 <<
110 regulator-max-microvolt = <420 <<
111 }; <<
112 <<
113 irda_regulator: regulator-irda { <<
114 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
115 enable-active-high; 108 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 109 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 110 regulator-name = "irda_regulator";
118 }; 111 };
119 112
120 sound { 113 sound {
121 compatible = "samsung,tm2-audi 114 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm !! 115 audio-codec = <&wm5110>;
123 i2s-controller = <&i2s0 0>, <& !! 116 i2s-controller = <&i2s0>;
124 audio-amplifier = <&max98504>; 117 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 118 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 119 model = "wm5110";
127 audio-routing = /* Headphone * !! 120 samsung,audio-routing =
128 "HP", "HPOUT1L !! 121 /* Headphone */
129 "HP", "HPOUT1R !! 122 "HP", "HPOUT1L",
130 !! 123 "HP", "HPOUT1R",
131 /* Speaker */ !! 124
132 "SPK", "SPKOUT !! 125 /* Speaker */
133 "SPKOUT", "HPO !! 126 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 127 "SPKOUT", "HPOUT2L",
135 !! 128 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 129
137 "RCV", "HPOUT3 !! 130 /* Receiver */
138 "RCV", "HPOUT3 !! 131 "RCV", "HPOUT3L",
>> 132 "RCV", "HPOUT3R";
>> 133 status = "okay";
139 }; 134 };
140 }; 135 };
141 136
142 &adc { 137 &adc {
143 vdd-supply = <&ldo3_reg>; 138 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 139 status = "okay";
145 140
146 thermistor-ap { 141 thermistor-ap {
147 compatible = "murata,ncp03wf10 142 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 143 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 144 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 145 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 146 io-channels = <&adc 0>;
152 }; 147 };
153 148
154 thermistor-battery { 149 thermistor-battery {
155 compatible = "murata,ncp03wf10 150 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 151 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 152 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 153 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 154 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 155 #thermal-sensor-cells = <0>;
161 }; 156 };
162 157
163 thermistor-charger { 158 thermistor-charger {
164 compatible = "murata,ncp03wf10 159 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 160 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 161 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 162 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 163 io-channels = <&adc 2>;
169 }; 164 };
170 }; 165 };
171 166
172 &bus_g2d_400 { 167 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 168 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 169 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 170 exynos,saturation-ratio = <10>;
176 status = "okay"; 171 status = "okay";
177 }; 172 };
178 173
179 &bus_g2d_266 { 174 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 175 devfreq = <&bus_g2d_400>;
181 status = "okay"; 176 status = "okay";
182 }; 177 };
183 178
184 &bus_gscl { 179 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 180 devfreq = <&bus_g2d_400>;
186 status = "okay"; 181 status = "okay";
187 }; 182 };
188 183
189 &bus_hevc { 184 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 185 devfreq = <&bus_g2d_400>;
191 status = "okay"; 186 status = "okay";
192 }; 187 };
193 188
194 &bus_jpeg { 189 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 190 devfreq = <&bus_g2d_400>;
196 status = "okay"; 191 status = "okay";
197 }; 192 };
198 193
199 &bus_mfc { 194 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 195 devfreq = <&bus_g2d_400>;
201 status = "okay"; 196 status = "okay";
202 }; 197 };
203 198
204 &bus_mscl { 199 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 200 devfreq = <&bus_g2d_400>;
206 status = "okay"; 201 status = "okay";
207 }; 202 };
208 203
209 &bus_noc0 { 204 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 205 devfreq = <&bus_g2d_400>;
211 status = "okay"; 206 status = "okay";
212 }; 207 };
213 208
214 &bus_noc1 { 209 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 210 devfreq = <&bus_g2d_400>;
216 status = "okay"; 211 status = "okay";
217 }; 212 };
218 213
219 &bus_noc2 { 214 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 215 devfreq = <&bus_g2d_400>;
221 status = "okay"; 216 status = "okay";
222 }; 217 };
223 218
224 &cmu_aud { 219 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A !! 220 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 !! 221 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC <<
228 <&cmu_top CLK_MOUT_AUD_PLL>, <<
229 <&cmu_top CLK_MOUT_AUD_PLL_USE <<
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 <<
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 <<
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> <<
233 <<
234 <&cmu_aud CLK_DIV_AUD_CA5>, <<
235 <&cmu_aud CLK_DIV_ACLK_AUD>, <<
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD <<
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S <<
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM <<
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI <<
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR <<
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> <<
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> <<
243 <&cmu_top CLK_DIV_SCLK_PCM1>, <<
244 <&cmu_top CLK_DIV_SCLK_I2S1>; <<
245 <<
246 assigned-clock-parents = <&cmu_top CLK <<
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE <<
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE <<
249 <&cmu_top CLK_FOUT_AUD_PLL>, <<
250 <&cmu_top CLK_MOUT_AUD_PLL>, <<
251 <&cmu_top CLK_MOUT_AUD_PLL_USE <<
252 <&cmu_top CLK_MOUT_AUD_PLL_USE <<
253 <&cmu_top CLK_SCLK_AUDIO0>; <<
254 <<
255 assigned-clock-rates = <0>, <0>, <0>, <<
256 <196608001>, <65536001>, <3276 <<
257 <2048001>, <24576001>, <196608 <<
258 <24576001>, <98304001>, <20480 <<
259 }; 222 };
260 223
261 &cmu_fsys { 224 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 225 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 226 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 227 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 228 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 229 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 230 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 231 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 232 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 233 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 234 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 235 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 236 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 237 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 238 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 239 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 240 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 241 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 242 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 243 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 244 <66700000>, <66700000>;
282 }; 245 };
283 246
284 &cmu_gscl { 247 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 248 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 249 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 250 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 251 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 252 };
290 253
291 &cmu_mfc { 254 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 255 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 256 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 257 };
295 258
296 &cmu_mif { <<
297 assigned-clocks = <&cmu_mif CLK_MOUT_S <<
298 assigned-clock-parents = <&cmu_mif CLK <<
299 assigned-clock-rates = <0>, <333000000 <<
300 }; <<
301 <<
302 &cmu_mscl { 259 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 260 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 261 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 262 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 263 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 264 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 265 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 266 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 267 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 268 };
312 269
313 &cmu_top { <<
314 assigned-clocks = <&cmu_top CLK_FOUT_A <<
315 assigned-clock-rates = <196608001>; <<
316 }; <<
317 <<
318 &cpu0 { 270 &cpu0 {
319 cpu-supply = <&buck3_reg>; 271 cpu-supply = <&buck3_reg>;
320 }; 272 };
321 273
322 &cpu4 { 274 &cpu4 {
323 cpu-supply = <&buck2_reg>; 275 cpu-supply = <&buck2_reg>;
324 }; 276 };
325 277
326 &decon { 278 &decon {
327 status = "okay"; 279 status = "okay";
328 }; 280 };
329 281
330 &decon_tv { 282 &decon_tv {
331 status = "okay"; 283 status = "okay";
332 284
333 ports { 285 ports {
334 #address-cells = <1>; 286 #address-cells = <1>;
335 #size-cells = <0>; 287 #size-cells = <0>;
336 288
337 port@0 { 289 port@0 {
338 reg = <0>; 290 reg = <0>;
339 tv_to_hdmi: endpoint { 291 tv_to_hdmi: endpoint {
340 remote-endpoin 292 remote-endpoint = <&hdmi_to_tv>;
341 }; 293 };
342 }; 294 };
343 }; 295 };
344 }; 296 };
345 297
346 &dsi { 298 &dsi {
347 status = "okay"; 299 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 300 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 301 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 302 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 303 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 304 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 305 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 306 pinctrl-0 = <&te_irq>;
355 }; 307 };
356 308
357 &gpu { <<
358 mali-supply = <&buck6_reg>; <<
359 status = "okay"; <<
360 }; <<
361 <<
362 &hdmi { 309 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 310 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 311 status = "okay";
365 vdd-supply = <&ldo6_reg>; 312 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 313 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 314 vdd_pll-supply = <&ldo6_reg>;
368 315
369 ports { 316 ports {
370 #address-cells = <1>; 317 #address-cells = <1>;
371 #size-cells = <0>; 318 #size-cells = <0>;
372 319
373 port@0 { 320 port@0 {
374 reg = <0>; 321 reg = <0>;
375 hdmi_to_tv: endpoint { 322 hdmi_to_tv: endpoint {
376 remote-endpoin 323 remote-endpoint = <&tv_to_hdmi>;
377 }; 324 };
378 }; 325 };
379 326
380 port@1 { 327 port@1 {
381 reg = <1>; 328 reg = <1>;
382 hdmi_to_mhl: endpoint 329 hdmi_to_mhl: endpoint {
383 remote-endpoin 330 remote-endpoint = <&mhl_to_hdmi>;
384 }; 331 };
385 }; 332 };
386 }; 333 };
387 }; 334 };
388 335
389 &hsi2c_0 { 336 &hsi2c_0 {
390 status = "okay"; 337 status = "okay";
391 clock-frequency = <2500000>; 338 clock-frequency = <2500000>;
392 339
393 pmic@66 { !! 340 s2mps13-pmic@66 {
394 compatible = "samsung,s2mps13- 341 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 342 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL !! 343 interrupts = <7 IRQ_TYPE_NONE>;
397 reg = <0x66>; 344 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 345 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; <<
400 346
401 s2mps13_osc: clocks { 347 s2mps13_osc: clocks {
402 compatible = "samsung, 348 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 349 #clock-cells = <1>;
404 clock-output-names = " 350 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 351 "s2mps13_bt";
406 }; 352 };
407 353
408 regulators { 354 regulators {
409 ldo1_reg: LDO1 { 355 ldo1_reg: LDO1 {
410 regulator-name 356 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 357 regulator-min-microvolt = <900000>;
412 regulator-max- 358 regulator-max-microvolt = <900000>;
413 regulator-alwa 359 regulator-always-on;
414 }; 360 };
415 361
416 ldo2_reg: LDO2 { 362 ldo2_reg: LDO2 {
417 regulator-name 363 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 364 regulator-min-microvolt = <2800000>;
419 regulator-max- 365 regulator-max-microvolt = <2800000>;
420 regulator-alwa 366 regulator-always-on;
421 regulator-stat 367 regulator-state-mem {
422 regula 368 regulator-off-in-suspend;
423 }; 369 };
424 }; 370 };
425 371
426 ldo3_reg: LDO3 { 372 ldo3_reg: LDO3 {
427 regulator-name 373 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 374 regulator-min-microvolt = <1800000>;
429 regulator-max- 375 regulator-max-microvolt = <1800000>;
430 regulator-alwa 376 regulator-always-on;
431 }; 377 };
432 378
433 ldo4_reg: LDO4 { 379 ldo4_reg: LDO4 {
434 regulator-name 380 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 381 regulator-min-microvolt = <1300000>;
436 regulator-max- 382 regulator-max-microvolt = <1300000>;
437 regulator-alwa 383 regulator-always-on;
438 regulator-stat 384 regulator-state-mem {
439 regula 385 regulator-off-in-suspend;
440 }; 386 };
441 }; 387 };
442 388
443 ldo5_reg: LDO5 { 389 ldo5_reg: LDO5 {
444 regulator-name 390 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 391 regulator-min-microvolt = <1000000>;
446 regulator-max- 392 regulator-max-microvolt = <1000000>;
447 regulator-alwa 393 regulator-always-on;
448 regulator-stat 394 regulator-state-mem {
449 regula 395 regulator-off-in-suspend;
450 }; 396 };
451 }; 397 };
452 398
453 ldo6_reg: LDO6 { 399 ldo6_reg: LDO6 {
454 regulator-name 400 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 401 regulator-min-microvolt = <1000000>;
456 regulator-max- 402 regulator-max-microvolt = <1000000>;
457 regulator-stat 403 regulator-state-mem {
458 regula 404 regulator-off-in-suspend;
459 }; 405 };
460 }; 406 };
461 407
462 ldo7_reg: LDO7 { 408 ldo7_reg: LDO7 {
463 regulator-name 409 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 410 regulator-min-microvolt = <1800000>;
465 regulator-max- 411 regulator-max-microvolt = <1800000>;
466 regulator-alwa 412 regulator-always-on;
467 regulator-stat 413 regulator-state-mem {
468 regula 414 regulator-off-in-suspend;
469 }; 415 };
470 }; 416 };
471 417
472 ldo8_reg: LDO8 { 418 ldo8_reg: LDO8 {
473 regulator-name 419 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 420 regulator-min-microvolt = <1800000>;
475 regulator-max- 421 regulator-max-microvolt = <1800000>;
476 regulator-alwa 422 regulator-always-on;
477 regulator-stat 423 regulator-state-mem {
478 regula 424 regulator-off-in-suspend;
479 }; 425 };
480 }; 426 };
481 427
482 ldo9_reg: LDO9 { 428 ldo9_reg: LDO9 {
483 regulator-name 429 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 430 regulator-min-microvolt = <1800000>;
485 regulator-max- 431 regulator-max-microvolt = <1800000>;
486 regulator-alwa 432 regulator-always-on;
487 regulator-stat 433 regulator-state-mem {
488 regula 434 regulator-off-in-suspend;
489 }; 435 };
490 }; 436 };
491 437
492 ldo10_reg: LDO10 { 438 ldo10_reg: LDO10 {
493 regulator-name 439 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 440 regulator-min-microvolt = <3000000>;
495 regulator-max- 441 regulator-max-microvolt = <3000000>;
496 regulator-stat 442 regulator-state-mem {
497 regula 443 regulator-off-in-suspend;
498 }; 444 };
499 }; 445 };
500 446
501 ldo11_reg: LDO11 { 447 ldo11_reg: LDO11 {
502 regulator-name 448 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 449 regulator-min-microvolt = <1000000>;
504 regulator-max- 450 regulator-max-microvolt = <1000000>;
505 regulator-alwa 451 regulator-always-on;
506 regulator-stat 452 regulator-state-mem {
507 regula 453 regulator-off-in-suspend;
508 }; 454 };
509 }; 455 };
510 456
511 ldo12_reg: LDO12 { 457 ldo12_reg: LDO12 {
512 regulator-name 458 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 459 regulator-min-microvolt = <800000>;
514 regulator-max- 460 regulator-max-microvolt = <1350000>;
515 regulator-alwa 461 regulator-always-on;
516 }; 462 };
517 463
518 ldo13_reg: LDO13 { 464 ldo13_reg: LDO13 {
519 regulator-name 465 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 466 regulator-min-microvolt = <950000>;
521 regulator-max- 467 regulator-max-microvolt = <950000>;
522 regulator-alwa 468 regulator-always-on;
523 regulator-stat 469 regulator-state-mem {
524 regula 470 regulator-off-in-suspend;
525 }; 471 };
526 }; 472 };
527 473
528 ldo14_reg: LDO14 { 474 ldo14_reg: LDO14 {
529 regulator-name 475 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 476 regulator-min-microvolt = <1200000>;
531 regulator-max- 477 regulator-max-microvolt = <1200000>;
532 regulator-alwa 478 regulator-always-on;
533 regulator-stat 479 regulator-state-mem {
534 regula 480 regulator-off-in-suspend;
535 }; 481 };
536 }; 482 };
537 483
538 ldo15_reg: LDO15 { 484 ldo15_reg: LDO15 {
539 regulator-name 485 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 486 regulator-min-microvolt = <1200000>;
541 regulator-max- 487 regulator-max-microvolt = <1200000>;
542 regulator-alwa 488 regulator-always-on;
543 regulator-stat 489 regulator-state-mem {
544 regula 490 regulator-off-in-suspend;
545 }; 491 };
546 }; 492 };
547 493
548 ldo16_reg: LDO16 { 494 ldo16_reg: LDO16 {
549 regulator-name 495 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 496 regulator-min-microvolt = <1400000>;
551 regulator-max- 497 regulator-max-microvolt = <3400000>;
552 regulator-alwa 498 regulator-always-on;
553 }; 499 };
554 500
555 ldo17_reg: LDO17 { 501 ldo17_reg: LDO17 {
556 regulator-name 502 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 503 regulator-min-microvolt = <2800000>;
558 regulator-max- 504 regulator-max-microvolt = <2800000>;
559 }; 505 };
560 506
561 ldo18_reg: LDO18 { 507 ldo18_reg: LDO18 {
562 regulator-name 508 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 509 regulator-min-microvolt = <1800000>;
564 regulator-max- 510 regulator-max-microvolt = <1800000>;
565 }; 511 };
566 512
567 ldo19_reg: LDO19 { 513 ldo19_reg: LDO19 {
568 regulator-name 514 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 515 regulator-min-microvolt = <1800000>;
570 regulator-max- 516 regulator-max-microvolt = <1800000>;
571 regulator-alwa 517 regulator-always-on;
572 }; 518 };
573 519
574 ldo20_reg: LDO20 { 520 ldo20_reg: LDO20 {
575 regulator-name 521 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 522 regulator-min-microvolt = <2800000>;
577 regulator-max- 523 regulator-max-microvolt = <2800000>;
578 regulator-alwa 524 regulator-always-on;
579 }; 525 };
580 526
581 ldo21_reg: LDO21 { 527 ldo21_reg: LDO21 {
582 regulator-name 528 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 529 regulator-min-microvolt = <1800000>;
584 regulator-max- 530 regulator-max-microvolt = <1800000>;
585 }; 531 };
586 532
587 ldo22_reg: LDO22 { 533 ldo22_reg: LDO22 {
588 regulator-name 534 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 535 regulator-min-microvolt = <1800000>;
590 regulator-max- 536 regulator-max-microvolt = <1800000>;
591 }; 537 };
592 538
593 ldo23_reg: LDO23 { 539 ldo23_reg: LDO23 {
594 regulator-name 540 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 541 regulator-min-microvolt = <1050000>;
596 regulator-max- 542 regulator-max-microvolt = <1050000>;
597 }; 543 };
598 544
599 ldo24_reg: LDO24 { 545 ldo24_reg: LDO24 {
600 regulator-name 546 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 547 regulator-min-microvolt = <1200000>;
602 regulator-max- 548 regulator-max-microvolt = <1200000>;
603 }; 549 };
604 550
605 ldo25_reg: LDO25 { 551 ldo25_reg: LDO25 {
606 regulator-name 552 regulator-name = "UNUSED_LDO25";
607 regulator-min- 553 regulator-min-microvolt = <2800000>;
608 regulator-max- 554 regulator-max-microvolt = <2800000>;
609 }; 555 };
610 556
611 ldo26_reg: LDO26 { 557 ldo26_reg: LDO26 {
612 regulator-name 558 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 559 regulator-min-microvolt = <2800000>;
614 regulator-max- 560 regulator-max-microvolt = <2800000>;
615 }; 561 };
616 562
617 ldo27_reg: LDO27 { 563 ldo27_reg: LDO27 {
618 regulator-name 564 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 565 regulator-min-microvolt = <3000000>;
620 regulator-max- 566 regulator-max-microvolt = <3000000>;
621 }; 567 };
622 568
623 ldo28_reg: LDO28 { 569 ldo28_reg: LDO28 {
624 regulator-name 570 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 571 regulator-min-microvolt = <1800000>;
626 regulator-max- 572 regulator-max-microvolt = <1800000>;
627 }; 573 };
628 574
629 ldo29_reg: LDO29 { 575 ldo29_reg: LDO29 {
630 regulator-name 576 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 577 regulator-min-microvolt = <3000000>;
632 regulator-max- 578 regulator-max-microvolt = <3000000>;
633 }; 579 };
634 580
635 ldo30_reg: LDO30 { 581 ldo30_reg: LDO30 {
636 regulator-name 582 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 583 regulator-min-microvolt = <3300000>;
638 regulator-max- 584 regulator-max-microvolt = <3300000>;
639 }; 585 };
640 586
641 ldo31_reg: LDO31 { 587 ldo31_reg: LDO31 {
642 /* 588 /*
643 * LDO31 diffe 589 * LDO31 differs from target to target,
644 * its definit 590 * its definition is in the .dts
645 */ 591 */
646 }; 592 };
647 593
648 ldo32_reg: LDO32 { 594 ldo32_reg: LDO32 {
649 regulator-name 595 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 596 regulator-min-microvolt = <1800000>;
651 regulator-max- 597 regulator-max-microvolt = <1800000>;
652 }; 598 };
653 599
654 ldo33_reg: LDO33 { 600 ldo33_reg: LDO33 {
655 regulator-name 601 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 602 regulator-min-microvolt = <2500000>;
657 regulator-max- 603 regulator-max-microvolt = <3300000>;
658 regulator-ramp 604 regulator-ramp-delay = <12500>;
659 }; 605 };
660 606
661 ldo34_reg: LDO34 { 607 ldo34_reg: LDO34 {
662 regulator-name 608 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 609 regulator-min-microvolt = <1000000>;
664 regulator-max- 610 regulator-max-microvolt = <2100000>;
665 }; 611 };
666 612
667 ldo35_reg: LDO35 { 613 ldo35_reg: LDO35 {
668 regulator-name 614 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 615 regulator-min-microvolt = <1800000>;
670 regulator-max- 616 regulator-max-microvolt = <2800000>;
671 }; 617 };
672 618
673 ldo36_reg: LDO36 { 619 ldo36_reg: LDO36 {
674 regulator-name 620 regulator-name = "VSIL_1.0V";
675 regulator-min- 621 regulator-min-microvolt = <1000000>;
676 regulator-max- 622 regulator-max-microvolt = <1000000>;
677 }; 623 };
678 624
679 ldo37_reg: LDO37 { 625 ldo37_reg: LDO37 {
680 regulator-name 626 regulator-name = "VF_1.8V";
681 regulator-min- 627 regulator-min-microvolt = <1800000>;
682 regulator-max- 628 regulator-max-microvolt = <1800000>;
683 }; 629 };
684 630
685 ldo38_reg: LDO38 { 631 ldo38_reg: LDO38 {
686 /* 632 /*
687 * LDO38 diffe 633 * LDO38 differs from target to target,
688 * its definit 634 * its definition is in the .dts
689 */ 635 */
690 }; 636 };
691 637
692 ldo39_reg: LDO39 { 638 ldo39_reg: LDO39 {
693 regulator-name 639 regulator-name = "V_HRM_1.8V";
694 regulator-min- 640 regulator-min-microvolt = <1800000>;
695 regulator-max- 641 regulator-max-microvolt = <1800000>;
696 }; 642 };
697 643
698 ldo40_reg: LDO40 { 644 ldo40_reg: LDO40 {
699 regulator-name 645 regulator-name = "V_HRM_3.3V";
700 regulator-min- 646 regulator-min-microvolt = <3300000>;
701 regulator-max- 647 regulator-max-microvolt = <3300000>;
702 }; 648 };
703 649
704 buck1_reg: BUCK1 { 650 buck1_reg: BUCK1 {
705 regulator-name 651 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 652 regulator-min-microvolt = <600000>;
707 regulator-max- 653 regulator-max-microvolt = <1500000>;
708 regulator-alwa 654 regulator-always-on;
709 regulator-stat 655 regulator-state-mem {
710 regula 656 regulator-off-in-suspend;
711 }; 657 };
712 }; 658 };
713 659
714 buck2_reg: BUCK2 { 660 buck2_reg: BUCK2 {
715 regulator-name 661 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 662 regulator-min-microvolt = <900000>;
717 regulator-max- 663 regulator-max-microvolt = <1300000>;
718 regulator-alwa 664 regulator-always-on;
719 regulator-stat 665 regulator-state-mem {
720 regula 666 regulator-off-in-suspend;
721 }; 667 };
722 }; 668 };
723 669
724 buck3_reg: BUCK3 { 670 buck3_reg: BUCK3 {
725 regulator-name 671 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 672 regulator-min-microvolt = <800000>;
727 regulator-max- 673 regulator-max-microvolt = <1200000>;
728 regulator-alwa 674 regulator-always-on;
729 regulator-stat 675 regulator-state-mem {
730 regula 676 regulator-off-in-suspend;
731 }; 677 };
732 }; 678 };
733 679
734 buck4_reg: BUCK4 { 680 buck4_reg: BUCK4 {
735 regulator-name 681 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 682 regulator-min-microvolt = <600000>;
737 regulator-max- 683 regulator-max-microvolt = <1500000>;
738 regulator-alwa 684 regulator-always-on;
739 regulator-stat 685 regulator-state-mem {
740 regula 686 regulator-off-in-suspend;
741 }; 687 };
742 }; 688 };
743 689
744 buck5_reg: BUCK5 { 690 buck5_reg: BUCK5 {
745 regulator-name 691 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 692 regulator-min-microvolt = <600000>;
747 regulator-max- 693 regulator-max-microvolt = <1500000>;
748 regulator-alwa 694 regulator-always-on;
749 regulator-stat 695 regulator-state-mem {
750 regula 696 regulator-off-in-suspend;
751 }; 697 };
752 }; 698 };
753 699
754 buck6_reg: BUCK6 { 700 buck6_reg: BUCK6 {
755 regulator-name 701 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 702 regulator-min-microvolt = <600000>;
757 regulator-max- 703 regulator-max-microvolt = <1500000>;
758 regulator-alwa 704 regulator-always-on;
759 regulator-stat 705 regulator-state-mem {
760 regula 706 regulator-off-in-suspend;
761 }; 707 };
762 }; 708 };
763 709
764 buck7_reg: BUCK7 { 710 buck7_reg: BUCK7 {
765 regulator-name 711 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 712 regulator-min-microvolt = <1200000>;
767 regulator-max- 713 regulator-max-microvolt = <1200000>;
768 regulator-alwa 714 regulator-always-on;
769 }; 715 };
770 716
771 buck8_reg: BUCK8 { 717 buck8_reg: BUCK8 {
772 regulator-name 718 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 719 regulator-min-microvolt = <1350000>;
774 regulator-max- 720 regulator-max-microvolt = <3300000>;
775 regulator-alwa 721 regulator-always-on;
776 }; 722 };
777 723
778 buck9_reg: BUCK9 { 724 buck9_reg: BUCK9 {
779 regulator-name 725 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 726 regulator-min-microvolt = <1350000>;
781 regulator-max- 727 regulator-max-microvolt = <3300000>;
782 regulator-alwa 728 regulator-always-on;
783 }; 729 };
784 730
785 buck10_reg: BUCK10 { 731 buck10_reg: BUCK10 {
786 regulator-name 732 regulator-name = "vdd_mem2";
787 regulator-min- 733 regulator-min-microvolt = <550000>;
788 regulator-max- 734 regulator-max-microvolt = <1500000>;
789 regulator-alwa 735 regulator-always-on;
790 }; 736 };
791 }; 737 };
792 }; 738 };
793 }; 739 };
794 740
795 &hsi2c_4 { 741 &hsi2c_4 {
796 status = "okay"; 742 status = "okay";
797 743
798 s3fwrn5: nfc@27 { 744 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 745 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 746 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 747 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ !! 748 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV !! 749 s3fwrn5,en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
804 wake-gpios = <&gpj0 2 GPIO_ACT !! 750 s3fwrn5,fw-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 751 };
806 }; 752 };
807 753
808 &hsi2c_5 { 754 &hsi2c_5 {
809 status = "okay"; 755 status = "okay";
810 756
811 stmfts: touchscreen@49 { 757 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 758 compatible = "st,stmfts";
813 reg = <0x49>; 759 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 760 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 761 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 762 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 763 vdd-supply = <&ldo31_reg>;
818 }; 764 };
819 }; 765 };
820 766
821 &hsi2c_7 { 767 &hsi2c_7 {
822 status = "okay"; 768 status = "okay";
823 clock-frequency = <1000000>; 769 clock-frequency = <1000000>;
824 770
825 bridge@39 { !! 771 sii8620@39 {
826 reg = <0x39>; 772 reg = <0x39>;
827 compatible = "sil,sii8620"; 773 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 774 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 775 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 776 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 777 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 778 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 779 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 780 clock-names = "xtal";
835 781
836 ports { !! 782 port {
837 #address-cells = <1>; !! 783 mhl_to_hdmi: endpoint {
838 #size-cells = <0>; !! 784 remote-endpoint = <&hdmi_to_mhl>;
839 <<
840 port@0 { <<
841 reg = <0>; <<
842 mhl_to_hdmi: e <<
843 remote <<
844 }; <<
845 }; <<
846 <<
847 port@1 { <<
848 reg = <1>; <<
849 mhl_to_musb_co <<
850 remote <<
851 }; <<
852 }; 785 };
853 }; 786 };
854 }; 787 };
855 }; 788 };
856 789
857 &hsi2c_8 { 790 &hsi2c_8 {
858 status = "okay"; 791 status = "okay";
859 792
860 pmic@66 { !! 793 max77843@66 {
861 compatible = "maxim,max77843"; 794 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 795 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 796 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 797 reg = <0x66>;
865 798
866 muic: extcon { !! 799 muic: max77843-muic {
867 compatible = "maxim,ma 800 compatible = "maxim,max77843-muic";
868 <<
869 musb_con: connector { <<
870 compatible = " <<
871 " <<
872 label = "micro <<
873 type = "micro" <<
874 <<
875 ports { <<
876 #addre <<
877 #size- <<
878 <<
879 port@0 <<
880 <<
881 <<
882 <<
883 <<
884 <<
885 <<
886 <<
887 <<
888 }; <<
889 <<
890 port@3 <<
891 <<
892 <<
893 <<
894 <<
895 }; <<
896 }; <<
897 }; <<
898 <<
899 ports { <<
900 port { <<
901 muic_t <<
902 <<
903 }; <<
904 }; <<
905 }; <<
906 }; 801 };
907 802
908 regulators { 803 regulators {
909 compatible = "maxim,ma 804 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 805 safeout1_reg: SAFEOUT1 {
911 regulator-name 806 regulator-name = "SAFEOUT1";
912 regulator-min- 807 regulator-min-microvolt = <3300000>;
913 regulator-max- 808 regulator-max-microvolt = <4950000>;
914 }; 809 };
915 810
916 safeout2_reg: SAFEOUT2 811 safeout2_reg: SAFEOUT2 {
917 regulator-name 812 regulator-name = "SAFEOUT2";
918 regulator-min- 813 regulator-min-microvolt = <3300000>;
919 regulator-max- 814 regulator-max-microvolt = <4950000>;
920 }; 815 };
921 816
922 charger_reg: CHARGER { 817 charger_reg: CHARGER {
923 regulator-name 818 regulator-name = "CHARGER";
924 regulator-min- 819 regulator-min-microamp = <100000>;
925 regulator-max- 820 regulator-max-microamp = <3150000>;
926 }; 821 };
927 }; 822 };
928 823
929 haptic: motor-driver { !! 824 haptic: max77843-haptic {
930 compatible = "maxim,ma 825 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 826 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 827 pwms = <&pwm 0 33670 0>;
>> 828 pwm-names = "haptic";
933 }; 829 };
934 }; 830 };
935 }; 831 };
936 832
937 &hsi2c_11 { 833 &hsi2c_11 {
938 status = "okay"; 834 status = "okay";
939 }; 835 };
940 836
941 &i2s0 { 837 &i2s0 {
942 status = "okay"; 838 status = "okay";
943 }; 839 };
944 840
945 &i2s1 { <<
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ <<
947 assigned-clock-parents = <&cmu_peric C <<
948 status = "okay"; <<
949 }; <<
950 <<
951 &mshc_0 { 841 &mshc_0 {
952 status = "okay"; 842 status = "okay";
953 mmc-ddr-1_8v; <<
954 mmc-hs200-1_8v; 843 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 844 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 845 cap-mmc-highspeed;
957 non-removable; 846 non-removable;
958 card-detect-delay = <200>; 847 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 848 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 849 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 850 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 851 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 852 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 853 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 854 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 855 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 856 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 857 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 858 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 859 assigned-clock-rates = <800000000>;
971 }; 860 };
972 861
973 &mshc_2 { 862 &mshc_2 {
974 status = "okay"; 863 status = "okay";
975 cap-sd-highspeed; 864 cap-sd-highspeed;
976 disable-wp; 865 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; !! 866 cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
>> 867 cd-inverted;
978 card-detect-delay = <200>; 868 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 869 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 870 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 871 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 872 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 873 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 874 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 875 bus-width = <4>;
986 }; 876 };
987 877
988 &pcie { <<
989 status = "okay"; <<
990 pinctrl-names = "default"; <<
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; <<
992 vdd10-supply = <&ldo6_reg>; <<
993 vdd18-supply = <&ldo7_reg>; <<
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ <<
995 <&cmu_top CLK_MOUT_S <<
996 assigned-clock-parents = <&cmu_top CLK <<
997 <&cmu_top CLK <<
998 assigned-clock-rates = <0>, <100000000 <<
999 interrupt-map-mask = <0 0 0 0>; <<
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI <<
1001 }; <<
1002 <<
1003 &pcie_phy { <<
1004 status = "okay"; <<
1005 }; <<
1006 <<
1007 &ppmu_d0_general { 878 &ppmu_d0_general {
1008 status = "okay"; 879 status = "okay";
1009 events { 880 events {
1010 ppmu_event0_d0_general: ppmu- 881 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 882 event-name = "ppmu-event0-d0-general";
1012 }; 883 };
1013 }; 884 };
1014 }; 885 };
1015 886
1016 &ppmu_d1_general { 887 &ppmu_d1_general {
1017 status = "okay"; 888 status = "okay";
1018 events { 889 events {
1019 ppmu_event0_d1_general: ppmu- 890 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 891 event-name = "ppmu-event0-d1-general";
1021 }; 892 };
1022 }; !! 893 };
1023 }; 894 };
1024 895
1025 &pinctrl_alive { 896 &pinctrl_alive {
1026 pinctrl-names = "default"; 897 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 898 pinctrl-0 = <&initial_alive>;
1028 899
1029 initial_alive: initial-state { 900 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 !! 901 PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 !! 902 PIN(INPUT, gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 !! 903 PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 !! 904 PIN(INPUT, gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 !! 905 PIN(INPUT, gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 !! 906 PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 !! 907 PIN(INPUT, gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 !! 908 PIN(INPUT, gpa0-7, NONE, FAST_SR1);
1038 !! 909
1039 PIN_IN(gpa1-0, UP, FAST_SR1); !! 910 PIN(INPUT, gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); !! 911 PIN(INPUT, gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 !! 912 PIN(INPUT, gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 !! 913 PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 !! 914 PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 !! 915 PIN(INPUT, gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 !! 916 PIN(INPUT, gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 !! 917 PIN(INPUT, gpa1-7, NONE, FAST_SR1);
1047 !! 918
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 !! 919 PIN(INPUT, gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 !! 920 PIN(INPUT, gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 !! 921 PIN(INPUT, gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 !! 922 PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 !! 923 PIN(INPUT, gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 !! 924 PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 !! 925 PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 !! 926 PIN(INPUT, gpa2-7, NONE, FAST_SR1);
1056 !! 927
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 !! 928 PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 !! 929 PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 !! 930 PIN(INPUT, gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 !! 931 PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 !! 932 PIN(INPUT, gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 !! 933 PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 !! 934 PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 !! 935 PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
1065 !! 936
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 !! 937 PIN(INPUT, gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 !! 938 PIN(INPUT, gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 !! 939 PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); !! 940 PIN(INPUT, gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 !! 941 PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 !! 942 PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 !! 943 PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
1073 !! 944
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 !! 945 PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 !! 946 PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 !! 947 PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 !! 948 PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
1078 !! 949
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 !! 950 PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 !! 951 PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 !! 952 PIN(INPUT, gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 !! 953 PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
1083 !! 954
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 !! 955 PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 !! 956 PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 !! 957 PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 !! 958 PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 !! 959 PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 !! 960 PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 !! 961 PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 !! 962 PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
1092 !! 963
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 !! 964 PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 !! 965 PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 !! 966 PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 !! 967 PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 !! 968 PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 !! 969 PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 !! 970 PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 !! 971 PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
1101 }; 972 };
1102 973
1103 te_irq: te-irq-pins { !! 974 te_irq: te_irq {
1104 samsung,pins = "gpf1-3"; 975 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 976 samsung,pin-function = <0xf>;
1106 }; 977 };
1107 }; 978 };
1108 979
1109 &pinctrl_cpif { 980 &pinctrl_cpif {
1110 pinctrl-names = "default"; 981 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 982 pinctrl-0 = <&initial_cpif>;
1112 983
1113 initial_cpif: initial-state { 984 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 !! 985 PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 !! 986 PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
1116 }; 987 };
1117 }; 988 };
1118 989
1119 &pinctrl_ese { 990 &pinctrl_ese {
1120 pinctrl-names = "default"; 991 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 992 pinctrl-0 = <&initial_ese>;
1122 993
1123 pcie_wlanen: pcie-wlanen-pins { <<
1124 samsung,pins = "gpj2-0"; <<
1125 samsung,pin-function = <EXYNO <<
1126 samsung,pin-pud = <EXYNOS_PIN <<
1127 samsung,pin-drv = <EXYNOS5433 <<
1128 }; <<
1129 <<
1130 initial_ese: initial-state { 994 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 !! 995 PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 !! 996 PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
>> 997 PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
1133 }; 998 };
1134 }; 999 };
1135 1000
1136 &pinctrl_fsys { 1001 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1002 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1003 pinctrl-0 = <&initial_fsys>;
1139 1004
1140 initial_fsys: initial-state { 1005 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 !! 1006 PIN(INPUT, gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 !! 1007 PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 !! 1008 PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 !! 1009 PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 !! 1010 PIN(INPUT, gpr3-7, NONE, FAST_SR1);
1146 }; 1011 };
1147 }; 1012 };
1148 1013
1149 &pinctrl_imem { 1014 &pinctrl_imem {
1150 pinctrl-names = "default"; 1015 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1016 pinctrl-0 = <&initial_imem>;
1152 1017
1153 initial_imem: initial-state { 1018 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); !! 1019 PIN(INPUT, gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); !! 1020 PIN(INPUT, gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 !! 1021 PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); !! 1022 PIN(INPUT, gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 !! 1023 PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 !! 1024 PIN(INPUT, gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 !! 1025 PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); !! 1026 PIN(INPUT, gpf0-7, UP, FAST_SR1);
1162 }; 1027 };
1163 }; 1028 };
1164 1029
1165 &pinctrl_nfc { 1030 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1031 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1032 pinctrl-0 = <&initial_nfc>;
1168 1033
1169 initial_nfc: initial-state { 1034 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 !! 1035 PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
1171 }; 1036 };
1172 }; 1037 };
1173 1038
1174 &pinctrl_peric { 1039 &pinctrl_peric {
1175 pinctrl-names = "default"; 1040 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1041 pinctrl-0 = <&initial_peric>;
1177 1042
1178 initial_peric: initial-state { 1043 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 !! 1044 PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 !! 1045 PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 !! 1046 PIN(INPUT, gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 !! 1047 PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 !! 1048 PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 !! 1049 PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
1185 1050
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 !! 1051 PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
1187 1052
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 !! 1053 PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 !! 1054 PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 !! 1055 PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
1191 1056
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 !! 1057 PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
1193 1058
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 !! 1059 PIN(INPUT, gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 !! 1060 PIN(INPUT, gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 !! 1061 PIN(INPUT, gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 !! 1062 PIN(INPUT, gpc3-7, NONE, FAST_SR1);
1198 1063
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 !! 1064 PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 !! 1065 PIN(2, gpg0-1, DOWN, FAST_SR1);
1201 1066
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 !! 1067 PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
1203 1068
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 !! 1069 PIN(INPUT, gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 !! 1070 PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 !! 1071 PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 !! 1072 PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 !! 1073 PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
1209 1074
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 !! 1075 PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
1211 1076
1212 PIN_IN(gpd8-1, UP, FAST_SR1); !! 1077 PIN(INPUT, gpd8-1, UP, FAST_SR1);
1213 1078
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 !! 1079 PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 !! 1080 PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 !! 1081 PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 !! 1082 PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 !! 1083 PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
1219 1084
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 !! 1085 PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 !! 1086 PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
1222 1087
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 !! 1088 PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 !! 1089 PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 !! 1090 PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
1226 }; 1091 };
1227 }; 1092 };
1228 1093
1229 &pinctrl_touch { 1094 &pinctrl_touch {
1230 pinctrl-names = "default"; 1095 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1096 pinctrl-0 = <&initial_touch>;
1232 1097
1233 initial_touch: initial-state { 1098 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 !! 1099 PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
1235 }; 1100 };
1236 }; 1101 };
1237 1102
1238 &pwm { 1103 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1104 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1105 pinctrl-names = "default";
1241 status = "okay"; 1106 status = "okay";
1242 }; 1107 };
1243 1108
1244 &mic { 1109 &mic {
1245 status = "okay"; 1110 status = "okay";
1246 }; 1111 };
1247 1112
1248 &pmu_system_controller { 1113 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1114 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1115 assigned-clock-parents = <&xxti>;
1251 }; 1116 };
1252 1117
1253 &serial_1 { 1118 &serial_1 {
1254 status = "okay"; 1119 status = "okay";
1255 }; 1120 };
1256 1121
1257 &serial_3 { <<
1258 status = "okay"; <<
1259 <<
1260 bluetooth { <<
1261 compatible = "brcm,bcm43438-b <<
1262 max-speed = <3000000>; <<
1263 shutdown-gpios = <&gpd4 0 GPI <<
1264 device-wakeup-gpios = <&gpr3 <<
1265 host-wakeup-gpios = <&gpa2 2 <<
1266 clocks = <&s2mps13_osc S2MPS1 <<
1267 clock-names = "extclk"; <<
1268 }; <<
1269 }; <<
1270 <<
1271 &spi_1 { 1122 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1123 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1124 status = "okay";
1274 1125
1275 wm5110: audio-codec@0 { !! 1126 wm5110: wm5110-codec@0 {
1276 compatible = "wlf,wm5110"; 1127 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1128 reg = <0x0>;
1278 spi-max-frequency = <20000000 1129 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1130 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1131 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1132 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1133 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1134 clock-names = "mclk1", "mclk2";
1284 1135
1285 gpio-controller; 1136 gpio-controller;
1286 #gpio-cells = <2>; 1137 #gpio-cells = <2>;
1287 interrupt-controller; <<
1288 #interrupt-cells = <2>; <<
1289 1138
1290 wlf,micd-detect-debounce = <3 1139 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1140 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1141 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; !! 1142 wlf,micd-dbtime = <0x1>;
1294 wlf,micd-force-micbias; 1143 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1144 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1145 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1146 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1147 wlf,inmode = <2 0 2 0>;
1299 1148
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1149 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1150 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1151
1303 /* core supplies */ 1152 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1153 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1154 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1155 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1156 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1157 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re <<
1310 SPKVDDR-supply = <&vph_pwr_re <<
1311 1158
1312 controller-data { 1159 controller-data {
1313 samsung,spi-feedback- 1160 samsung,spi-feedback-delay = <0>;
1314 }; 1161 };
1315 }; 1162 };
1316 }; 1163 };
1317 1164
1318 &spi_3 { 1165 &spi_3 {
1319 status = "okay"; 1166 status = "okay";
1320 no-cs-readback; 1167 no-cs-readback;
1321 1168
1322 irled@0 { 1169 irled@0 {
1323 compatible = "ir-spi-led"; 1170 compatible = "ir-spi-led";
1324 reg = <0x0>; 1171 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1172 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1173 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; !! 1174 duty-cycle = <60>;
1328 led-active-low; 1175 led-active-low;
1329 1176
1330 controller-data { 1177 controller-data {
1331 samsung,spi-feedback- 1178 samsung,spi-feedback-delay = <0>;
1332 }; 1179 };
1333 }; 1180 };
1334 }; 1181 };
1335 1182
1336 &timer { 1183 &timer {
1337 clock-frequency = <24000000>; 1184 clock-frequency = <24000000>;
1338 }; 1185 };
1339 1186
1340 &tmu_atlas0 { 1187 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1188 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1189 status = "okay";
1343 }; 1190 };
1344 1191
1345 &tmu_apollo { 1192 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1193 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1194 status = "okay";
1348 }; 1195 };
1349 1196
1350 &tmu_g3d { 1197 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1198 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1199 status = "okay";
1353 }; 1200 };
1354 1201
1355 &usbdrd30 { 1202 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1203 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1204 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1205 status = "okay";
1359 }; 1206 };
1360 1207
1361 &usbdrd_dwc3 { 1208 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1209 dr_mode = "otg";
>> 1210 extcon = <&muic>;
1363 }; 1211 };
1364 1212
1365 &usbdrd30_phy { 1213 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1214 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1215 status = "okay";
1368 <<
1369 port { <<
1370 usb_to_muic: endpoint { <<
1371 remote-endpoint = <&m <<
1372 }; <<
1373 }; <<
1374 }; 1216 };
1375 1217
1376 &xxti { 1218 &xxti {
1377 clock-frequency = <24000000>; 1219 clock-frequency = <24000000>;
1378 }; 1220 };
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