1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so 3 * Samsung Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; <<
25 mmc2 = &mshc_2; <<
26 pinctrl0 = &pinctrl_alive; 24 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 25 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 26 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 27 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 28 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 29 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 30 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 31 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 32 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 33 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 34 serial0 = &serial_0;
37 serial1 = &serial_1; 35 serial1 = &serial_1;
38 serial2 = &serial_2; 36 serial2 = &serial_2;
39 serial3 = &serial_3; 37 serial3 = &serial_3;
40 spi0 = &spi_0; 38 spi0 = &spi_0;
41 spi1 = &spi_1; 39 spi1 = &spi_1;
42 spi2 = &spi_2; 40 spi2 = &spi_2;
43 spi3 = &spi_3; 41 spi3 = &spi_3;
44 spi4 = &spi_4; 42 spi4 = &spi_4;
>> 43 mshc0 = &mshc_0;
>> 44 mshc2 = &mshc_2;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91 scl-gpios = <&gpd0 0 GPIO_ACTI 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 max98504: amplifier@31 { 96 max98504: amplifier@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 !! 99 maxim,rx-path = <1>;
100 DIOVDD-supply = <&ldo3 !! 100 maxim,tx-path = <1>;
101 DVDD-supply = <&ldo3_r !! 101 maxim,tx-channel-mask = <3>;
102 PVDD-supply = <&vph_pw !! 102 maxim,tx-channel-source = <2>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { !! 106 irda_regulator: irda-regulator {
107 compatible = "regulator-fixed" <<
108 regulator-name = "VPH_PWR"; <<
109 regulator-min-microvolt = <420 <<
110 regulator-max-microvolt = <420 <<
111 }; <<
112 <<
113 irda_regulator: regulator-irda { <<
114 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
115 enable-active-high; 108 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 109 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 110 regulator-name = "irda_regulator";
118 }; 111 };
119 112
120 sound { 113 sound {
121 compatible = "samsung,tm2-audi 114 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 115 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 116 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 117 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 118 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 119 model = "wm5110";
127 audio-routing = /* Headphone * !! 120 samsung,audio-routing =
128 "HP", "HPOUT1L !! 121 /* Headphone */
129 "HP", "HPOUT1R !! 122 "HP", "HPOUT1L",
130 !! 123 "HP", "HPOUT1R",
131 /* Speaker */ !! 124
132 "SPK", "SPKOUT !! 125 /* Speaker */
133 "SPKOUT", "HPO !! 126 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 127 "SPKOUT", "HPOUT2L",
135 !! 128 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 129
137 "RCV", "HPOUT3 !! 130 /* Receiver */
138 "RCV", "HPOUT3 !! 131 "RCV", "HPOUT3L",
>> 132 "RCV", "HPOUT3R";
>> 133 status = "okay";
139 }; 134 };
140 }; 135 };
141 136
142 &adc { 137 &adc {
143 vdd-supply = <&ldo3_reg>; 138 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 139 status = "okay";
145 140
146 thermistor-ap { 141 thermistor-ap {
147 compatible = "murata,ncp03wf10 142 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 143 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 144 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 145 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 146 io-channels = <&adc 0>;
152 }; 147 };
153 148
154 thermistor-battery { 149 thermistor-battery {
155 compatible = "murata,ncp03wf10 150 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 151 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 152 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 153 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 154 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 155 #thermal-sensor-cells = <0>;
161 }; 156 };
162 157
163 thermistor-charger { 158 thermistor-charger {
164 compatible = "murata,ncp03wf10 159 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 160 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 161 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 162 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 163 io-channels = <&adc 2>;
169 }; 164 };
170 }; 165 };
171 166
172 &bus_g2d_400 { 167 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 168 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 169 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 170 exynos,saturation-ratio = <10>;
176 status = "okay"; 171 status = "okay";
177 }; 172 };
178 173
179 &bus_g2d_266 { 174 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 175 devfreq = <&bus_g2d_400>;
181 status = "okay"; 176 status = "okay";
182 }; 177 };
183 178
184 &bus_gscl { 179 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 180 devfreq = <&bus_g2d_400>;
186 status = "okay"; 181 status = "okay";
187 }; 182 };
188 183
189 &bus_hevc { 184 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 185 devfreq = <&bus_g2d_400>;
191 status = "okay"; 186 status = "okay";
192 }; 187 };
193 188
194 &bus_jpeg { 189 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 190 devfreq = <&bus_g2d_400>;
196 status = "okay"; 191 status = "okay";
197 }; 192 };
198 193
199 &bus_mfc { 194 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 195 devfreq = <&bus_g2d_400>;
201 status = "okay"; 196 status = "okay";
202 }; 197 };
203 198
204 &bus_mscl { 199 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 200 devfreq = <&bus_g2d_400>;
206 status = "okay"; 201 status = "okay";
207 }; 202 };
208 203
209 &bus_noc0 { 204 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 205 devfreq = <&bus_g2d_400>;
211 status = "okay"; 206 status = "okay";
212 }; 207 };
213 208
214 &bus_noc1 { 209 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 210 devfreq = <&bus_g2d_400>;
216 status = "okay"; 211 status = "okay";
217 }; 212 };
218 213
219 &bus_noc2 { 214 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 215 devfreq = <&bus_g2d_400>;
221 status = "okay"; 216 status = "okay";
222 }; 217 };
223 218
224 &cmu_aud { 219 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 220 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 221 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 222 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 223 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 224 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 225 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 226 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 227 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 228
234 <&cmu_aud CLK_DIV_AUD_CA5>, 229 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 230 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 231 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 232 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 233 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 234 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 235 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 236 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 237 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 238 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 239 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 240
246 assigned-clock-parents = <&cmu_top CLK 241 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 242 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 243 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 244 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 245 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 246 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 247 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 248 <&cmu_top CLK_SCLK_AUDIO0>;
254 249
255 assigned-clock-rates = <0>, <0>, <0>, 250 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 251 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 252 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 253 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 254 };
260 255
261 &cmu_fsys { 256 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 257 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 258 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 259 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 260 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 261 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 262 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 263 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 264 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 265 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 266 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 267 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 268 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 269 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 270 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 271 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 272 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 273 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 274 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 275 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 276 <66700000>, <66700000>;
282 }; 277 };
283 278
284 &cmu_gscl { 279 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 280 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 281 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 282 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 283 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 284 };
290 285
291 &cmu_mfc { 286 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 287 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 288 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 289 };
295 290
296 &cmu_mif { 291 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 292 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 293 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 294 assigned-clock-rates = <0>, <333000000>;
300 }; 295 };
301 296
302 &cmu_mscl { 297 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 298 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 299 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 300 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 301 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 302 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 303 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 304 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 305 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 306 };
312 307
313 &cmu_top { 308 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 309 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 310 assigned-clock-rates = <196608001>;
316 }; 311 };
317 312
318 &cpu0 { 313 &cpu0 {
319 cpu-supply = <&buck3_reg>; 314 cpu-supply = <&buck3_reg>;
320 }; 315 };
321 316
322 &cpu4 { 317 &cpu4 {
323 cpu-supply = <&buck2_reg>; 318 cpu-supply = <&buck2_reg>;
324 }; 319 };
325 320
326 &decon { 321 &decon {
327 status = "okay"; 322 status = "okay";
328 }; 323 };
329 324
330 &decon_tv { 325 &decon_tv {
331 status = "okay"; 326 status = "okay";
332 327
333 ports { 328 ports {
334 #address-cells = <1>; 329 #address-cells = <1>;
335 #size-cells = <0>; 330 #size-cells = <0>;
336 331
337 port@0 { 332 port@0 {
338 reg = <0>; 333 reg = <0>;
339 tv_to_hdmi: endpoint { 334 tv_to_hdmi: endpoint {
340 remote-endpoin 335 remote-endpoint = <&hdmi_to_tv>;
341 }; 336 };
342 }; 337 };
343 }; 338 };
344 }; 339 };
345 340
346 &dsi { 341 &dsi {
347 status = "okay"; 342 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 343 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 344 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 345 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 346 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 347 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 348 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 349 pinctrl-0 = <&te_irq>;
355 }; 350 };
356 351
357 &gpu { 352 &gpu {
358 mali-supply = <&buck6_reg>; 353 mali-supply = <&buck6_reg>;
359 status = "okay"; 354 status = "okay";
360 }; 355 };
361 356
362 &hdmi { 357 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 358 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 359 status = "okay";
365 vdd-supply = <&ldo6_reg>; 360 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 361 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 362 vdd_pll-supply = <&ldo6_reg>;
368 363
369 ports { 364 ports {
370 #address-cells = <1>; 365 #address-cells = <1>;
371 #size-cells = <0>; 366 #size-cells = <0>;
372 367
373 port@0 { 368 port@0 {
374 reg = <0>; 369 reg = <0>;
375 hdmi_to_tv: endpoint { 370 hdmi_to_tv: endpoint {
376 remote-endpoin 371 remote-endpoint = <&tv_to_hdmi>;
377 }; 372 };
378 }; 373 };
379 374
380 port@1 { 375 port@1 {
381 reg = <1>; 376 reg = <1>;
382 hdmi_to_mhl: endpoint 377 hdmi_to_mhl: endpoint {
383 remote-endpoin 378 remote-endpoint = <&mhl_to_hdmi>;
384 }; 379 };
385 }; 380 };
386 }; 381 };
387 }; 382 };
388 383
389 &hsi2c_0 { 384 &hsi2c_0 {
390 status = "okay"; 385 status = "okay";
391 clock-frequency = <2500000>; 386 clock-frequency = <2500000>;
392 387
393 pmic@66 { 388 pmic@66 {
394 compatible = "samsung,s2mps13- 389 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 390 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL 391 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
397 reg = <0x66>; 392 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 393 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; <<
400 394
401 s2mps13_osc: clocks { 395 s2mps13_osc: clocks {
402 compatible = "samsung, 396 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 397 #clock-cells = <1>;
404 clock-output-names = " 398 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 399 "s2mps13_bt";
406 }; 400 };
407 401
408 regulators { 402 regulators {
409 ldo1_reg: LDO1 { 403 ldo1_reg: LDO1 {
410 regulator-name 404 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 405 regulator-min-microvolt = <900000>;
412 regulator-max- 406 regulator-max-microvolt = <900000>;
413 regulator-alwa 407 regulator-always-on;
414 }; 408 };
415 409
416 ldo2_reg: LDO2 { 410 ldo2_reg: LDO2 {
417 regulator-name 411 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 412 regulator-min-microvolt = <2800000>;
419 regulator-max- 413 regulator-max-microvolt = <2800000>;
420 regulator-alwa 414 regulator-always-on;
421 regulator-stat 415 regulator-state-mem {
422 regula 416 regulator-off-in-suspend;
423 }; 417 };
424 }; 418 };
425 419
426 ldo3_reg: LDO3 { 420 ldo3_reg: LDO3 {
427 regulator-name 421 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 422 regulator-min-microvolt = <1800000>;
429 regulator-max- 423 regulator-max-microvolt = <1800000>;
430 regulator-alwa 424 regulator-always-on;
431 }; 425 };
432 426
433 ldo4_reg: LDO4 { 427 ldo4_reg: LDO4 {
434 regulator-name 428 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 429 regulator-min-microvolt = <1300000>;
436 regulator-max- 430 regulator-max-microvolt = <1300000>;
437 regulator-alwa 431 regulator-always-on;
438 regulator-stat 432 regulator-state-mem {
439 regula 433 regulator-off-in-suspend;
440 }; 434 };
441 }; 435 };
442 436
443 ldo5_reg: LDO5 { 437 ldo5_reg: LDO5 {
444 regulator-name 438 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 439 regulator-min-microvolt = <1000000>;
446 regulator-max- 440 regulator-max-microvolt = <1000000>;
447 regulator-alwa 441 regulator-always-on;
448 regulator-stat 442 regulator-state-mem {
449 regula 443 regulator-off-in-suspend;
450 }; 444 };
451 }; 445 };
452 446
453 ldo6_reg: LDO6 { 447 ldo6_reg: LDO6 {
454 regulator-name 448 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 449 regulator-min-microvolt = <1000000>;
456 regulator-max- 450 regulator-max-microvolt = <1000000>;
457 regulator-stat 451 regulator-state-mem {
458 regula 452 regulator-off-in-suspend;
459 }; 453 };
460 }; 454 };
461 455
462 ldo7_reg: LDO7 { 456 ldo7_reg: LDO7 {
463 regulator-name 457 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 458 regulator-min-microvolt = <1800000>;
465 regulator-max- 459 regulator-max-microvolt = <1800000>;
466 regulator-alwa 460 regulator-always-on;
467 regulator-stat 461 regulator-state-mem {
468 regula 462 regulator-off-in-suspend;
469 }; 463 };
470 }; 464 };
471 465
472 ldo8_reg: LDO8 { 466 ldo8_reg: LDO8 {
473 regulator-name 467 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 468 regulator-min-microvolt = <1800000>;
475 regulator-max- 469 regulator-max-microvolt = <1800000>;
476 regulator-alwa 470 regulator-always-on;
477 regulator-stat 471 regulator-state-mem {
478 regula 472 regulator-off-in-suspend;
479 }; 473 };
480 }; 474 };
481 475
482 ldo9_reg: LDO9 { 476 ldo9_reg: LDO9 {
483 regulator-name 477 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 478 regulator-min-microvolt = <1800000>;
485 regulator-max- 479 regulator-max-microvolt = <1800000>;
486 regulator-alwa 480 regulator-always-on;
487 regulator-stat 481 regulator-state-mem {
488 regula 482 regulator-off-in-suspend;
489 }; 483 };
490 }; 484 };
491 485
492 ldo10_reg: LDO10 { 486 ldo10_reg: LDO10 {
493 regulator-name 487 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 488 regulator-min-microvolt = <3000000>;
495 regulator-max- 489 regulator-max-microvolt = <3000000>;
496 regulator-stat 490 regulator-state-mem {
497 regula 491 regulator-off-in-suspend;
498 }; 492 };
499 }; 493 };
500 494
501 ldo11_reg: LDO11 { 495 ldo11_reg: LDO11 {
502 regulator-name 496 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 497 regulator-min-microvolt = <1000000>;
504 regulator-max- 498 regulator-max-microvolt = <1000000>;
505 regulator-alwa 499 regulator-always-on;
506 regulator-stat 500 regulator-state-mem {
507 regula 501 regulator-off-in-suspend;
508 }; 502 };
509 }; 503 };
510 504
511 ldo12_reg: LDO12 { 505 ldo12_reg: LDO12 {
512 regulator-name 506 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 507 regulator-min-microvolt = <800000>;
514 regulator-max- 508 regulator-max-microvolt = <1350000>;
515 regulator-alwa 509 regulator-always-on;
516 }; 510 };
517 511
518 ldo13_reg: LDO13 { 512 ldo13_reg: LDO13 {
519 regulator-name 513 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 514 regulator-min-microvolt = <950000>;
521 regulator-max- 515 regulator-max-microvolt = <950000>;
522 regulator-alwa 516 regulator-always-on;
523 regulator-stat 517 regulator-state-mem {
524 regula 518 regulator-off-in-suspend;
525 }; 519 };
526 }; 520 };
527 521
528 ldo14_reg: LDO14 { 522 ldo14_reg: LDO14 {
529 regulator-name 523 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 524 regulator-min-microvolt = <1200000>;
531 regulator-max- 525 regulator-max-microvolt = <1200000>;
532 regulator-alwa 526 regulator-always-on;
533 regulator-stat 527 regulator-state-mem {
534 regula 528 regulator-off-in-suspend;
535 }; 529 };
536 }; 530 };
537 531
538 ldo15_reg: LDO15 { 532 ldo15_reg: LDO15 {
539 regulator-name 533 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 534 regulator-min-microvolt = <1200000>;
541 regulator-max- 535 regulator-max-microvolt = <1200000>;
542 regulator-alwa 536 regulator-always-on;
543 regulator-stat 537 regulator-state-mem {
544 regula 538 regulator-off-in-suspend;
545 }; 539 };
546 }; 540 };
547 541
548 ldo16_reg: LDO16 { 542 ldo16_reg: LDO16 {
549 regulator-name 543 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 544 regulator-min-microvolt = <1400000>;
551 regulator-max- 545 regulator-max-microvolt = <3400000>;
552 regulator-alwa 546 regulator-always-on;
553 }; 547 };
554 548
555 ldo17_reg: LDO17 { 549 ldo17_reg: LDO17 {
556 regulator-name 550 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 551 regulator-min-microvolt = <2800000>;
558 regulator-max- 552 regulator-max-microvolt = <2800000>;
559 }; 553 };
560 554
561 ldo18_reg: LDO18 { 555 ldo18_reg: LDO18 {
562 regulator-name 556 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 557 regulator-min-microvolt = <1800000>;
564 regulator-max- 558 regulator-max-microvolt = <1800000>;
565 }; 559 };
566 560
567 ldo19_reg: LDO19 { 561 ldo19_reg: LDO19 {
568 regulator-name 562 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 563 regulator-min-microvolt = <1800000>;
570 regulator-max- 564 regulator-max-microvolt = <1800000>;
571 regulator-alwa 565 regulator-always-on;
572 }; 566 };
573 567
574 ldo20_reg: LDO20 { 568 ldo20_reg: LDO20 {
575 regulator-name 569 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 570 regulator-min-microvolt = <2800000>;
577 regulator-max- 571 regulator-max-microvolt = <2800000>;
578 regulator-alwa 572 regulator-always-on;
579 }; 573 };
580 574
581 ldo21_reg: LDO21 { 575 ldo21_reg: LDO21 {
582 regulator-name 576 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 577 regulator-min-microvolt = <1800000>;
584 regulator-max- 578 regulator-max-microvolt = <1800000>;
585 }; 579 };
586 580
587 ldo22_reg: LDO22 { 581 ldo22_reg: LDO22 {
588 regulator-name 582 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 583 regulator-min-microvolt = <1800000>;
590 regulator-max- 584 regulator-max-microvolt = <1800000>;
591 }; 585 };
592 586
593 ldo23_reg: LDO23 { 587 ldo23_reg: LDO23 {
594 regulator-name 588 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 589 regulator-min-microvolt = <1050000>;
596 regulator-max- 590 regulator-max-microvolt = <1050000>;
597 }; 591 };
598 592
599 ldo24_reg: LDO24 { 593 ldo24_reg: LDO24 {
600 regulator-name 594 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 595 regulator-min-microvolt = <1200000>;
602 regulator-max- 596 regulator-max-microvolt = <1200000>;
603 }; 597 };
604 598
605 ldo25_reg: LDO25 { 599 ldo25_reg: LDO25 {
606 regulator-name 600 regulator-name = "UNUSED_LDO25";
607 regulator-min- 601 regulator-min-microvolt = <2800000>;
608 regulator-max- 602 regulator-max-microvolt = <2800000>;
609 }; 603 };
610 604
611 ldo26_reg: LDO26 { 605 ldo26_reg: LDO26 {
612 regulator-name 606 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 607 regulator-min-microvolt = <2800000>;
614 regulator-max- 608 regulator-max-microvolt = <2800000>;
615 }; 609 };
616 610
617 ldo27_reg: LDO27 { 611 ldo27_reg: LDO27 {
618 regulator-name 612 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 613 regulator-min-microvolt = <3000000>;
620 regulator-max- 614 regulator-max-microvolt = <3000000>;
621 }; 615 };
622 616
623 ldo28_reg: LDO28 { 617 ldo28_reg: LDO28 {
624 regulator-name 618 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 619 regulator-min-microvolt = <1800000>;
626 regulator-max- 620 regulator-max-microvolt = <1800000>;
627 }; 621 };
628 622
629 ldo29_reg: LDO29 { 623 ldo29_reg: LDO29 {
630 regulator-name 624 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 625 regulator-min-microvolt = <3000000>;
632 regulator-max- 626 regulator-max-microvolt = <3000000>;
633 }; 627 };
634 628
635 ldo30_reg: LDO30 { 629 ldo30_reg: LDO30 {
636 regulator-name 630 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 631 regulator-min-microvolt = <3300000>;
638 regulator-max- 632 regulator-max-microvolt = <3300000>;
639 }; 633 };
640 634
641 ldo31_reg: LDO31 { 635 ldo31_reg: LDO31 {
642 /* 636 /*
643 * LDO31 diffe 637 * LDO31 differs from target to target,
644 * its definit 638 * its definition is in the .dts
645 */ 639 */
646 }; 640 };
647 641
648 ldo32_reg: LDO32 { 642 ldo32_reg: LDO32 {
649 regulator-name 643 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 644 regulator-min-microvolt = <1800000>;
651 regulator-max- 645 regulator-max-microvolt = <1800000>;
652 }; 646 };
653 647
654 ldo33_reg: LDO33 { 648 ldo33_reg: LDO33 {
655 regulator-name 649 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 650 regulator-min-microvolt = <2500000>;
657 regulator-max- 651 regulator-max-microvolt = <3300000>;
658 regulator-ramp 652 regulator-ramp-delay = <12500>;
659 }; 653 };
660 654
661 ldo34_reg: LDO34 { 655 ldo34_reg: LDO34 {
662 regulator-name 656 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 657 regulator-min-microvolt = <1000000>;
664 regulator-max- 658 regulator-max-microvolt = <2100000>;
665 }; 659 };
666 660
667 ldo35_reg: LDO35 { 661 ldo35_reg: LDO35 {
668 regulator-name 662 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 663 regulator-min-microvolt = <1800000>;
670 regulator-max- 664 regulator-max-microvolt = <2800000>;
671 }; 665 };
672 666
673 ldo36_reg: LDO36 { 667 ldo36_reg: LDO36 {
674 regulator-name 668 regulator-name = "VSIL_1.0V";
675 regulator-min- 669 regulator-min-microvolt = <1000000>;
676 regulator-max- 670 regulator-max-microvolt = <1000000>;
677 }; 671 };
678 672
679 ldo37_reg: LDO37 { 673 ldo37_reg: LDO37 {
680 regulator-name 674 regulator-name = "VF_1.8V";
681 regulator-min- 675 regulator-min-microvolt = <1800000>;
682 regulator-max- 676 regulator-max-microvolt = <1800000>;
683 }; 677 };
684 678
685 ldo38_reg: LDO38 { 679 ldo38_reg: LDO38 {
686 /* 680 /*
687 * LDO38 diffe 681 * LDO38 differs from target to target,
688 * its definit 682 * its definition is in the .dts
689 */ 683 */
690 }; 684 };
691 685
692 ldo39_reg: LDO39 { 686 ldo39_reg: LDO39 {
693 regulator-name 687 regulator-name = "V_HRM_1.8V";
694 regulator-min- 688 regulator-min-microvolt = <1800000>;
695 regulator-max- 689 regulator-max-microvolt = <1800000>;
696 }; 690 };
697 691
698 ldo40_reg: LDO40 { 692 ldo40_reg: LDO40 {
699 regulator-name 693 regulator-name = "V_HRM_3.3V";
700 regulator-min- 694 regulator-min-microvolt = <3300000>;
701 regulator-max- 695 regulator-max-microvolt = <3300000>;
702 }; 696 };
703 697
704 buck1_reg: BUCK1 { 698 buck1_reg: BUCK1 {
705 regulator-name 699 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 700 regulator-min-microvolt = <600000>;
707 regulator-max- 701 regulator-max-microvolt = <1500000>;
708 regulator-alwa 702 regulator-always-on;
709 regulator-stat 703 regulator-state-mem {
710 regula 704 regulator-off-in-suspend;
711 }; 705 };
712 }; 706 };
713 707
714 buck2_reg: BUCK2 { 708 buck2_reg: BUCK2 {
715 regulator-name 709 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 710 regulator-min-microvolt = <900000>;
717 regulator-max- 711 regulator-max-microvolt = <1300000>;
718 regulator-alwa 712 regulator-always-on;
719 regulator-stat 713 regulator-state-mem {
720 regula 714 regulator-off-in-suspend;
721 }; 715 };
722 }; 716 };
723 717
724 buck3_reg: BUCK3 { 718 buck3_reg: BUCK3 {
725 regulator-name 719 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 720 regulator-min-microvolt = <800000>;
727 regulator-max- 721 regulator-max-microvolt = <1200000>;
728 regulator-alwa 722 regulator-always-on;
729 regulator-stat 723 regulator-state-mem {
730 regula 724 regulator-off-in-suspend;
731 }; 725 };
732 }; 726 };
733 727
734 buck4_reg: BUCK4 { 728 buck4_reg: BUCK4 {
735 regulator-name 729 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 730 regulator-min-microvolt = <600000>;
737 regulator-max- 731 regulator-max-microvolt = <1500000>;
738 regulator-alwa 732 regulator-always-on;
739 regulator-stat 733 regulator-state-mem {
740 regula 734 regulator-off-in-suspend;
741 }; 735 };
742 }; 736 };
743 737
744 buck5_reg: BUCK5 { 738 buck5_reg: BUCK5 {
745 regulator-name 739 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 740 regulator-min-microvolt = <600000>;
747 regulator-max- 741 regulator-max-microvolt = <1500000>;
748 regulator-alwa 742 regulator-always-on;
749 regulator-stat 743 regulator-state-mem {
750 regula 744 regulator-off-in-suspend;
751 }; 745 };
752 }; 746 };
753 747
754 buck6_reg: BUCK6 { 748 buck6_reg: BUCK6 {
755 regulator-name 749 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 750 regulator-min-microvolt = <600000>;
757 regulator-max- 751 regulator-max-microvolt = <1500000>;
758 regulator-alwa 752 regulator-always-on;
759 regulator-stat 753 regulator-state-mem {
760 regula 754 regulator-off-in-suspend;
761 }; 755 };
762 }; 756 };
763 757
764 buck7_reg: BUCK7 { 758 buck7_reg: BUCK7 {
765 regulator-name 759 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 760 regulator-min-microvolt = <1200000>;
767 regulator-max- 761 regulator-max-microvolt = <1200000>;
768 regulator-alwa 762 regulator-always-on;
769 }; 763 };
770 764
771 buck8_reg: BUCK8 { 765 buck8_reg: BUCK8 {
772 regulator-name 766 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 767 regulator-min-microvolt = <1350000>;
774 regulator-max- 768 regulator-max-microvolt = <3300000>;
775 regulator-alwa 769 regulator-always-on;
776 }; 770 };
777 771
778 buck9_reg: BUCK9 { 772 buck9_reg: BUCK9 {
779 regulator-name 773 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 774 regulator-min-microvolt = <1350000>;
781 regulator-max- 775 regulator-max-microvolt = <3300000>;
782 regulator-alwa 776 regulator-always-on;
783 }; 777 };
784 778
785 buck10_reg: BUCK10 { 779 buck10_reg: BUCK10 {
786 regulator-name 780 regulator-name = "vdd_mem2";
787 regulator-min- 781 regulator-min-microvolt = <550000>;
788 regulator-max- 782 regulator-max-microvolt = <1500000>;
789 regulator-alwa 783 regulator-always-on;
790 }; 784 };
791 }; 785 };
792 }; 786 };
793 }; 787 };
794 788
795 &hsi2c_4 { 789 &hsi2c_4 {
796 status = "okay"; 790 status = "okay";
797 791
798 s3fwrn5: nfc@27 { 792 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 793 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 794 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 795 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ 796 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV !! 797 en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
804 wake-gpios = <&gpj0 2 GPIO_ACT 798 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 799 };
806 }; 800 };
807 801
808 &hsi2c_5 { 802 &hsi2c_5 {
809 status = "okay"; 803 status = "okay";
810 804
811 stmfts: touchscreen@49 { 805 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 806 compatible = "st,stmfts";
813 reg = <0x49>; 807 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 808 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 809 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 810 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 811 vdd-supply = <&ldo31_reg>;
818 }; 812 };
819 }; 813 };
820 814
821 &hsi2c_7 { 815 &hsi2c_7 {
822 status = "okay"; 816 status = "okay";
823 clock-frequency = <1000000>; 817 clock-frequency = <1000000>;
824 818
825 bridge@39 { 819 bridge@39 {
826 reg = <0x39>; 820 reg = <0x39>;
827 compatible = "sil,sii8620"; 821 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 822 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 823 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 824 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 825 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 826 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 827 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 828 clock-names = "xtal";
835 829
836 ports { 830 ports {
837 #address-cells = <1>; 831 #address-cells = <1>;
838 #size-cells = <0>; 832 #size-cells = <0>;
839 833
840 port@0 { 834 port@0 {
841 reg = <0>; 835 reg = <0>;
842 mhl_to_hdmi: e 836 mhl_to_hdmi: endpoint {
843 remote 837 remote-endpoint = <&hdmi_to_mhl>;
844 }; 838 };
845 }; 839 };
846 840
847 port@1 { 841 port@1 {
848 reg = <1>; 842 reg = <1>;
849 mhl_to_musb_co 843 mhl_to_musb_con: endpoint {
850 remote 844 remote-endpoint = <&musb_con_to_mhl>;
851 }; 845 };
852 }; 846 };
853 }; 847 };
854 }; 848 };
855 }; 849 };
856 850
857 &hsi2c_8 { 851 &hsi2c_8 {
858 status = "okay"; 852 status = "okay";
859 853
860 pmic@66 { 854 pmic@66 {
861 compatible = "maxim,max77843"; 855 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 856 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 857 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 858 reg = <0x66>;
865 859
866 muic: extcon { !! 860 muic: max77843-muic {
867 compatible = "maxim,ma 861 compatible = "maxim,max77843-muic";
868 862
869 musb_con: connector { !! 863 musb_con: musb-connector {
870 compatible = " 864 compatible = "samsung,usb-connector-11pin",
871 " 865 "usb-b-connector";
872 label = "micro 866 label = "micro-USB";
873 type = "micro" 867 type = "micro";
874 868
875 ports { 869 ports {
876 #addre 870 #address-cells = <1>;
877 #size- 871 #size-cells = <0>;
878 872
879 port@0 <<
880 <<
881 <<
882 <<
883 <<
884 <<
885 <<
886 <<
887 <<
888 }; <<
889 <<
890 port@3 873 port@3 {
891 874 reg = <3>;
892 875 musb_con_to_mhl: endpoint {
893 876 remote-endpoint = <&mhl_to_musb_con>;
894 877 };
895 }; 878 };
896 }; 879 };
897 }; 880 };
898 881
899 ports { 882 ports {
900 port { 883 port {
901 muic_t 884 muic_to_usb: endpoint {
902 885 remote-endpoint = <&usb_to_muic>;
903 }; 886 };
904 }; 887 };
905 }; 888 };
906 }; 889 };
907 890
908 regulators { 891 regulators {
909 compatible = "maxim,ma 892 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 893 safeout1_reg: SAFEOUT1 {
911 regulator-name 894 regulator-name = "SAFEOUT1";
912 regulator-min- 895 regulator-min-microvolt = <3300000>;
913 regulator-max- 896 regulator-max-microvolt = <4950000>;
914 }; 897 };
915 898
916 safeout2_reg: SAFEOUT2 899 safeout2_reg: SAFEOUT2 {
917 regulator-name 900 regulator-name = "SAFEOUT2";
918 regulator-min- 901 regulator-min-microvolt = <3300000>;
919 regulator-max- 902 regulator-max-microvolt = <4950000>;
920 }; 903 };
921 904
922 charger_reg: CHARGER { 905 charger_reg: CHARGER {
923 regulator-name 906 regulator-name = "CHARGER";
924 regulator-min- 907 regulator-min-microamp = <100000>;
925 regulator-max- 908 regulator-max-microamp = <3150000>;
926 }; 909 };
927 }; 910 };
928 911
929 haptic: motor-driver { !! 912 haptic: max77843-haptic {
930 compatible = "maxim,ma 913 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 914 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 915 pwms = <&pwm 0 33670 0>;
>> 916 pwm-names = "haptic";
933 }; 917 };
934 }; 918 };
935 }; 919 };
936 920
937 &hsi2c_11 { 921 &hsi2c_11 {
938 status = "okay"; 922 status = "okay";
939 }; 923 };
940 924
941 &i2s0 { 925 &i2s0 {
942 status = "okay"; 926 status = "okay";
943 }; 927 };
944 928
945 &i2s1 { 929 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 930 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 931 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 932 status = "okay";
949 }; 933 };
950 934
951 &mshc_0 { 935 &mshc_0 {
952 status = "okay"; 936 status = "okay";
953 mmc-ddr-1_8v; <<
954 mmc-hs200-1_8v; 937 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 938 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 939 cap-mmc-highspeed;
957 non-removable; 940 non-removable;
958 card-detect-delay = <200>; 941 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 942 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 943 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 944 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 945 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 946 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 947 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 948 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 949 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 950 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 951 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 952 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 953 assigned-clock-rates = <800000000>;
971 }; 954 };
972 955
973 &mshc_2 { 956 &mshc_2 {
974 status = "okay"; 957 status = "okay";
975 cap-sd-highspeed; 958 cap-sd-highspeed;
976 disable-wp; 959 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 960 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 961 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 962 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 963 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 964 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 965 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 966 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 967 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 968 bus-width = <4>;
986 }; 969 };
987 970
988 &pcie { 971 &pcie {
989 status = "okay"; 972 status = "okay";
990 pinctrl-names = "default"; 973 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 974 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>; 975 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>; 976 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ 977 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
995 <&cmu_top CLK_MOUT_S 978 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK 979 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK 980 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
998 assigned-clock-rates = <0>, <100000000 981 assigned-clock-rates = <0>, <100000000>;
999 interrupt-map-mask = <0 0 0 0>; 982 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 983 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1001 }; 984 };
1002 985
1003 &pcie_phy { 986 &pcie_phy {
1004 status = "okay"; 987 status = "okay";
1005 }; 988 };
1006 989
1007 &ppmu_d0_general { 990 &ppmu_d0_general {
1008 status = "okay"; 991 status = "okay";
1009 events { 992 events {
1010 ppmu_event0_d0_general: ppmu- 993 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 994 event-name = "ppmu-event0-d0-general";
1012 }; 995 };
1013 }; 996 };
1014 }; 997 };
1015 998
1016 &ppmu_d1_general { 999 &ppmu_d1_general {
1017 status = "okay"; 1000 status = "okay";
1018 events { 1001 events {
1019 ppmu_event0_d1_general: ppmu- 1002 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 1003 event-name = "ppmu-event0-d1-general";
1021 }; 1004 };
1022 }; 1005 };
1023 }; 1006 };
1024 1007
1025 &pinctrl_alive { 1008 &pinctrl_alive {
1026 pinctrl-names = "default"; 1009 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 1010 pinctrl-0 = <&initial_alive>;
1028 1011
1029 initial_alive: initial-state { 1012 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 !! 1013 PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 !! 1014 PIN(INPUT, gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 !! 1015 PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 !! 1016 PIN(INPUT, gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 !! 1017 PIN(INPUT, gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 !! 1018 PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 !! 1019 PIN(INPUT, gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 !! 1020 PIN(INPUT, gpa0-7, NONE, FAST_SR1);
1038 !! 1021
1039 PIN_IN(gpa1-0, UP, FAST_SR1); !! 1022 PIN(INPUT, gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); !! 1023 PIN(INPUT, gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 !! 1024 PIN(INPUT, gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 !! 1025 PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 !! 1026 PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 !! 1027 PIN(INPUT, gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 !! 1028 PIN(INPUT, gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 !! 1029 PIN(INPUT, gpa1-7, NONE, FAST_SR1);
1047 !! 1030
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 !! 1031 PIN(INPUT, gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 !! 1032 PIN(INPUT, gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 !! 1033 PIN(INPUT, gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 !! 1034 PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 !! 1035 PIN(INPUT, gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 !! 1036 PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 !! 1037 PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 !! 1038 PIN(INPUT, gpa2-7, NONE, FAST_SR1);
1056 !! 1039
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 !! 1040 PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 !! 1041 PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 !! 1042 PIN(INPUT, gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 !! 1043 PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 !! 1044 PIN(INPUT, gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 !! 1045 PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 !! 1046 PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 !! 1047 PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
1065 !! 1048
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 !! 1049 PIN(INPUT, gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 !! 1050 PIN(INPUT, gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 !! 1051 PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); !! 1052 PIN(INPUT, gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 !! 1053 PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 !! 1054 PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 !! 1055 PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
1073 !! 1056
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 !! 1057 PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 !! 1058 PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 !! 1059 PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 !! 1060 PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
1078 !! 1061
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 !! 1062 PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 !! 1063 PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 !! 1064 PIN(INPUT, gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 !! 1065 PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
1083 !! 1066
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 !! 1067 PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 !! 1068 PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 !! 1069 PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 !! 1070 PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 !! 1071 PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 !! 1072 PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 !! 1073 PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 !! 1074 PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
1092 !! 1075
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 !! 1076 PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 !! 1077 PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 !! 1078 PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 !! 1079 PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 !! 1080 PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 !! 1081 PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 !! 1082 PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 !! 1083 PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
1101 }; 1084 };
1102 1085
1103 te_irq: te-irq-pins { !! 1086 te_irq: te-irq {
1104 samsung,pins = "gpf1-3"; 1087 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 1088 samsung,pin-function = <0xf>;
1106 }; 1089 };
1107 }; 1090 };
1108 1091
1109 &pinctrl_cpif { 1092 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1093 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1094 pinctrl-0 = <&initial_cpif>;
1112 1095
1113 initial_cpif: initial-state { 1096 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 !! 1097 PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 !! 1098 PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
1116 }; 1099 };
1117 }; 1100 };
1118 1101
1119 &pinctrl_ese { 1102 &pinctrl_ese {
1120 pinctrl-names = "default"; 1103 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1104 pinctrl-0 = <&initial_ese>;
1122 1105
1123 pcie_wlanen: pcie-wlanen-pins { !! 1106 pcie_wlanen: pcie-wlanen {
1124 samsung,pins = "gpj2-0"; !! 1107 PIN(INPUT, gpj2-0, UP, FAST_SR4);
1125 samsung,pin-function = <EXYNO <<
1126 samsung,pin-pud = <EXYNOS_PIN <<
1127 samsung,pin-drv = <EXYNOS5433 <<
1128 }; 1108 };
1129 1109
1130 initial_ese: initial-state { 1110 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 !! 1111 PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 !! 1112 PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
1133 }; 1113 };
1134 }; 1114 };
1135 1115
1136 &pinctrl_fsys { 1116 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1117 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1118 pinctrl-0 = <&initial_fsys>;
1139 1119
1140 initial_fsys: initial-state { 1120 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 !! 1121 PIN(INPUT, gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 !! 1122 PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 !! 1123 PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 !! 1124 PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 !! 1125 PIN(INPUT, gpr3-7, NONE, FAST_SR1);
1146 }; 1126 };
1147 }; 1127 };
1148 1128
1149 &pinctrl_imem { 1129 &pinctrl_imem {
1150 pinctrl-names = "default"; 1130 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1131 pinctrl-0 = <&initial_imem>;
1152 1132
1153 initial_imem: initial-state { 1133 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); !! 1134 PIN(INPUT, gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); !! 1135 PIN(INPUT, gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 !! 1136 PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); !! 1137 PIN(INPUT, gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 !! 1138 PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 !! 1139 PIN(INPUT, gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 !! 1140 PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); !! 1141 PIN(INPUT, gpf0-7, UP, FAST_SR1);
1162 }; 1142 };
1163 }; 1143 };
1164 1144
1165 &pinctrl_nfc { 1145 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1146 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1147 pinctrl-0 = <&initial_nfc>;
1168 1148
1169 initial_nfc: initial-state { 1149 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 !! 1150 PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
1171 }; 1151 };
1172 }; 1152 };
1173 1153
1174 &pinctrl_peric { 1154 &pinctrl_peric {
1175 pinctrl-names = "default"; 1155 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1156 pinctrl-0 = <&initial_peric>;
1177 1157
1178 initial_peric: initial-state { 1158 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 !! 1159 PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 !! 1160 PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 !! 1161 PIN(INPUT, gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 !! 1162 PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 !! 1163 PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 !! 1164 PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
1185 1165
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 !! 1166 PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
1187 1167
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 !! 1168 PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 !! 1169 PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 !! 1170 PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
1191 1171
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 !! 1172 PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
1193 1173
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 !! 1174 PIN(INPUT, gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 !! 1175 PIN(INPUT, gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 !! 1176 PIN(INPUT, gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 !! 1177 PIN(INPUT, gpc3-7, NONE, FAST_SR1);
1198 1178
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 !! 1179 PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 !! 1180 PIN(2, gpg0-1, DOWN, FAST_SR1);
1201 1181
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 !! 1182 PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
1203 1183
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 !! 1184 PIN(INPUT, gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 !! 1185 PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 !! 1186 PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 !! 1187 PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 !! 1188 PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
1209 1189
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 !! 1190 PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
1211 1191
1212 PIN_IN(gpd8-1, UP, FAST_SR1); !! 1192 PIN(INPUT, gpd8-1, UP, FAST_SR1);
1213 1193
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 !! 1194 PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 !! 1195 PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 !! 1196 PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 !! 1197 PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 !! 1198 PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
1219 1199
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 !! 1200 PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 !! 1201 PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
1222 1202
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 !! 1203 PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 !! 1204 PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 !! 1205 PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
1226 }; 1206 };
1227 }; 1207 };
1228 1208
1229 &pinctrl_touch { 1209 &pinctrl_touch {
1230 pinctrl-names = "default"; 1210 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1211 pinctrl-0 = <&initial_touch>;
1232 1212
1233 initial_touch: initial-state { 1213 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 !! 1214 PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
1235 }; 1215 };
1236 }; 1216 };
1237 1217
1238 &pwm { 1218 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1219 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1220 pinctrl-names = "default";
1241 status = "okay"; 1221 status = "okay";
1242 }; 1222 };
1243 1223
1244 &mic { 1224 &mic {
1245 status = "okay"; 1225 status = "okay";
1246 }; 1226 };
1247 1227
1248 &pmu_system_controller { 1228 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1229 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1230 assigned-clock-parents = <&xxti>;
1251 }; 1231 };
1252 1232
1253 &serial_1 { 1233 &serial_1 {
1254 status = "okay"; 1234 status = "okay";
1255 }; 1235 };
1256 1236
1257 &serial_3 { 1237 &serial_3 {
1258 status = "okay"; 1238 status = "okay";
1259 1239
1260 bluetooth { 1240 bluetooth {
1261 compatible = "brcm,bcm43438-b 1241 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1242 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1243 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1244 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1245 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1246 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1247 clock-names = "extclk";
1268 }; 1248 };
1269 }; 1249 };
1270 1250
1271 &spi_1 { 1251 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1252 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1253 status = "okay";
1274 1254
1275 wm5110: audio-codec@0 { 1255 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110"; 1256 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1257 reg = <0x0>;
1278 spi-max-frequency = <20000000 1258 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1259 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1260 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1261 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1262 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1263 clock-names = "mclk1", "mclk2";
1284 1264
1285 gpio-controller; 1265 gpio-controller;
1286 #gpio-cells = <2>; 1266 #gpio-cells = <2>;
1287 interrupt-controller; <<
1288 #interrupt-cells = <2>; <<
1289 1267
1290 wlf,micd-detect-debounce = <3 1268 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1269 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1270 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; !! 1271 wlf,micd-dbtime = <0x1>;
1294 wlf,micd-force-micbias; 1272 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1273 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1274 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1275 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1276 wlf,inmode = <2 0 2 0>;
1299 1277
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1278 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1279 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1280
1303 /* core supplies */ 1281 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1282 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1283 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1284 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1285 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1286 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re <<
1310 SPKVDDR-supply = <&vph_pwr_re <<
1311 1287
1312 controller-data { 1288 controller-data {
1313 samsung,spi-feedback- 1289 samsung,spi-feedback-delay = <0>;
1314 }; 1290 };
1315 }; 1291 };
1316 }; 1292 };
1317 1293
1318 &spi_3 { 1294 &spi_3 {
1319 status = "okay"; 1295 status = "okay";
1320 no-cs-readback; 1296 no-cs-readback;
1321 1297
1322 irled@0 { 1298 irled@0 {
1323 compatible = "ir-spi-led"; 1299 compatible = "ir-spi-led";
1324 reg = <0x0>; 1300 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1301 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1302 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; !! 1303 duty-cycle = <60>;
1328 led-active-low; 1304 led-active-low;
1329 1305
1330 controller-data { 1306 controller-data {
1331 samsung,spi-feedback- 1307 samsung,spi-feedback-delay = <0>;
1332 }; 1308 };
1333 }; 1309 };
1334 }; 1310 };
1335 1311
1336 &timer { 1312 &timer {
1337 clock-frequency = <24000000>; 1313 clock-frequency = <24000000>;
1338 }; 1314 };
1339 1315
1340 &tmu_atlas0 { 1316 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1317 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1318 status = "okay";
1343 }; 1319 };
1344 1320
1345 &tmu_apollo { 1321 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1322 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1323 status = "okay";
1348 }; 1324 };
1349 1325
1350 &tmu_g3d { 1326 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1327 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1328 status = "okay";
1353 }; 1329 };
1354 1330
1355 &usbdrd30 { 1331 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1332 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1333 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1334 status = "okay";
1359 }; 1335 };
1360 1336
1361 &usbdrd_dwc3 { 1337 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1338 dr_mode = "otg";
1363 }; 1339 };
1364 1340
1365 &usbdrd30_phy { 1341 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1342 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1343 status = "okay";
1368 1344
1369 port { 1345 port {
1370 usb_to_muic: endpoint { 1346 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1347 remote-endpoint = <&muic_to_usb>;
1372 }; 1348 };
1373 }; 1349 };
1374 }; 1350 };
1375 1351
1376 &xxti { 1352 &xxti {
1377 clock-frequency = <24000000>; 1353 clock-frequency = <24000000>;
1378 }; 1354 };
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