1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so 3 * Samsung Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; <<
25 mmc2 = &mshc_2; <<
26 pinctrl0 = &pinctrl_alive; 24 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 25 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 26 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 27 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 28 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 29 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 30 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 31 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 32 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 33 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 34 serial0 = &serial_0;
37 serial1 = &serial_1; 35 serial1 = &serial_1;
38 serial2 = &serial_2; 36 serial2 = &serial_2;
39 serial3 = &serial_3; 37 serial3 = &serial_3;
40 spi0 = &spi_0; 38 spi0 = &spi_0;
41 spi1 = &spi_1; 39 spi1 = &spi_1;
42 spi2 = &spi_2; 40 spi2 = &spi_2;
43 spi3 = &spi_3; 41 spi3 = &spi_3;
44 spi4 = &spi_4; 42 spi4 = &spi_4;
>> 43 mshc0 = &mshc_0;
>> 44 mshc2 = &mshc_2;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91 scl-gpios = <&gpd0 0 GPIO_ACTI 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 max98504: amplifier@31 { 96 max98504: amplifier@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 !! 99 maxim,rx-path = <1>;
100 DIOVDD-supply = <&ldo3 !! 100 maxim,tx-path = <1>;
101 DVDD-supply = <&ldo3_r !! 101 maxim,tx-channel-mask = <3>;
102 PVDD-supply = <&vph_pw !! 102 maxim,tx-channel-source = <2>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { !! 106 irda_regulator: irda-regulator {
107 compatible = "regulator-fixed" <<
108 regulator-name = "VPH_PWR"; <<
109 regulator-min-microvolt = <420 <<
110 regulator-max-microvolt = <420 <<
111 }; <<
112 <<
113 irda_regulator: regulator-irda { <<
114 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
115 enable-active-high; 108 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 109 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 110 regulator-name = "irda_regulator";
118 }; 111 };
119 112
120 sound { 113 sound {
121 compatible = "samsung,tm2-audi 114 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 115 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 116 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 117 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 118 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 119 model = "wm5110";
127 audio-routing = /* Headphone * !! 120 samsung,audio-routing =
128 "HP", "HPOUT1L !! 121 /* Headphone */
129 "HP", "HPOUT1R !! 122 "HP", "HPOUT1L",
130 !! 123 "HP", "HPOUT1R",
131 /* Speaker */ !! 124
132 "SPK", "SPKOUT !! 125 /* Speaker */
133 "SPKOUT", "HPO !! 126 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 127 "SPKOUT", "HPOUT2L",
135 !! 128 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 129
137 "RCV", "HPOUT3 !! 130 /* Receiver */
138 "RCV", "HPOUT3 !! 131 "RCV", "HPOUT3L",
>> 132 "RCV", "HPOUT3R";
>> 133 status = "okay";
139 }; 134 };
140 }; 135 };
141 136
142 &adc { 137 &adc {
143 vdd-supply = <&ldo3_reg>; 138 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 139 status = "okay";
145 140
146 thermistor-ap { 141 thermistor-ap {
147 compatible = "murata,ncp03wf10 142 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 143 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 144 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 145 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 146 io-channels = <&adc 0>;
152 }; 147 };
153 148
154 thermistor-battery { 149 thermistor-battery {
155 compatible = "murata,ncp03wf10 150 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 151 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 152 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 153 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 154 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 155 #thermal-sensor-cells = <0>;
161 }; 156 };
162 157
163 thermistor-charger { 158 thermistor-charger {
164 compatible = "murata,ncp03wf10 159 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 160 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 161 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 162 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 163 io-channels = <&adc 2>;
169 }; 164 };
170 }; 165 };
171 166
172 &bus_g2d_400 { 167 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 168 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 169 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 170 exynos,saturation-ratio = <10>;
176 status = "okay"; 171 status = "okay";
177 }; 172 };
178 173
179 &bus_g2d_266 { 174 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 175 devfreq = <&bus_g2d_400>;
181 status = "okay"; 176 status = "okay";
182 }; 177 };
183 178
184 &bus_gscl { 179 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 180 devfreq = <&bus_g2d_400>;
186 status = "okay"; 181 status = "okay";
187 }; 182 };
188 183
189 &bus_hevc { 184 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 185 devfreq = <&bus_g2d_400>;
191 status = "okay"; 186 status = "okay";
192 }; 187 };
193 188
194 &bus_jpeg { 189 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 190 devfreq = <&bus_g2d_400>;
196 status = "okay"; 191 status = "okay";
197 }; 192 };
198 193
199 &bus_mfc { 194 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 195 devfreq = <&bus_g2d_400>;
201 status = "okay"; 196 status = "okay";
202 }; 197 };
203 198
204 &bus_mscl { 199 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 200 devfreq = <&bus_g2d_400>;
206 status = "okay"; 201 status = "okay";
207 }; 202 };
208 203
209 &bus_noc0 { 204 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 205 devfreq = <&bus_g2d_400>;
211 status = "okay"; 206 status = "okay";
212 }; 207 };
213 208
214 &bus_noc1 { 209 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 210 devfreq = <&bus_g2d_400>;
216 status = "okay"; 211 status = "okay";
217 }; 212 };
218 213
219 &bus_noc2 { 214 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 215 devfreq = <&bus_g2d_400>;
221 status = "okay"; 216 status = "okay";
222 }; 217 };
223 218
224 &cmu_aud { 219 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 220 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 221 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 222 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 223 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 224 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 225 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 226 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 227 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 228
234 <&cmu_aud CLK_DIV_AUD_CA5>, 229 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 230 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 231 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 232 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 233 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 234 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 235 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 236 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 237 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 238 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 239 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 240
246 assigned-clock-parents = <&cmu_top CLK 241 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 242 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 243 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 244 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 245 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 246 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 247 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 248 <&cmu_top CLK_SCLK_AUDIO0>;
254 249
255 assigned-clock-rates = <0>, <0>, <0>, 250 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 251 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 252 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 253 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 254 };
260 255
261 &cmu_fsys { 256 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 257 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 258 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 259 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 260 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 261 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 262 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 263 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 264 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 265 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 266 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 267 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 268 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 269 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 270 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 271 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 272 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 273 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 274 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 275 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 276 <66700000>, <66700000>;
282 }; 277 };
283 278
284 &cmu_gscl { 279 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 280 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 281 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 282 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 283 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 284 };
290 285
291 &cmu_mfc { 286 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 287 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 288 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 289 };
295 290
296 &cmu_mif { 291 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 292 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 293 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 294 assigned-clock-rates = <0>, <333000000>;
300 }; 295 };
301 296
302 &cmu_mscl { 297 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 298 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 299 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 300 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 301 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 302 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 303 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 304 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 305 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 306 };
312 307
313 &cmu_top { 308 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 309 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 310 assigned-clock-rates = <196608001>;
316 }; 311 };
317 312
318 &cpu0 { 313 &cpu0 {
319 cpu-supply = <&buck3_reg>; 314 cpu-supply = <&buck3_reg>;
320 }; 315 };
321 316
322 &cpu4 { 317 &cpu4 {
323 cpu-supply = <&buck2_reg>; 318 cpu-supply = <&buck2_reg>;
324 }; 319 };
325 320
326 &decon { 321 &decon {
327 status = "okay"; 322 status = "okay";
328 }; 323 };
329 324
330 &decon_tv { 325 &decon_tv {
331 status = "okay"; 326 status = "okay";
332 327
333 ports { 328 ports {
334 #address-cells = <1>; 329 #address-cells = <1>;
335 #size-cells = <0>; 330 #size-cells = <0>;
336 331
337 port@0 { 332 port@0 {
338 reg = <0>; 333 reg = <0>;
339 tv_to_hdmi: endpoint { 334 tv_to_hdmi: endpoint {
340 remote-endpoin 335 remote-endpoint = <&hdmi_to_tv>;
341 }; 336 };
342 }; 337 };
343 }; 338 };
344 }; 339 };
345 340
346 &dsi { 341 &dsi {
347 status = "okay"; 342 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 343 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 344 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 345 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 346 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 347 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 348 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 349 pinctrl-0 = <&te_irq>;
355 }; 350 };
356 351
357 &gpu { 352 &gpu {
358 mali-supply = <&buck6_reg>; 353 mali-supply = <&buck6_reg>;
359 status = "okay"; 354 status = "okay";
360 }; 355 };
361 356
362 &hdmi { 357 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 358 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 359 status = "okay";
365 vdd-supply = <&ldo6_reg>; 360 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 361 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 362 vdd_pll-supply = <&ldo6_reg>;
368 363
369 ports { 364 ports {
370 #address-cells = <1>; 365 #address-cells = <1>;
371 #size-cells = <0>; 366 #size-cells = <0>;
372 367
373 port@0 { 368 port@0 {
374 reg = <0>; 369 reg = <0>;
375 hdmi_to_tv: endpoint { 370 hdmi_to_tv: endpoint {
376 remote-endpoin 371 remote-endpoint = <&tv_to_hdmi>;
377 }; 372 };
378 }; 373 };
379 374
380 port@1 { 375 port@1 {
381 reg = <1>; 376 reg = <1>;
382 hdmi_to_mhl: endpoint 377 hdmi_to_mhl: endpoint {
383 remote-endpoin 378 remote-endpoint = <&mhl_to_hdmi>;
384 }; 379 };
385 }; 380 };
386 }; 381 };
387 }; 382 };
388 383
389 &hsi2c_0 { 384 &hsi2c_0 {
390 status = "okay"; 385 status = "okay";
391 clock-frequency = <2500000>; 386 clock-frequency = <2500000>;
392 387
393 pmic@66 { 388 pmic@66 {
394 compatible = "samsung,s2mps13- 389 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 390 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL 391 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
397 reg = <0x66>; 392 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 393 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; 394 wakeup-source;
400 395
401 s2mps13_osc: clocks { 396 s2mps13_osc: clocks {
402 compatible = "samsung, 397 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 398 #clock-cells = <1>;
404 clock-output-names = " 399 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 400 "s2mps13_bt";
406 }; 401 };
407 402
408 regulators { 403 regulators {
409 ldo1_reg: LDO1 { 404 ldo1_reg: LDO1 {
410 regulator-name 405 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 406 regulator-min-microvolt = <900000>;
412 regulator-max- 407 regulator-max-microvolt = <900000>;
413 regulator-alwa 408 regulator-always-on;
414 }; 409 };
415 410
416 ldo2_reg: LDO2 { 411 ldo2_reg: LDO2 {
417 regulator-name 412 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 413 regulator-min-microvolt = <2800000>;
419 regulator-max- 414 regulator-max-microvolt = <2800000>;
420 regulator-alwa 415 regulator-always-on;
421 regulator-stat 416 regulator-state-mem {
422 regula 417 regulator-off-in-suspend;
423 }; 418 };
424 }; 419 };
425 420
426 ldo3_reg: LDO3 { 421 ldo3_reg: LDO3 {
427 regulator-name 422 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 423 regulator-min-microvolt = <1800000>;
429 regulator-max- 424 regulator-max-microvolt = <1800000>;
430 regulator-alwa 425 regulator-always-on;
431 }; 426 };
432 427
433 ldo4_reg: LDO4 { 428 ldo4_reg: LDO4 {
434 regulator-name 429 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 430 regulator-min-microvolt = <1300000>;
436 regulator-max- 431 regulator-max-microvolt = <1300000>;
437 regulator-alwa 432 regulator-always-on;
438 regulator-stat 433 regulator-state-mem {
439 regula 434 regulator-off-in-suspend;
440 }; 435 };
441 }; 436 };
442 437
443 ldo5_reg: LDO5 { 438 ldo5_reg: LDO5 {
444 regulator-name 439 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 440 regulator-min-microvolt = <1000000>;
446 regulator-max- 441 regulator-max-microvolt = <1000000>;
447 regulator-alwa 442 regulator-always-on;
448 regulator-stat 443 regulator-state-mem {
449 regula 444 regulator-off-in-suspend;
450 }; 445 };
451 }; 446 };
452 447
453 ldo6_reg: LDO6 { 448 ldo6_reg: LDO6 {
454 regulator-name 449 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 450 regulator-min-microvolt = <1000000>;
456 regulator-max- 451 regulator-max-microvolt = <1000000>;
457 regulator-stat 452 regulator-state-mem {
458 regula 453 regulator-off-in-suspend;
459 }; 454 };
460 }; 455 };
461 456
462 ldo7_reg: LDO7 { 457 ldo7_reg: LDO7 {
463 regulator-name 458 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 459 regulator-min-microvolt = <1800000>;
465 regulator-max- 460 regulator-max-microvolt = <1800000>;
466 regulator-alwa 461 regulator-always-on;
467 regulator-stat 462 regulator-state-mem {
468 regula 463 regulator-off-in-suspend;
469 }; 464 };
470 }; 465 };
471 466
472 ldo8_reg: LDO8 { 467 ldo8_reg: LDO8 {
473 regulator-name 468 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 469 regulator-min-microvolt = <1800000>;
475 regulator-max- 470 regulator-max-microvolt = <1800000>;
476 regulator-alwa 471 regulator-always-on;
477 regulator-stat 472 regulator-state-mem {
478 regula 473 regulator-off-in-suspend;
479 }; 474 };
480 }; 475 };
481 476
482 ldo9_reg: LDO9 { 477 ldo9_reg: LDO9 {
483 regulator-name 478 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 479 regulator-min-microvolt = <1800000>;
485 regulator-max- 480 regulator-max-microvolt = <1800000>;
486 regulator-alwa 481 regulator-always-on;
487 regulator-stat 482 regulator-state-mem {
488 regula 483 regulator-off-in-suspend;
489 }; 484 };
490 }; 485 };
491 486
492 ldo10_reg: LDO10 { 487 ldo10_reg: LDO10 {
493 regulator-name 488 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 489 regulator-min-microvolt = <3000000>;
495 regulator-max- 490 regulator-max-microvolt = <3000000>;
496 regulator-stat 491 regulator-state-mem {
497 regula 492 regulator-off-in-suspend;
498 }; 493 };
499 }; 494 };
500 495
501 ldo11_reg: LDO11 { 496 ldo11_reg: LDO11 {
502 regulator-name 497 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 498 regulator-min-microvolt = <1000000>;
504 regulator-max- 499 regulator-max-microvolt = <1000000>;
505 regulator-alwa 500 regulator-always-on;
506 regulator-stat 501 regulator-state-mem {
507 regula 502 regulator-off-in-suspend;
508 }; 503 };
509 }; 504 };
510 505
511 ldo12_reg: LDO12 { 506 ldo12_reg: LDO12 {
512 regulator-name 507 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 508 regulator-min-microvolt = <800000>;
514 regulator-max- 509 regulator-max-microvolt = <1350000>;
515 regulator-alwa 510 regulator-always-on;
516 }; 511 };
517 512
518 ldo13_reg: LDO13 { 513 ldo13_reg: LDO13 {
519 regulator-name 514 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 515 regulator-min-microvolt = <950000>;
521 regulator-max- 516 regulator-max-microvolt = <950000>;
522 regulator-alwa 517 regulator-always-on;
523 regulator-stat 518 regulator-state-mem {
524 regula 519 regulator-off-in-suspend;
525 }; 520 };
526 }; 521 };
527 522
528 ldo14_reg: LDO14 { 523 ldo14_reg: LDO14 {
529 regulator-name 524 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 525 regulator-min-microvolt = <1200000>;
531 regulator-max- 526 regulator-max-microvolt = <1200000>;
532 regulator-alwa 527 regulator-always-on;
533 regulator-stat 528 regulator-state-mem {
534 regula 529 regulator-off-in-suspend;
535 }; 530 };
536 }; 531 };
537 532
538 ldo15_reg: LDO15 { 533 ldo15_reg: LDO15 {
539 regulator-name 534 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 535 regulator-min-microvolt = <1200000>;
541 regulator-max- 536 regulator-max-microvolt = <1200000>;
542 regulator-alwa 537 regulator-always-on;
543 regulator-stat 538 regulator-state-mem {
544 regula 539 regulator-off-in-suspend;
545 }; 540 };
546 }; 541 };
547 542
548 ldo16_reg: LDO16 { 543 ldo16_reg: LDO16 {
549 regulator-name 544 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 545 regulator-min-microvolt = <1400000>;
551 regulator-max- 546 regulator-max-microvolt = <3400000>;
552 regulator-alwa 547 regulator-always-on;
553 }; 548 };
554 549
555 ldo17_reg: LDO17 { 550 ldo17_reg: LDO17 {
556 regulator-name 551 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 552 regulator-min-microvolt = <2800000>;
558 regulator-max- 553 regulator-max-microvolt = <2800000>;
559 }; 554 };
560 555
561 ldo18_reg: LDO18 { 556 ldo18_reg: LDO18 {
562 regulator-name 557 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 558 regulator-min-microvolt = <1800000>;
564 regulator-max- 559 regulator-max-microvolt = <1800000>;
565 }; 560 };
566 561
567 ldo19_reg: LDO19 { 562 ldo19_reg: LDO19 {
568 regulator-name 563 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 564 regulator-min-microvolt = <1800000>;
570 regulator-max- 565 regulator-max-microvolt = <1800000>;
571 regulator-alwa 566 regulator-always-on;
572 }; 567 };
573 568
574 ldo20_reg: LDO20 { 569 ldo20_reg: LDO20 {
575 regulator-name 570 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 571 regulator-min-microvolt = <2800000>;
577 regulator-max- 572 regulator-max-microvolt = <2800000>;
578 regulator-alwa 573 regulator-always-on;
579 }; 574 };
580 575
581 ldo21_reg: LDO21 { 576 ldo21_reg: LDO21 {
582 regulator-name 577 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 578 regulator-min-microvolt = <1800000>;
584 regulator-max- 579 regulator-max-microvolt = <1800000>;
585 }; 580 };
586 581
587 ldo22_reg: LDO22 { 582 ldo22_reg: LDO22 {
588 regulator-name 583 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 584 regulator-min-microvolt = <1800000>;
590 regulator-max- 585 regulator-max-microvolt = <1800000>;
591 }; 586 };
592 587
593 ldo23_reg: LDO23 { 588 ldo23_reg: LDO23 {
594 regulator-name 589 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 590 regulator-min-microvolt = <1050000>;
596 regulator-max- 591 regulator-max-microvolt = <1050000>;
597 }; 592 };
598 593
599 ldo24_reg: LDO24 { 594 ldo24_reg: LDO24 {
600 regulator-name 595 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 596 regulator-min-microvolt = <1200000>;
602 regulator-max- 597 regulator-max-microvolt = <1200000>;
603 }; 598 };
604 599
605 ldo25_reg: LDO25 { 600 ldo25_reg: LDO25 {
606 regulator-name 601 regulator-name = "UNUSED_LDO25";
607 regulator-min- 602 regulator-min-microvolt = <2800000>;
608 regulator-max- 603 regulator-max-microvolt = <2800000>;
609 }; 604 };
610 605
611 ldo26_reg: LDO26 { 606 ldo26_reg: LDO26 {
612 regulator-name 607 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 608 regulator-min-microvolt = <2800000>;
614 regulator-max- 609 regulator-max-microvolt = <2800000>;
615 }; 610 };
616 611
617 ldo27_reg: LDO27 { 612 ldo27_reg: LDO27 {
618 regulator-name 613 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 614 regulator-min-microvolt = <3000000>;
620 regulator-max- 615 regulator-max-microvolt = <3000000>;
621 }; 616 };
622 617
623 ldo28_reg: LDO28 { 618 ldo28_reg: LDO28 {
624 regulator-name 619 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 620 regulator-min-microvolt = <1800000>;
626 regulator-max- 621 regulator-max-microvolt = <1800000>;
627 }; 622 };
628 623
629 ldo29_reg: LDO29 { 624 ldo29_reg: LDO29 {
630 regulator-name 625 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 626 regulator-min-microvolt = <3000000>;
632 regulator-max- 627 regulator-max-microvolt = <3000000>;
633 }; 628 };
634 629
635 ldo30_reg: LDO30 { 630 ldo30_reg: LDO30 {
636 regulator-name 631 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 632 regulator-min-microvolt = <3300000>;
638 regulator-max- 633 regulator-max-microvolt = <3300000>;
639 }; 634 };
640 635
641 ldo31_reg: LDO31 { 636 ldo31_reg: LDO31 {
642 /* 637 /*
643 * LDO31 diffe 638 * LDO31 differs from target to target,
644 * its definit 639 * its definition is in the .dts
645 */ 640 */
646 }; 641 };
647 642
648 ldo32_reg: LDO32 { 643 ldo32_reg: LDO32 {
649 regulator-name 644 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 645 regulator-min-microvolt = <1800000>;
651 regulator-max- 646 regulator-max-microvolt = <1800000>;
652 }; 647 };
653 648
654 ldo33_reg: LDO33 { 649 ldo33_reg: LDO33 {
655 regulator-name 650 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 651 regulator-min-microvolt = <2500000>;
657 regulator-max- 652 regulator-max-microvolt = <3300000>;
658 regulator-ramp 653 regulator-ramp-delay = <12500>;
659 }; 654 };
660 655
661 ldo34_reg: LDO34 { 656 ldo34_reg: LDO34 {
662 regulator-name 657 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 658 regulator-min-microvolt = <1000000>;
664 regulator-max- 659 regulator-max-microvolt = <2100000>;
665 }; 660 };
666 661
667 ldo35_reg: LDO35 { 662 ldo35_reg: LDO35 {
668 regulator-name 663 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 664 regulator-min-microvolt = <1800000>;
670 regulator-max- 665 regulator-max-microvolt = <2800000>;
671 }; 666 };
672 667
673 ldo36_reg: LDO36 { 668 ldo36_reg: LDO36 {
674 regulator-name 669 regulator-name = "VSIL_1.0V";
675 regulator-min- 670 regulator-min-microvolt = <1000000>;
676 regulator-max- 671 regulator-max-microvolt = <1000000>;
677 }; 672 };
678 673
679 ldo37_reg: LDO37 { 674 ldo37_reg: LDO37 {
680 regulator-name 675 regulator-name = "VF_1.8V";
681 regulator-min- 676 regulator-min-microvolt = <1800000>;
682 regulator-max- 677 regulator-max-microvolt = <1800000>;
683 }; 678 };
684 679
685 ldo38_reg: LDO38 { 680 ldo38_reg: LDO38 {
686 /* 681 /*
687 * LDO38 diffe 682 * LDO38 differs from target to target,
688 * its definit 683 * its definition is in the .dts
689 */ 684 */
690 }; 685 };
691 686
692 ldo39_reg: LDO39 { 687 ldo39_reg: LDO39 {
693 regulator-name 688 regulator-name = "V_HRM_1.8V";
694 regulator-min- 689 regulator-min-microvolt = <1800000>;
695 regulator-max- 690 regulator-max-microvolt = <1800000>;
696 }; 691 };
697 692
698 ldo40_reg: LDO40 { 693 ldo40_reg: LDO40 {
699 regulator-name 694 regulator-name = "V_HRM_3.3V";
700 regulator-min- 695 regulator-min-microvolt = <3300000>;
701 regulator-max- 696 regulator-max-microvolt = <3300000>;
702 }; 697 };
703 698
704 buck1_reg: BUCK1 { 699 buck1_reg: BUCK1 {
705 regulator-name 700 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 701 regulator-min-microvolt = <600000>;
707 regulator-max- 702 regulator-max-microvolt = <1500000>;
708 regulator-alwa 703 regulator-always-on;
709 regulator-stat 704 regulator-state-mem {
710 regula 705 regulator-off-in-suspend;
711 }; 706 };
712 }; 707 };
713 708
714 buck2_reg: BUCK2 { 709 buck2_reg: BUCK2 {
715 regulator-name 710 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 711 regulator-min-microvolt = <900000>;
717 regulator-max- 712 regulator-max-microvolt = <1300000>;
718 regulator-alwa 713 regulator-always-on;
719 regulator-stat 714 regulator-state-mem {
720 regula 715 regulator-off-in-suspend;
721 }; 716 };
722 }; 717 };
723 718
724 buck3_reg: BUCK3 { 719 buck3_reg: BUCK3 {
725 regulator-name 720 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 721 regulator-min-microvolt = <800000>;
727 regulator-max- 722 regulator-max-microvolt = <1200000>;
728 regulator-alwa 723 regulator-always-on;
729 regulator-stat 724 regulator-state-mem {
730 regula 725 regulator-off-in-suspend;
731 }; 726 };
732 }; 727 };
733 728
734 buck4_reg: BUCK4 { 729 buck4_reg: BUCK4 {
735 regulator-name 730 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 731 regulator-min-microvolt = <600000>;
737 regulator-max- 732 regulator-max-microvolt = <1500000>;
738 regulator-alwa 733 regulator-always-on;
739 regulator-stat 734 regulator-state-mem {
740 regula 735 regulator-off-in-suspend;
741 }; 736 };
742 }; 737 };
743 738
744 buck5_reg: BUCK5 { 739 buck5_reg: BUCK5 {
745 regulator-name 740 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 741 regulator-min-microvolt = <600000>;
747 regulator-max- 742 regulator-max-microvolt = <1500000>;
748 regulator-alwa 743 regulator-always-on;
749 regulator-stat 744 regulator-state-mem {
750 regula 745 regulator-off-in-suspend;
751 }; 746 };
752 }; 747 };
753 748
754 buck6_reg: BUCK6 { 749 buck6_reg: BUCK6 {
755 regulator-name 750 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 751 regulator-min-microvolt = <600000>;
757 regulator-max- 752 regulator-max-microvolt = <1500000>;
758 regulator-alwa 753 regulator-always-on;
759 regulator-stat 754 regulator-state-mem {
760 regula 755 regulator-off-in-suspend;
761 }; 756 };
762 }; 757 };
763 758
764 buck7_reg: BUCK7 { 759 buck7_reg: BUCK7 {
765 regulator-name 760 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 761 regulator-min-microvolt = <1200000>;
767 regulator-max- 762 regulator-max-microvolt = <1200000>;
768 regulator-alwa 763 regulator-always-on;
769 }; 764 };
770 765
771 buck8_reg: BUCK8 { 766 buck8_reg: BUCK8 {
772 regulator-name 767 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 768 regulator-min-microvolt = <1350000>;
774 regulator-max- 769 regulator-max-microvolt = <3300000>;
775 regulator-alwa 770 regulator-always-on;
776 }; 771 };
777 772
778 buck9_reg: BUCK9 { 773 buck9_reg: BUCK9 {
779 regulator-name 774 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 775 regulator-min-microvolt = <1350000>;
781 regulator-max- 776 regulator-max-microvolt = <3300000>;
782 regulator-alwa 777 regulator-always-on;
783 }; 778 };
784 779
785 buck10_reg: BUCK10 { 780 buck10_reg: BUCK10 {
786 regulator-name 781 regulator-name = "vdd_mem2";
787 regulator-min- 782 regulator-min-microvolt = <550000>;
788 regulator-max- 783 regulator-max-microvolt = <1500000>;
789 regulator-alwa 784 regulator-always-on;
790 }; 785 };
791 }; 786 };
792 }; 787 };
793 }; 788 };
794 789
795 &hsi2c_4 { 790 &hsi2c_4 {
796 status = "okay"; 791 status = "okay";
797 792
798 s3fwrn5: nfc@27 { 793 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 794 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 795 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 796 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ 797 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV !! 798 en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
804 wake-gpios = <&gpj0 2 GPIO_ACT 799 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 800 };
806 }; 801 };
807 802
808 &hsi2c_5 { 803 &hsi2c_5 {
809 status = "okay"; 804 status = "okay";
810 805
811 stmfts: touchscreen@49 { 806 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 807 compatible = "st,stmfts";
813 reg = <0x49>; 808 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 809 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 810 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 811 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 812 vdd-supply = <&ldo31_reg>;
818 }; 813 };
819 }; 814 };
820 815
821 &hsi2c_7 { 816 &hsi2c_7 {
822 status = "okay"; 817 status = "okay";
823 clock-frequency = <1000000>; 818 clock-frequency = <1000000>;
824 819
825 bridge@39 { 820 bridge@39 {
826 reg = <0x39>; 821 reg = <0x39>;
827 compatible = "sil,sii8620"; 822 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 823 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 824 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 825 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 826 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 827 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 828 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 829 clock-names = "xtal";
835 830
836 ports { 831 ports {
837 #address-cells = <1>; 832 #address-cells = <1>;
838 #size-cells = <0>; 833 #size-cells = <0>;
839 834
840 port@0 { 835 port@0 {
841 reg = <0>; 836 reg = <0>;
842 mhl_to_hdmi: e 837 mhl_to_hdmi: endpoint {
843 remote 838 remote-endpoint = <&hdmi_to_mhl>;
844 }; 839 };
845 }; 840 };
846 841
847 port@1 { 842 port@1 {
848 reg = <1>; 843 reg = <1>;
849 mhl_to_musb_co 844 mhl_to_musb_con: endpoint {
850 remote 845 remote-endpoint = <&musb_con_to_mhl>;
851 }; 846 };
852 }; 847 };
853 }; 848 };
854 }; 849 };
855 }; 850 };
856 851
857 &hsi2c_8 { 852 &hsi2c_8 {
858 status = "okay"; 853 status = "okay";
859 854
860 pmic@66 { 855 pmic@66 {
861 compatible = "maxim,max77843"; 856 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 857 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 858 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 859 reg = <0x66>;
865 860
866 muic: extcon { 861 muic: extcon {
867 compatible = "maxim,ma 862 compatible = "maxim,max77843-muic";
868 863
869 musb_con: connector { 864 musb_con: connector {
870 compatible = " 865 compatible = "samsung,usb-connector-11pin",
871 " 866 "usb-b-connector";
872 label = "micro 867 label = "micro-USB";
873 type = "micro" 868 type = "micro";
874 869
875 ports { 870 ports {
876 #addre 871 #address-cells = <1>;
877 #size- 872 #size-cells = <0>;
878 873
879 port@0 874 port@0 {
880 875 /*
881 876 * TODO: The DTS this is based on does not have
882 877 * port@0 which is a required property. The ports
883 878 * look incomplete and need fixing.
884 879 * Add a disabled port just to satisfy dtschema.
885 880 */
886 881 reg = <0>;
887 882 status = "disabled";
888 }; 883 };
889 884
890 port@3 885 port@3 {
891 886 reg = <3>;
892 887 musb_con_to_mhl: endpoint {
893 888 remote-endpoint = <&mhl_to_musb_con>;
894 889 };
895 }; 890 };
896 }; 891 };
897 }; 892 };
898 893
899 ports { 894 ports {
900 port { 895 port {
901 muic_t 896 muic_to_usb: endpoint {
902 897 remote-endpoint = <&usb_to_muic>;
903 }; 898 };
904 }; 899 };
905 }; 900 };
906 }; 901 };
907 902
908 regulators { 903 regulators {
909 compatible = "maxim,ma 904 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 905 safeout1_reg: SAFEOUT1 {
911 regulator-name 906 regulator-name = "SAFEOUT1";
912 regulator-min- 907 regulator-min-microvolt = <3300000>;
913 regulator-max- 908 regulator-max-microvolt = <4950000>;
914 }; 909 };
915 910
916 safeout2_reg: SAFEOUT2 911 safeout2_reg: SAFEOUT2 {
917 regulator-name 912 regulator-name = "SAFEOUT2";
918 regulator-min- 913 regulator-min-microvolt = <3300000>;
919 regulator-max- 914 regulator-max-microvolt = <4950000>;
920 }; 915 };
921 916
922 charger_reg: CHARGER { 917 charger_reg: CHARGER {
923 regulator-name 918 regulator-name = "CHARGER";
924 regulator-min- 919 regulator-min-microamp = <100000>;
925 regulator-max- 920 regulator-max-microamp = <3150000>;
926 }; 921 };
927 }; 922 };
928 923
929 haptic: motor-driver { 924 haptic: motor-driver {
930 compatible = "maxim,ma 925 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 926 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 927 pwms = <&pwm 0 33670 0>;
>> 928 pwm-names = "haptic";
933 }; 929 };
934 }; 930 };
935 }; 931 };
936 932
937 &hsi2c_11 { 933 &hsi2c_11 {
938 status = "okay"; 934 status = "okay";
939 }; 935 };
940 936
941 &i2s0 { 937 &i2s0 {
942 status = "okay"; 938 status = "okay";
943 }; 939 };
944 940
945 &i2s1 { 941 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 942 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 943 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 944 status = "okay";
949 }; 945 };
950 946
951 &mshc_0 { 947 &mshc_0 {
952 status = "okay"; 948 status = "okay";
953 mmc-ddr-1_8v; <<
954 mmc-hs200-1_8v; 949 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 950 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 951 cap-mmc-highspeed;
957 non-removable; 952 non-removable;
958 card-detect-delay = <200>; 953 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 954 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 955 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 956 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 957 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 958 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 959 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 960 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 961 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 962 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 963 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 964 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 965 assigned-clock-rates = <800000000>;
971 }; 966 };
972 967
973 &mshc_2 { 968 &mshc_2 {
974 status = "okay"; 969 status = "okay";
975 cap-sd-highspeed; 970 cap-sd-highspeed;
976 disable-wp; 971 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 972 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 973 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 974 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 975 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 976 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 977 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 978 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 979 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 980 bus-width = <4>;
986 }; 981 };
987 982
988 &pcie { 983 &pcie {
989 status = "okay"; 984 status = "okay";
990 pinctrl-names = "default"; 985 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 986 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>; 987 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>; 988 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ 989 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
995 <&cmu_top CLK_MOUT_S 990 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK 991 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK 992 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
998 assigned-clock-rates = <0>, <100000000 993 assigned-clock-rates = <0>, <100000000>;
999 interrupt-map-mask = <0 0 0 0>; 994 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 995 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1001 }; 996 };
1002 997
1003 &pcie_phy { 998 &pcie_phy {
1004 status = "okay"; 999 status = "okay";
1005 }; 1000 };
1006 1001
1007 &ppmu_d0_general { 1002 &ppmu_d0_general {
1008 status = "okay"; 1003 status = "okay";
1009 events { 1004 events {
1010 ppmu_event0_d0_general: ppmu- 1005 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 1006 event-name = "ppmu-event0-d0-general";
1012 }; 1007 };
1013 }; 1008 };
1014 }; 1009 };
1015 1010
1016 &ppmu_d1_general { 1011 &ppmu_d1_general {
1017 status = "okay"; 1012 status = "okay";
1018 events { 1013 events {
1019 ppmu_event0_d1_general: ppmu- 1014 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 1015 event-name = "ppmu-event0-d1-general";
1021 }; 1016 };
1022 }; 1017 };
1023 }; 1018 };
1024 1019
1025 &pinctrl_alive { 1020 &pinctrl_alive {
1026 pinctrl-names = "default"; 1021 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 1022 pinctrl-0 = <&initial_alive>;
1028 1023
1029 initial_alive: initial-state { 1024 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 1025 PIN_IN(gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 1026 PIN_IN(gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 1027 PIN_IN(gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 1028 PIN_IN(gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 1029 PIN_IN(gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 1030 PIN_IN(gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 1031 PIN_IN(gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 1032 PIN_IN(gpa0-7, NONE, FAST_SR1);
1038 1033
1039 PIN_IN(gpa1-0, UP, FAST_SR1); 1034 PIN_IN(gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); 1035 PIN_IN(gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 1036 PIN_IN(gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 1037 PIN_IN(gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 1038 PIN_IN(gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 1039 PIN_IN(gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 1040 PIN_IN(gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 1041 PIN_IN(gpa1-7, NONE, FAST_SR1);
1047 1042
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 1043 PIN_IN(gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 1044 PIN_IN(gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 1045 PIN_IN(gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 1046 PIN_IN(gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 1047 PIN_IN(gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 1048 PIN_IN(gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 1049 PIN_IN(gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 1050 PIN_IN(gpa2-7, NONE, FAST_SR1);
1056 1051
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 1052 PIN_IN(gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 1053 PIN_IN(gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 1054 PIN_IN(gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 1055 PIN_IN(gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 1056 PIN_IN(gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 1057 PIN_IN(gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 1058 PIN_IN(gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 1059 PIN_IN(gpa3-7, DOWN, FAST_SR1);
1065 1060
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 1061 PIN_IN(gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 1062 PIN_IN(gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 1063 PIN_IN(gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); 1064 PIN_IN(gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 1065 PIN_OT(gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 1066 PIN_IN(gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 1067 PIN_IN(gpf1-7, DOWN, FAST_SR1);
1073 1068
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 1069 PIN_IN(gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 1070 PIN_IN(gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 1071 PIN_IN(gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 1072 PIN_IN(gpf2-3, DOWN, FAST_SR1);
1078 1073
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 1074 PIN_IN(gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 1075 PIN_IN(gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 1076 PIN_IN(gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 1077 PIN_IN(gpf3-3, DOWN, FAST_SR1);
1083 1078
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 1079 PIN_IN(gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 1080 PIN_IN(gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 1081 PIN_IN(gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 1082 PIN_IN(gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 1083 PIN_IN(gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 1084 PIN_IN(gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 1085 PIN_IN(gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 1086 PIN_IN(gpf4-7, DOWN, FAST_SR1);
1092 1087
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 1088 PIN_IN(gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 1089 PIN_IN(gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 1090 PIN_IN(gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 1091 PIN_IN(gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 1092 PIN_OT(gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 1093 PIN_IN(gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 1094 PIN_IN(gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 1095 PIN_IN(gpf5-7, DOWN, FAST_SR1);
1101 }; 1096 };
1102 1097
1103 te_irq: te-irq-pins { 1098 te_irq: te-irq-pins {
1104 samsung,pins = "gpf1-3"; 1099 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 1100 samsung,pin-function = <0xf>;
1106 }; 1101 };
1107 }; 1102 };
1108 1103
1109 &pinctrl_cpif { 1104 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1105 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1106 pinctrl-0 = <&initial_cpif>;
1112 1107
1113 initial_cpif: initial-state { 1108 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 1109 PIN_IN(gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 1110 PIN_IN(gpv6-1, DOWN, FAST_SR1);
1116 }; 1111 };
1117 }; 1112 };
1118 1113
1119 &pinctrl_ese { 1114 &pinctrl_ese {
1120 pinctrl-names = "default"; 1115 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1116 pinctrl-0 = <&initial_ese>;
1122 1117
1123 pcie_wlanen: pcie-wlanen-pins { 1118 pcie_wlanen: pcie-wlanen-pins {
1124 samsung,pins = "gpj2-0"; 1119 samsung,pins = "gpj2-0";
1125 samsung,pin-function = <EXYNO 1120 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1126 samsung,pin-pud = <EXYNOS_PIN 1121 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1127 samsung,pin-drv = <EXYNOS5433 1122 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
1128 }; 1123 };
1129 1124
1130 initial_ese: initial-state { 1125 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 1126 PIN_IN(gpj2-1, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 1127 PIN_IN(gpj2-2, DOWN, FAST_SR1);
1133 }; 1128 };
1134 }; 1129 };
1135 1130
1136 &pinctrl_fsys { 1131 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1132 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1133 pinctrl-0 = <&initial_fsys>;
1139 1134
1140 initial_fsys: initial-state { 1135 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 1136 PIN_IN(gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 1137 PIN_IN(gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 1138 PIN_IN(gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 1139 PIN_IN(gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 1140 PIN_IN(gpr3-7, NONE, FAST_SR1);
1146 }; 1141 };
1147 }; 1142 };
1148 1143
1149 &pinctrl_imem { 1144 &pinctrl_imem {
1150 pinctrl-names = "default"; 1145 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1146 pinctrl-0 = <&initial_imem>;
1152 1147
1153 initial_imem: initial-state { 1148 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); 1149 PIN_IN(gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); 1150 PIN_IN(gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 1151 PIN_IN(gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); 1152 PIN_IN(gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 1153 PIN_IN(gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 1154 PIN_IN(gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 1155 PIN_IN(gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); 1156 PIN_IN(gpf0-7, UP, FAST_SR1);
1162 }; 1157 };
1163 }; 1158 };
1164 1159
1165 &pinctrl_nfc { 1160 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1161 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1162 pinctrl-0 = <&initial_nfc>;
1168 1163
1169 initial_nfc: initial-state { 1164 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 1165 PIN_IN(gpj0-2, DOWN, FAST_SR1);
1171 }; 1166 };
1172 }; 1167 };
1173 1168
1174 &pinctrl_peric { 1169 &pinctrl_peric {
1175 pinctrl-names = "default"; 1170 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1171 pinctrl-0 = <&initial_peric>;
1177 1172
1178 initial_peric: initial-state { 1173 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 1174 PIN_IN(gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 1175 PIN_IN(gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 1176 PIN_IN(gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 1177 PIN_IN(gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 1178 PIN_IN(gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 1179 PIN_IN(gpv7-5, DOWN, FAST_SR1);
1185 1180
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 1181 PIN_IN(gpb0-4, DOWN, FAST_SR1);
1187 1182
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 1183 PIN_IN(gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 1184 PIN_IN(gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 1185 PIN_IN(gpc0-7, DOWN, FAST_SR1);
1191 1186
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 1187 PIN_IN(gpc1-1, DOWN, FAST_SR1);
1193 1188
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 1189 PIN_IN(gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 1190 PIN_IN(gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 1191 PIN_IN(gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 1192 PIN_IN(gpc3-7, NONE, FAST_SR1);
1198 1193
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 1194 PIN_OT(gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 1195 PIN_F2(gpg0-1, DOWN, FAST_SR1);
1201 1196
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 1197 PIN_IN(gpd2-5, DOWN, FAST_SR1);
1203 1198
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 1199 PIN_IN(gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 1200 PIN_IN(gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 1201 PIN_IN(gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 1202 PIN_IN(gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 1203 PIN_IN(gpd4-4, DOWN, FAST_SR1);
1209 1204
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 1205 PIN_IN(gpd6-3, DOWN, FAST_SR1);
1211 1206
1212 PIN_IN(gpd8-1, UP, FAST_SR1); 1207 PIN_IN(gpd8-1, UP, FAST_SR1);
1213 1208
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 1209 PIN_IN(gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 1210 PIN_IN(gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 1211 PIN_IN(gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 1212 PIN_IN(gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 1213 PIN_IN(gpg1-4, DOWN, FAST_SR1);
1219 1214
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 1215 PIN_IN(gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 1216 PIN_IN(gpg2-1, DOWN, FAST_SR1);
1222 1217
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 1218 PIN_IN(gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 1219 PIN_IN(gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 1220 PIN_IN(gpg3-5, DOWN, FAST_SR1);
1226 }; 1221 };
1227 }; 1222 };
1228 1223
1229 &pinctrl_touch { 1224 &pinctrl_touch {
1230 pinctrl-names = "default"; 1225 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1226 pinctrl-0 = <&initial_touch>;
1232 1227
1233 initial_touch: initial-state { 1228 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 1229 PIN_IN(gpj1-2, DOWN, FAST_SR1);
1235 }; 1230 };
1236 }; 1231 };
1237 1232
1238 &pwm { 1233 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1234 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1235 pinctrl-names = "default";
1241 status = "okay"; 1236 status = "okay";
1242 }; 1237 };
1243 1238
1244 &mic { 1239 &mic {
1245 status = "okay"; 1240 status = "okay";
1246 }; 1241 };
1247 1242
1248 &pmu_system_controller { 1243 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1244 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1245 assigned-clock-parents = <&xxti>;
1251 }; 1246 };
1252 1247
1253 &serial_1 { 1248 &serial_1 {
1254 status = "okay"; 1249 status = "okay";
1255 }; 1250 };
1256 1251
1257 &serial_3 { 1252 &serial_3 {
1258 status = "okay"; 1253 status = "okay";
1259 1254
1260 bluetooth { 1255 bluetooth {
1261 compatible = "brcm,bcm43438-b 1256 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1257 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1258 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1259 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1260 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1261 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1262 clock-names = "extclk";
1268 }; 1263 };
1269 }; 1264 };
1270 1265
1271 &spi_1 { 1266 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1267 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1268 status = "okay";
1274 1269
1275 wm5110: audio-codec@0 { 1270 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110"; 1271 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1272 reg = <0x0>;
1278 spi-max-frequency = <20000000 1273 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1274 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1275 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1276 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1277 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1278 clock-names = "mclk1", "mclk2";
1284 1279
1285 gpio-controller; 1280 gpio-controller;
1286 #gpio-cells = <2>; 1281 #gpio-cells = <2>;
1287 interrupt-controller; <<
1288 #interrupt-cells = <2>; <<
1289 1282
1290 wlf,micd-detect-debounce = <3 1283 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1284 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1285 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; !! 1286 wlf,micd-dbtime = <0x1>;
1294 wlf,micd-force-micbias; 1287 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1288 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1289 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1290 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1291 wlf,inmode = <2 0 2 0>;
1299 1292
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1293 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1294 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1295
1303 /* core supplies */ 1296 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1297 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1298 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1299 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1300 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1301 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re <<
1310 SPKVDDR-supply = <&vph_pwr_re <<
1311 1302
1312 controller-data { 1303 controller-data {
1313 samsung,spi-feedback- 1304 samsung,spi-feedback-delay = <0>;
1314 }; 1305 };
1315 }; 1306 };
1316 }; 1307 };
1317 1308
1318 &spi_3 { 1309 &spi_3 {
1319 status = "okay"; 1310 status = "okay";
1320 no-cs-readback; 1311 no-cs-readback;
1321 1312
1322 irled@0 { 1313 irled@0 {
1323 compatible = "ir-spi-led"; 1314 compatible = "ir-spi-led";
1324 reg = <0x0>; 1315 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1316 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1317 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; !! 1318 duty-cycle = <60>;
1328 led-active-low; 1319 led-active-low;
1329 1320
1330 controller-data { 1321 controller-data {
1331 samsung,spi-feedback- 1322 samsung,spi-feedback-delay = <0>;
1332 }; 1323 };
1333 }; 1324 };
1334 }; 1325 };
1335 1326
1336 &timer { 1327 &timer {
1337 clock-frequency = <24000000>; 1328 clock-frequency = <24000000>;
1338 }; 1329 };
1339 1330
1340 &tmu_atlas0 { 1331 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1332 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1333 status = "okay";
1343 }; 1334 };
1344 1335
1345 &tmu_apollo { 1336 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1337 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1338 status = "okay";
1348 }; 1339 };
1349 1340
1350 &tmu_g3d { 1341 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1342 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1343 status = "okay";
1353 }; 1344 };
1354 1345
1355 &usbdrd30 { 1346 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1347 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1348 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1349 status = "okay";
1359 }; 1350 };
1360 1351
1361 &usbdrd_dwc3 { 1352 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1353 dr_mode = "otg";
1363 }; 1354 };
1364 1355
1365 &usbdrd30_phy { 1356 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1357 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1358 status = "okay";
1368 1359
1369 port { 1360 port {
1370 usb_to_muic: endpoint { 1361 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1362 remote-endpoint = <&muic_to_usb>;
1372 }; 1363 };
1373 }; 1364 };
1374 }; 1365 };
1375 1366
1376 &xxti { 1367 &xxti {
1377 clock-frequency = <24000000>; 1368 clock-frequency = <24000000>;
1378 }; 1369 };
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