1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so !! 3 * SAMSUNG Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; <<
25 mmc2 = &mshc_2; <<
26 pinctrl0 = &pinctrl_alive; 24 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 25 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 26 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 27 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 28 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 29 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 30 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 31 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 32 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 33 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 34 serial0 = &serial_0;
37 serial1 = &serial_1; 35 serial1 = &serial_1;
38 serial2 = &serial_2; 36 serial2 = &serial_2;
39 serial3 = &serial_3; 37 serial3 = &serial_3;
40 spi0 = &spi_0; 38 spi0 = &spi_0;
41 spi1 = &spi_1; 39 spi1 = &spi_1;
42 spi2 = &spi_2; 40 spi2 = &spi_2;
43 spi3 = &spi_3; 41 spi3 = &spi_3;
44 spi4 = &spi_4; 42 spi4 = &spi_4;
>> 43 mshc0 = &mshc_0;
>> 44 mshc2 = &mshc_2;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI !! 90 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
91 scl-gpios = <&gpd0 0 GPIO_ACTI !! 91 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
>> 95 status = "okay";
95 96
96 max98504: amplifier@31 { !! 97 max98504: max98504@31 {
97 compatible = "maxim,ma 98 compatible = "maxim,max98504";
98 reg = <0x31>; 99 reg = <0x31>;
99 !! 100 maxim,rx-path = <1>;
100 DIOVDD-supply = <&ldo3 !! 101 maxim,tx-path = <1>;
101 DVDD-supply = <&ldo3_r !! 102 maxim,tx-channel-mask = <3>;
102 PVDD-supply = <&vph_pw !! 103 maxim,tx-channel-source = <2>;
103 }; 104 };
104 }; 105 };
105 106
106 vph_pwr_regulator: regulator-vph-pwr { !! 107 irda_regulator: irda-regulator {
107 compatible = "regulator-fixed" <<
108 regulator-name = "VPH_PWR"; <<
109 regulator-min-microvolt = <420 <<
110 regulator-max-microvolt = <420 <<
111 }; <<
112 <<
113 irda_regulator: regulator-irda { <<
114 compatible = "regulator-fixed" 108 compatible = "regulator-fixed";
115 enable-active-high; 109 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 110 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 111 regulator-name = "irda_regulator";
118 }; 112 };
119 113
120 sound { 114 sound {
121 compatible = "samsung,tm2-audi 115 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 116 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 117 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 118 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 119 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 120 model = "wm5110";
127 audio-routing = /* Headphone * !! 121 samsung,audio-routing =
128 "HP", "HPOUT1L !! 122 /* Headphone */
129 "HP", "HPOUT1R !! 123 "HP", "HPOUT1L",
130 !! 124 "HP", "HPOUT1R",
131 /* Speaker */ !! 125
132 "SPK", "SPKOUT !! 126 /* Speaker */
133 "SPKOUT", "HPO !! 127 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 128 "SPKOUT", "HPOUT2L",
135 !! 129 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 130
137 "RCV", "HPOUT3 !! 131 /* Receiver */
138 "RCV", "HPOUT3 !! 132 "RCV", "HPOUT3L",
>> 133 "RCV", "HPOUT3R";
>> 134 status = "okay";
139 }; 135 };
140 }; 136 };
141 137
142 &adc { 138 &adc {
143 vdd-supply = <&ldo3_reg>; 139 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 140 status = "okay";
145 141
146 thermistor-ap { 142 thermistor-ap {
147 compatible = "murata,ncp03wf10 143 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 144 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 145 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 146 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 147 io-channels = <&adc 0>;
152 }; 148 };
153 149
154 thermistor-battery { 150 thermistor-battery {
155 compatible = "murata,ncp03wf10 151 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 152 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 153 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 154 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 155 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 156 #thermal-sensor-cells = <0>;
161 }; 157 };
162 158
163 thermistor-charger { 159 thermistor-charger {
164 compatible = "murata,ncp03wf10 160 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 161 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 162 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 163 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 164 io-channels = <&adc 2>;
169 }; 165 };
170 }; 166 };
171 167
172 &bus_g2d_400 { 168 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 169 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 170 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 171 exynos,saturation-ratio = <10>;
176 status = "okay"; 172 status = "okay";
177 }; 173 };
178 174
179 &bus_g2d_266 { 175 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 176 devfreq = <&bus_g2d_400>;
181 status = "okay"; 177 status = "okay";
182 }; 178 };
183 179
184 &bus_gscl { 180 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 181 devfreq = <&bus_g2d_400>;
186 status = "okay"; 182 status = "okay";
187 }; 183 };
188 184
189 &bus_hevc { 185 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 186 devfreq = <&bus_g2d_400>;
191 status = "okay"; 187 status = "okay";
192 }; 188 };
193 189
194 &bus_jpeg { 190 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 191 devfreq = <&bus_g2d_400>;
196 status = "okay"; 192 status = "okay";
197 }; 193 };
198 194
199 &bus_mfc { 195 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 196 devfreq = <&bus_g2d_400>;
201 status = "okay"; 197 status = "okay";
202 }; 198 };
203 199
204 &bus_mscl { 200 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 201 devfreq = <&bus_g2d_400>;
206 status = "okay"; 202 status = "okay";
207 }; 203 };
208 204
209 &bus_noc0 { 205 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 206 devfreq = <&bus_g2d_400>;
211 status = "okay"; 207 status = "okay";
212 }; 208 };
213 209
214 &bus_noc1 { 210 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 211 devfreq = <&bus_g2d_400>;
216 status = "okay"; 212 status = "okay";
217 }; 213 };
218 214
219 &bus_noc2 { 215 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 216 devfreq = <&bus_g2d_400>;
221 status = "okay"; 217 status = "okay";
222 }; 218 };
223 219
224 &cmu_aud { 220 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 221 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 222 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 223 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 224 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 225 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 226 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 227 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 228 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 229
234 <&cmu_aud CLK_DIV_AUD_CA5>, 230 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 231 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 232 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 233 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 234 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 235 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 236 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 237 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 238 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 239 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 240 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 241
246 assigned-clock-parents = <&cmu_top CLK 242 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 243 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 244 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 245 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 246 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 247 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 248 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 249 <&cmu_top CLK_SCLK_AUDIO0>;
254 250
255 assigned-clock-rates = <0>, <0>, <0>, 251 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 252 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 253 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 254 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 255 };
260 256
261 &cmu_fsys { 257 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 258 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 259 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 260 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 261 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 262 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 263 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 264 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 265 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 266 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 267 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 268 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 269 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 270 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 271 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 272 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 273 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 274 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 275 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 276 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 277 <66700000>, <66700000>;
282 }; 278 };
283 279
284 &cmu_gscl { 280 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 281 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 282 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 283 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 284 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 285 };
290 286
291 &cmu_mfc { 287 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 288 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 289 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 290 };
295 291
296 &cmu_mif { 292 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 293 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 294 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 295 assigned-clock-rates = <0>, <333000000>;
300 }; 296 };
301 297
302 &cmu_mscl { 298 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 299 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 300 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 301 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 302 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 303 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 304 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 305 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 306 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 307 };
312 308
313 &cmu_top { 309 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 310 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 311 assigned-clock-rates = <196608001>;
316 }; 312 };
317 313
318 &cpu0 { 314 &cpu0 {
319 cpu-supply = <&buck3_reg>; 315 cpu-supply = <&buck3_reg>;
320 }; 316 };
321 317
322 &cpu4 { 318 &cpu4 {
323 cpu-supply = <&buck2_reg>; 319 cpu-supply = <&buck2_reg>;
324 }; 320 };
325 321
326 &decon { 322 &decon {
327 status = "okay"; 323 status = "okay";
328 }; 324 };
329 325
330 &decon_tv { 326 &decon_tv {
331 status = "okay"; 327 status = "okay";
332 328
333 ports { 329 ports {
334 #address-cells = <1>; 330 #address-cells = <1>;
335 #size-cells = <0>; 331 #size-cells = <0>;
336 332
337 port@0 { 333 port@0 {
338 reg = <0>; 334 reg = <0>;
339 tv_to_hdmi: endpoint { 335 tv_to_hdmi: endpoint {
340 remote-endpoin 336 remote-endpoint = <&hdmi_to_tv>;
341 }; 337 };
342 }; 338 };
343 }; 339 };
344 }; 340 };
345 341
346 &dsi { 342 &dsi {
347 status = "okay"; 343 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 344 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 345 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 346 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 347 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 348 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 349 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 350 pinctrl-0 = <&te_irq>;
355 }; 351 };
356 352
357 &gpu { <<
358 mali-supply = <&buck6_reg>; <<
359 status = "okay"; <<
360 }; <<
361 <<
362 &hdmi { 353 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 354 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 355 status = "okay";
365 vdd-supply = <&ldo6_reg>; 356 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 357 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 358 vdd_pll-supply = <&ldo6_reg>;
368 359
369 ports { 360 ports {
370 #address-cells = <1>; 361 #address-cells = <1>;
371 #size-cells = <0>; 362 #size-cells = <0>;
372 363
373 port@0 { 364 port@0 {
374 reg = <0>; 365 reg = <0>;
375 hdmi_to_tv: endpoint { 366 hdmi_to_tv: endpoint {
376 remote-endpoin 367 remote-endpoint = <&tv_to_hdmi>;
377 }; 368 };
378 }; 369 };
379 370
380 port@1 { 371 port@1 {
381 reg = <1>; 372 reg = <1>;
382 hdmi_to_mhl: endpoint 373 hdmi_to_mhl: endpoint {
383 remote-endpoin 374 remote-endpoint = <&mhl_to_hdmi>;
384 }; 375 };
385 }; 376 };
386 }; 377 };
387 }; 378 };
388 379
389 &hsi2c_0 { 380 &hsi2c_0 {
390 status = "okay"; 381 status = "okay";
391 clock-frequency = <2500000>; 382 clock-frequency = <2500000>;
392 383
393 pmic@66 { !! 384 s2mps13-pmic@66 {
394 compatible = "samsung,s2mps13- 385 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 386 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL !! 387 interrupts = <7 IRQ_TYPE_NONE>;
397 reg = <0x66>; 388 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 389 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; <<
400 390
401 s2mps13_osc: clocks { 391 s2mps13_osc: clocks {
402 compatible = "samsung, 392 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 393 #clock-cells = <1>;
404 clock-output-names = " 394 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 395 "s2mps13_bt";
406 }; 396 };
407 397
408 regulators { 398 regulators {
409 ldo1_reg: LDO1 { 399 ldo1_reg: LDO1 {
410 regulator-name 400 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 401 regulator-min-microvolt = <900000>;
412 regulator-max- 402 regulator-max-microvolt = <900000>;
413 regulator-alwa 403 regulator-always-on;
414 }; 404 };
415 405
416 ldo2_reg: LDO2 { 406 ldo2_reg: LDO2 {
417 regulator-name 407 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 408 regulator-min-microvolt = <2800000>;
419 regulator-max- 409 regulator-max-microvolt = <2800000>;
420 regulator-alwa 410 regulator-always-on;
421 regulator-stat 411 regulator-state-mem {
422 regula 412 regulator-off-in-suspend;
423 }; 413 };
424 }; 414 };
425 415
426 ldo3_reg: LDO3 { 416 ldo3_reg: LDO3 {
427 regulator-name 417 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 418 regulator-min-microvolt = <1800000>;
429 regulator-max- 419 regulator-max-microvolt = <1800000>;
430 regulator-alwa 420 regulator-always-on;
431 }; 421 };
432 422
433 ldo4_reg: LDO4 { 423 ldo4_reg: LDO4 {
434 regulator-name 424 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 425 regulator-min-microvolt = <1300000>;
436 regulator-max- 426 regulator-max-microvolt = <1300000>;
437 regulator-alwa 427 regulator-always-on;
438 regulator-stat 428 regulator-state-mem {
439 regula 429 regulator-off-in-suspend;
440 }; 430 };
441 }; 431 };
442 432
443 ldo5_reg: LDO5 { 433 ldo5_reg: LDO5 {
444 regulator-name 434 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 435 regulator-min-microvolt = <1000000>;
446 regulator-max- 436 regulator-max-microvolt = <1000000>;
447 regulator-alwa 437 regulator-always-on;
448 regulator-stat 438 regulator-state-mem {
449 regula 439 regulator-off-in-suspend;
450 }; 440 };
451 }; 441 };
452 442
453 ldo6_reg: LDO6 { 443 ldo6_reg: LDO6 {
454 regulator-name 444 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 445 regulator-min-microvolt = <1000000>;
456 regulator-max- 446 regulator-max-microvolt = <1000000>;
457 regulator-stat 447 regulator-state-mem {
458 regula 448 regulator-off-in-suspend;
459 }; 449 };
460 }; 450 };
461 451
462 ldo7_reg: LDO7 { 452 ldo7_reg: LDO7 {
463 regulator-name 453 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 454 regulator-min-microvolt = <1800000>;
465 regulator-max- 455 regulator-max-microvolt = <1800000>;
466 regulator-alwa 456 regulator-always-on;
467 regulator-stat 457 regulator-state-mem {
468 regula 458 regulator-off-in-suspend;
469 }; 459 };
470 }; 460 };
471 461
472 ldo8_reg: LDO8 { 462 ldo8_reg: LDO8 {
473 regulator-name 463 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 464 regulator-min-microvolt = <1800000>;
475 regulator-max- 465 regulator-max-microvolt = <1800000>;
476 regulator-alwa 466 regulator-always-on;
477 regulator-stat 467 regulator-state-mem {
478 regula 468 regulator-off-in-suspend;
479 }; 469 };
480 }; 470 };
481 471
482 ldo9_reg: LDO9 { 472 ldo9_reg: LDO9 {
483 regulator-name 473 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 474 regulator-min-microvolt = <1800000>;
485 regulator-max- 475 regulator-max-microvolt = <1800000>;
486 regulator-alwa 476 regulator-always-on;
487 regulator-stat 477 regulator-state-mem {
488 regula 478 regulator-off-in-suspend;
489 }; 479 };
490 }; 480 };
491 481
492 ldo10_reg: LDO10 { 482 ldo10_reg: LDO10 {
493 regulator-name 483 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 484 regulator-min-microvolt = <3000000>;
495 regulator-max- 485 regulator-max-microvolt = <3000000>;
496 regulator-stat 486 regulator-state-mem {
497 regula 487 regulator-off-in-suspend;
498 }; 488 };
499 }; 489 };
500 490
501 ldo11_reg: LDO11 { 491 ldo11_reg: LDO11 {
502 regulator-name 492 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 493 regulator-min-microvolt = <1000000>;
504 regulator-max- 494 regulator-max-microvolt = <1000000>;
505 regulator-alwa 495 regulator-always-on;
506 regulator-stat 496 regulator-state-mem {
507 regula 497 regulator-off-in-suspend;
508 }; 498 };
509 }; 499 };
510 500
511 ldo12_reg: LDO12 { 501 ldo12_reg: LDO12 {
512 regulator-name 502 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 503 regulator-min-microvolt = <800000>;
514 regulator-max- 504 regulator-max-microvolt = <1350000>;
515 regulator-alwa 505 regulator-always-on;
516 }; 506 };
517 507
518 ldo13_reg: LDO13 { 508 ldo13_reg: LDO13 {
519 regulator-name 509 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 510 regulator-min-microvolt = <950000>;
521 regulator-max- 511 regulator-max-microvolt = <950000>;
522 regulator-alwa 512 regulator-always-on;
523 regulator-stat 513 regulator-state-mem {
524 regula 514 regulator-off-in-suspend;
525 }; 515 };
526 }; 516 };
527 517
528 ldo14_reg: LDO14 { 518 ldo14_reg: LDO14 {
529 regulator-name 519 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 520 regulator-min-microvolt = <1200000>;
531 regulator-max- 521 regulator-max-microvolt = <1200000>;
532 regulator-alwa 522 regulator-always-on;
533 regulator-stat 523 regulator-state-mem {
534 regula 524 regulator-off-in-suspend;
535 }; 525 };
536 }; 526 };
537 527
538 ldo15_reg: LDO15 { 528 ldo15_reg: LDO15 {
539 regulator-name 529 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 530 regulator-min-microvolt = <1200000>;
541 regulator-max- 531 regulator-max-microvolt = <1200000>;
542 regulator-alwa 532 regulator-always-on;
543 regulator-stat 533 regulator-state-mem {
544 regula 534 regulator-off-in-suspend;
545 }; 535 };
546 }; 536 };
547 537
548 ldo16_reg: LDO16 { 538 ldo16_reg: LDO16 {
549 regulator-name 539 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 540 regulator-min-microvolt = <1400000>;
551 regulator-max- 541 regulator-max-microvolt = <3400000>;
552 regulator-alwa 542 regulator-always-on;
553 }; 543 };
554 544
555 ldo17_reg: LDO17 { 545 ldo17_reg: LDO17 {
556 regulator-name 546 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 547 regulator-min-microvolt = <2800000>;
558 regulator-max- 548 regulator-max-microvolt = <2800000>;
559 }; 549 };
560 550
561 ldo18_reg: LDO18 { 551 ldo18_reg: LDO18 {
562 regulator-name 552 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 553 regulator-min-microvolt = <1800000>;
564 regulator-max- 554 regulator-max-microvolt = <1800000>;
565 }; 555 };
566 556
567 ldo19_reg: LDO19 { 557 ldo19_reg: LDO19 {
568 regulator-name 558 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 559 regulator-min-microvolt = <1800000>;
570 regulator-max- 560 regulator-max-microvolt = <1800000>;
571 regulator-alwa 561 regulator-always-on;
572 }; 562 };
573 563
574 ldo20_reg: LDO20 { 564 ldo20_reg: LDO20 {
575 regulator-name 565 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 566 regulator-min-microvolt = <2800000>;
577 regulator-max- 567 regulator-max-microvolt = <2800000>;
578 regulator-alwa 568 regulator-always-on;
579 }; 569 };
580 570
581 ldo21_reg: LDO21 { 571 ldo21_reg: LDO21 {
582 regulator-name 572 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 573 regulator-min-microvolt = <1800000>;
584 regulator-max- 574 regulator-max-microvolt = <1800000>;
585 }; 575 };
586 576
587 ldo22_reg: LDO22 { 577 ldo22_reg: LDO22 {
588 regulator-name 578 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 579 regulator-min-microvolt = <1800000>;
590 regulator-max- 580 regulator-max-microvolt = <1800000>;
591 }; 581 };
592 582
593 ldo23_reg: LDO23 { 583 ldo23_reg: LDO23 {
594 regulator-name 584 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 585 regulator-min-microvolt = <1050000>;
596 regulator-max- 586 regulator-max-microvolt = <1050000>;
597 }; 587 };
598 588
599 ldo24_reg: LDO24 { 589 ldo24_reg: LDO24 {
600 regulator-name 590 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 591 regulator-min-microvolt = <1200000>;
602 regulator-max- 592 regulator-max-microvolt = <1200000>;
603 }; 593 };
604 594
605 ldo25_reg: LDO25 { 595 ldo25_reg: LDO25 {
606 regulator-name 596 regulator-name = "UNUSED_LDO25";
607 regulator-min- 597 regulator-min-microvolt = <2800000>;
608 regulator-max- 598 regulator-max-microvolt = <2800000>;
609 }; 599 };
610 600
611 ldo26_reg: LDO26 { 601 ldo26_reg: LDO26 {
612 regulator-name 602 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 603 regulator-min-microvolt = <2800000>;
614 regulator-max- 604 regulator-max-microvolt = <2800000>;
615 }; 605 };
616 606
617 ldo27_reg: LDO27 { 607 ldo27_reg: LDO27 {
618 regulator-name 608 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 609 regulator-min-microvolt = <3000000>;
620 regulator-max- 610 regulator-max-microvolt = <3000000>;
621 }; 611 };
622 612
623 ldo28_reg: LDO28 { 613 ldo28_reg: LDO28 {
624 regulator-name 614 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 615 regulator-min-microvolt = <1800000>;
626 regulator-max- 616 regulator-max-microvolt = <1800000>;
627 }; 617 };
628 618
629 ldo29_reg: LDO29 { 619 ldo29_reg: LDO29 {
630 regulator-name 620 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 621 regulator-min-microvolt = <3000000>;
632 regulator-max- 622 regulator-max-microvolt = <3000000>;
633 }; 623 };
634 624
635 ldo30_reg: LDO30 { 625 ldo30_reg: LDO30 {
636 regulator-name 626 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 627 regulator-min-microvolt = <3300000>;
638 regulator-max- 628 regulator-max-microvolt = <3300000>;
639 }; 629 };
640 630
641 ldo31_reg: LDO31 { 631 ldo31_reg: LDO31 {
642 /* 632 /*
643 * LDO31 diffe 633 * LDO31 differs from target to target,
644 * its definit 634 * its definition is in the .dts
645 */ 635 */
646 }; 636 };
647 637
648 ldo32_reg: LDO32 { 638 ldo32_reg: LDO32 {
649 regulator-name 639 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 640 regulator-min-microvolt = <1800000>;
651 regulator-max- 641 regulator-max-microvolt = <1800000>;
652 }; 642 };
653 643
654 ldo33_reg: LDO33 { 644 ldo33_reg: LDO33 {
655 regulator-name 645 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 646 regulator-min-microvolt = <2500000>;
657 regulator-max- 647 regulator-max-microvolt = <3300000>;
658 regulator-ramp 648 regulator-ramp-delay = <12500>;
659 }; 649 };
660 650
661 ldo34_reg: LDO34 { 651 ldo34_reg: LDO34 {
662 regulator-name 652 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 653 regulator-min-microvolt = <1000000>;
664 regulator-max- 654 regulator-max-microvolt = <2100000>;
665 }; 655 };
666 656
667 ldo35_reg: LDO35 { 657 ldo35_reg: LDO35 {
668 regulator-name 658 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 659 regulator-min-microvolt = <1800000>;
670 regulator-max- 660 regulator-max-microvolt = <2800000>;
671 }; 661 };
672 662
673 ldo36_reg: LDO36 { 663 ldo36_reg: LDO36 {
674 regulator-name 664 regulator-name = "VSIL_1.0V";
675 regulator-min- 665 regulator-min-microvolt = <1000000>;
676 regulator-max- 666 regulator-max-microvolt = <1000000>;
677 }; 667 };
678 668
679 ldo37_reg: LDO37 { 669 ldo37_reg: LDO37 {
680 regulator-name 670 regulator-name = "VF_1.8V";
681 regulator-min- 671 regulator-min-microvolt = <1800000>;
682 regulator-max- 672 regulator-max-microvolt = <1800000>;
683 }; 673 };
684 674
685 ldo38_reg: LDO38 { 675 ldo38_reg: LDO38 {
686 /* 676 /*
687 * LDO38 diffe 677 * LDO38 differs from target to target,
688 * its definit 678 * its definition is in the .dts
689 */ 679 */
690 }; 680 };
691 681
692 ldo39_reg: LDO39 { 682 ldo39_reg: LDO39 {
693 regulator-name 683 regulator-name = "V_HRM_1.8V";
694 regulator-min- 684 regulator-min-microvolt = <1800000>;
695 regulator-max- 685 regulator-max-microvolt = <1800000>;
696 }; 686 };
697 687
698 ldo40_reg: LDO40 { 688 ldo40_reg: LDO40 {
699 regulator-name 689 regulator-name = "V_HRM_3.3V";
700 regulator-min- 690 regulator-min-microvolt = <3300000>;
701 regulator-max- 691 regulator-max-microvolt = <3300000>;
702 }; 692 };
703 693
704 buck1_reg: BUCK1 { 694 buck1_reg: BUCK1 {
705 regulator-name 695 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 696 regulator-min-microvolt = <600000>;
707 regulator-max- 697 regulator-max-microvolt = <1500000>;
708 regulator-alwa 698 regulator-always-on;
709 regulator-stat 699 regulator-state-mem {
710 regula 700 regulator-off-in-suspend;
711 }; 701 };
712 }; 702 };
713 703
714 buck2_reg: BUCK2 { 704 buck2_reg: BUCK2 {
715 regulator-name 705 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 706 regulator-min-microvolt = <900000>;
717 regulator-max- 707 regulator-max-microvolt = <1300000>;
718 regulator-alwa 708 regulator-always-on;
719 regulator-stat 709 regulator-state-mem {
720 regula 710 regulator-off-in-suspend;
721 }; 711 };
722 }; 712 };
723 713
724 buck3_reg: BUCK3 { 714 buck3_reg: BUCK3 {
725 regulator-name 715 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 716 regulator-min-microvolt = <800000>;
727 regulator-max- 717 regulator-max-microvolt = <1200000>;
728 regulator-alwa 718 regulator-always-on;
729 regulator-stat 719 regulator-state-mem {
730 regula 720 regulator-off-in-suspend;
731 }; 721 };
732 }; 722 };
733 723
734 buck4_reg: BUCK4 { 724 buck4_reg: BUCK4 {
735 regulator-name 725 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 726 regulator-min-microvolt = <600000>;
737 regulator-max- 727 regulator-max-microvolt = <1500000>;
738 regulator-alwa 728 regulator-always-on;
739 regulator-stat 729 regulator-state-mem {
740 regula 730 regulator-off-in-suspend;
741 }; 731 };
742 }; 732 };
743 733
744 buck5_reg: BUCK5 { 734 buck5_reg: BUCK5 {
745 regulator-name 735 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 736 regulator-min-microvolt = <600000>;
747 regulator-max- 737 regulator-max-microvolt = <1500000>;
748 regulator-alwa 738 regulator-always-on;
749 regulator-stat 739 regulator-state-mem {
750 regula 740 regulator-off-in-suspend;
751 }; 741 };
752 }; 742 };
753 743
754 buck6_reg: BUCK6 { 744 buck6_reg: BUCK6 {
755 regulator-name 745 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 746 regulator-min-microvolt = <600000>;
757 regulator-max- 747 regulator-max-microvolt = <1500000>;
758 regulator-alwa 748 regulator-always-on;
759 regulator-stat 749 regulator-state-mem {
760 regula 750 regulator-off-in-suspend;
761 }; 751 };
762 }; 752 };
763 753
764 buck7_reg: BUCK7 { 754 buck7_reg: BUCK7 {
765 regulator-name 755 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 756 regulator-min-microvolt = <1200000>;
767 regulator-max- 757 regulator-max-microvolt = <1200000>;
768 regulator-alwa 758 regulator-always-on;
769 }; 759 };
770 760
771 buck8_reg: BUCK8 { 761 buck8_reg: BUCK8 {
772 regulator-name 762 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 763 regulator-min-microvolt = <1350000>;
774 regulator-max- 764 regulator-max-microvolt = <3300000>;
775 regulator-alwa 765 regulator-always-on;
776 }; 766 };
777 767
778 buck9_reg: BUCK9 { 768 buck9_reg: BUCK9 {
779 regulator-name 769 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 770 regulator-min-microvolt = <1350000>;
781 regulator-max- 771 regulator-max-microvolt = <3300000>;
782 regulator-alwa 772 regulator-always-on;
783 }; 773 };
784 774
785 buck10_reg: BUCK10 { 775 buck10_reg: BUCK10 {
786 regulator-name 776 regulator-name = "vdd_mem2";
787 regulator-min- 777 regulator-min-microvolt = <550000>;
788 regulator-max- 778 regulator-max-microvolt = <1500000>;
789 regulator-alwa 779 regulator-always-on;
790 }; 780 };
791 }; 781 };
792 }; 782 };
793 }; 783 };
794 784
795 &hsi2c_4 { 785 &hsi2c_4 {
796 status = "okay"; 786 status = "okay";
797 787
798 s3fwrn5: nfc@27 { 788 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 789 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 790 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 791 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ !! 792 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV !! 793 s3fwrn5,en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
804 wake-gpios = <&gpj0 2 GPIO_ACT !! 794 s3fwrn5,fw-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 795 };
806 }; 796 };
807 797
808 &hsi2c_5 { 798 &hsi2c_5 {
809 status = "okay"; 799 status = "okay";
810 800
811 stmfts: touchscreen@49 { 801 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 802 compatible = "st,stmfts";
813 reg = <0x49>; 803 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 804 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 805 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 806 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 807 vdd-supply = <&ldo31_reg>;
818 }; 808 };
819 }; 809 };
820 810
821 &hsi2c_7 { 811 &hsi2c_7 {
822 status = "okay"; 812 status = "okay";
823 clock-frequency = <1000000>; 813 clock-frequency = <1000000>;
824 814
825 bridge@39 { !! 815 sii8620@39 {
826 reg = <0x39>; 816 reg = <0x39>;
827 compatible = "sil,sii8620"; 817 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 818 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 819 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 820 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 821 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 822 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 823 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 824 clock-names = "xtal";
835 825
836 ports { 826 ports {
837 #address-cells = <1>; 827 #address-cells = <1>;
838 #size-cells = <0>; 828 #size-cells = <0>;
839 829
840 port@0 { 830 port@0 {
841 reg = <0>; 831 reg = <0>;
842 mhl_to_hdmi: e 832 mhl_to_hdmi: endpoint {
843 remote 833 remote-endpoint = <&hdmi_to_mhl>;
844 }; 834 };
845 }; 835 };
846 836
847 port@1 { 837 port@1 {
848 reg = <1>; 838 reg = <1>;
849 mhl_to_musb_co 839 mhl_to_musb_con: endpoint {
850 remote 840 remote-endpoint = <&musb_con_to_mhl>;
851 }; 841 };
852 }; 842 };
853 }; 843 };
854 }; 844 };
855 }; 845 };
856 846
857 &hsi2c_8 { 847 &hsi2c_8 {
858 status = "okay"; 848 status = "okay";
859 849
860 pmic@66 { !! 850 max77843@66 {
861 compatible = "maxim,max77843"; 851 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 852 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 853 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 854 reg = <0x66>;
865 855
866 muic: extcon { !! 856 muic: max77843-muic {
867 compatible = "maxim,ma 857 compatible = "maxim,max77843-muic";
868 858
869 musb_con: connector { !! 859 musb_con: musb_connector {
870 compatible = " 860 compatible = "samsung,usb-connector-11pin",
871 " 861 "usb-b-connector";
872 label = "micro 862 label = "micro-USB";
873 type = "micro" 863 type = "micro";
874 864
875 ports { 865 ports {
876 #addre 866 #address-cells = <1>;
877 #size- 867 #size-cells = <0>;
878 868
879 port@0 <<
880 <<
881 <<
882 <<
883 <<
884 <<
885 <<
886 <<
887 <<
888 }; <<
889 <<
890 port@3 869 port@3 {
891 870 reg = <3>;
892 871 musb_con_to_mhl: endpoint {
893 872 remote-endpoint = <&mhl_to_musb_con>;
894 873 };
895 }; 874 };
896 }; 875 };
897 }; 876 };
898 877
899 ports { 878 ports {
900 port { 879 port {
901 muic_t 880 muic_to_usb: endpoint {
902 881 remote-endpoint = <&usb_to_muic>;
903 }; 882 };
904 }; 883 };
905 }; 884 };
906 }; 885 };
907 886
908 regulators { 887 regulators {
909 compatible = "maxim,ma 888 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 889 safeout1_reg: SAFEOUT1 {
911 regulator-name 890 regulator-name = "SAFEOUT1";
912 regulator-min- 891 regulator-min-microvolt = <3300000>;
913 regulator-max- 892 regulator-max-microvolt = <4950000>;
914 }; 893 };
915 894
916 safeout2_reg: SAFEOUT2 895 safeout2_reg: SAFEOUT2 {
917 regulator-name 896 regulator-name = "SAFEOUT2";
918 regulator-min- 897 regulator-min-microvolt = <3300000>;
919 regulator-max- 898 regulator-max-microvolt = <4950000>;
920 }; 899 };
921 900
922 charger_reg: CHARGER { 901 charger_reg: CHARGER {
923 regulator-name 902 regulator-name = "CHARGER";
924 regulator-min- 903 regulator-min-microamp = <100000>;
925 regulator-max- 904 regulator-max-microamp = <3150000>;
926 }; 905 };
927 }; 906 };
928 907
929 haptic: motor-driver { !! 908 haptic: max77843-haptic {
930 compatible = "maxim,ma 909 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 910 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 911 pwms = <&pwm 0 33670 0>;
>> 912 pwm-names = "haptic";
933 }; 913 };
934 }; 914 };
935 }; 915 };
936 916
937 &hsi2c_11 { 917 &hsi2c_11 {
938 status = "okay"; 918 status = "okay";
939 }; 919 };
940 920
941 &i2s0 { 921 &i2s0 {
942 status = "okay"; 922 status = "okay";
943 }; 923 };
944 924
945 &i2s1 { 925 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 926 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 927 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 928 status = "okay";
949 }; 929 };
950 930
951 &mshc_0 { 931 &mshc_0 {
952 status = "okay"; 932 status = "okay";
953 mmc-ddr-1_8v; <<
954 mmc-hs200-1_8v; 933 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 934 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 935 cap-mmc-highspeed;
957 non-removable; 936 non-removable;
958 card-detect-delay = <200>; 937 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 938 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 939 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 940 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 941 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 942 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 943 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 944 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 945 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 946 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 947 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 948 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 949 assigned-clock-rates = <800000000>;
971 }; 950 };
972 951
973 &mshc_2 { 952 &mshc_2 {
974 status = "okay"; 953 status = "okay";
975 cap-sd-highspeed; 954 cap-sd-highspeed;
976 disable-wp; 955 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 956 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 957 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 958 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 959 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 960 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 961 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 962 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 963 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 964 bus-width = <4>;
986 }; 965 };
987 966
988 &pcie { <<
989 status = "okay"; <<
990 pinctrl-names = "default"; <<
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; <<
992 vdd10-supply = <&ldo6_reg>; <<
993 vdd18-supply = <&ldo7_reg>; <<
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ <<
995 <&cmu_top CLK_MOUT_S <<
996 assigned-clock-parents = <&cmu_top CLK <<
997 <&cmu_top CLK <<
998 assigned-clock-rates = <0>, <100000000 <<
999 interrupt-map-mask = <0 0 0 0>; <<
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI <<
1001 }; <<
1002 <<
1003 &pcie_phy { <<
1004 status = "okay"; <<
1005 }; <<
1006 <<
1007 &ppmu_d0_general { 967 &ppmu_d0_general {
1008 status = "okay"; 968 status = "okay";
1009 events { 969 events {
1010 ppmu_event0_d0_general: ppmu- 970 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 971 event-name = "ppmu-event0-d0-general";
1012 }; 972 };
1013 }; 973 };
1014 }; 974 };
1015 975
1016 &ppmu_d1_general { 976 &ppmu_d1_general {
1017 status = "okay"; 977 status = "okay";
1018 events { 978 events {
1019 ppmu_event0_d1_general: ppmu- 979 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 980 event-name = "ppmu-event0-d1-general";
1021 }; 981 };
1022 }; !! 982 };
1023 }; 983 };
1024 984
1025 &pinctrl_alive { 985 &pinctrl_alive {
1026 pinctrl-names = "default"; 986 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 987 pinctrl-0 = <&initial_alive>;
1028 988
1029 initial_alive: initial-state { 989 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 !! 990 PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 !! 991 PIN(INPUT, gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 !! 992 PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 !! 993 PIN(INPUT, gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 !! 994 PIN(INPUT, gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 !! 995 PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 !! 996 PIN(INPUT, gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 !! 997 PIN(INPUT, gpa0-7, NONE, FAST_SR1);
1038 !! 998
1039 PIN_IN(gpa1-0, UP, FAST_SR1); !! 999 PIN(INPUT, gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); !! 1000 PIN(INPUT, gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 !! 1001 PIN(INPUT, gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 !! 1002 PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 !! 1003 PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 !! 1004 PIN(INPUT, gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 !! 1005 PIN(INPUT, gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 !! 1006 PIN(INPUT, gpa1-7, NONE, FAST_SR1);
1047 !! 1007
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 !! 1008 PIN(INPUT, gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 !! 1009 PIN(INPUT, gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 !! 1010 PIN(INPUT, gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 !! 1011 PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 !! 1012 PIN(INPUT, gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 !! 1013 PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 !! 1014 PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 !! 1015 PIN(INPUT, gpa2-7, NONE, FAST_SR1);
1056 !! 1016
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 !! 1017 PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 !! 1018 PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 !! 1019 PIN(INPUT, gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 !! 1020 PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 !! 1021 PIN(INPUT, gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 !! 1022 PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 !! 1023 PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 !! 1024 PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
1065 !! 1025
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 !! 1026 PIN(INPUT, gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 !! 1027 PIN(INPUT, gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 !! 1028 PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); !! 1029 PIN(INPUT, gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 !! 1030 PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 !! 1031 PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 !! 1032 PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
1073 !! 1033
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 !! 1034 PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 !! 1035 PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 !! 1036 PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 !! 1037 PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
1078 !! 1038
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 !! 1039 PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 !! 1040 PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 !! 1041 PIN(INPUT, gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 !! 1042 PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
1083 !! 1043
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 !! 1044 PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 !! 1045 PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 !! 1046 PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 !! 1047 PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 !! 1048 PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 !! 1049 PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 !! 1050 PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 !! 1051 PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
1092 !! 1052
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 !! 1053 PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 !! 1054 PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 !! 1055 PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 !! 1056 PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 !! 1057 PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 !! 1058 PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 !! 1059 PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 !! 1060 PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
1101 }; 1061 };
1102 1062
1103 te_irq: te-irq-pins { !! 1063 te_irq: te_irq {
1104 samsung,pins = "gpf1-3"; 1064 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 1065 samsung,pin-function = <0xf>;
1106 }; 1066 };
1107 }; 1067 };
1108 1068
1109 &pinctrl_cpif { 1069 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1070 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1071 pinctrl-0 = <&initial_cpif>;
1112 1072
1113 initial_cpif: initial-state { 1073 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 !! 1074 PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 !! 1075 PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
1116 }; 1076 };
1117 }; 1077 };
1118 1078
1119 &pinctrl_ese { 1079 &pinctrl_ese {
1120 pinctrl-names = "default"; 1080 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1081 pinctrl-0 = <&initial_ese>;
1122 1082
1123 pcie_wlanen: pcie-wlanen-pins { <<
1124 samsung,pins = "gpj2-0"; <<
1125 samsung,pin-function = <EXYNO <<
1126 samsung,pin-pud = <EXYNOS_PIN <<
1127 samsung,pin-drv = <EXYNOS5433 <<
1128 }; <<
1129 <<
1130 initial_ese: initial-state { 1083 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 !! 1084 PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 !! 1085 PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
>> 1086 PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
1133 }; 1087 };
1134 }; 1088 };
1135 1089
1136 &pinctrl_fsys { 1090 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1091 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1092 pinctrl-0 = <&initial_fsys>;
1139 1093
1140 initial_fsys: initial-state { 1094 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 !! 1095 PIN(INPUT, gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 !! 1096 PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 !! 1097 PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 !! 1098 PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 !! 1099 PIN(INPUT, gpr3-7, NONE, FAST_SR1);
1146 }; 1100 };
1147 }; 1101 };
1148 1102
1149 &pinctrl_imem { 1103 &pinctrl_imem {
1150 pinctrl-names = "default"; 1104 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1105 pinctrl-0 = <&initial_imem>;
1152 1106
1153 initial_imem: initial-state { 1107 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); !! 1108 PIN(INPUT, gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); !! 1109 PIN(INPUT, gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 !! 1110 PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); !! 1111 PIN(INPUT, gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 !! 1112 PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 !! 1113 PIN(INPUT, gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 !! 1114 PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); !! 1115 PIN(INPUT, gpf0-7, UP, FAST_SR1);
1162 }; 1116 };
1163 }; 1117 };
1164 1118
1165 &pinctrl_nfc { 1119 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1120 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1121 pinctrl-0 = <&initial_nfc>;
1168 1122
1169 initial_nfc: initial-state { 1123 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 !! 1124 PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
1171 }; 1125 };
1172 }; 1126 };
1173 1127
1174 &pinctrl_peric { 1128 &pinctrl_peric {
1175 pinctrl-names = "default"; 1129 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1130 pinctrl-0 = <&initial_peric>;
1177 1131
1178 initial_peric: initial-state { 1132 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 !! 1133 PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 !! 1134 PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 !! 1135 PIN(INPUT, gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 !! 1136 PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 !! 1137 PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 !! 1138 PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
1185 1139
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 !! 1140 PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
1187 1141
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 !! 1142 PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 !! 1143 PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 !! 1144 PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
1191 1145
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 !! 1146 PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
1193 1147
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 !! 1148 PIN(INPUT, gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 !! 1149 PIN(INPUT, gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 !! 1150 PIN(INPUT, gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 !! 1151 PIN(INPUT, gpc3-7, NONE, FAST_SR1);
1198 1152
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 !! 1153 PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 !! 1154 PIN(2, gpg0-1, DOWN, FAST_SR1);
1201 1155
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 !! 1156 PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
1203 1157
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 !! 1158 PIN(INPUT, gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 !! 1159 PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 !! 1160 PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 !! 1161 PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 !! 1162 PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
1209 1163
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 !! 1164 PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
1211 1165
1212 PIN_IN(gpd8-1, UP, FAST_SR1); !! 1166 PIN(INPUT, gpd8-1, UP, FAST_SR1);
1213 1167
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 !! 1168 PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 !! 1169 PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 !! 1170 PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 !! 1171 PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 !! 1172 PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
1219 1173
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 !! 1174 PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 !! 1175 PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
1222 1176
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 !! 1177 PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 !! 1178 PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 !! 1179 PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
1226 }; 1180 };
1227 }; 1181 };
1228 1182
1229 &pinctrl_touch { 1183 &pinctrl_touch {
1230 pinctrl-names = "default"; 1184 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1185 pinctrl-0 = <&initial_touch>;
1232 1186
1233 initial_touch: initial-state { 1187 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 !! 1188 PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
1235 }; 1189 };
1236 }; 1190 };
1237 1191
1238 &pwm { 1192 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1193 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1194 pinctrl-names = "default";
1241 status = "okay"; 1195 status = "okay";
1242 }; 1196 };
1243 1197
1244 &mic { 1198 &mic {
1245 status = "okay"; 1199 status = "okay";
1246 }; 1200 };
1247 1201
1248 &pmu_system_controller { 1202 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1203 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1204 assigned-clock-parents = <&xxti>;
1251 }; 1205 };
1252 1206
1253 &serial_1 { 1207 &serial_1 {
1254 status = "okay"; 1208 status = "okay";
1255 }; 1209 };
1256 1210
1257 &serial_3 { 1211 &serial_3 {
1258 status = "okay"; 1212 status = "okay";
1259 1213
1260 bluetooth { 1214 bluetooth {
1261 compatible = "brcm,bcm43438-b 1215 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1216 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1217 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1218 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1219 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1220 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1221 clock-names = "extclk";
1268 }; 1222 };
1269 }; 1223 };
1270 1224
1271 &spi_1 { 1225 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1226 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1227 status = "okay";
1274 1228
1275 wm5110: audio-codec@0 { !! 1229 wm5110: wm5110-codec@0 {
1276 compatible = "wlf,wm5110"; 1230 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1231 reg = <0x0>;
1278 spi-max-frequency = <20000000 1232 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1233 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1234 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1235 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1236 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1237 clock-names = "mclk1", "mclk2";
1284 1238
1285 gpio-controller; 1239 gpio-controller;
1286 #gpio-cells = <2>; 1240 #gpio-cells = <2>;
1287 interrupt-controller; <<
1288 #interrupt-cells = <2>; <<
1289 1241
1290 wlf,micd-detect-debounce = <3 1242 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1243 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1244 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; !! 1245 wlf,micd-dbtime = <0x1>;
1294 wlf,micd-force-micbias; 1246 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1247 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1248 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1249 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1250 wlf,inmode = <2 0 2 0>;
1299 1251
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1252 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1253 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1254
1303 /* core supplies */ 1255 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1256 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1257 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1258 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1259 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1260 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re <<
1310 SPKVDDR-supply = <&vph_pwr_re <<
1311 1261
1312 controller-data { 1262 controller-data {
1313 samsung,spi-feedback- 1263 samsung,spi-feedback-delay = <0>;
1314 }; 1264 };
1315 }; 1265 };
1316 }; 1266 };
1317 1267
1318 &spi_3 { 1268 &spi_3 {
1319 status = "okay"; 1269 status = "okay";
1320 no-cs-readback; 1270 no-cs-readback;
1321 1271
1322 irled@0 { 1272 irled@0 {
1323 compatible = "ir-spi-led"; 1273 compatible = "ir-spi-led";
1324 reg = <0x0>; 1274 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1275 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1276 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; !! 1277 duty-cycle = <60>;
1328 led-active-low; 1278 led-active-low;
1329 1279
1330 controller-data { 1280 controller-data {
1331 samsung,spi-feedback- 1281 samsung,spi-feedback-delay = <0>;
1332 }; 1282 };
1333 }; 1283 };
1334 }; 1284 };
1335 1285
1336 &timer { 1286 &timer {
1337 clock-frequency = <24000000>; 1287 clock-frequency = <24000000>;
1338 }; 1288 };
1339 1289
1340 &tmu_atlas0 { 1290 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1291 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1292 status = "okay";
1343 }; 1293 };
1344 1294
1345 &tmu_apollo { 1295 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1296 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1297 status = "okay";
1348 }; 1298 };
1349 1299
1350 &tmu_g3d { 1300 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1301 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1302 status = "okay";
1353 }; 1303 };
1354 1304
1355 &usbdrd30 { 1305 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1306 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1307 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1308 status = "okay";
1359 }; 1309 };
1360 1310
1361 &usbdrd_dwc3 { 1311 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1312 dr_mode = "otg";
1363 }; 1313 };
1364 1314
1365 &usbdrd30_phy { 1315 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1316 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1317 status = "okay";
1368 1318
1369 port { 1319 port {
1370 usb_to_muic: endpoint { 1320 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1321 remote-endpoint = <&muic_to_usb>;
1372 }; 1322 };
1373 }; 1323 };
1374 }; 1324 };
1375 1325
1376 &xxti { 1326 &xxti {
1377 clock-frequency = <24000000>; 1327 clock-frequency = <24000000>;
1378 }; 1328 };
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