1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so 3 * Samsung Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; 24 mmc0 = &mshc_0;
25 mmc2 = &mshc_2; 25 mmc2 = &mshc_2;
26 pinctrl0 = &pinctrl_alive; 26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 36 serial0 = &serial_0;
37 serial1 = &serial_1; 37 serial1 = &serial_1;
38 serial2 = &serial_2; 38 serial2 = &serial_2;
39 serial3 = &serial_3; 39 serial3 = &serial_3;
40 spi0 = &spi_0; 40 spi0 = &spi_0;
41 spi1 = &spi_1; 41 spi1 = &spi_1;
42 spi2 = &spi_2; 42 spi2 = &spi_2;
43 spi3 = &spi_3; 43 spi3 = &spi_3;
44 spi4 = &spi_4; 44 spi4 = &spi_4;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91 scl-gpios = <&gpd0 0 GPIO_ACTI 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 max98504: amplifier@31 { 96 max98504: amplifier@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 99
100 DIOVDD-supply = <&ldo3 100 DIOVDD-supply = <&ldo3_reg>;
101 DVDD-supply = <&ldo3_r 101 DVDD-supply = <&ldo3_reg>;
102 PVDD-supply = <&vph_pw 102 PVDD-supply = <&vph_pwr_regulator>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { 106 vph_pwr_regulator: regulator-vph-pwr {
107 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
108 regulator-name = "VPH_PWR"; 108 regulator-name = "VPH_PWR";
109 regulator-min-microvolt = <420 109 regulator-min-microvolt = <4200000>;
110 regulator-max-microvolt = <420 110 regulator-max-microvolt = <4200000>;
111 }; 111 };
112 112
113 irda_regulator: regulator-irda { 113 irda_regulator: regulator-irda {
114 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
115 enable-active-high; 115 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 116 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 117 regulator-name = "irda_regulator";
118 }; 118 };
119 119
120 sound { 120 sound {
121 compatible = "samsung,tm2-audi 121 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 122 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 123 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 124 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 125 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 126 model = "wm5110";
127 audio-routing = /* Headphone * !! 127 samsung,audio-routing =
128 "HP", "HPOUT1L !! 128 /* Headphone */
129 "HP", "HPOUT1R !! 129 "HP", "HPOUT1L",
130 !! 130 "HP", "HPOUT1R",
131 /* Speaker */ !! 131
132 "SPK", "SPKOUT !! 132 /* Speaker */
133 "SPKOUT", "HPO !! 133 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 134 "SPKOUT", "HPOUT2L",
135 !! 135 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 136
137 "RCV", "HPOUT3 !! 137 /* Receiver */
138 "RCV", "HPOUT3 !! 138 "RCV", "HPOUT3L",
>> 139 "RCV", "HPOUT3R";
>> 140 status = "okay";
139 }; 141 };
140 }; 142 };
141 143
142 &adc { 144 &adc {
143 vdd-supply = <&ldo3_reg>; 145 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 146 status = "okay";
145 147
146 thermistor-ap { 148 thermistor-ap {
147 compatible = "murata,ncp03wf10 149 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 150 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 151 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 152 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 153 io-channels = <&adc 0>;
152 }; 154 };
153 155
154 thermistor-battery { 156 thermistor-battery {
155 compatible = "murata,ncp03wf10 157 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 158 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 159 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 160 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 161 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 162 #thermal-sensor-cells = <0>;
161 }; 163 };
162 164
163 thermistor-charger { 165 thermistor-charger {
164 compatible = "murata,ncp03wf10 166 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 167 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 168 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 169 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 170 io-channels = <&adc 2>;
169 }; 171 };
170 }; 172 };
171 173
172 &bus_g2d_400 { 174 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 175 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 176 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 177 exynos,saturation-ratio = <10>;
176 status = "okay"; 178 status = "okay";
177 }; 179 };
178 180
179 &bus_g2d_266 { 181 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 182 devfreq = <&bus_g2d_400>;
181 status = "okay"; 183 status = "okay";
182 }; 184 };
183 185
184 &bus_gscl { 186 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 187 devfreq = <&bus_g2d_400>;
186 status = "okay"; 188 status = "okay";
187 }; 189 };
188 190
189 &bus_hevc { 191 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 192 devfreq = <&bus_g2d_400>;
191 status = "okay"; 193 status = "okay";
192 }; 194 };
193 195
194 &bus_jpeg { 196 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 197 devfreq = <&bus_g2d_400>;
196 status = "okay"; 198 status = "okay";
197 }; 199 };
198 200
199 &bus_mfc { 201 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 202 devfreq = <&bus_g2d_400>;
201 status = "okay"; 203 status = "okay";
202 }; 204 };
203 205
204 &bus_mscl { 206 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 207 devfreq = <&bus_g2d_400>;
206 status = "okay"; 208 status = "okay";
207 }; 209 };
208 210
209 &bus_noc0 { 211 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 212 devfreq = <&bus_g2d_400>;
211 status = "okay"; 213 status = "okay";
212 }; 214 };
213 215
214 &bus_noc1 { 216 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 217 devfreq = <&bus_g2d_400>;
216 status = "okay"; 218 status = "okay";
217 }; 219 };
218 220
219 &bus_noc2 { 221 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 222 devfreq = <&bus_g2d_400>;
221 status = "okay"; 223 status = "okay";
222 }; 224 };
223 225
224 &cmu_aud { 226 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 227 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 228 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 229 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 230 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 231 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 232 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 233 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 234 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 235
234 <&cmu_aud CLK_DIV_AUD_CA5>, 236 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 237 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 238 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 239 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 240 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 241 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 242 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 243 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 244 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 245 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 246 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 247
246 assigned-clock-parents = <&cmu_top CLK 248 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 249 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 250 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 251 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 252 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 253 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 254 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 255 <&cmu_top CLK_SCLK_AUDIO0>;
254 256
255 assigned-clock-rates = <0>, <0>, <0>, 257 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 258 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 259 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 260 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 261 };
260 262
261 &cmu_fsys { 263 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 264 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 265 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 266 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 267 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 268 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 269 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 270 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 271 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 272 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 273 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 274 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 275 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 276 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 277 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 278 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 279 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 280 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 281 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 282 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 283 <66700000>, <66700000>;
282 }; 284 };
283 285
284 &cmu_gscl { 286 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 287 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 288 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 289 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 290 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 291 };
290 292
291 &cmu_mfc { 293 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 294 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 295 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 296 };
295 297
296 &cmu_mif { 298 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 299 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 300 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 301 assigned-clock-rates = <0>, <333000000>;
300 }; 302 };
301 303
302 &cmu_mscl { 304 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 305 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 306 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 307 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 308 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 309 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 310 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 311 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 312 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 313 };
312 314
313 &cmu_top { 315 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 316 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 317 assigned-clock-rates = <196608001>;
316 }; 318 };
317 319
318 &cpu0 { 320 &cpu0 {
319 cpu-supply = <&buck3_reg>; 321 cpu-supply = <&buck3_reg>;
320 }; 322 };
321 323
322 &cpu4 { 324 &cpu4 {
323 cpu-supply = <&buck2_reg>; 325 cpu-supply = <&buck2_reg>;
324 }; 326 };
325 327
326 &decon { 328 &decon {
327 status = "okay"; 329 status = "okay";
328 }; 330 };
329 331
330 &decon_tv { 332 &decon_tv {
331 status = "okay"; 333 status = "okay";
332 334
333 ports { 335 ports {
334 #address-cells = <1>; 336 #address-cells = <1>;
335 #size-cells = <0>; 337 #size-cells = <0>;
336 338
337 port@0 { 339 port@0 {
338 reg = <0>; 340 reg = <0>;
339 tv_to_hdmi: endpoint { 341 tv_to_hdmi: endpoint {
340 remote-endpoin 342 remote-endpoint = <&hdmi_to_tv>;
341 }; 343 };
342 }; 344 };
343 }; 345 };
344 }; 346 };
345 347
346 &dsi { 348 &dsi {
347 status = "okay"; 349 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 350 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 351 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 352 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 353 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 354 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 355 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 356 pinctrl-0 = <&te_irq>;
355 }; 357 };
356 358
357 &gpu { 359 &gpu {
358 mali-supply = <&buck6_reg>; 360 mali-supply = <&buck6_reg>;
359 status = "okay"; 361 status = "okay";
360 }; 362 };
361 363
362 &hdmi { 364 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 365 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 366 status = "okay";
365 vdd-supply = <&ldo6_reg>; 367 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 368 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 369 vdd_pll-supply = <&ldo6_reg>;
368 370
369 ports { 371 ports {
370 #address-cells = <1>; 372 #address-cells = <1>;
371 #size-cells = <0>; 373 #size-cells = <0>;
372 374
373 port@0 { 375 port@0 {
374 reg = <0>; 376 reg = <0>;
375 hdmi_to_tv: endpoint { 377 hdmi_to_tv: endpoint {
376 remote-endpoin 378 remote-endpoint = <&tv_to_hdmi>;
377 }; 379 };
378 }; 380 };
379 381
380 port@1 { 382 port@1 {
381 reg = <1>; 383 reg = <1>;
382 hdmi_to_mhl: endpoint 384 hdmi_to_mhl: endpoint {
383 remote-endpoin 385 remote-endpoint = <&mhl_to_hdmi>;
384 }; 386 };
385 }; 387 };
386 }; 388 };
387 }; 389 };
388 390
389 &hsi2c_0 { 391 &hsi2c_0 {
390 status = "okay"; 392 status = "okay";
391 clock-frequency = <2500000>; 393 clock-frequency = <2500000>;
392 394
393 pmic@66 { 395 pmic@66 {
394 compatible = "samsung,s2mps13- 396 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 397 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL 398 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
397 reg = <0x66>; 399 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 400 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; 401 wakeup-source;
400 402
401 s2mps13_osc: clocks { 403 s2mps13_osc: clocks {
402 compatible = "samsung, 404 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 405 #clock-cells = <1>;
404 clock-output-names = " 406 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 407 "s2mps13_bt";
406 }; 408 };
407 409
408 regulators { 410 regulators {
409 ldo1_reg: LDO1 { 411 ldo1_reg: LDO1 {
410 regulator-name 412 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 413 regulator-min-microvolt = <900000>;
412 regulator-max- 414 regulator-max-microvolt = <900000>;
413 regulator-alwa 415 regulator-always-on;
414 }; 416 };
415 417
416 ldo2_reg: LDO2 { 418 ldo2_reg: LDO2 {
417 regulator-name 419 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 420 regulator-min-microvolt = <2800000>;
419 regulator-max- 421 regulator-max-microvolt = <2800000>;
420 regulator-alwa 422 regulator-always-on;
421 regulator-stat 423 regulator-state-mem {
422 regula 424 regulator-off-in-suspend;
423 }; 425 };
424 }; 426 };
425 427
426 ldo3_reg: LDO3 { 428 ldo3_reg: LDO3 {
427 regulator-name 429 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 430 regulator-min-microvolt = <1800000>;
429 regulator-max- 431 regulator-max-microvolt = <1800000>;
430 regulator-alwa 432 regulator-always-on;
431 }; 433 };
432 434
433 ldo4_reg: LDO4 { 435 ldo4_reg: LDO4 {
434 regulator-name 436 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 437 regulator-min-microvolt = <1300000>;
436 regulator-max- 438 regulator-max-microvolt = <1300000>;
437 regulator-alwa 439 regulator-always-on;
438 regulator-stat 440 regulator-state-mem {
439 regula 441 regulator-off-in-suspend;
440 }; 442 };
441 }; 443 };
442 444
443 ldo5_reg: LDO5 { 445 ldo5_reg: LDO5 {
444 regulator-name 446 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 447 regulator-min-microvolt = <1000000>;
446 regulator-max- 448 regulator-max-microvolt = <1000000>;
447 regulator-alwa 449 regulator-always-on;
448 regulator-stat 450 regulator-state-mem {
449 regula 451 regulator-off-in-suspend;
450 }; 452 };
451 }; 453 };
452 454
453 ldo6_reg: LDO6 { 455 ldo6_reg: LDO6 {
454 regulator-name 456 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 457 regulator-min-microvolt = <1000000>;
456 regulator-max- 458 regulator-max-microvolt = <1000000>;
457 regulator-stat 459 regulator-state-mem {
458 regula 460 regulator-off-in-suspend;
459 }; 461 };
460 }; 462 };
461 463
462 ldo7_reg: LDO7 { 464 ldo7_reg: LDO7 {
463 regulator-name 465 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 466 regulator-min-microvolt = <1800000>;
465 regulator-max- 467 regulator-max-microvolt = <1800000>;
466 regulator-alwa 468 regulator-always-on;
467 regulator-stat 469 regulator-state-mem {
468 regula 470 regulator-off-in-suspend;
469 }; 471 };
470 }; 472 };
471 473
472 ldo8_reg: LDO8 { 474 ldo8_reg: LDO8 {
473 regulator-name 475 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 476 regulator-min-microvolt = <1800000>;
475 regulator-max- 477 regulator-max-microvolt = <1800000>;
476 regulator-alwa 478 regulator-always-on;
477 regulator-stat 479 regulator-state-mem {
478 regula 480 regulator-off-in-suspend;
479 }; 481 };
480 }; 482 };
481 483
482 ldo9_reg: LDO9 { 484 ldo9_reg: LDO9 {
483 regulator-name 485 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 486 regulator-min-microvolt = <1800000>;
485 regulator-max- 487 regulator-max-microvolt = <1800000>;
486 regulator-alwa 488 regulator-always-on;
487 regulator-stat 489 regulator-state-mem {
488 regula 490 regulator-off-in-suspend;
489 }; 491 };
490 }; 492 };
491 493
492 ldo10_reg: LDO10 { 494 ldo10_reg: LDO10 {
493 regulator-name 495 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 496 regulator-min-microvolt = <3000000>;
495 regulator-max- 497 regulator-max-microvolt = <3000000>;
496 regulator-stat 498 regulator-state-mem {
497 regula 499 regulator-off-in-suspend;
498 }; 500 };
499 }; 501 };
500 502
501 ldo11_reg: LDO11 { 503 ldo11_reg: LDO11 {
502 regulator-name 504 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 505 regulator-min-microvolt = <1000000>;
504 regulator-max- 506 regulator-max-microvolt = <1000000>;
505 regulator-alwa 507 regulator-always-on;
506 regulator-stat 508 regulator-state-mem {
507 regula 509 regulator-off-in-suspend;
508 }; 510 };
509 }; 511 };
510 512
511 ldo12_reg: LDO12 { 513 ldo12_reg: LDO12 {
512 regulator-name 514 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 515 regulator-min-microvolt = <800000>;
514 regulator-max- 516 regulator-max-microvolt = <1350000>;
515 regulator-alwa 517 regulator-always-on;
516 }; 518 };
517 519
518 ldo13_reg: LDO13 { 520 ldo13_reg: LDO13 {
519 regulator-name 521 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 522 regulator-min-microvolt = <950000>;
521 regulator-max- 523 regulator-max-microvolt = <950000>;
522 regulator-alwa 524 regulator-always-on;
523 regulator-stat 525 regulator-state-mem {
524 regula 526 regulator-off-in-suspend;
525 }; 527 };
526 }; 528 };
527 529
528 ldo14_reg: LDO14 { 530 ldo14_reg: LDO14 {
529 regulator-name 531 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 532 regulator-min-microvolt = <1200000>;
531 regulator-max- 533 regulator-max-microvolt = <1200000>;
532 regulator-alwa 534 regulator-always-on;
533 regulator-stat 535 regulator-state-mem {
534 regula 536 regulator-off-in-suspend;
535 }; 537 };
536 }; 538 };
537 539
538 ldo15_reg: LDO15 { 540 ldo15_reg: LDO15 {
539 regulator-name 541 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 542 regulator-min-microvolt = <1200000>;
541 regulator-max- 543 regulator-max-microvolt = <1200000>;
542 regulator-alwa 544 regulator-always-on;
543 regulator-stat 545 regulator-state-mem {
544 regula 546 regulator-off-in-suspend;
545 }; 547 };
546 }; 548 };
547 549
548 ldo16_reg: LDO16 { 550 ldo16_reg: LDO16 {
549 regulator-name 551 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 552 regulator-min-microvolt = <1400000>;
551 regulator-max- 553 regulator-max-microvolt = <3400000>;
552 regulator-alwa 554 regulator-always-on;
553 }; 555 };
554 556
555 ldo17_reg: LDO17 { 557 ldo17_reg: LDO17 {
556 regulator-name 558 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 559 regulator-min-microvolt = <2800000>;
558 regulator-max- 560 regulator-max-microvolt = <2800000>;
559 }; 561 };
560 562
561 ldo18_reg: LDO18 { 563 ldo18_reg: LDO18 {
562 regulator-name 564 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 565 regulator-min-microvolt = <1800000>;
564 regulator-max- 566 regulator-max-microvolt = <1800000>;
565 }; 567 };
566 568
567 ldo19_reg: LDO19 { 569 ldo19_reg: LDO19 {
568 regulator-name 570 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 571 regulator-min-microvolt = <1800000>;
570 regulator-max- 572 regulator-max-microvolt = <1800000>;
571 regulator-alwa 573 regulator-always-on;
572 }; 574 };
573 575
574 ldo20_reg: LDO20 { 576 ldo20_reg: LDO20 {
575 regulator-name 577 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 578 regulator-min-microvolt = <2800000>;
577 regulator-max- 579 regulator-max-microvolt = <2800000>;
578 regulator-alwa 580 regulator-always-on;
579 }; 581 };
580 582
581 ldo21_reg: LDO21 { 583 ldo21_reg: LDO21 {
582 regulator-name 584 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 585 regulator-min-microvolt = <1800000>;
584 regulator-max- 586 regulator-max-microvolt = <1800000>;
585 }; 587 };
586 588
587 ldo22_reg: LDO22 { 589 ldo22_reg: LDO22 {
588 regulator-name 590 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 591 regulator-min-microvolt = <1800000>;
590 regulator-max- 592 regulator-max-microvolt = <1800000>;
591 }; 593 };
592 594
593 ldo23_reg: LDO23 { 595 ldo23_reg: LDO23 {
594 regulator-name 596 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 597 regulator-min-microvolt = <1050000>;
596 regulator-max- 598 regulator-max-microvolt = <1050000>;
597 }; 599 };
598 600
599 ldo24_reg: LDO24 { 601 ldo24_reg: LDO24 {
600 regulator-name 602 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 603 regulator-min-microvolt = <1200000>;
602 regulator-max- 604 regulator-max-microvolt = <1200000>;
603 }; 605 };
604 606
605 ldo25_reg: LDO25 { 607 ldo25_reg: LDO25 {
606 regulator-name 608 regulator-name = "UNUSED_LDO25";
607 regulator-min- 609 regulator-min-microvolt = <2800000>;
608 regulator-max- 610 regulator-max-microvolt = <2800000>;
609 }; 611 };
610 612
611 ldo26_reg: LDO26 { 613 ldo26_reg: LDO26 {
612 regulator-name 614 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 615 regulator-min-microvolt = <2800000>;
614 regulator-max- 616 regulator-max-microvolt = <2800000>;
615 }; 617 };
616 618
617 ldo27_reg: LDO27 { 619 ldo27_reg: LDO27 {
618 regulator-name 620 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 621 regulator-min-microvolt = <3000000>;
620 regulator-max- 622 regulator-max-microvolt = <3000000>;
621 }; 623 };
622 624
623 ldo28_reg: LDO28 { 625 ldo28_reg: LDO28 {
624 regulator-name 626 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 627 regulator-min-microvolt = <1800000>;
626 regulator-max- 628 regulator-max-microvolt = <1800000>;
627 }; 629 };
628 630
629 ldo29_reg: LDO29 { 631 ldo29_reg: LDO29 {
630 regulator-name 632 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 633 regulator-min-microvolt = <3000000>;
632 regulator-max- 634 regulator-max-microvolt = <3000000>;
633 }; 635 };
634 636
635 ldo30_reg: LDO30 { 637 ldo30_reg: LDO30 {
636 regulator-name 638 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 639 regulator-min-microvolt = <3300000>;
638 regulator-max- 640 regulator-max-microvolt = <3300000>;
639 }; 641 };
640 642
641 ldo31_reg: LDO31 { 643 ldo31_reg: LDO31 {
642 /* 644 /*
643 * LDO31 diffe 645 * LDO31 differs from target to target,
644 * its definit 646 * its definition is in the .dts
645 */ 647 */
646 }; 648 };
647 649
648 ldo32_reg: LDO32 { 650 ldo32_reg: LDO32 {
649 regulator-name 651 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 652 regulator-min-microvolt = <1800000>;
651 regulator-max- 653 regulator-max-microvolt = <1800000>;
652 }; 654 };
653 655
654 ldo33_reg: LDO33 { 656 ldo33_reg: LDO33 {
655 regulator-name 657 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 658 regulator-min-microvolt = <2500000>;
657 regulator-max- 659 regulator-max-microvolt = <3300000>;
658 regulator-ramp 660 regulator-ramp-delay = <12500>;
659 }; 661 };
660 662
661 ldo34_reg: LDO34 { 663 ldo34_reg: LDO34 {
662 regulator-name 664 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 665 regulator-min-microvolt = <1000000>;
664 regulator-max- 666 regulator-max-microvolt = <2100000>;
665 }; 667 };
666 668
667 ldo35_reg: LDO35 { 669 ldo35_reg: LDO35 {
668 regulator-name 670 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 671 regulator-min-microvolt = <1800000>;
670 regulator-max- 672 regulator-max-microvolt = <2800000>;
671 }; 673 };
672 674
673 ldo36_reg: LDO36 { 675 ldo36_reg: LDO36 {
674 regulator-name 676 regulator-name = "VSIL_1.0V";
675 regulator-min- 677 regulator-min-microvolt = <1000000>;
676 regulator-max- 678 regulator-max-microvolt = <1000000>;
677 }; 679 };
678 680
679 ldo37_reg: LDO37 { 681 ldo37_reg: LDO37 {
680 regulator-name 682 regulator-name = "VF_1.8V";
681 regulator-min- 683 regulator-min-microvolt = <1800000>;
682 regulator-max- 684 regulator-max-microvolt = <1800000>;
683 }; 685 };
684 686
685 ldo38_reg: LDO38 { 687 ldo38_reg: LDO38 {
686 /* 688 /*
687 * LDO38 diffe 689 * LDO38 differs from target to target,
688 * its definit 690 * its definition is in the .dts
689 */ 691 */
690 }; 692 };
691 693
692 ldo39_reg: LDO39 { 694 ldo39_reg: LDO39 {
693 regulator-name 695 regulator-name = "V_HRM_1.8V";
694 regulator-min- 696 regulator-min-microvolt = <1800000>;
695 regulator-max- 697 regulator-max-microvolt = <1800000>;
696 }; 698 };
697 699
698 ldo40_reg: LDO40 { 700 ldo40_reg: LDO40 {
699 regulator-name 701 regulator-name = "V_HRM_3.3V";
700 regulator-min- 702 regulator-min-microvolt = <3300000>;
701 regulator-max- 703 regulator-max-microvolt = <3300000>;
702 }; 704 };
703 705
704 buck1_reg: BUCK1 { 706 buck1_reg: BUCK1 {
705 regulator-name 707 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 708 regulator-min-microvolt = <600000>;
707 regulator-max- 709 regulator-max-microvolt = <1500000>;
708 regulator-alwa 710 regulator-always-on;
709 regulator-stat 711 regulator-state-mem {
710 regula 712 regulator-off-in-suspend;
711 }; 713 };
712 }; 714 };
713 715
714 buck2_reg: BUCK2 { 716 buck2_reg: BUCK2 {
715 regulator-name 717 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 718 regulator-min-microvolt = <900000>;
717 regulator-max- 719 regulator-max-microvolt = <1300000>;
718 regulator-alwa 720 regulator-always-on;
719 regulator-stat 721 regulator-state-mem {
720 regula 722 regulator-off-in-suspend;
721 }; 723 };
722 }; 724 };
723 725
724 buck3_reg: BUCK3 { 726 buck3_reg: BUCK3 {
725 regulator-name 727 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 728 regulator-min-microvolt = <800000>;
727 regulator-max- 729 regulator-max-microvolt = <1200000>;
728 regulator-alwa 730 regulator-always-on;
729 regulator-stat 731 regulator-state-mem {
730 regula 732 regulator-off-in-suspend;
731 }; 733 };
732 }; 734 };
733 735
734 buck4_reg: BUCK4 { 736 buck4_reg: BUCK4 {
735 regulator-name 737 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 738 regulator-min-microvolt = <600000>;
737 regulator-max- 739 regulator-max-microvolt = <1500000>;
738 regulator-alwa 740 regulator-always-on;
739 regulator-stat 741 regulator-state-mem {
740 regula 742 regulator-off-in-suspend;
741 }; 743 };
742 }; 744 };
743 745
744 buck5_reg: BUCK5 { 746 buck5_reg: BUCK5 {
745 regulator-name 747 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 748 regulator-min-microvolt = <600000>;
747 regulator-max- 749 regulator-max-microvolt = <1500000>;
748 regulator-alwa 750 regulator-always-on;
749 regulator-stat 751 regulator-state-mem {
750 regula 752 regulator-off-in-suspend;
751 }; 753 };
752 }; 754 };
753 755
754 buck6_reg: BUCK6 { 756 buck6_reg: BUCK6 {
755 regulator-name 757 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 758 regulator-min-microvolt = <600000>;
757 regulator-max- 759 regulator-max-microvolt = <1500000>;
758 regulator-alwa 760 regulator-always-on;
759 regulator-stat 761 regulator-state-mem {
760 regula 762 regulator-off-in-suspend;
761 }; 763 };
762 }; 764 };
763 765
764 buck7_reg: BUCK7 { 766 buck7_reg: BUCK7 {
765 regulator-name 767 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 768 regulator-min-microvolt = <1200000>;
767 regulator-max- 769 regulator-max-microvolt = <1200000>;
768 regulator-alwa 770 regulator-always-on;
769 }; 771 };
770 772
771 buck8_reg: BUCK8 { 773 buck8_reg: BUCK8 {
772 regulator-name 774 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 775 regulator-min-microvolt = <1350000>;
774 regulator-max- 776 regulator-max-microvolt = <3300000>;
775 regulator-alwa 777 regulator-always-on;
776 }; 778 };
777 779
778 buck9_reg: BUCK9 { 780 buck9_reg: BUCK9 {
779 regulator-name 781 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 782 regulator-min-microvolt = <1350000>;
781 regulator-max- 783 regulator-max-microvolt = <3300000>;
782 regulator-alwa 784 regulator-always-on;
783 }; 785 };
784 786
785 buck10_reg: BUCK10 { 787 buck10_reg: BUCK10 {
786 regulator-name 788 regulator-name = "vdd_mem2";
787 regulator-min- 789 regulator-min-microvolt = <550000>;
788 regulator-max- 790 regulator-max-microvolt = <1500000>;
789 regulator-alwa 791 regulator-always-on;
790 }; 792 };
791 }; 793 };
792 }; 794 };
793 }; 795 };
794 796
795 &hsi2c_4 { 797 &hsi2c_4 {
796 status = "okay"; 798 status = "okay";
797 799
798 s3fwrn5: nfc@27 { 800 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 801 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 802 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 803 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ 804 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV 805 en-gpios = <&gpf1 4 GPIO_ACTIVE_LOW>;
804 wake-gpios = <&gpj0 2 GPIO_ACT 806 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 807 };
806 }; 808 };
807 809
808 &hsi2c_5 { 810 &hsi2c_5 {
809 status = "okay"; 811 status = "okay";
810 812
811 stmfts: touchscreen@49 { 813 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 814 compatible = "st,stmfts";
813 reg = <0x49>; 815 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 816 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 817 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 818 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 819 vdd-supply = <&ldo31_reg>;
818 }; 820 };
819 }; 821 };
820 822
821 &hsi2c_7 { 823 &hsi2c_7 {
822 status = "okay"; 824 status = "okay";
823 clock-frequency = <1000000>; 825 clock-frequency = <1000000>;
824 826
825 bridge@39 { 827 bridge@39 {
826 reg = <0x39>; 828 reg = <0x39>;
827 compatible = "sil,sii8620"; 829 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 830 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 831 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 832 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 833 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 834 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 835 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 836 clock-names = "xtal";
835 837
836 ports { 838 ports {
837 #address-cells = <1>; 839 #address-cells = <1>;
838 #size-cells = <0>; 840 #size-cells = <0>;
839 841
840 port@0 { 842 port@0 {
841 reg = <0>; 843 reg = <0>;
842 mhl_to_hdmi: e 844 mhl_to_hdmi: endpoint {
843 remote 845 remote-endpoint = <&hdmi_to_mhl>;
844 }; 846 };
845 }; 847 };
846 848
847 port@1 { 849 port@1 {
848 reg = <1>; 850 reg = <1>;
849 mhl_to_musb_co 851 mhl_to_musb_con: endpoint {
850 remote 852 remote-endpoint = <&musb_con_to_mhl>;
851 }; 853 };
852 }; 854 };
853 }; 855 };
854 }; 856 };
855 }; 857 };
856 858
857 &hsi2c_8 { 859 &hsi2c_8 {
858 status = "okay"; 860 status = "okay";
859 861
860 pmic@66 { 862 pmic@66 {
861 compatible = "maxim,max77843"; 863 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 864 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 865 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 866 reg = <0x66>;
865 867
866 muic: extcon { 868 muic: extcon {
867 compatible = "maxim,ma 869 compatible = "maxim,max77843-muic";
868 870
869 musb_con: connector { 871 musb_con: connector {
870 compatible = " 872 compatible = "samsung,usb-connector-11pin",
871 " 873 "usb-b-connector";
872 label = "micro 874 label = "micro-USB";
873 type = "micro" 875 type = "micro";
874 876
875 ports { 877 ports {
876 #addre 878 #address-cells = <1>;
877 #size- 879 #size-cells = <0>;
878 880
879 port@0 881 port@0 {
880 882 /*
881 883 * TODO: The DTS this is based on does not have
882 884 * port@0 which is a required property. The ports
883 885 * look incomplete and need fixing.
884 886 * Add a disabled port just to satisfy dtschema.
885 887 */
886 888 reg = <0>;
887 889 status = "disabled";
888 }; 890 };
889 891
890 port@3 892 port@3 {
891 893 reg = <3>;
892 894 musb_con_to_mhl: endpoint {
893 895 remote-endpoint = <&mhl_to_musb_con>;
894 896 };
895 }; 897 };
896 }; 898 };
897 }; 899 };
898 900
899 ports { 901 ports {
900 port { 902 port {
901 muic_t 903 muic_to_usb: endpoint {
902 904 remote-endpoint = <&usb_to_muic>;
903 }; 905 };
904 }; 906 };
905 }; 907 };
906 }; 908 };
907 909
908 regulators { 910 regulators {
909 compatible = "maxim,ma 911 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 912 safeout1_reg: SAFEOUT1 {
911 regulator-name 913 regulator-name = "SAFEOUT1";
912 regulator-min- 914 regulator-min-microvolt = <3300000>;
913 regulator-max- 915 regulator-max-microvolt = <4950000>;
914 }; 916 };
915 917
916 safeout2_reg: SAFEOUT2 918 safeout2_reg: SAFEOUT2 {
917 regulator-name 919 regulator-name = "SAFEOUT2";
918 regulator-min- 920 regulator-min-microvolt = <3300000>;
919 regulator-max- 921 regulator-max-microvolt = <4950000>;
920 }; 922 };
921 923
922 charger_reg: CHARGER { 924 charger_reg: CHARGER {
923 regulator-name 925 regulator-name = "CHARGER";
924 regulator-min- 926 regulator-min-microamp = <100000>;
925 regulator-max- 927 regulator-max-microamp = <3150000>;
926 }; 928 };
927 }; 929 };
928 930
929 haptic: motor-driver { 931 haptic: motor-driver {
930 compatible = "maxim,ma 932 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 933 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 934 pwms = <&pwm 0 33670 0>;
933 }; 935 };
934 }; 936 };
935 }; 937 };
936 938
937 &hsi2c_11 { 939 &hsi2c_11 {
938 status = "okay"; 940 status = "okay";
939 }; 941 };
940 942
941 &i2s0 { 943 &i2s0 {
942 status = "okay"; 944 status = "okay";
943 }; 945 };
944 946
945 &i2s1 { 947 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 948 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 949 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 950 status = "okay";
949 }; 951 };
950 952
951 &mshc_0 { 953 &mshc_0 {
952 status = "okay"; 954 status = "okay";
953 mmc-ddr-1_8v; 955 mmc-ddr-1_8v;
954 mmc-hs200-1_8v; 956 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 957 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 958 cap-mmc-highspeed;
957 non-removable; 959 non-removable;
958 card-detect-delay = <200>; 960 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 961 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 962 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 963 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 964 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 965 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 966 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 967 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 968 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 969 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 970 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 971 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 972 assigned-clock-rates = <800000000>;
971 }; 973 };
972 974
973 &mshc_2 { 975 &mshc_2 {
974 status = "okay"; 976 status = "okay";
975 cap-sd-highspeed; 977 cap-sd-highspeed;
976 disable-wp; 978 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 979 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 980 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 981 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 982 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 983 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 984 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 985 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 986 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 987 bus-width = <4>;
986 }; 988 };
987 989
988 &pcie { 990 &pcie {
989 status = "okay"; 991 status = "okay";
990 pinctrl-names = "default"; 992 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 993 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>; 994 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>; 995 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ 996 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
995 <&cmu_top CLK_MOUT_S 997 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK 998 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK 999 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
998 assigned-clock-rates = <0>, <100000000 1000 assigned-clock-rates = <0>, <100000000>;
999 interrupt-map-mask = <0 0 0 0>; 1001 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 1002 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1001 }; 1003 };
1002 1004
1003 &pcie_phy { 1005 &pcie_phy {
1004 status = "okay"; 1006 status = "okay";
1005 }; 1007 };
1006 1008
1007 &ppmu_d0_general { 1009 &ppmu_d0_general {
1008 status = "okay"; 1010 status = "okay";
1009 events { 1011 events {
1010 ppmu_event0_d0_general: ppmu- 1012 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 1013 event-name = "ppmu-event0-d0-general";
1012 }; 1014 };
1013 }; 1015 };
1014 }; 1016 };
1015 1017
1016 &ppmu_d1_general { 1018 &ppmu_d1_general {
1017 status = "okay"; 1019 status = "okay";
1018 events { 1020 events {
1019 ppmu_event0_d1_general: ppmu- 1021 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 1022 event-name = "ppmu-event0-d1-general";
1021 }; 1023 };
1022 }; 1024 };
1023 }; 1025 };
1024 1026
1025 &pinctrl_alive { 1027 &pinctrl_alive {
1026 pinctrl-names = "default"; 1028 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 1029 pinctrl-0 = <&initial_alive>;
1028 1030
1029 initial_alive: initial-state { 1031 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 1032 PIN_IN(gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 1033 PIN_IN(gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 1034 PIN_IN(gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 1035 PIN_IN(gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 1036 PIN_IN(gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 1037 PIN_IN(gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 1038 PIN_IN(gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 1039 PIN_IN(gpa0-7, NONE, FAST_SR1);
1038 1040
1039 PIN_IN(gpa1-0, UP, FAST_SR1); 1041 PIN_IN(gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); 1042 PIN_IN(gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 1043 PIN_IN(gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 1044 PIN_IN(gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 1045 PIN_IN(gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 1046 PIN_IN(gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 1047 PIN_IN(gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 1048 PIN_IN(gpa1-7, NONE, FAST_SR1);
1047 1049
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 1050 PIN_IN(gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 1051 PIN_IN(gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 1052 PIN_IN(gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 1053 PIN_IN(gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 1054 PIN_IN(gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 1055 PIN_IN(gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 1056 PIN_IN(gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 1057 PIN_IN(gpa2-7, NONE, FAST_SR1);
1056 1058
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 1059 PIN_IN(gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 1060 PIN_IN(gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 1061 PIN_IN(gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 1062 PIN_IN(gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 1063 PIN_IN(gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 1064 PIN_IN(gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 1065 PIN_IN(gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 1066 PIN_IN(gpa3-7, DOWN, FAST_SR1);
1065 1067
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 1068 PIN_IN(gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 1069 PIN_IN(gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 1070 PIN_IN(gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); 1071 PIN_IN(gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 1072 PIN_OT(gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 1073 PIN_IN(gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 1074 PIN_IN(gpf1-7, DOWN, FAST_SR1);
1073 1075
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 1076 PIN_IN(gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 1077 PIN_IN(gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 1078 PIN_IN(gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 1079 PIN_IN(gpf2-3, DOWN, FAST_SR1);
1078 1080
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 1081 PIN_IN(gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 1082 PIN_IN(gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 1083 PIN_IN(gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 1084 PIN_IN(gpf3-3, DOWN, FAST_SR1);
1083 1085
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 1086 PIN_IN(gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 1087 PIN_IN(gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 1088 PIN_IN(gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 1089 PIN_IN(gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 1090 PIN_IN(gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 1091 PIN_IN(gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 1092 PIN_IN(gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 1093 PIN_IN(gpf4-7, DOWN, FAST_SR1);
1092 1094
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 1095 PIN_IN(gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 1096 PIN_IN(gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 1097 PIN_IN(gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 1098 PIN_IN(gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 1099 PIN_OT(gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 1100 PIN_IN(gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 1101 PIN_IN(gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 1102 PIN_IN(gpf5-7, DOWN, FAST_SR1);
1101 }; 1103 };
1102 1104
1103 te_irq: te-irq-pins { 1105 te_irq: te-irq-pins {
1104 samsung,pins = "gpf1-3"; 1106 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 1107 samsung,pin-function = <0xf>;
1106 }; 1108 };
1107 }; 1109 };
1108 1110
1109 &pinctrl_cpif { 1111 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1112 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1113 pinctrl-0 = <&initial_cpif>;
1112 1114
1113 initial_cpif: initial-state { 1115 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 1116 PIN_IN(gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 1117 PIN_IN(gpv6-1, DOWN, FAST_SR1);
1116 }; 1118 };
1117 }; 1119 };
1118 1120
1119 &pinctrl_ese { 1121 &pinctrl_ese {
1120 pinctrl-names = "default"; 1122 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1123 pinctrl-0 = <&initial_ese>;
1122 1124
1123 pcie_wlanen: pcie-wlanen-pins { 1125 pcie_wlanen: pcie-wlanen-pins {
1124 samsung,pins = "gpj2-0"; 1126 samsung,pins = "gpj2-0";
1125 samsung,pin-function = <EXYNO 1127 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1126 samsung,pin-pud = <EXYNOS_PIN 1128 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1127 samsung,pin-drv = <EXYNOS5433 1129 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
1128 }; 1130 };
1129 1131
1130 initial_ese: initial-state { 1132 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 1133 PIN_IN(gpj2-1, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 1134 PIN_IN(gpj2-2, DOWN, FAST_SR1);
1133 }; 1135 };
1134 }; 1136 };
1135 1137
1136 &pinctrl_fsys { 1138 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1139 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1140 pinctrl-0 = <&initial_fsys>;
1139 1141
1140 initial_fsys: initial-state { 1142 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 1143 PIN_IN(gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 1144 PIN_IN(gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 1145 PIN_IN(gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 1146 PIN_IN(gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 1147 PIN_IN(gpr3-7, NONE, FAST_SR1);
1146 }; 1148 };
1147 }; 1149 };
1148 1150
1149 &pinctrl_imem { 1151 &pinctrl_imem {
1150 pinctrl-names = "default"; 1152 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1153 pinctrl-0 = <&initial_imem>;
1152 1154
1153 initial_imem: initial-state { 1155 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); 1156 PIN_IN(gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); 1157 PIN_IN(gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 1158 PIN_IN(gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); 1159 PIN_IN(gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 1160 PIN_IN(gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 1161 PIN_IN(gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 1162 PIN_IN(gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); 1163 PIN_IN(gpf0-7, UP, FAST_SR1);
1162 }; 1164 };
1163 }; 1165 };
1164 1166
1165 &pinctrl_nfc { 1167 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1168 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1169 pinctrl-0 = <&initial_nfc>;
1168 1170
1169 initial_nfc: initial-state { 1171 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 1172 PIN_IN(gpj0-2, DOWN, FAST_SR1);
1171 }; 1173 };
1172 }; 1174 };
1173 1175
1174 &pinctrl_peric { 1176 &pinctrl_peric {
1175 pinctrl-names = "default"; 1177 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1178 pinctrl-0 = <&initial_peric>;
1177 1179
1178 initial_peric: initial-state { 1180 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 1181 PIN_IN(gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 1182 PIN_IN(gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 1183 PIN_IN(gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 1184 PIN_IN(gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 1185 PIN_IN(gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 1186 PIN_IN(gpv7-5, DOWN, FAST_SR1);
1185 1187
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 1188 PIN_IN(gpb0-4, DOWN, FAST_SR1);
1187 1189
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 1190 PIN_IN(gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 1191 PIN_IN(gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 1192 PIN_IN(gpc0-7, DOWN, FAST_SR1);
1191 1193
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 1194 PIN_IN(gpc1-1, DOWN, FAST_SR1);
1193 1195
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 1196 PIN_IN(gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 1197 PIN_IN(gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 1198 PIN_IN(gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 1199 PIN_IN(gpc3-7, NONE, FAST_SR1);
1198 1200
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 1201 PIN_OT(gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 1202 PIN_F2(gpg0-1, DOWN, FAST_SR1);
1201 1203
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 1204 PIN_IN(gpd2-5, DOWN, FAST_SR1);
1203 1205
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 1206 PIN_IN(gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 1207 PIN_IN(gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 1208 PIN_IN(gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 1209 PIN_IN(gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 1210 PIN_IN(gpd4-4, DOWN, FAST_SR1);
1209 1211
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 1212 PIN_IN(gpd6-3, DOWN, FAST_SR1);
1211 1213
1212 PIN_IN(gpd8-1, UP, FAST_SR1); 1214 PIN_IN(gpd8-1, UP, FAST_SR1);
1213 1215
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 1216 PIN_IN(gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 1217 PIN_IN(gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 1218 PIN_IN(gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 1219 PIN_IN(gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 1220 PIN_IN(gpg1-4, DOWN, FAST_SR1);
1219 1221
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 1222 PIN_IN(gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 1223 PIN_IN(gpg2-1, DOWN, FAST_SR1);
1222 1224
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 1225 PIN_IN(gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 1226 PIN_IN(gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 1227 PIN_IN(gpg3-5, DOWN, FAST_SR1);
1226 }; 1228 };
1227 }; 1229 };
1228 1230
1229 &pinctrl_touch { 1231 &pinctrl_touch {
1230 pinctrl-names = "default"; 1232 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1233 pinctrl-0 = <&initial_touch>;
1232 1234
1233 initial_touch: initial-state { 1235 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 1236 PIN_IN(gpj1-2, DOWN, FAST_SR1);
1235 }; 1237 };
1236 }; 1238 };
1237 1239
1238 &pwm { 1240 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1241 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1242 pinctrl-names = "default";
1241 status = "okay"; 1243 status = "okay";
1242 }; 1244 };
1243 1245
1244 &mic { 1246 &mic {
1245 status = "okay"; 1247 status = "okay";
1246 }; 1248 };
1247 1249
1248 &pmu_system_controller { 1250 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1251 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1252 assigned-clock-parents = <&xxti>;
1251 }; 1253 };
1252 1254
1253 &serial_1 { 1255 &serial_1 {
1254 status = "okay"; 1256 status = "okay";
1255 }; 1257 };
1256 1258
1257 &serial_3 { 1259 &serial_3 {
1258 status = "okay"; 1260 status = "okay";
1259 1261
1260 bluetooth { 1262 bluetooth {
1261 compatible = "brcm,bcm43438-b 1263 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1264 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1265 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1266 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1267 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1268 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1269 clock-names = "extclk";
1268 }; 1270 };
1269 }; 1271 };
1270 1272
1271 &spi_1 { 1273 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1274 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1275 status = "okay";
1274 1276
1275 wm5110: audio-codec@0 { 1277 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110"; 1278 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1279 reg = <0x0>;
1278 spi-max-frequency = <20000000 1280 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1281 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1282 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1283 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1284 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1285 clock-names = "mclk1", "mclk2";
1284 1286
1285 gpio-controller; 1287 gpio-controller;
1286 #gpio-cells = <2>; 1288 #gpio-cells = <2>;
1287 interrupt-controller; 1289 interrupt-controller;
1288 #interrupt-cells = <2>; 1290 #interrupt-cells = <2>;
1289 1291
1290 wlf,micd-detect-debounce = <3 1292 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1293 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1294 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; 1295 wlf,micd-dbtime = <0x2>;
1294 wlf,micd-force-micbias; 1296 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1297 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1298 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1299 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1300 wlf,inmode = <2 0 2 0>;
1299 1301
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1302 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1303 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1304
1303 /* core supplies */ 1305 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1306 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1307 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1308 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1309 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1310 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re 1311 SPKVDDL-supply = <&vph_pwr_regulator>;
1310 SPKVDDR-supply = <&vph_pwr_re 1312 SPKVDDR-supply = <&vph_pwr_regulator>;
1311 1313
1312 controller-data { 1314 controller-data {
1313 samsung,spi-feedback- 1315 samsung,spi-feedback-delay = <0>;
1314 }; 1316 };
1315 }; 1317 };
1316 }; 1318 };
1317 1319
1318 &spi_3 { 1320 &spi_3 {
1319 status = "okay"; 1321 status = "okay";
1320 no-cs-readback; 1322 no-cs-readback;
1321 1323
1322 irled@0 { 1324 irled@0 {
1323 compatible = "ir-spi-led"; 1325 compatible = "ir-spi-led";
1324 reg = <0x0>; 1326 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1327 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1328 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; 1329 duty-cycle = /bits/ 8 <60>;
1328 led-active-low; 1330 led-active-low;
1329 1331
1330 controller-data { 1332 controller-data {
1331 samsung,spi-feedback- 1333 samsung,spi-feedback-delay = <0>;
1332 }; 1334 };
1333 }; 1335 };
1334 }; 1336 };
1335 1337
1336 &timer { 1338 &timer {
1337 clock-frequency = <24000000>; 1339 clock-frequency = <24000000>;
1338 }; 1340 };
1339 1341
1340 &tmu_atlas0 { 1342 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1343 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1344 status = "okay";
1343 }; 1345 };
1344 1346
1345 &tmu_apollo { 1347 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1348 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1349 status = "okay";
1348 }; 1350 };
1349 1351
1350 &tmu_g3d { 1352 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1353 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1354 status = "okay";
1353 }; 1355 };
1354 1356
1355 &usbdrd30 { 1357 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1358 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1359 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1360 status = "okay";
1359 }; 1361 };
1360 1362
1361 &usbdrd_dwc3 { 1363 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1364 dr_mode = "otg";
1363 }; 1365 };
1364 1366
1365 &usbdrd30_phy { 1367 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1368 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1369 status = "okay";
1368 1370
1369 port { 1371 port {
1370 usb_to_muic: endpoint { 1372 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1373 remote-endpoint = <&muic_to_usb>;
1372 }; 1374 };
1373 }; 1375 };
1374 }; 1376 };
1375 1377
1376 &xxti { 1378 &xxti {
1377 clock-frequency = <24000000>; 1379 clock-frequency = <24000000>;
1378 }; 1380 };
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